Tutorial: Working with schematics, and 3700 Lab Kit components in ISE 10.1i

This tutorial will show you how to:

• Set up a new project in ISE • Use components from the Lab Kit in your schematic • Simulate the circuit using the ISE simulator and a Verilog test fixture

I assume that you’re using a DSL lab machine, or that you’ve installed Xilinx ISE 10.1i on your own machine. Setting up a New Project and Drawing a Schematic

1. Open the ISE Project Manager. You can click on the Xilinx ISE 10.1i icon

on the desktop , or use Start → All Programs → Xilinx ISE Design Suite 10.1i → ISE → Project Navigator The screen should look something like the following:

2. Now select File → New Project… and change the Project Name and Project Location to whatever you like. Note that Xilinx does not allow spaces in path or file names! I’ve also selected the Top Level Source Type to be Schematic because that’s what I plan on using. This is not critical. You can always add a new source file of any type later. My dialog box looks like:

3. In the Next dialog box you should fill in the fields as shown here. We are using a General Purpose Product in the Spartan2 family. The specific chip on our board is an XC2S50 in a TQ144 package and the –6 speed grade. Make sure that the Synthesis Tool is XST, the Simulator is the ISE Simulator, and the Preferred Language is Verilog.

4. You can ignore the next two boxes (Create New Source and Add Existing Sources), click Next to get to the Finish box. Mine looks like:

5. Now you should have a new project that targets the correct Xilinx part and other features of the ISE system. Note that you won’t use the Xilinx part for the first lab at least, but it’s good to get things set up correctly for later.

6. Now you want to open a new schematic in your project. Choose Project → New Source to get the dialog that adds a new source file to your project (or use the New Source widget on the tool bar ). Source files can be of many types. We’ll add a Schematic named foo. Make sure to both fill in the File Name and select the Schematic type from the list on the left. I’ve filled in my dialog box as shown:

7. After you Next and Finish you will get a blank schematic view, and also a Design Summary view in the main pane of the ISE window. You can switch between windows in the main pane with the tabs along the bottom. The (empty) schematic looks like:

If you don’t see this exact view, you may be looking at a different tab in a window. Each pane has tabs at the bottom that let you switch to look at different things. For example, for the top left pane this image above is of the “Sources” tab. There will also be “Files”, “Snapshot”, “Libraries”, and “Symbols” tabs that you can click on and get different information about the project. The lower left pane has a Processes tab and an Options tab that each show different info. The main window in the figure above has a “foo.sch” tab for the new schematic, and a “Design Summary” tab. If you open more schematics, or other types of files (like Verilog files) the main pane will have additional tabs. 8. Now you can select components from the Symbols tab of the upper left

pane and drag them to your schematic. You can narrow down your choices using the Categories, or by typing the first few characters of the symbol you’re looking for in the Symbol Name Filter, or just scroll through the lists and see what’s there. The most important categories for now are:

• Logic: General logic gates. See the Lab handouts for restrictions on which logic gates you should use!

• General: Some utility components like gnd, vcc, pullup, and pulldown.

I’ll grab some components from those Categories to make a very simple schematic.

9. Use the wiring tool to wire up the components. It is in the tool bar and looks like a red line and a pencil . You could also use Add →Wire from the menu. I’m using the following components (from the Logic category) in this example:

a. nand2: a two-input nand gate b. or2b2: a two-input OR gate with both inputs inverted c. inv: an inverter

10. I’ve also placed I/O Markers to the inputs and outputs. I’ve used the I/O Marker widget that looks like two little labels . You can also use the Add → I/O Marker command from the menu. Click on the endpoints of the wire to add the marker, and change the name of the marker to whatever you want the signals to be named. You can double click the marker, or select the marker and right click to get a menu and choose Edit → Properties. I’m calling the inputs A, B and S and the output F. An I/O Marker dialog box looks like:

The resulting schematic looks like the following:

If I zoom in to the circuit part of the schematic (using the Zoom to Box command which is in the View menu or a widget in the control bar ), it looks like this:

11. When you are happy with your schematic (and your schematic will likely include other logic gates from the Logic category that I haven’t used in this example!), save it. Hopefully you don’t have any errors or warnings. If you do, you need to fix them. Once your schematic is saved it should show up in the Sources pane in the upper left of the ISE screen.

12. Now click on the Sources tab in the upper left pane, making sure that the Source For field is Implementation. Also click on the Processes tab of the lower left pane. In the Processes pane, expand the Design Utilities. You should see Create Schematic Symbol. Double click that to make a symbol for the schematic that you just saved. This will allow you to use this schematic as a component in another schematic, but it also is important for the simulation step that’s coming up.

Simulating your Circuit: Now that you have a saved schematic, you need to simulate its behavior. The simulator we’ll use is the ISE built in simulator, which is essentially a Verilog simulator. The schematic that you just drew will be saved as a piece of Verilog behind your back. In order to simulate the circuit you need: • A description of the circuit in Verilog. ISE will create this for you

• A testbench file that applies inputs to your circuit, and potentially checks that the outputs are correct. This will be another Verilog file. The testbench will instantiate one copy of your circuit, and call it UUT for Unit Under Test. You will then write the Verilog statements that set the inputs to your circuit (the UUT), and looks at the outputs produced by your circuit. You need to know only very basic Verilog syntax to do this.

To simulate the circuit:

1. Go to the top left pane and change the Sources For: field to be Behavioral Simulation.

2. This changes the options in the bottom left pane to the simulator options. In that pane double-click Create New Source. This will bring up the New Source Wizard. In that dialog type in the name of your testbench file, and make sure to select Verilog Test Fixture in the list on the left. I will name my testbench foo_tf (where the tf stands for test fixture). The box looks like:

3. The Next dialog asks you which source you want the testbench constructed from. At this point I only have one source in my project. Larger projects will have many sources to choose from. Choose the schematic that you want to simulate. In this case, my schematic was named foo, so I’ll select that one:

4. When you Next and Finish, you’ll get a new piece of Verilog code generated for you. This Verilog code instantiates my schematic (foo) as the UUT, and includes some other stuff related to how the UUT is connected to the testbench. It looks like this:

5. You can ignore that ‘ifdef / ‘endif stuff. We may get into that later, but at this point you can assume that auto_init is not defined so that code is not executed. You can now write your testbench code as an initial block right before the endmodule. Basically you set the values of your inputs, and tell the simulator how long to wait between each change on the inputs. The results will eventually be plotted on a waveform for you. Verilog syntax for setting a variable is very simple, and the #20 notation just means for the simulation to wait for 20 ticks of the simulation clock before moving on to the next statement. A very simple testbench for this circuit looks like the following. I added the lines between initial and end to drive the inputs with different values so that we can see what the circuit result is. Note that each statement in Verilog ends with a semicolon, and you can put multiple

statements on a line if you like.

This just changes the input values and then waits 20 ticks before changing them again. You can obviously write much more complex Verilog here if you want to! And you will before the semester is out…

6. Save this file. Now assuming that your upper left pane is still in Behavioral mode, you’ll see the foo_tf.v file listed in the source list. Select it, expand the Xilinx ISE Simulator choice in the lower left pane and double-click the Check Syntax command. This will check to make sure that your testbench doesn’t have any syntax errors in it. If there are, you need to fix them!

7. Double-Click the Simulate Behavioral Model. This will fire up the simulator on your testbench file. Because your testbench includes an instance of your schematic (the UUT) and some commands to drive signals into your schematic, this will result in simulating your schematic. The output will be displayed as waveforms as shown. Note that the simulator is by default set up to simulate for 1000ns, so all the stuff I did is bunched up at the beginning of the simulation (the first 70ns). I had to zoom a little to see this view. The values reported for A, B, S, and F are the values seen at the blue bar. You can pick up (with the mouse) and move the blue bar to see the values at different points in the simulation.

This example is now finished. The operation of the circuit is validated through simulation. When the inputs are changed to different values, the circuit simulation shows the answer for the F output signal. You can verify that the function is correctly implemented by the circuit by looking at the waveform outputs. In future labs we’ll dramatically expand our use of ISE to include larger and more complex Verilog programs, letting the test fixture check the answers for you so you don’t have to stare at the waveforms, synthesizing the circuit to the Xilinx part, and many other things, but this should get you going.