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fpga
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COE758 XilinxISE9.2Tutorial1CreatingSimpleProjectg p j
StartXilinxISEsoftware,andpressOKonTipoftheDaytogettoascreenas shown aboveasshownabove
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CreatenewprojectbyselectingFile>NewProjectNew window will openNewwindowwillopen.
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Projectlocation selectthedirectoryfortheprojectsProject Name select project name Notice how directory with sameProjectName selectprojectname.NoticehowdirectorywithsameprojectnameisaddedintheProjectLocationtextfield.PressNext>
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In the Device Properties selection of the device and package is done.IntheDevicePropertiesselectionofthedeviceandpackageisdone.Family:Spartan3EDevice:XC3S500EPackage:FG320S d 5Speed:5PreferredLanguage:VHDLKeeptherestofthesettingsandpressNext> 5
Inthiswindowyoucaneitheraddnewsource,orleaveitforlaterasitisdone in this tutorialdoneinthistutorial.Press Next>severaltimesuntilfinishandpressFinish onthelastwindow.
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Whennewprojectiscreatedsourcefilescanbeadded.Rightclickonthedevice and select New SourcedeviceandselectNewSource.NewWizardwindowisopened
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SelectVHDLModuleandenterthenameofthevhdl sourcefile.Press Next>PressNext>
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Inthiswindowinputandoutputsignalsarespecified.Notice that for led and switch signals Bus checkbox is selected and size ofNoticethatforledandswitchsignalsBuscheckboxisselectedandsizeofthebusisspecified.PressNext>
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Lastwindowinthewizardshowssummaryofthesourceincludinginputsand outputs for that moduleandoutputsforthatmodule.PressFinish toaddsourcefiletoproject.
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WhensourcefileisaddedISEtoolwindowshouldlookasaboveNext step is to add actual processing source codeNextstepistoaddactualprocessingsourcecode.
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SampleVHDLprogram
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;
Librarydefinitions
entitytutorialisPort(clk :inSTD_LOGIC;
led:outSTD_LOGIC_VECTOR(7downto 0);switch:inSTD_LOGIC_VECTOR(3downto 0));
endtutorial;
Input/Output definitions
architectureBehavioraloftutorialis
signalcounter:std_logic_vector(29downto 0);
begin
process(clk)
counterdefinition
process(clk)begin
if(clk'Event andclk='1')thenif(switch(0)='1')then
counter
WhenprogramiswrittenitssyntaxcanbecheckedbyexpandingSynthesizeand double clicking on Check Syntax If errors are found double click onanddoubleclickingonCheckSyntax.Iferrorsarefound,doubleclickonerrorandcorrectthemistake.
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WhenalloftheerrorswerecorrectedandSynthesishasbeencompletedsuccessfullyanassignmentofinputsandoutputshastobedone.Sincey g p pFPGAisalreadymountedonthedevelopmentplatforminputsandoutputsarerestrictedandhavetobespecified.Onlyonesthatareusedhavetobespecifiedintheconstraintfile.Add new source same way as before but this time select ImplementationAddnewsourcesamewayasbefore,butthistimeselect ImplementationConstraintFile,andspecifynamefortheconstraintfile.Press Next> 14
UCFconstraintfileisaddedtotheVHDLfile.Select constraint file and double click on Edit Constraints (Text)SelectconstraintfileanddoubleclickonEditConstraints(Text)
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EnterconstraintsfortheLEDsandSwitchesthatarelocatedinthelowerright cornerrightcorner.ClocksignalforallofthedesignsisconnectedtopinC9onFPGA
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Whencodeisdebuggedandconstraintfileiscorrectlyenteredwecangenerate a configuration file Right click on Generate Programming File andgenerateaconfigurationfile.RightclickonGenerateProgrammingFileandselectRun.Similarlyasbefore,iferrorsoccur,doubleclickontheerrorandcorrectit.
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Ifconfigurationfileisgeneratedsuccessfullywecanloaditontotheplatformplatform.
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ExpandGenerateProgrammingFile,rightclickonConfigureDevice(iMPACT) and select Run iMPACT wizard window will open(iMPACT)andselectRun.iMPACT wizardwindowwillopen.
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SelecttopoptionofconfiguringusingJTAGandpressFINISH.
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OntheinitialiMPACT loadwizardwillprompttoselectconfigurationfilesfor all of the devices present on the JTAG chain Press Esc key for all of theforallofthedevicespresentontheJTAGchain.PressEsc keyforallofthewindows.RightclickontheleftdevicewhichrepresentsSpartan3EFPGAandselectAssignNewConfigurationFile
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ToloadprogramontheFPGAdevice,rightclickontheFPGAiconandselectProgram Programming properties window will be shownProgram.Programmingpropertieswindowwillbeshown.
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OntheProgrammingPropertiesmakesureverifyisUNCHECKED.Press OK at which point configuration file will be uploaded to FPGAPressOK atwhichpointconfigurationfilewillbeuploadedtoFPGA.
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Conclusion
Thiscompletesfirstsimpletutorialwhichincluded:
CreatingnewprojectAdding VHDL source fileAddingVHDLsourcefileWritingsimpleprograminvolvinginputsandoutputswithsimpleinternalcounterCreatingconstraintfileG i fi i filGeneratingconfigurationfileUploadingconfigurationtoFPGAdevice
SecondtutorialcoversuseofinternalBlockRAM andaChipscope Proembeddedf p plogicanalyzerwhichisrequiredforcompletionofallthelabsinthecourse.
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