Two-dimensional dynamic analysis of short-channel thin-film MOS transistors using a minicomputer

618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4, APRIL 1982

[IO] S. Asai, H. Inomata, A. Yanagisawa, E. Takeda, I. Miwa, and M. Fujihami, “Distortion correction and deflection calibration by means of laser interferometry in an electron-beam exposure system,” J. Vac. Sei. Technol., vol. 16, no. 6, pp. 1710-1714, Dec. 1974.

[ l l ] T. A. Ning, “Hot-electron emission from silicon into silicon dioxide,”Solid-State Electron., vol. 21, pp. 273-282, 1978.

[ 121 -, “Electron trapping in SiOz due to electron-6eam deposition of aluminum,” J. A p p l . Phys., vol. 49, pp, 4077-4082, 1977.

[13] T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot electrons from silicon into silicon dioxide,” J. Appl. Phys.,

[14] T. Toyabe and H. Kodera, “A theory for inter-valley transfer effect in two-valley semiconductors,” Japan. J . A p p l . Phys.,

VO~. 48, pp. 286-293, 1977.

V O ~ . 1 3 , pp. 1404-1413,1974.

[15] T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock, “A numerical model of avalance breakdown in MOSFET’s,” IEEE Trans. Elec- tron Devices, vol. ED-25, pp. 825-832, July 1978.

[16] Y. Kamigaki and K. Ito, “N-channel MOSFET with high brcak- down voltages,” t o be published.

[17] D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREM 11-A program for IC process modeling and simulation,” Stanford Electronics Lab. Tech. Rep. 5019-2, 1978.

[18] H. Sunami and M. Koyanagi, “Selective oxide coating of silicon gate (SELOCS),” Japan. J. A p p l . Phys., vol. 18, pp. 255-260, 1979.

[19] S. Ogura, P. J . Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, “Design and characteristics of the lightly doped drain- source (LDD) insulated gate field effect transistor,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1359-1367, Aug. 1980.

Two-Dimensional Dynamic Analysis of Short-Channel Thin-Film MOS Transistors Using a Minicomputer

ALFRED C . IPRI, MEMBER, IEEE, LAWRENCE B. MEDWIN, NORMAN GOLDSMITH, AND FREDERIC W. BREHM, MEMBER, IEEE

Abstract-A computer program is described for simulating twodimensional thin-film MOS transistors on a minicomputer. Data are presented showing thevariation of internal carrier density with time until a steady- state condition is reached. These data show the formation of a drain- induced back channel whose conduction properties depend on the back- channel length and carrier mobility.

For channel lengths below 2.0 Mm, the two-dimensional steady-state drain current is shown to fit the expression

for values of drain voltage below a specific saturation value ( ~ D M ) ; and

I D - lo-’ (vc - VT)’12 -- W * (VD - VDMj 4- IDM

L

for drain voltages above the saturation value.

Manuscript received October 2, 198l;revised January 14, 1982. A. C. Ipri, N. Goldsmith, and F. W. Brehm are with RCA Laboratories,

L. B. Medwin is with John Fluke Mfg. Co. Princeton, NJ 08540.

LIST OF SYMBOLS

Channel oxide capacitance (Flcm’)). Diffusion coefficient (cm2//s). Electric field (Vlcm). Distance between two lattice points along the

Distance between two lattice points perpendicular

Lattice point location along the source-drain di-

Drain current (A). Maximum value of drain current calculated from

Lattice point location perpendicular to the source-

Channel length (cm). Ionized impurity concentration ( ~ m - ~ ) . Surface charge density (cm-2). Temperature (K). Gate oxide thickness (cm).

source-drain direction (cm).

to the source-drain direction (cm).

rection.

(1 2) (A).

drain direction.

0018-9383/82/0400-0618$00.75 0 1982 IEEE

IPRI e t al.: ANALYSIS OF MOS TRANSISTORS USING A MINICOMPUTER 619

V Potential (V). V, Drain voltage (V). V’j, Drain voltage necessary to produce maximum drain

V, Gate voltage (V). VDSAT Drain voltage at which a surface depletion region

current as calculated from (12) (V).

forms (V). Threshold voltage (V). Channel width (cm). Velocity saturation factor. Boltzmann’s constant (1.38 X J X K). Electron density ( ~ m - ~ ) . Intrinsic carrier density ( ~ m - ~ ) . Number of carriers which must be generated or

recombined such that equilibrium is reached ( ~ m - ~ ) .

Electron charge (1.6 X C). Time (s). Carrier velocity (cmls). Carrier saturation velocity (cmls). Component of carrier velocity along the source-

Dielectric constant for silicon (F/cm). Carrier mobility (cm2/V * s). Low-field carrier mobility (cm2/V. s). Carrier lifetime (s).

drain direction (cmls).

I. INTRODUCTION

A TWO-DIMENSIONAL mathematical analysis of the MOS transistor was originally described in Kennedy and

Murley [ l ] , and Mock [2] . The technique, based upon Gum- mel’s analysis [3] of bipolar transistors, involved a finite- difference method of dc solution and introduced a graded lattice concept to improve accuracy and minimize computer time. Sutherland [4] has extended the original program of Mock, and has also generated overrelaxation techniques to reduce convergence time [ 51 . Finite-element techniques have been used to study MESFET devices [6] and more recently MOSFET devices [7] . All of these techniques, however, re- quire large computers and substantial computer time and, hence, cost.

Reiser [SI has described a time iterative technique for obtaining two-dimensional solutions to the current flow in MESFET devices. This technique uses a minimum amount of computer memory and, hence, is suitable for use on a minicomputer. We have combined this technique with the boundary conditions and graded lattice expressions of Mock [ 2 ] to produce a computer program for the analysis of floatingsubstrate MOS transistors. The program runs on a Data General Eclipse@ C300 minicomputer and requires 65K bytes of memory.

11. MATHEMATICAL MODEL The equations of interest are Poisson’s equation

V 2 V = X ( N - n) €Si

and the continuity equation

- = V * ( p n E t D V n ) an at

GATE (TOP ROW1 ___,

1

I

2

Fig. 1. Thin-film MOS device showing discrete lattice points in the source-drain, gate-dielectric, substrate-dielectric, and epi-silicon regions.

and

The various assumptions inherent in these equations have been discussed by Reiser [8] , An expression for carrier velocity as a function of electric field ( E ) has been derived by Huang and Ladbrooke [9]

This expression is shown by Thornber [9] to be a simple scaler representation of the more complex vector expression,

The method of solution involves the partitioning of the thin- film MOS structure into source, drain, silicon substrate, gate oxide, and dielectric substrate as shown in Fig. 1. Each of these regions is further subdivided into boxes of constant carrier concentration and electric potential. Note that the silicon substrate also contains a region where the mobility can be substantially reduced (BADEPI). The outer source and drain rows as well as the gate and back-surface potentials are futed as is the doping concentration in the source,. drain, and silicon substrate. No charges are present in the Si02 or sapphire layers and the mobility in these layers is set equal to zero. For a given set of perimeter potentials and initial zero values elsewhere, the voltage at each matrix point in the device is calculated using the finite-difference representation of (1)

V(1 -!- 1, J) - V(1, J) V(1, J ) - V(Z - 1, J) =- HX (1) H A I - 1)

HXU) - 1)

V(Z, J + 1) - V(Z, J) - V(I, J) - V(1, J - 1)

2

2

Equation (6) is a variation of the simple five-point formula [ lo ] including. the effect of the graded lattice. The graded


b ( I , J + I I

Fig. 2 . A triad of lattice points used for current-flow calculations.

lattice spacings are calculated from the expressions of Mock [ 2 ] and all four boundaries around the silicon substrate have increased lattice point densities. The potential calculations at each matrix point are repeated until the largest difference between successive calculations is less than 0.1 mV. The overrelaxation method of Sutherland [5] is used to minimize the number of iterations.

After the potential is calculated at each lattice point, a triad of points, as shown in Fig. 2, is used to move carriers according to (2). An incremental time At is chosen over which an incremental number of carriers An will flow by both drift and diffusion. Rewriting (2) as a difference equation and substi- tuting (3) and (4)

An n A t HX(Z) 'x* _ - --

where

The assumption here is that the velocity of carriers in the x direction (v,) is due to both the drift field and the quasi-Fermi levels. A velocity saturation factor (f) can also be calculated based on ( 5 )

The velocity, therefore, is assumed to saturate due to both the effect of the drift field and the concentration gradient. Bosman et al. [ 111 have shown that for silicon, both the mobility and diffusion coefficients appear to have the same dependence on electric field and, hence, this assumption appears to be justified. When vx is positive, (7) becomes

while for negative ux

The new concentrations at points ( I , J) and (I + 1, J) are calculated by adding or subtracting An to or from each point depending upon the sign of the velocity.

The charge flow An is calculated for both the x and y direc- tions and for each lattice point in the device using the triad system.

The value of At is set as large as possible to minimize computer time. Values of At which are too large, however, cause

oscillations in the charge flow and, hence, are easily detectable. Charge-flow calculations are repeated several times for all lattice points before a new set of potential values are calculated (7) , again, in order to minimize computer time. The number of repetitions is set equal to that necessary to cause no more than 0.01-mV maximum upset in any lattice point potential. Electron and hole currents are calculated at both the source and drain by summing the charge flow values in the x direction along one of the source rows and one of the drain rows. The device is assumed to have reached a steady-state condition when the difference between the source and drain current is less than 0.5 percent. After the new electron and hole concentrations have been determined, carriers may be generated or recombined according to the expression [ 121

Since the time increment is much less then the lifetime of carriers, only a small percentage of carriers is affected for each time step.

In summary, therefore, a steady-state solution to the two- dimensional current flow in MOS transistors is obtained by:

a) solving Poisson's equation (7) for a given set of boundary

b) repeatedly solving the continuity equation (8) for a spe-

c) generating or recombining carriers; d) obtaining a new set of potential values by, again, solving

Poisson's equation, e) repeating the current flow, carrier generation-recombina-

tion, and potential calculations until the drain current is approximately equal to the source current.

and initial conditions;

cific time increment;

Note that the mobility degradation with gate field and mobility degradation with depth into the film have been neglected.

111. TIME-DEPENDENT CALCULATIONS Using this program, it is possible to plot the carrier density

and potential as a function of time and position throughout the transistor. The movement of carriers, therefore, can be observed as they flow through the device and eventually reach steady-state values. Fig. 3(a) shows the electron density of a 0.5-pm channel-length MOS transistor having a source-drain doping concentration of 1 X 10'g/cm3 and a substrate concentration of 3 X lOl6/cm3. The x axis represents the distance in micrometers from source to drain, the y axis is the distance from the Si02 layer to the sapphire substrate, and the z axis is the log of the electron concentration. The initial concentrations were determined from the doping densities while the initial potentials were set equal to zero everywhere except around the perimeter. With a time step of 0.5 fs it is seen that, at 4 fs, there has been some injection of electrons from the source due to the drift field but none of these electrons has reached the drain. There has also been some small injection of electrons from the drain due to the high concentration gradient. This is due to the nonphysical nature of the junction formation. At 22 fs, some of the source electrons have reached the injected drain electrons and the overall electron concentration throughout the device is beginning to increase. Note

IPRI e t al.: ANALYSIS O F MOS TRANSISTORS USING A MINICOMPUTER 62 1

V G A I E . 6 0 T I M E . 4 0 0 0 0 E - 1 5 V D R A I N .6 0

V G A T E . 6 0 T I M E . 2 2 0 0 0 E - 1 4 V D R A I N = 6 0

(a)

V G A T E * 6 0 TIME * I 0 0 2 0 E - 1 2 V D R A I N .6 0

Fig. 3. Electron density distribution in a 0.5-pm channel-length thin- film MOS device at time: (a) 4 fs, (b) 22 fs, (c) 1 ps, and (d) 9 ps.

that the electron concentration in the vicinity of the silicon- substrate interface is still quite low due to the reduced mobility in this region. The back-surface mobility has been set equal to 4.5 cm2/V s.

At 1 ps, it is seen that an inversion region has formed in the vicinity of the source as shown in Fig. 3(c). The relatively high gate voltage has caused an inversion of electrons at the silicon surface while the floating substrate has permitted an increased electron density throughout most of the substrate. The back-channel region still shows a relatively low electron concentration. By 9 ps, a complete channel has formed along the Si-Si02 interface from source to drain and the drain current is approximately 50 percent of the source current. In addition to the Si02-Si inversion layer, a back-surface inversion layer has also formed. For devices with high back-channel mobilities, the current flow through this channel would add significantly to the overall device current. This channel current, however, is drain-field induced and hence, the current flow is drain-voltage dependent. Note that there are no fixed charges in the sapphire substrate to induce a back channel.

For this particular case, it took approximately 37 ps for the drain current t o reach 0.5 percent of the source current. The carrier transit time for this device is estimated to be about 9 ps or about twice the channel length divided by the saturation velocity. This method of MOS transistor analysis is, of course,

particularly well suited to the determination of transit time calculations when compared to other two-dimensional solutions. Since the maximum electric field in the device was in excess of 105/cm, the velocity of carriers, at least in the vicinity of the drain, was saturated. It is to be expected, therefore, that the transit time would be a simple function of the channel length over the saturation velocity.

IV. STEADY-STATE CALCULATIONS The distribution of electrons in 5.0-pm and 0.5-pm channel-

length devices are shown in Fig. 4 for a gate voltage of 2.0 V and a drain voltage of 6.0 V. Table I contains the specific device parameters used in the simulations. The 5.0-pm channel- length device shows a substantial depletion width near the drain junction and very few electrons at the silicon-sapphire interface due to the length of the channel. The 0.5-pm channel-length device, on the other hand, shows very little depletion near the drain but a substantial back channel. The overall electron concentration throughout the device is seen to be much higher for the 0.5-pm device than for the 5.Oym device. Note, however, that the total simulation times were an order of magnitude apart (524 versus 50 ps). The total simulation time is based upon equal source-drain currents and, hence, while the surface inversion-layer currents are saturated due to the velocity limitations, the depletion region has not yet had


V G A T E . 2 0 I I M E . 5 2 3 7 0 E - I O V DRAIN 6 0

(b)

Fig. 4. Electron density distribution in (a) 5.0-km channel-length device and (b) 0.5-pm channel-length device.

5 0

6000 300 I x l o i 9 3 x 1 0 ' ~ 0 5

6 0 0 0 5 0 0 I x 1 0 ' ~ I x l o t 5

time to form and carriers have not yet totally recombined in the silicon substrate. Extending the simulation time reduces the electron concentration in the vicinity of the drain but does not substantially affect the inversion-layer current.

The two-dimensional simulation program has been used to generate families of characteristic curves for various channel lengths, oxide thicknesses, and doping concentrations The simulated results have then been compared to experimentally fabricated devices. Fig. 5 shows calculated and experimental results for a 0.5-pm channel length, p+ polysilicon gate NMOS SOS transistor. The experimental results have been described previously I131 , It is seen that the initial presaturation characteristics are almost identical while the saturated characteristics indicate somewhat higher experimental currents. This has been shown to be due to avalanche multiplication effects in floating-substrate devices [ 141 , [ I S ] which are not included in this computer model.

This device in Fig. 5 was modeled with a 16 X 17 matrix of

VD ( V )

Fig. 5 . Comparison between two-dimensional calculations and experimental results for a 0.5-km channel-length device.

points and a grading of 0.1 X 0.2. Several matrix configura- tions were investigated and it was found that, in general, the size of the boxes along the silicon-silicon dioxide interface had the largest impact on accuracy. Similar results were obtained, for instance, with a 14 X 17 matrix. With a contact doping of 1 X 10'9/cm3, the convergence time to steady state was about 60 min. As seen from Fig. 3(d), the contact doping concentration was about a factor of two greater than the surface electron concentration. Using high contact doping concentrations had very little effect on drain current but substantially increased the convergence time while doping levels below the channel concentration caused a reduction in drain current in addition to reduced convergence time. The contact concentration, therefore, must be set only slightly above the maximum channel concentration to assure accuracy as well as minimum convergence time. The Appendix presents typical simulation results t o measure the accuracy of the model.

v. SIMPLE CLOSED-FORM EXPRESSIONS FOR DRAIN CURRENT

The one-dimensional expressions for drain current are usually derived from the simple integral equation [ 121

Using (6) to describe the mobility as a function of electric field parallel to the surface and assuming a constant electric field along the channel from source to drain, (1 1) becomes

where

IPRI er al.: ANALYSIS OF MOS TRANSISTORS USING A MINICOMPUTER 623

For simplicity, the gate oxide thickness is assumed to be much less than the channel depletion width and the carrier mobility dependence on gate field has been neglected.

For relatively short-channel lengths, the drain current will reach a maximum value well before the drain voltage equals the gate voltage minus the threshold voltage. The maximum drain current is found by setting the derivative of (12) equal to zero

Equation (13) reduces to

VDM = (VG - V,), large L

and

For drain voltages greater than VDM, no increase in drain current would be expected due to the saturation of the carrier velocity. The channel shortening effect, which has been sug- gested by Kennedy and Murley [l] and more recently by Klaasen and DeGroot [ 161 , has not begun as yet because the drain voltage is not greater than the gate voltage minus the threshold voltage. Fukurna and Okuto [17] have assumed that the carrier velocity is saturated in only a portion of the channel region and have shown that the expression for the length of this saturated portion is similar to that used for channel shortening, namely

Attempts to fit expressions of the form given in (14) to our two-dimensional results have been unsuccessful. We have observed, for instance, that the slope of all characteristic curves for channel lengths below 2.0 pm are linear and independent of substrate doping (except for V,). The empirical expression which seems to fit our two-dimensional results is

Equations (1 2) and (1 5) are compared to the two-dimensional results in Figs. 6,7, and 8. Fig. 6 shows the results for a 5.O-pm channel-length device and indicates that (12) reduces to the simple constant mobility expression for drain current in the nonsaturated region. In the saturation region, (15) predicts too shallow a slope, presumably because of channel shortening effects. Fig. 7 shows similar results for a 2.0-pm channel-length device. Eauation (1 2) oredicts nonsaturated drain currents

T O X = 500% i S D ' 5 0 p m N, = I x 10'5/cm3 FET 301

- O N E D I M E N S I O N A L E C A L C U L A T I O N S

I . X I

7 -

/ 6 -

/ x

I I

(15) for a 5 . 0 - ~ m channel-length device, Fig 6 . Comparison between two-dimensional calculations and (12) and

1

i

Fig. 7. Comparison between two-dimension calculations and (12) and (15) for a 2.O-~m channel-length device.

which are slightly higher than those calculated by the two- dimensional computer model. The slope in the saturated region is correctly determined from (15) while the actual magnitude of the drain current is somewhat lower than that of the two-dimensional model. The simulated characteristics for a 0.5-pm channel-length device are shown in Fig. 8. The drain current values given by (12) are again seen to be somewhat higher than the two-dimensional calculations while the oppo- site effect is true after drain current saturation.

\ , I . ~ .. ~.~ ..... The results indicate that (12) is only an approximation to


0-

T o y = 300H L s D : 0 5 p m

N~ = 3 x 1016/Cm3

F E T 3 0 0

Fig. 8. Comparison between two-dimensional calculations and (12) and (15) for a 0.5-pm channel-length device.

the initial drain current characteristics of the short-channel MOS transistor. Comparisons between (12) and (IS), and two- dimensional computations, however, have shown a maximum error of only 10 percent. Since the maximum error occurs in the transition region between (12) and (1 5 ) , the likely cause of the error is the inaccuracy of the constant electric field assumption in the derivation of ( 1 2 ) .

VI. CONCLUSIONS A computer program representing a twodimensional MOS

transistor has been outlined. The program can accurately simulate the potential and charge distribution within the device as a function of time and also calculate the steady-state current flow through the device. Using a Data General Eclipse@' C300, typical real times to obtain a steady-state current value are about 60 min. Shorter convergence times are possible when lower contact doping concentrations can be used.

Charge-density distributions have demonstrated the presence of a drain-induced back channel whose conduction properties are a function of the back-channel mobility. A simple closed- form expression for the drain current has been derived assuming a specific mobility-field dependence and constant internal electric field. The expression has been compared with the two-dimensional calculations and appears to accurately predict the presaturated drain current. Beyond drain current saturation, an empirical expression is presented for calculating the increase in drain current with an increase in drain voltage. The empirical expression appears to hold for devices with channel lengths of 2.0 pm and below.

APPENDIX MODEL ACCURACY

As mentioned in Section IV, the accuracy of the model as a function of mesh size, grading factor, number of contact rows, and contact doping concentration was measured by varying

X 16 x 15 ( 2 - 1 4 ) 0 8 x 15 1 2 - 6 1

12x 15 ( 2 - 1 0 )

A 2 4 x 15 1 2 - 2 2 ) 2 0 x 1 5 12-18)

'0 I O 2 0 3 0 4 0 5 0 6 0 VD ( V )

Fig. 9. Steady-state drain current as a function of drain voltage for various numbers of rows parallel to the source-drain junctions. Two of these rows are in the source contact and two are in the drain contact.

12 1

8

I

o 2 0 x 1 5 1 2 - 1 8 ) 2 0 x 1 5 ( 4 - 1 6 )

2 I 0

0 I O 2 0 3 0 4 0 5 0 6 0 VD I V )

Fig. 10. Steady-state drain current as a function of drain voltage for 2 and 4 rows of contacts, respectively.

these parameters and observing the dependence of these parameters on source-drain current. Values were then chosen which impacted the drain current by less than 1.0 percent. Fig. 9 shows the variation of steady-state drain current as a function of drain voltage with the number of rows parallel to the source or drain junctions as the parameter. Note that no more than 16 rows were needed to achieve the necessary accuracy. The numbers in parentheses correspond to the last source row and first drain row, respectively.

Fig. 10 again shows the steady-state drain current as a function of drain voltage where the number of contact rows has been increased from two to four. As seen from the figure, there is little dependence on the number of contact rows. Additional simulations confirmed the accuracy of the remain- ing parameters.

REFERENCES [ 11 D. P. Kennedy and P. C. Murley, IBM J. Res. Develop., vol. 17,

[2] S. Mock, Solid-state Electron., vol. 19, p. 601, 1973. p. 2, 1973.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4 , APRIL 1982 625

[3] K. Gummel, IEEE Trans. Electron Devices, vol. ED-11, p. 455,

[4] D. Sutherland, U.S. Army Electronics Res. Develop., Tech. Rep.

[ 5 ] A. D. Sutherland, IEEE Trans. Electron Devices, vol. ED-27,

[6] J . J. Barnes and R. J. Lomax, IEEE Trans. Electron Devices,

[7] J . D. Meindl, Computer Aided Engineering, of Semiconductor Integrated Circuits. Stanford, CA: Stanford Univ. Press.

[8] M . Reiser, IEEE Trans. Electron Devices, vol. ED-20, p. 35, 1973. [9] K. K. Thornber,J. Appl. Phys., vol. 51, no. 4, p. 2127, 1980.

[ 101 S. K. Godvnov and U. S. Ryabenki, Theory of Difference Schemes.

1964.

COM-75-1344-F, Sept. 1977.

p. 1297, 1980.

V O ~ . ED-24, p. 1082, 1977.

Amsterdam, The Netherlands: North-Holland, 1964.

[ 111 G. Bosman, R. J . Zijlstra, and F. Nava, Solid-State Electron., vol.

[ 121 A. S. Grove, Physics and Technology of Semiconductor Devices.

[ 131 A. C. Ipri, J . C. Sokoloski, and D. W. Flatley, IEEE Trans. Elec-

[14] D. Farrington, in Extended Abstracts Electrochem. Soc., p. 345,

[15] W. Fichtner, Solid-state Electron Devices, vol. 2, no. 2, p. 47,

[16] F. M. Kldasen and W. C. DeGroot, Solid-State Electron., vol. 23,

[17] M . Fukuma and Y. Okuto, IEEE Trans. Electron Devices, vol.

24, p. 5, 1981.

New York: Wiley, 1967.

tron Devices, vol. ED-27, no. 7, p. 1275, 1980.

1974.

1978.

p. 237, 1980.

ED-27, no. 11, p. 2109, 1980.

Two-Dimensional Nature of Diffused Layers and Certain Limitations in Scaling-Down

Coplanar Structure

HIROSHI IWAI, MEMBER, IEEE, KENJI TANIGUCHI, MASAMI KONAKA, SATOSHI MAEDA, AND YOSHIO NISHI

Abgtracf-Limitation of the coplanar technology to geometry minia- turization has been investigated.

Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.

A INTRODUCTION

LTHOUGH a coplanar structure has widely been used in MOS LSI's, several increasing difficulties have been de-

lineated with reduction of device feature size. The difficulties which one has first to point out are those appearing in fabrication of small-sized devices. They are the bird's beak, the white ribbon, and the defects along coplanar field edge as illustrated in Fig. 1 as 0-0, [ I ] - [4] .

Manuscript received October 20, 1981;revised December 28, 1981. H. Iwai, S. Maeda, and Y. Nishi are with the Semiconductor Device

Engineering Laboratory, Toshiba Corporation, Kawasaki, 2 10 Japan. K. Taniguchi and M. Konaka are with Toshiba Research and Devel-

opment %enter, Toshiba Corporation, Kawasaki, 210 Japan.

@ D E F E C 1

a WHITE R BBON , 0 B I RD'S BEAK

: I // @ N'- P SUB CAPACITANCE

Q ' N A R R O W CHANNEL i ,' EFFECT '@ P - N ,'UNCTION BREAKDOWN

, @ FIELD PARASITIC M O S

Fig. 1. Various problems arising from the scaled-down coplanar structure.

In addition to the above mentioned fabrication difficulties, the scaled-down coplanar structure has serious problems in device characteristics. These problems are associated with boron as parasitic channel-stop implantation impurity. They are a) a relative increase in sidewall capacitance with respect to flat-bed capacitance of the n+ diffused line, b) the narrow-

0018-9383/82/0400-0625$00.75 @ 1982 IEEE

Documents

Two-dimensional dynamic analysis of short-channel thin-film MOS transistors using a minicomputer