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1
Two-step Beat Frequency Quantizer Based ADC with Adaptive Reference Control for
Low Swing Bio-potential Signals
Somnath Kundu1, Bongjin Kim1,2, Chris H. Kim1
1Dept. of ECE, University of Minnesota, Minneapolis, MN2Rambus Inc., Sunnyvale, CA
2
Outline
• Motivation
• Conventional Linear VCO based ADC
• Beat Frequency ADC
• Proposed Two-step Beat Frequency ADC
• 65nm Circuit Implementation Details
• Measurement Results
• Conclusion
3
Typical Bio-Signal Sensing Block
CH #1CH #2
CH #M
REFLNA VGA
CH #M-1MUX ADC
MUXCTRL
Dout
• Consists of amplifiers/filters, A/D converter (ADC), etc.
• Multi-channel amplifiers with active or passive filters
• ADC converts a time-multiplexed analog input to N-bit
digital outputs ���� processed by on-chip or off-chip DSP
4
State-of-the-art Bio-potential Acquisition ASICs
• ADC area is small
• A significant portion of the chip area is occupied by
frontend amplifiers/filters
J. Yoo, ISSCC 2012N. Helleputte, ISSCC 2012
ADCADC
5
Area and Power Break-up in Bio-potential Acquisition ASICs
• ADC designs typically don’t account for the design
complexity, area and power overhead of the AFE circuits
• Motivation of this work: Direct conversion of low-swing
(<10mV) signal to simplify or even eliminate AFE circuits
6
AFE Overhead Reduction by Beat Frequency ADC
• Beat frequency ADC can simplify or eliminate signal pre-
conditioning amplifiers (LNA/VGA)
7
Conventional VCO Based Linear ADC
Ou
tpu
t C
od
e
fSIG
ΔqMax. Δq
constant
• Linear signal detection by VCO
• Poor resolution for low swing signals
8
Beat Frequency Detection
• Frequency sensing resolution inversely proportional to signal swing
1% frequency change in CK1
changes the output count by
50%
[ref] T. Kim, VLSI 2007, JSSC 2008
9
Single Step Beat Frequency ADC
Fixed freq=fREF
DFFSIG
CKREF
DOUT
=(fREF/Δf)DFF
CKS
DOUT
Low Δq High Δq
fSIG
Δf=fREF - fSIG
Counter
fSIGfREF
DOUT∞
Δf
1
Ou
tpu
t C
od
e
Δf
fSIG
Max. Δq
increases for
higher Δf
Qu
an
t. E
rro
r (Δ
q)
• High resolution beat frequency detection
• Resolution degrades as frequency difference increases
[ref] B. Kim, CICC 2013, CICC 2014
10
Two-Step Beat Frequency ADC
MU
X
fSIG
fREF1
Low Δq
fREF2
Ou
tpu
t Co
de
fSIG
Low max. Δq
due to lower Δf2
Qu
an
t. E
rro
r (Δ
q)
• Two step detection scheme to change
the reference depending on signal
11
65nm Circuit Implementation
CKREF1
Sel. Logic 4:1
Prog.Divider
CKSIGP
BF Quantizer #0
BF Quantizer #2
Short pulse generator
Counter
DFF
DFF
RST READ Async. to Sync.
Converter
CKS
10b
Sel. Logic 4:1
BF Quantizer #1
BF Quantizer #3
High freq. VCO
CKSIGN
CKS CKS
CKS CKS
Ref. freq. generation
CKREF2P
CKREF2N
CKSIG
CKREF
SIGP
SIGN
REF
DOUT1P DOUT2P
DOUT1N DOUT2N
Unity-gain input buffer
CKBF
CNTBF
DOUT
CK0
CK1
CK2
CK3
1st step 2nd step
VCM
VCM
BF Quantizer
• Multiple references are generated by diving a high speed
reference oscillator
• Same input clock (CKSIGP, CKSIGN) applied in both steps
12
Triple Sampling Synchronization
• BF quantizer output data is
sampled at a fixed rate without
meta-stability
13
Measured BF Count and Reconstructed Signal
• Input: 300Hz, 10mVpp differential sinusoidal wave
14
Measured FFT and SNDR vs. Input Amplitude
Frequency (Hz)10
110
210
3 104
Signal BW=1.2kHz
SFDR=57dB
0
-20
-40
-60
-80
-100
-120
Po
wer
(dB
FS
)
One-step
Two-step
• SNDR @ 10mV=44.5dB for two-step, 38.9dB for single step
• Ideal linear ADC has better SNDR for input amplitude >-
40dBFS
15
65nm Die Photo
• Core chip area 0.096mm2
16
Performance Comparison
17
Conclusion
• Two-step VCO based beat frequency detection
scheme is designed using 65nm CMOS for
direct A-to-D conversion
• A triple sampling synchronization technique is
implemented to sample ADC output at a fixed
sampling rate
• 44.5dB SNDR (i.e. 7.1 ENOB) is achieved for a
10mVpp differential input signal