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TypeC (USB3.1/3.0)
Introduction and Test solution
Leo Cao
3 MAY 2018
• Type-C Overview
• USB 3.1 Electrical Specification & CTS
• USB 3.1 Tx Test Challenges & Solutions
• USB 3.1 Rx Test Challenges & Solutions
• Q & A
Agenda
Type-C Overview
Increasing Serial Data Bandwidth
• USB 2.0, 480 Mb/s (2000)
◦ Shift from slower, wide, parallel buses to narrow, high speed
serial bus
◦ 40x faster data rate, support for new connectors & charging
• USB 3.0, 5 Gb/s (2008)
◦ ~10x faster data rate over 3 meter cable
◦ Faster edges, ‘closed eye’ architecture
• USB 3.1, 5/10 Gb/s (2013)
◦ 2x faster data rate over 1 meter cable
◦ ‘Scaled’ SuperSpeed implementation
Overview: Cable AssemblyStd A Connector (host) mB Connector (device)
USB3 USB2
Std B Connector (device)
Cable
Cross-section
USB3
USB3
USB2
USB2
USB3
3 MAY 2018
NEW Type C connector
Used in very thin platforms as its total system
height for the mounted receptacle is under 3
mm
Enhances ease of use by being plug-able in
either upside-up or upside-down directions
Enhances ease of use by being plug-able in
either direction between host and devices
New Configuration Control signal (low speed)
for handshaking
Two high speed diff pairs for mux’ing data
Connector Transition
Plug 1 Plug 2 Version Length
A C USB 2.0 ≤ 4m
A C USB 3.1 Gen2 ≤ 1m
C B USB 2.0 ≤ 4m
C B USB 3.1 Gen2 ≤ 1m
C Micro-B USB 2.0 ≤ 2m
C Micro-B USB 3.1 Gen2 ≤ 1m
Plug 1 Plug 2 Version Length
C Micro-B USB 2.0 ≤ 0.15 m
C A USB 3.1 Gen1 ≤ 0.15 m
Legacy Cables
Defined Adapters
Host (Type-C)
Cable
(C to Micro-B)
Device
(Micro-B)
Type-C Industry Pick Up
Source: USBIF
3 MAY 2018
What Does Type-C Mean to You?
Source: USB-IF
Power
DeliveryMore Power with USB Power Delivery (100 W)
Type-C More Flexibility with new reversible USB Type-C connector
USB IF More Speed with USB 3.1 (10 Gbit/s)
Alternate
ModeMore Protocols (Display Port, Thunderbolt, HDMI, etc.)
3 MAY 2018
Type-C Comparison (USB-C)
• Rounded, reversible, flip-able
• ~25% less width vs.µB
• Signaling
◦ Two SS differential pairs
◦ Vbus power
◦ Configuration Channel (CC)
◦ USB 2.0 differential pair
◦ Sideband Use (SBU)
◦ Plug power (VCONN)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
GND TX1+ TX1- VBUS CC D+ D- SBU1 VBUS RX2- RX2+ GND
GND RX1+ RX1- VBUS SBU2 VCONN VBUS TX2- TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
Micro B Plug
Type-C Plug
3 MAY 2018
Cable
Ground
Tx High-speed data path
(USB, or TBT/DP Alt-Mode)
Cable
bus
Power
Plug configuration detection
• One becomes VCONN, cable power
• CC is used for USB-PD communication
USB 2.0Rx High-speed data path
(USB, or TBT/DP Alt-Mode)
Sideband Use
(not used for USB, only
Alt-modes)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND
GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
Type-C Pin Definitions
3 MAY 2018
Why is Configuration Channel (CC) Signal so Important?• Used to determine downstream and upstream positions (role swapping)
• Discover and configure optional Alternate and Accessory modes
• Resolve cable orientation and twist connections to establish USB data bus
routing
Type-C Test Conditions
• USB 2.0 Electrical
◦ Signal Quality
◦ Packet Parameter, Chirp, Receiver Sensitivity…etc.
• USB 3.1 Gen1 (5Gb) & Gen2 (10Gb)
◦ Transmitter jitter/eye tests with new reference receiver models
◦ Receiver Jitter Tolerance with expanded templates
• USB Power Delivery
◦ eMark, Provider, Consumer…etc.
• Alternate Mode
◦ DP over Type-C
◦ MHL, Thunderbolt…etc.
USB 3.1 Comparison of Gen1 vs. Gen2
Copyright © 2015,Tektronix.
USB 3.1 Gen1 Gen2
Data Rate 5 Gb/s 10 Gb/s
Encoding 8b/10b 128b/132b
Target Channel 3m/2m + Host/Device channels (-17dB, 2.5 GHz) 1m + board ref channels (-23dB, 5 GHz)
LTSSM LFPS, TSEQ, TS1, TS2 LFPSPlus, SCD, TSEQ, TS1, TS2,
Reference Tx EQ De-emphasis 3-tap (Preshoot/De-emphasis)
Reference Rx EQ CTLE CTLE + 1-tap DFE
JTF Bandwidth 4.9 MHz 7.5 MHz
Eye Height (TP1) 100 mV 70 mV
TJ@BER 132 ps (0.66 UI) 67.1 ps (0.671 UI)
Backwards Compatibility Y Y
Connector Std. A, Micro, Type-C Std. A, Micro, Type-C
3 MAY 2018
Challenges in validating Type-C designs• Channel considerations
◦ Need to account for > 20 dB channel loss
◦ >10 Gb requires more complicated (EQ/repeaters) signal conditioning
• New Challenges
◦ 4” Long Host Channels @ 10 Gbps
◦ Closed Eye at Rx
◦ Equalization
▪ 3 tap EQ at Tx
▪ Continuous Time Linear Equalizer (CTLE) & Decision Feedback equalization (DFE) at Rx
USB 3.1 Transmitter Measurement OverviewUSB Type-C Gen1Measurements Sigtest v.3.2.11.2 DPOJET Compliance Pattern
Jitter budget(RJ,DJ and TJ) Yes Yes CP0, CP1
Eye diagram Yes Yes CP0
Width@BER – 10E-12 Yes Yes CP0
SSC deviation No Yes CP1
SSC modulation rate No Yes CP1
Differential pk-pk voltage No Yes CP0
LFPS Yes Yes NA
USB Type-C Gen2Measurements Sigtest v.4.0.23.1 DPOJET Compliance Pattern
Jitter budget(RJ,DJ and TJ) Yes Yes CP9, CP10
Eye diagram Yes Yes CP9
Width@BER – 10 E-6 Yes Yes CP9
Height@BER – 10E-6 No Yes CP9
SSC deviation Yes Yes CP10
SSC modulation rate Yes Yes CP10
Differential pk-pk voltage No Yes CP9
Tx Equalization (Preshoot & De-emphasis) Yes Yes CP13, 14,15
LFPS Yes Yes NA
3 MAY 2018
End-to-End PHY Validation
TP0 – Near End TP1 – Far EndMeasurements are specified at TP1
3 MAY 2018
Compliance Test Pattern
3 MAY 2018
Typical Steps Involved to Run Tx Tests
1. Connect DUT to scope via test fixture
2. Transmit CP10 (clock) & measure 2x106
consecutive UI
◦ This step used to measure RJ
3. Repeat with CP9 (scrambled data pattern)
◦ Will combine RJ (step 2) with DJ to extrapolate TJ (step 5)
4. Post-process the waveforms with the compliance channel, the reference CTLE, & jitter transfer function
◦ Channels are S-Parameter-based and are embedded into
captured waveform
5. Accumulate jitter to 10-6 BER
Spec Min Max Units
Eye Height 70 1200 mV
Dj @ 10-6 BER 0.530 UI
Rj @ 10-6 BER 0.094 UI
Tj @ 10-6 BER 0.671 UI
New Channel Budget – USB 3.1 Gen2 Type-C
Target 23 dB @ 5 GHz loss budget (die-to-die)
Equal channel allocation for host/device
Tx EQ settings (normative)
◦ 2.2 dB Preshoot and -3.1 dB De-emphasis
◦ Requires additional compliance patterns (CP13, 14 &15) for Tx testing
Host or device loss that exceeds 8.5 dB may require repeater
◦ Need end-to-end training -> link aware repeaters
8.5 dB 6 dB 8.5 dB
3 MAY 2018
Reference Receiver Equalizer – Gen1
Reference Receiver Equalizer – Gen2
Far End (TP1) Eye closed
Need to open eye with EQ
Adaptation only for Rx
◦ No back channel Tx negotiation
Iterate through multiple CTLE gain
settings + 1-tap DFE
USB Tx Testing Challenges
Tx Testing Workflow
Type-C Testing
Setup
Acquire
Analyze
Report
Configure Scope
Automate DUT to generate patterns
Capture and save waveforms
Load acquired waveformRun Measurements
Display measured values
Create reports in user defined format(.csv, .pdf, .mht)
X
X
X
X
X
X
X
Configure DUT
DUT - ON TIME
DUT - OFF
DUT is available for other testing
3 MAY 2018
How do I Collaborate with Global Teams?T
hese
sites c
aptu
re/a
naly
ze
wavefo
rms
These
sites c
an a
lso a
naly
ze
wavefo
rms a
cqu
ire
d e
lsew
here TYPICAL USE
CASE
Design and Test teams are
located in different regions
Customers want Tektronix
to look into root cause
Comparison of previous
data with latest one
Japan Japan
India India
China China
SOLUTION
• Save & Recall waveforms
• Analyze recalled waveforms in offline mode
3 MAY 2018
How do I Debug Compliance Failures?3 EASY STEPS:
• Manually setup standard specific measurement and
analyze
• Vary measurement parameters and monitor behavior
• Add different plots to get deep insight into DUT
characteristics
SOLUTION:
• Standard Specific Modules and measurement analysis
on single acquisition
• Comprehensive Measurements for
• Jitter Analysis, Noise & Margin Analysis
• Eye Diagram with BER Contour
• Multiple plots like Bath Tub Curve etc.
• Amplitude, Timing and Frequency Analysis
3 MAY 2018
How do I Analyze Channel Loss?
SOLUTION:
• Enables virtual probing through test points
• Remove the effects of the cables, probes and fixtures
• Open a closed eye
• Model each block through different techniques and
visualize each test point in the block using plots
PROBLEMS WITH CHANNEL BEHAVIOR
• Inability to probe at required location in signal path
• Reflections, cross-coupling, fixture losses, cable
effects
• Closed eye analysis
• Standards mandate eye analysis at various test points
3 MAY 2018
USB Tx Solutions
USB DPOJET & SDLA Analysis ToolsDEVICE CHARACTERIZATION, MARGIN ANALYSIS AND FAILURE ANALYSIS
3 MAY 2018
USB Automated Compliance ToolsUSER DEFINED LIMITS, OFFLINE ANALYSIS, DPOJET & SIG-TEST SUPPORT
Test selection panel showing
Gen1, Gen2 and LFPS tests
User editable parameters
Offline Analysis
Measurements using
both Sig-Test & DPOJET
3 MAY 2018
Example Host Test Setup
USB-IF Fixtures - TxUSB3ET FOR TYPEA/MICROB @ 5GBPS
3 MAY 2018
USB-IF Fixtures – TxUSB31AET FOR TYPEA/MICROB @10G/5GBPS
3 MAY 2018
USB-IF Fixtures – TxUSB31CET
3 MAY 2018
Challenges of Tx Testing for Type-C DevicesFROM COMPLEXITY TO CONFIDENCE
•Only with Tektronix can you get more insight into measurements failures with DPOJET & SDLA debugging tools
Beyond Compliance
•Only with Tektronix’ can you finish testing both USB Gen1 and Gen 2 test suites in less than 20 mins.
Reduce Validation time
•Only with Tektronix can you analyze waveforms in offline mode and use that to collaborate with global teams
Global Collaboration
SMA cables to scope Host
1m USB
Type-C
cable
Ping.LFPS from
signal generator
(pattern toggle)
3 MAY 2018
USB Rx Test Challenges
Basics of Rx TestingAt the simplest level, receiver
testing is composed of:
1. Send impaired signal to the
receiver under test
2. The receiver decides
whether the incoming bits
are a one or a zero
3. The chip loops back the bit
stream to the transmitter
4. The transmitter sends out
exactly the bits it received
5. An error counter compares
the bits to the expected
signal and looks for
mistakes (errors)
Pattern
Generator with
Stress
12
3
4
5Error Counter
3 MAY 2018
USB3.1 Rx Test Challenges
• Receiver testing now requires
◦ Jitter tolerance
◦ LTSSM are different for Gen 1 and Gen 2 and need to comply with Spec
• New Challenges
◦ 4” Long Host Channels @ 10 Gbps
◦ Closed Eye at Rx
◦ Equalization
▪ 3 tap EQ at Tx
▪ Continuous Time Linear Equalizer (CTLE) &
Decision Feedback equalization (DFE) at Rx
◦ New 128b/132b encoding requires SKP
filtering
3 MAY 2018
USB 3.1 Rx Testing Overview
A jitter tolerance test is required for certification, though debug and characterization capabilities are needed to ensure that receivers will work in real world conditions
◦ Send specific test data patterns to the device-under-test (DUT) through a known channel
(fixtures and cables)
◦ Add a specific “recipe” of stresses and de-emphasis
◦ Command the DUT into loopback mode (far-end retimed)
◦ Return “echoed” data to a BERT
◦ Detected errors are inferred to be a result of bad DUT receiver decisions
3 MAY 2018
Generic RX Test Configuration
BERTScope (BSX) USB 3.1 RX Test Configuration
USB Switchcreates the low-frequency
periodic signaling (LFPS)
required to initiate
Loopback-mode
CR125A
Clock Recovery
BSX125C
BERTScope
BSX series models and applicationsLegacy Standards
USB 3.1, SAS3,
PCIe3
Gen4 Standards
PCIe Gen4, SAS4,
Thunderbolt
25-28G and future
standards up to 32
Gb/s
BSX125 BERTScope
up to 12.5 Gb/s
BSX240 BERTScope
up to 24 Gb/s
BSX320 BERTScope
up to 32 Gb/s
Recommended
Tek Scope for RX
stress calibration
70K DX series 70K DX series or
70K SX series
70K SX series
3 MAY 2018
Getting a DUT Into Loopback Mode
• Basic Overview
◦ DUT starts in Power-off, or test fixture un-
plugged
◦ At device power-on or hot plug, BERT sends
LFPS signaling
◦ Device responds by going from LFPS.Polling
to training sequence
Handshaking sequence between DUT and BERT: TSEQ
> TS1 > TS2
TS2 sequence from BERT sets loopback bit to force
DUT into loopback for Rx testing
3 MAY 2018
Initiating Loopback – Power On Device
POLLING.LFPS
TSEQ TS1 TS2 CP9_Tek
• Error Detector sees a “1” from the first bit
of the LFPS signal and registers an error
• Error sends trigger out to switch
• On trigger, the switch swaps to LFPS
Generator, sending 400 LFPS bursts
Trigger In from
BERT
Signal in from
BERT
D-D+
+ -
LFPS
Generator
3 MAY 2018
Initiating Loopback – DUT Equalization Training
POLLING.RXEQ
TSEQ TS1 TS2 CP9_Tek
Trigger In from
BERT
Signal in from
BERT
D-D+
+ -
LFPS
Generator
• On completion of LFPS, the SW returns the
switch to the D+/D- inputs, passing the TSEQ
pattern to DUT for training
• During LFPS stage BERT is loading TSEQ into
Pattern Generator and setting ED to see TSEQ
3 MAY 2018
Initiating Loopback – TS1
POLLING.ACTIVE
TSEQ TS1 TS2 CP9_Tek
Trigger In from
BERT
Signal in from
BERT
D-D+
+ -
LFPS
Generator
• Switch continues to route signal from
BERT to DUT
3 MAY 2018
Initiating Loopback – TS2
POLLING.CONFIGURATION
TSEQ TS1 TS2 CP9_Tek
Trigger In from
BERT
Signal in from
BERT
D-D+
+ -
LFPS
Generator
• Switch continues to route signal from
BERT to DUT
• After TS1 repeats, PG sends TS2 pattern
with loopback bit set
3 MAY 2018
Initiating Loopback – TS2
LOOPBACK
TSEQ TS1 TS2 CP9_Tek
Trigger In from
BERT
Signal in from
BERT
D-D+
+ -
LFPS
Generator
• Switch continues to route signal from
BERT to DUT
• PG sends CP9 to DUT and sets ED to
expect it. This pattern is used to verify
successful loopback.
3 MAY 2018
USB-IF Fixtures - RxUSB3ET FOR TYPEA/MICROB @ 5GBPS LONG CHANNEL
3 MAY 2018
USB-IF Fixtures – RxUSB31AET FOR TYPEA/MICROB @10GBPS LONG CHANNEL
Rx Calibration Setup Rx Test Setup
3 MAY 2018
USB-IF Fixtures – RxUSB31CET FOR TYPEC LONG/SHORT CHANNEL
10Gbps Long Channel
5Gbps Long Channel
10G/5Gbps Short Channel
3 MAY 2018
Rx Tolerance Test Overview (JTOL)
• Nine Test Points (USB3.1 Gen2)
• SSC Clocking is enabled
• BER Test is performed at 10-10
• Preshoot/De-emphasis enabled
• Stress verified by TJ/Eye Height
• Each SJ term in the table is tested one at a time after the device is in loopback mode
Frequency SJ RJ
500kHz 476ps 1.308ps RMS
1MHz 203ps 1.308ps RMS
2MHz 87ps 1.308ps RMS
4MHz 37ps 1.308ps RMS
7.5MHz 17ps 1.308ps RMS
15MHz 17ps 1.308ps RMS
30MHz 17ps 1.308ps RMS
50MHz 17ps 1.308ps RMS
100MHz 17ps 1.308ps RMS
3 MAY 2018
Challenges of Rx Testing for Type-C DevicesFROM COMPLEXITY TO CONFIDENCE
• Only with Tektronix can you track down handshaking and link training issues when things go wrong
Protocol Awareness
• Only with Tektronix can you have sophisticated error analysis tools such as Bit Error Location and Forward Error Correction
Debug
• Only with Tektronix can you root-cause factors leading to bit-error or link training problems
Beyond Compliance
3 MAY 2018
Beyond Compliance: BERTScope Analysis Tools
• Besides being a BERT, the BERTScope’s “Scope” functionality brings
benefits that complement those of the Tektronix scopes
• Analysis tools are full featured and easy to use
Eye diagram for quick
diagnosis of
synchronization and BER
failure issues
Debug challenging signal
integrity problems
Error Location Analysis
Pattern Capture
Jitter Map
BER Contour
JitterJitter
Error
Correlation
Error
Correlation
BERBER
Jitter
Decomposition
Jitter
Decomposition
Jitter
Tolerance
Jitter
Tolerance
PLUS…PLUS…
Bertscope的调试分析功能BERTSCOPE ANALYSIS TOOLS
User Challenge:
• Need more than a bit-error rate (BER) number
• Need to understand factors leading to bit error
problems in order to debug issues
BSX Series BERTScope provides:
• “Scope” functionality that complement those of the
Tektronix scopes
• Full-featured and easy to use analysis tools
• Eye diagram for quick diagnosis of synchronization
and BER failure issues
• Debug challenging signal integrity problems
◦ Error Location Analysis
◦ Pattern Capture
◦ Jitter Map
◦ BER Contour
◦ FEC Emulation
Only with Tek can you obtain Rx failure
insight using BERT error location analysis
BER Contour Eye Diagram
Error Location Correlation FEC Emulation
Jitter Map BER
Jitter Jitter Tolerance
3 MAY 2018
物理层调试分析功能
ERROR BIT LOCATION
EXPECTED BIT
200,457 0
1,247,356 1
1,447,890 03,885,245 04,001,876 18,233,191 0
…• BERTScope记录每个误码的确切位置:
0 00
0
1
1
1
00 1 1
10
BER = 3.9 x 10-9
1
• 错误位置错误码型独特的调试信息• FEC仿真提供了前向纠错前和前向纠错后的BER
只有泰克提供了错误位置分析功能
3 MAY 2018
Bertscope的调试分析功能Bertscope对于抖动和眼图的分析能力：能够对高速信号准确的进行抖动和眼图分析。
1.Bertscope能够精确的测量信号输出的总体抖动，我们一般上称为Tj(Total jitter),Tj一般是用来衡量芯片的信号输出的最重要的指标。由于Tj定义为10^12
次方的比特下的抖动值，只有误码仪能够准确测量连续的10^12比特下的抖动，而传统的示波器由于存储深度的限制，都是测量10^5-10^6下的抖动，然后通过各种算法去推算10^2次方下的抖动的，并不是真正测试出来的.
2.Bertscope能够对信号的抖动成分进行分离，可以分离出信号里面的Sj,Rj,DDj等等，供调试者能够知道信号的抖动成分来至于哪一方面。并且能够根据抖动的特性描绘出抖动浴盆曲线。
3.Bertscope能够分析出抖动频谱，供调试者分析抖动来自于那个频率，以快速的查找干扰源。
Bertscope的调试分析功能
4.对于眼图测试Bertscope能够快速的描绘出信号的眼图，由于Bertscope采用两个非常精确的采样头，所以能够实现精确快速的眼图测试。其眼图测试结果与实时示波器和采样示波器有非常好的一致性。速度比它们要快5-10倍。当然眼图测试也支持标准的通信模版和用户自定义模版。
5.由于Bertscope的采样头可以在水平和垂直方向任意精确可调，所以Bertscope能够描绘误码率等高线图，可以从三维的角度去看信号由于样本数量的增加劣化的程度，而示波器一般只能从水平方向去看信号的劣化程度
Bertscope的调试分析功能
1.Bertscope Pattern sensitivity 能够定位PRBS里面每一个出现误码的比特，并告知其除于PRBS中的哪一位，比如PRBS7的信号出现误码的时候，可以定位出其是第22位还是第23位出现误码，并统计出每一个位出现误码的数量。
2.Bertscope的Strip Chart分析能够追踪长时间老化测试的时候每个误码出现的准确时间，并统计误码在不同时间里出现的数量。比如24小时不间断的高低温老化测试，误码仪能够统计出误码是出现在那个时间点，误码是间隔出现还是连续出现，都能够准确统计追踪出来。可以观察误码随温度的变化而变化的情况，判断温度高低对系统稳定性的影响。
Bertscope的调试分析功能3. Bertscope Error free interval 的误码分析功能能够分
析误码出现的时间及其规律（即是误码间隔出现的
频率），根据时间规律则可以推算出引起误码的可
能原因，比如电源纹波或者噪声引起芯片工作不稳
定引起的误码，这这个误码间隔的频率必然与电源
的变化频率相关。如果是其他高速信号的串扰引起
的，必然与串扰源有关。
4.FEC emulation的功能能够模拟芯片的输出经过长链
路后，通过接受端芯片FEC纠正后能够修正的误码率，
客户在做链路的调试的时候不需要搭建这个发送和
接受的整个链路环境，只需要将链路的发送连接到
误码仪的输入端即可，可以节省大量的时间快速的
验证在进行发送端参数修改后的效果，经过用户的
多次验证，其结果与真正的芯片接受后进行FEC修正
后的效果在误码率的量级上非常一致。
客户实际应用案例-误码分析功能
• 芯片自适应响应时间测试
• 芯片FEC模拟
• 长时间误码率老化测试
Clock output
Pattern Generator
Clock input
Error Detecto
r
Be
rt
Clock Recovery
Data
input
Data
output
Clock
output
DUT
RX
TX
0 1
0 0
1 0
1 1
00
1 0
0 1
0 1
1 0
芯片的自适应时间测试
CDR
->Decision Circuit
FFE/D
FE
Reset连接拓扑图
测试目标参数和方法
• 芯片的接收端的CDR,FFE/DFE的自适应时间：涉及到芯片的时钟恢复的锁定时间，FFE、DFE的自动调
节时间，一般为几百微妙到几百毫秒补不等。
• 1.先按照第一页的连接图连接好，将被测芯片设置为环回模式，设置Bertscope的PG输出为被测速率，码
型设置为PRBS31，确认泰克CDR模块可以正确锁定，Error Detector能够正确的Sync码型，并且测试没
有误码。记得要将ED端设置为Auto-resync。
• 2.点击View里面的Error analysis，选择Error free interval。点击Error free interval界面，设置,Hist的end
为500000(bit)，这个参数需要根据芯片的特性灵活调节，如果芯片的自适应时间较长，则可以适当增加，
以保证整个自适应过程的误码变化情况都能够在所选的时间范围之内。这个界面的横轴是bit，可以根据信
号的速率转化为绝对的时间，纵轴是误码个数。我们可以根据误码的变化从而计算出自适应的收敛时间。
设置好以后点击auto center。然后点击Run。
测试目标参数和方法
• 3.设置好误码仪后，用命令将芯片的RX部分进行一次hot reset，这时候芯片会进行一次时钟恢复的同步，
重新调节DFE，FFE，在Bertscope的Error Free interval里面就可以看到出现大量误码然后在慢慢减少到没
有误码的过程。在300000bit左右就不再出现误码，我们认为这个时候自适应过程就已经完成。为了保证测
试结果的重复性和一致性，建议将这个hot reset的过程做十次，Error free interval会自动将这十次的结果进
行叠加。从测试的结果看，芯片的自适应时间约为300000X(1/20.62G)约为15us左右。
误码分析功能应用：
使用Error free interval的功能来测试芯片的自适应时间
误码分析功能应用-FEC emulation
RX
TX
Tx setting:
25.78125Gbps
PRBS31 pattern
1V differential output
Rx setting:
Auto pattern and resync
CR286
Data&Recovered CLK
Chip
误码分析功能应用：
高低温老化测试-strip chart
USB Solutions Portfolio
BERTScope
USB Solutions Portfolio
Technology
TX
USB @ 20G
70K Series Scopes
USB TX Analysis (DPOJET)
Automated
USBSSP
RXAutomated
USB RX
USB 3.1
Gen 1 - 5 Gbps
Gen 2 - 10 Gbps
5K/7K Series Scopes
SR – USB
Protocol Decode
USB - PD
USB 2
TX & RX
3 MAY 2018
USB-IF Logo Certification
• USB 3.1 Gen2 Tx & Rx – USBIF Approved Gold Test Suite
• USB 3.1 Gen1 Tx & Rx – USBIF Approved Gold Test Suite
• USB 2.0 – USBIF Approved Gold Test Suite
• USB PD – USBIF Approved Gold Test Suite
TEKTRONIX APPROVED GOLD TEST SUITES AT USB-IF WORKSHOPS
3 MAY 2018
Information & Resources
• http://www.tek.com/usb
• Application Notes
• Methods of Implementation
• Serial Configurator
• Webinar
3 MAY 2018
Q and A
