UCS2114 USB Dual-Port Power Switch and Current …ww1.microchip.com/downloads/en/DeviceDoc/20005743A.pdf• Configurable Per-Port BC1.2 VBUS Discharge Function • Wide Operating Temperature

UCS2114USB Dual-Port Power Switch and Current Monitor

Features

• Dual-Port Power Switches:

- 2.9V to 5.5V source voltage range

- 3.0A continuous current per VBUS port with 18 m On resistance per switch

- Independent port power switch enable pins

- DUAL fault ALERT# active drain output pins

- Constant Current or Trip mode current limiting behaviors

- Undervoltage and overvoltage lockout

- Back-drive, back-voltage protection

- Auto-recovery fault handling with low test current

- BOOST# logic output to increase DC-DC converter output under large load conditions

• SMBus 2.0/I2C Mode Features:

- Eight programmable current limits assignable to each power switch

- Other SMBus addresses available upon request

- Block read and block write

• Self-Contained Current Monitoring (No External Sense Resistor Required)

• Fully Programmable Per-Port Charge Rationing and Behaviors

• Configurable Per-Port BC1.2 VBUS Discharge Function

• Wide Operating Temperature Range:

- –40°C to +105°C

Description

The UCS2114 is a dual USB port power switchconfiguration that can provide 3.0A continuous current(3.4A maximum) per VBUS port with precisionovercurrent limiting (OCL), port power switch enables,auto-recovery fault handling, undervoltage andovervoltage lockout, back-drive and back-voltageprotection, and thermal protection.

The UCS2114 is well-suited for both stand-alone andapplications having SMBus/I2C communications.

For applications with SMBus, the UCS2114 providesper-port current monitoring and eight programmablecurrent limits per switch, ranging from 0.53A to 3.0Acontinuous current (3.4A maximum). Per-port chargerationing is also provided, ranging from 3.8 mAh to246.3 Ah.

In Stand-Alone mode, the UCS2114 provides eightcurrent limits for both switches, ranging from0.53A + 0.53A to 3A + 3A total continuous current(see Table 1-1).

Both power switches include an independent VBUSdischarge function and Constant Current mode limitingfor BC1.2 applications.

The UCS2114 is available in a 3x3 mm 20-pin VQFNpackage.

Package TypeA

LE

RT

#2

2

COMM_ILIM

VBUS1

PWR_EN1 PWR_EN2

GND

VS

BOOST#

VS

VD

D

VS

VBUS2

ALE

RT

#1

SM

CL

K

SM

DA

TA

GN

D

GND

20

1

19 18 17

3

4

14

13

12

11

6 7 8 9

5

10

15

16

VBUS1

VS

VBUS2

UCS21143 x 3 VQFN

2017 Microchip Technology Inc. DS20005743A-page 1

UCS2114

Block Diagram

Charger Control,

Measurement, OCL

Inte

rface

Log

ic

SMCLKSMDATA

PWR_EN2

PowerSwitch 2

Temp

ALERT#2

VBUS

GND

COMM_ILIM

PowerSwitch 1

VBUSVS

UVLO, OVLO

PWR_EN1

BOOST#

ALERT#1

VBUSdischarge

VDD

VS

DS20005743A-page 2 2017 Microchip Technology Inc.

UCS2114
1.0 ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on VDD, VS and VBUS pins ...................................................................................................................–0.3 to 6V

Pull-Up Voltage (VPULLUP) .....................................................................................................................–0.3 to VDD + 0.3

Port Power Switch Current ..................................................................................................................... Internally limited

Voltage on any Other Pin to Ground ..................................................................................................–0.3 to VDD + 0.3V

Current on any Other Pin ..................................................................................................................................... ±10 mA

Operating Ambient Temperature Range................................................................................................ –40°C to +105°C

Storage Temperature Range ................................................................................................................. –55°C to +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periodsmay affect device reliability.

TABLE 1-1: ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = –40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.

Characteristic Symbol Min. Typ. Max. Unit Conditions

Power and Interrupts - DC

Supply Voltage VDD 4.5 5 5.5 V

Supply Current in Active (IDD_ACT + IS1_ACT + IS2_ACT)

IACTIVE — 700 — µA Average current IBUS = 0 mA

Supply Current in Sleep (IDD_SLEEP + IS1_SLEEP + IS2_SLEEP)

ISLEEP — 6 20 µA Average current VPULLUP VDD

Power-on Reset

VDD Low Threshold VDD_TH — 4 4.3 V VDD voltage increasing (Note 1)

VDD Low Hysteresis VDD_TH_HYST — 500 600 mV VDD voltage decreasing (Note 1)

Note 1: This parameter is characterized, not 100% tested.2: This parameter is ensured by design and not 100% tested.3: The current measurement full scale range maximum value is 3.4A. However, the UCS2114 cannot report values above

ILIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).


UCS2114

I/O Pins - SMCLK, SMDATA, PWR_EN, ALERT#, BOOST# - DC Parameters

Output Low Voltage VOL — — 0.4 V ISINK_IO = 8 mASMDATA, ALERT#, BOOST#

Input High Voltage VIH 2.0 — — V PWR_EN, SMDATA, SMCLK

Input Low Voltage VIL — — 0.8 V PWR_EN, SMDATA, SMCLK

Leakage Current ILEAK — — ±5 µA Powered or unpoweredVPULLUP VDDTA < 85°C (Note 1)

Interrupt Pins - AC Parameters

ALERT# Pin Blanking Time tBLANK — 25 — ms Blanking time, coming out of reset

ALERT# Pin Interrupt Masking Time

tMASK — 5 — ms

BOOST# Pin Minimum Assertion Time

tBOOST_MAT — 1 — s

BOOST# Pin Assertion Current

IBOOST — 1.9 — A

SMBus/I2C Timing

Input Capacitance CIN — 5 — pF

Clock Frequency fSMB 10 — 400 kHz

Spike Suppression tSP — — 50 ns

Bus Free Time Stop to Start tBUF 1.3 — — µs

Start Setup Time tSU:STA 0.6 — — µs

Start Hold Time tHD:STA 0.6 — — µs

Stop Setup Time tSU:STO 0.6 — — µs

Data Hold Time tHD:DAT 0 — — µs When transmitting to the master

Data Hold Time tHD:DAT 0.3 — — µs When receiving from the master

Data Setup Time tSU:DAT 0.6 — — µs

Clock Low Period tLOW 1.3 — — µs

Clock High Period tHIGH 0.6 — — µs

Clock/Data Fall Time tFALL — — 300 ns Min. = 20+0.1CLOAD ns (Note 1)

Clock/Data Rise Time tRISE — — 300 ns Min. = 20+0.1CLOAD ns(Note 1)

Capacitive Load CLOAD — — 400 pF Per bus line (Note 1)

Time Out tTIMEOUT 25 — 35 ms Disabled by default (Note 1)

Idle Reset tIDLE_RESET 350 — — µs Disabled by default (Note 1)

TABLE 1-1: ELECTRICAL SPECIFICATIONS (CONTINUED)






UCS2114

Port Power Switch

Port Power Switch - DC Parameter

Overvoltage Lockout VS_OV — 6 — V Note 2

VS Low Threshold VS_UVLO — 2.5 — V Note 2

VS Low Hysteresis VS_UVLO_HYST — 100 — mV Note 2

On Resistance RON_PSW — 18 30 m 4.75V < VS < 5.25V

VS Leakage Current ILEAK_VS — — 5 µA Sleep state into VS pin on one channel (Note 1)

Back-Voltage Protection Threshold

VBV_TH — 150 — mV VBUS > VSVS > VS_UVLO

Leakage Current ILKG_1 — 0 3 µA VDD < VDD_TH,Leakage current from VBUS pins to the VDD and the VS pins (Note 1)

ILKG_2 — 0 2 µA VDD > VDD_TH,Leakage current from VBUS pins to the VS pins, when the power switch is open

Selectable Current Limits ILIM1 — 530 — mA ILIM Resistor = 0 or 47 k(530 mA setting)

ILIM2 — 960 — mA ILIM Resistor = 10 k or 56 k(960 mA setting)





ILIM7 2500 2670 2900 mA ILIM Resistor = 27 k or 150 k(2670 mA setting)

ILIM8 3000 3200 3400 mA ILIM Resistor = 33 k or VDD(3200 mA setting)

Pin Wake Time tPIN_WAKE — 3 — ms

SMBus Wake Time tSMB_WAKE — 4 — ms

Idle Sleep Time tIDLE_SLEEP — 200 — ms

First Thermal Shutdown Stage Threshold

TTSD_LOW — 120 — °C Die Temperature at which the power switch will open if it is in Constant Current mode







UCS2114

First Thermal Shutdown Stage Hysteresis

TTSD_LOW_HYST — 10 — °C Hysteresis for TTSD_LOW func-tionality. Temperature must drop by this value before any of the power switches can be closed.

Second Thermal Shutdown Stage Threshold

TTSD_HIGH — 135 — °C Die Temperature at which both power switches will open

Second Thermal Shutdown Stage Hysteresis

TTSD_HIGH_HYST — 25 — °C Hysteresis for TTSD_HIGH functionality. Temperature must drop by this value before any of the power switches can be closed.

Auto-Recovery Test Current ITEST — 190 — mA Portable device attached, VBUS = 0 V, Die temp < TTSD

Auto-Recovery Test Voltage VTEST — 750 — mV Portable device attached, VBUS = 0 V before application, Die temp < TTSDProgrammable, 250-1000 mV, default listed

Discharge Impedance RDISCHARGE — 100 —

Port Power Switch - AC Parameters

Turn-on Delay tON_PSW — 0.9 — ms PWR_EN active toggle toswitch on time, VBUS discharge not active

Turn-off Time tOFF_PSW_INA — 0.75 — ms PWR_EN inactive toggle to switch off timeCBUS = 120 µF

Turn-off Time tOFF_PSW_ERR — 1 — ms Overcurrent Error, VBUS Min Error, or Discharge Error to switch off CBUS = 120 µF

Turn-off Time tOFF_PSW_ERR1 — 100 — ns TSD or Back-drive Error to switch offCBUS = 120 µF

VBUS Output Rise Time tR_BUS — 1.1 — ms Measured from 10% to 90% of VBUS, CLOAD = 220 µFILIM = 1.0A

Soft Turn-On Rate IBUS/t — 100 — mA/µs

Temperature Update Time tDC_TEMP — 200 — ms

Short-Circuit Response Time tSHORT_LIM — 1.5 — µs Time from detection of short to current limit applied.No CBUS applied

Short-Circuit Detection Time tSHORT — 6 — ms Time from detection of short to port power switch disconnect and ALERT# pin assertion







UCS2114

Latched Mode Cycle Time tUL — 7 — ms From PWR_EN edge transition from inactive to active to begin error recovery.

Auto-Recovery Mode Cycle Time

tCYCLE — 25 — ms Time delay before error condition check.Programmable 15-50 ms, default listed.

Auto-Recovery Delay tTST — 20 — ms Portable device attached, VBUS must be > VTEST after this time.Programmable 10-25 ms, default listed.

Discharge Time tDISCHARGE — 200 — ms Amount of time discharge resistor applied.Programmable 100-400 ms, default listed.

Port Power Switch Operation with Trip Mode Current Limiting

Region 2 Current Keep-Out

IBUS_R2MIN_1 — — 0.1 A Note 2

Minimum VBUS Allowed at Output

VBUS_MIN_1 2.0 — — V Note 2

Port Power Switch Operation with Constant Current Limiting (Variable Slope)

Region 2 Current Keep-Out

IBUS_R2MIN — — 2.13 A Note 2

Minimum VBUS Allowed at Output

VBUS_MIN 2.0 — — V Note 2

Current Measurement - DC

Current Measurement Range IBUS_M 0 — 3400 mA Range (Note 2 and Note 3)

Reported Current Measurement Resolution

IBUS_M — 13.3 — mA 1 LSB

Current Measurement Accuracy

— ±2 — % 200 mA < IBUS < ILIM

— ±2 — LSB IBUS < 200 mA

Current Measurement - AC

Sampling Rate — — 1.1 — ms Note 2

Conversion Time Both Channels

tCONV — 2.2 — ms All registers updated in digital(Note 2)

Charge Rationing - DC

Accumulated Current Measurement Accuracy

— — ±4.5 — %

Charge Rationing - AC

Current Measurement Update Time

tPCYCLE — 1 — s







UCS2114

FIGURE 1-1: SMBus Timing.

SMDATA

SMCLK

TBUF

P S S - Start Condition P - Stop Condition PS

T HIGHT LOW T HD:STA T SU:STO

T HD:STAT HD:DAT

T SU:DAT T SU:STA

T FALL

T RISE

TABLE 1-2: TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Operating Temperature Range TA -40 — +105 °C

Operating Junction Temperature TJ -40 — +125 °C

Storage Temperature Range TA -55 — +150 °C

Thermal Package Resistances

3x3 mm 20-pin VQFN θJA — 48 — °C/W Typical 4-layer board with interconnecting vias, recommended land pattern from this document.


UCS2114

1.1 ESD and Transient Performance

1.1.1 HUMAN BODY MODEL (HBM) PERFORMANCE

HBM testing verifies the ability to withstand ESDstrikes, like those that occur during handling andmanufacturing, and is done without power applied tothe IC. To pass the test, the device must have nochange in operation or performance due to the event.

1.1.2 CHARGED DEVICE MODEL (CDM) PERFORMANCE

CDM testing verifies the ability to withstand ESDstrikes, like those that occur during handling andassembly, with pick-and-place-style machinery and isdone without power applied to the IC. To pass the test,the device must have no change in operation orperformance due to the event.

TABLE 1-3: ESD RATINGS

ESD Specification Rating or Value

Human Body Model (JEDEC JESD22-A114) - All pins 8 kV

Charged Device Model (JEDEC JESD22-C101) - All pins 500V


UCS2114

NOTES:


UCS2114

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.

FIGURE 2-1: Short Applied after Power-Up.

FIGURE 2-2: Power-Up Into a Short.

FIGURE 2-3: Internal Power Switch Short Response.

FIGURE 2-4: VBUS Discharge Behavior.

FIGURE 2-5: Power Switch On Resistance vs. Temperature.

FIGURE 2-6: Power Switch On/Off Time vs. Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-1

0

1

2

3

4

5

6

-1

0

1

2

3

4

5

6

0 2 4 6 8 10C

urre

nt (A

)

Volta

ge (V

)

Time (ms)

IBUS

VBUS

VS = VDD = 5VILIM = 3A min (3.4A max), short applied at 2 ms

-1

0

1

2

3

4

5

6

-1

0

1

2

3

4

5

6

0 20 40 60 80 100 120 140 160 180 200

Cur

rent

(A)

Volta

ge (V

)

Time (ms)

VS = VDD

ALERT#

IBUS

-4

0

4

8

12

16

20

24

28

-2

-1

0

1

2

3

4

5

6

0 20 40

Cur

rent

(A)

Volta

ge (V

)

Time (µs)

VS = VDD = 5VILIM = 2.13A (typical), short applied at 10 µs

IBUS

VBUS

-1

0

1

2

3

4

5

6

0 100 200 300 400 500

Volta

ge (V

)

Time (ms)

VBUS

02468

101214161820

-40 -15 10 35 60 85 110

On

Resi

stan

ce (m

Ω)

Temperature (°C)

0,6

0,65

0,7

0,75

0,8

0,85

0,9

0,95

1

-40 -15 10 35 60 85 110

Tim

e (m

s)

Temperature (°C)

Turn on time

Turn off time


UCS2114


FIGURE 2-7: VS Overvoltage Threshold vs. Temperature.

FIGURE 2-8: VS Undervoltage Threshold vs. Temperature.

FIGURE 2-9: Trip Current Limit Operation vs. Temperature.

FIGURE 2-10: IBUS Measurement Accuracy.

FIGURE 2-11: Active State Current vs. Temperature (both channels on, PWR_EN1 = PWR_EN2 = 1).

5.905.925.945.965.986.006.026.046.066.086.10

-40 -15 10 35 60 85 110

V STh

resh

old

Volta

ge (V

)

Temperature (°C)

VDD = 5V

2.02.12.22.32.42.52.62.72.82.93.0

-40 -15 10 35 60 85 110

V STh

resh

old

Volta

ge (V

)

Temperature (°C)

VDD = 5V

Threshold

Hysteresis

-12%

-10%

-8%

-6%

-4%

-2%

0%

-40 -15 10 35 60 85 110

Cur

rent

Lim

it A

ccur

acy

%)

Temperature (°C)

VS = VDD = 5VILIM = 3.0A min. (3.2A typ., 3.4A max.)

Note: The percentage is relative to the maximum specification (3.4A)

-5

-4

-3

-2

-1

0

1

2

3

4

5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Acc

urac

y (%

)

Current (A)

0

100

200

300

400

500

600

700

800

-40 -15 10 35 60 85 110

Supp

ly C

urre

nt (

A)

Temperature (°C)

IDD + IS1 + IS2

IDD

IS1 + IS2


UCS2114


FIGURE 2-12: Sleep State Current vs. Temperature.

FIGURE 2-13: ILIM1 Trip Current Distribution.

FIGURE 2-14: ILIM2 Trip Current Distribution(1).




0

2

4

6

8

10

12

14

-40 -15 10 35 60 85 110

Supp

ly C

urre

nt (

A)

Temperature (°C)

IDD + IS1 + IS2

IDD

IS1 + IS2

0%

10%

20%

30%

40%

50%

60%

0.50

5

0.51

0.51

5

0.52

0.52

5

0.53

0.53

5

0.54

0.54

5

0.55

0.55

5

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99 1

1.01

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09 1.

1

1.11

1.12

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.23

1.24

1.25

1.26

1.27

1.28

1.29 1.

3

1.31

1.32

1.33

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

1.52

5

1.54

1.55

5

1.57

1.58

5

1.6

1.61

5

1.63

1.64

5

1.66

1.67

5

Sam

ples

(%)

VBUS Current (A)

Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels.


UCS2114





0%

10%

20%

30%

40%

50%

60%2.

03

2.05

2.07

2.09

2.11

2.13

2.15

2.17

2.19

2.21

2.23

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

2.54

5

2.57

2.59

5

2.62

2.64

5

2.67

2.69

5

2.72

2.74

5

2.77

2.79

5

Sam

ples

(%)

VBUS Current (A)

0%

10%

20%

30%

40%

50%

60%

3

3.04

3.08

3.12

3.16 3.

2

3.24

3.28

3.32

3.36 3.

4

Sam

ples

(%)

VBUS Current (A)

Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two VBUS channels.


UC

S2114

DS

20005743A

-page 15

2017 M

icrochip Technolo

gy Inc.

Connection Type if Pin Not Used

Connect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin)

N/A

N/A

O Leave open

O Connect to ground

N/A

O Connect to ground

O Leave open

Connect to ground

N/A

Connect to ground or VDD (depending on the polarity decoded via COMM_ILIM pin)

Connect to ground

N/A

Connect to VPULLUP (or to ground in Stand-Alone mode)

Connect to VPULLUP(or to ground in Stand-Alone mode)

Connect to ground

3.0 PIN DESCRIPTION

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

UCS21143x3 VQFN

Symbol Function Pin Type

1 PWR_EN1 Port power switch enable #1 DI

2 GND Ground Power

3 COMM_ILIM Enables SMBus or Stand-Alone mode at power-up. Hardware strap for maximum current limit.

AIO

4, 5 VBUS1 Port power switch #1 output (requires both pins tied together) High Power, AI

6, 7 VS Voltage input to port power switch VBUS1 (requires both pins tied together)

High Power, AI

8 VDD Common supply voltage Power

9, 10 VS Voltage input to port power switch VBUS2 (requires both pins tied together)

High Power, AI

11, 12 VBUS2 Port power switch #2 output (requires both pins tied together) High Power, AI

13 BOOST# Logic output for DC-DC converter voltage increase (requires pull-up resistor)

OD

14 GND Ground Power

15 PWR_EN2 Port power switch enable #2 DI

16 ALERT#2 Output fault ALERT for VBUS2 (requires pull-up resistor) OD

17 GND Ground Power

18 SMDATA SMDATA - SMBus data input/output (requires pull-up resistor) DIOD

19 SMCLK SMCLK - SMBus clock input (requires pull-up resistor) DI

20 ALERT#1 Output fault ALERT for VBUS1 (requires pull-up resistor) OD

UCS2114

TABLE 3-2: PIN TYPES

Pin Type Description

Power This pin is used to supply power or ground to the device

Hi-Power This pin is a high-current pin

AIO Analog Input/Output - this pin is used as an I/O for analog signals

DI Digital Input - this pin is used as a digital input

DIOD Open-Drain Digital Input/Output - this pin is bidirectional. It is open-drain and requires a pull-up resistor.

OD Open-Drain Digital Output - used as a digital output. It is open-drain and requires a pull-up resistor.


UCS2114

4.0 TERMS AND ABBREVIATIONS

Note: The PWR_EN2 and PWR_EN1 pins each have configuration bits (“<pin name>_S” in GeneralConfiguration 2 register (Address 11h) and General Configuration 1 register (Address 12h)) that may beused to perform the same function as the external pin state. These bits are accessed via the SMBus/I2Cand are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced asthe <pin name> control.

TABLE 4-1: TERMS AND ABBREVIATIONS

Term/Abbreviation Description

CC Constant Current

Current Limiting mode

Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip opens the port power switch. Constant Current (variable slope) allows VBUS to be dropped by the portable device.

IBUS_R2MIN Current limiter mode boundary

ILIM The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the port power switch is opened. In Constant Current mode, when the current exceeds ILIM, operation continues at a reduced voltage and increased current; if VBUS voltage drops below VBUS_MIN, the port power switch is opened.

OCL Overcurrent limit

POR Power-on Reset

Portable Device USB device attached to the USB port

Stand-Alone mode Indicates that the communications protocol is not active and all communications between the UCS2114 and a controller are done via the external pins only (PWR_EN1 and PWR_EN2 as inputs, and ALERT1# and ALERT2# as outputs)


UCS2114

NOTES:


UCS2114

5.0 GENERAL DESCRIPTION

The UCS2114 is a dual-port power switch. Two USBpower ports are supported with current limits up to 3.0Acontinuous current (3.4A maximum) each. Selectableand programmable current limiting configurations arealso available to the application. A typical blockdiagram is shown in Figure 5-1.

FIGURE 5-1: Typical USB Application.

VBUS

2 PORT HUB

PD_ALERT1

PD_ALERT2

D+

D-

USB Port 1 Connector

SMDATSMCLK

SMDATSMCLK

D+

D-

D+

D-

UCS2114

PWR_EN1ALERT1

VBUS1

PWR_EN2ALERT2

VBUS2

USB Port 2 Connector

D+

D-

VBUS


UCS2114

5.1 UCS2114 Power StatesPower states are indicators of the device’s currentconsumption in the system and of the functionality ofthe digital logic. Table 5-1 details the UCS2114 powerstates.

Table 5-2 shows the settings for the various powerstates, except Off and Error. If VDD < VDD_TH, theUCS2114 is in the Off state.

5.1.1 OFF STATE OPERATION

The device will be in the Off state if VDD is less thanVDD_TH. When the UCS2114 is in the Off state, it will donothing and all circuitry will be disabled. Digital registervalues are not stored and the device will not respond toSMBus commands.

5.1.2 SLEEP STATE OPERATIONThe PWR_EN1 and PWR_EN2 pins may be used tocause the UCS2114 to enter/exit Sleep. These pins areAND’ed for Sleep mode.

When the UCS2114 is in the Sleep state, the device willbe in its lowest power state. The port power switch willbe disabled. VBUS1 and VBUS2 will be near ground

potential. The ALERT#1 and ALERT#2 pins will not beasserted. If asserted prior to entering the Sleep state,the ALERT# pin will be released. SMBus activity islimited to single byte read or write.

The first data byte read from the UCS2114 when it is inthe Sleep state will wake it; however, the data to beread will return all 0’s and should be considered invalid.This is a “dummy” read byte meant to wake theUCS2114. Subsequent read or write bytes will beaccepted normally. After the dummy read, theUCS2114 will be in a higher power state (seeFigure 5-2). After communication has not occurred fortIDLE_SLEEP, the UCS2114 will return to Sleep.

TABLE 5-1: POWER STATES DESCRIPTION

State Description

Off This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is considered “off”. The UCS2114 will not retain its digital states and register contents nor respond to SMBus/I2C communications. The port power switch will be off. See Section 5.1.1 “Off State Operation”.

Sleep This is the lowest power state available. While in this state, the UCS2114 will retain digital functionality and wake to respond to SMBus/I2C communications. See Section 5.1.2 “Sleep State Operation”.

Error This power state is entered when a fault condition exists. Error power state is one or both channels in Fault Handling. This state is updated as Priority One. The Interrupt Status registers for each channel will update the fault detected per channel. Only the channel that has detected a Fault will be affected since the other channel can remain active if no fault is detected. See Section 5.1.4 “Error State Operation”.

Active Active power State is one, or both channels active and sourcing current to the VBUS Port. This state is updated as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in this state, operations include activation of the port power switch, current limiting and charge rationing. See Section 5.1.3 “Active State Operation”.

TABLE 5-2: POWER STATES CONTROL SETTINGS

Power State

PWR_EN1 PWR_EN2 Behavior

Sleep disabled disabled • All switches disabled

• VBUS will be near ground potential

• The UCS2114 wakes to respond to SMBus communications

Active enabled disabled • Port power switch is on for VBUS1

• VBUS2 pins are near ground potential or floating (Note 1)

disabled enabled • Port power switch is on for VBUS2

• VBUS1 pins are near ground potential or floating (Note 1)

enabled enabled • Port power switch is on for VBUS1 and VBUS2

Note 1: If the bit EN_VBUS_DISCHG is '1', the VBUS is discharged automatically and VBUS is near ground potential. If the bit EN_VBUS_DISCHG is '0', then the corresponding VBUS pins are floating (VBUS discharge is controlled by the SMBus master).


UCS2114

FIGURE 5-2: Wake from Sleep using SMBus Read.

5.1.3 ACTIVE STATE OPERATION

Every time the UCS2114 enters the Active state, theport power switches are closed. The UCS2114 cannotbe in the Active state (and therefore, the port powerswitch cannot be turned on) if any of the followingconditions exist:

• VS < VS_UVLO

• PWR_EN1 and PWR_EN2 are disabled.

5.1.4 ERROR STATE OPERATION

The UCS2114 will enter the Error state from the Activestate when any of the following events are detected:

• The maximum allowable internal die temperature (TTSD_HIGH) has been exceeded.

• The TTSD_LOW die temperature has been exceeded and any of the following conditions is met:

- a power switch operates in Constant Current mode.

- PWR_EN1 and/or PWR_EN2 controls transition from inactive to active.

- it is a power-up situation and PWR_EN1 and/or PWR_EN2 pins are active.

• An overcurrent condition has been detected.

• An undervoltage condition on either VBUS pin has been detected (see Section 5.3.4 “Undervoltage Lockout on VS”).

• A back-voltage condition has been detected (see Section 5.3.2 “Back-Voltage Detection”).

• A discharge error has been detected.

• An overvoltage condition on the VS pin.

When the UCS2114 enters the Error state, the portpower switch will be disabled while the ALERT# pin isasserted. It will remain off while in this power state. TheUCS2114 will leave this state as determined by the faulthandling selection.

With the Auto-recovery fault handler, after the tCYCLEtime period, the UCS2114 will check that all of the errorconditions have been removed.

If all of the error conditions have been removed, theUCS2114 will return to the Active state.

If both PWR_EN1 and PWR_EN2 controls transitionfrom active to inactive while the UCS2114 is in the Errorstate, the device will not enter the Sleep state. After thefault has been removed, the UCS2114 will notautomatically enter the Sleep state if theEN_VBUS_DISCHG bit from the GeneralConfiguration 1 register is not set (default setting). Toenter the Sleep state, the PWR_EN pins must betoggled or an SMBus read register command must besent.

_1110 A invalid dataN P

SMBus Read

A0001_0000 valid data N P_1110A0001_0000SS

tIDLE_SLEEP

Sleep Sleep

Dummy read returns invalid data and places device in temporary

Active state Read returns valid data

_1111 AS _1111 ASA

Power State temporary Active state(not all functionality available)

tSMB_WAKE


UCS2114

5.2 Communication

The UCS2114 can operate in SMBus mode (seeSection 7.0 “System Management Bus Protocol”)or Stand-Alone mode. The resistor connected to theCOMM_ILIM pin determines the operating mode and

the hardware-set ILIM setting, as shown in Table 5-3.Unless connected to GND or VDD, the resistors inTable 5-3 are external pull-down resistors.

The SMBus address is specified in Section 7.2“SMBus Address and RD/WR Bit”.

5.3 Supply Voltages

5.3.1 VDD SUPPLY VOLTAGE

The UCS2114 requires 4.5V to 5.5V to be present onthe VDD pin for core device functionality. Core devicefunctionality consists of maintaining register states andwake-up upon SMBus/I2C query.

5.3.2 BACK-VOLTAGE DETECTION

The back-voltage detector is functional in all powerstates (Sleep and Active).

When in Sleep, the UCS2114 will enter the Error statefrom Sleep if a back-voltage condition was detected.

Whenever the following condition is true for either port,the port power switch will be disabled and aback-voltage event will be flagged. This will cause theUCS2114 to enter the Error power state (seeSection 5.1.4 “Error State Operation”).

TABLE 5-3: COMMUNICATION DECODE

COMM_ILIM Pull Down Resistor (±1%)

PWR_EN1 and PWR_EN2 Polarity

ILIM (A)Total ILIM (A)

(Note 1)Communication

Mode

GND Active-High 0.53 0.53 + 0.53 SMBUS

10 k Active-High 0.96 0.96 + 0.96 SMBUS







47 k Active-Low 0.53 0.53 + 0.53 Stand-Alone







VDD Active-Low 3.2 3.2 + 3.2 Stand-Alone

Note 1: The total maximum current depends on the power dissipation characteristics of the design (see Table 1-1).

Note: The VBUS voltage exceeds the VS and/orthe VDD pin voltage by VBV_TH and theport power switch is closed. The portpower switch will be opened immediately.If the condition lasts for longer than tMASK,then the UCS2114 will enter the Errorstate. Otherwise, the port power switchwill be turned on as soon as the conditionis removed.


UCS2114

5.3.3 BACK-DRIVE CURRENT PROTECTION

If a portable self-powered device is attached, it maydrive the VBUS port to its power supply voltage level;however, the UCS2114 is designed such that leakagecurrent from the VBUS pins to the VDD and/or the VS pinshall not exceed ILKG_1 (if the VDD and/or VS voltage iszero) or ILKG_2 (if the VDD and/or VS voltage exceedsVDD_TH and the power switch is open).

5.3.4 UNDERVOLTAGE LOCKOUT ON VS

The UCS2114 requires a minimum voltage (VS_UVLO)to be present on the VS pin for Active power state.

5.3.5 OVERVOLTAGE DETECTION AND LOCKOUT ON VS

Both power switches will be disabled if the voltage onany VS pin exceeds a voltage (VS_OV) for longer thanthe specified time (tMASK). This will cause the device toenter the Error state and both ALERT#1 and ALERT#2pins will be asserted.

5.3.6 PWR_EN1 AND PWR_EN2 INPUT

The PWR_EN control affects the power state and enablesthe port power switch to be turned on if conditions are met(see Table 5-2). The port power switch cannot be closedif PWR_EN is disabled. However, if PWR_EN is enabled,the port power switch is not necessarily closed (seeSection 5.1.3 “Active State Operation”). In SMBusmode, the PWR_EN1 and PWR_EN2 pins states will beignored by the UCS2114 if the PIN_IGN configuration bitis set; otherwise, the PWR_EN1S and PWR_EN2Sconfiguration bits are checked along with the pins.


UCS2114

5.4 Discrete Output Pins

5.4.1 ALERT#1 AND ALERT#2 OUTPUT PINS

The UCS2114 has two independent ALERT# out pins.ALERT#1 is tied to the status of the VBUS1 pin.ALERT#2 is tied to the status of the VBUS2 pin.

The ALERT# pin is an active-low open-drain interruptto the host controller. The ALERT# pin is assertedwhen an error occurs. Also, when charge rationing isenabled, the ALERT# pin is asserted by default whenthe current rationing threshold is reached (asdetermined by RATION_BEH<1:0>). The ALERT# pinis released when all error conditions that may assertthe ALERT# pin (such as an error condition and chargerationing) have been removed or reset as necessary.

The UCS2114 is compatible with the Microchip hubdevices supporting single pin power control feature.These hub devices have a single connection to thePWR_EN and ALERT# pins of the UCS2114, which aretied together in the application.

5.4.2 BOOST# OUTPUT PIN

The UCS2114 provides a BOOST# output pin tocompensate for voltage drops during high loads. TheBOOST# pin is an active-low, open-drain output thatwould be connected to a resistor in the DC-DCconverter’s feedback error voltage loop (seeFigure 5-3).

The BOOST# pin can then be asserted when theVBUS Current > IBOOST. IBOOST typical value is 1.9A.The BOOST# is OR’ed for both VBUS1 and VBUS2 ports.When the BOOST# pin is asserted, it will remain in thisstate for at least tBOOST_MAT (minimum assertion time).

FIGURE 5-3: BOOST# Pin Usage.

5.5 Discrete Input Pins

5.5.1 COMM_ILIM INPUT

The COMM_ILIM input determines thecommunications mode, as shown in Table 6-1. This isalso the hardware strap for MAX Current Limit.

5.5.2 SMCLK

When operated in Stand-Alone mode, this pin should betied to ground. When the UCS2114 is configured forSMBus communications, the SMCLK is the clock input.

5.5.3 SMDATA

When used in Stand-Alone, this pin should be tied toground.

When the UCS2114 is configured for SMBuscommunications, the SMDATA is the data input/output.

DC-DCConverter Block

5.0VOUT

FeedBack

GND

R1

R2

R3

R4

VFB

GN

DGND

PWR_EN1

COMM_ILIM

V S

1

2

3

4

6 7 8 9

SM

DA

TA/L

OW

_ILM

5

10

15

14

13

12

20 19 18 17

VS

PWR_EN2

ALE

RT#

1

VS

GND

SM

CLK

VS

ALE

RT#

2

VBUS1

VD

D

BOOST#

11

16UCS2114

20-VQFN 3 x 3 mm

VBUS1 VBUS2

VBUS2

5VOUT

R1 R2 R3+ + VFB

R3--------------------------------------------------------=

VOUTR2 R3+ R1 VFB

R3 R4--------------------------------------------------------=

VOUT5VOUTVFB--------------------

R1R3------–

R1 VFB

R4------------------------=

If R1 R3 VOUT5VOUT R1

R4---------------------------------


UCS2114

6.0 USB PORT POWER SWITCH

To assure compliance to various chargingspecifications, the UCS2114 contains a USB portpower switch that supports two current-limiting modes:Trip and Constant current (variable slope). The currentlimit (ILIM) is pin selectable (and may be updated viathe register set). The switch also includes soft-startcircuitry and a separate short-circuit current limit.

The port power switch is on in the Active state (exceptwhen VBUS is discharging).

6.1 Current Limiting

6.1.1 CURRENT LIMIT SETTING

The UCS2114 hardware set current limit, ILIM, can beone of eight values. This resistor value is read onceupon UCS2114 power-up. The current limit can bechanged via the SMBus/I2C after power-up; however,the programmed current limit cannot exceed the hard-ware set current limit. Unless connected to VDD, theresistors in Table 6-1 are pull-down resistors.

At power-up, the communication mode (Stand-Aloneor SMBus/I2C) and hardware current limit (ILIM) aredetermined via the pull-down resistor (or pull-upresistor if connected to VDD) on the COMM_ILIM pin,as shown in Table 6-1.

6.1.2 SHORT-CIRCUIT OUTPUT CURRENT LIMITING

Short-circuit current limiting occurs when the outputcurrent is above the selectable current limit (ILIMx).This event will be detected and the current willimmediately be limited (within tSHORT_LIM time). If thecondition remains, the port power switch will flag anError condition and enter the Error state.

6.1.3 SOFT START

When the PWR_EN control changes states to enable theport power switch, the UCS2114 invokes a soft-startroutine for the duration of the VBUS rise time (tR_BUS).This soft-start routine will limit current flow from VS intoVBUS while it is active. This circuitry will prevent currentspikes due to a step in the portable device current draw.

In the case when a portable device is attached while thePWR_EN pin is already enabled, if the bus currentexceeds ILIM, the UCS2114 current limiter will respondwithin a specified time (tSHORT_LIM) and will operatenormally at this point. The CBUS capacitor will deliver theextra current, if any, as required by the load change.

6.1.4 CURRENT LIMITING MODES

The UCS2114 current limiting has two modes: Trip andConstant Current (variable slope). Either modefunctions at all times when the port power switch isclosed.

6.1.4.1 Trip Mode

When using Trip current limiting, the UCS2114 USBport power switch functions as a low-resistance switchand rapidly turns off if the current limit is exceeded.While operating using Trip current limiting, the VBUSoutput voltage will be held relatively constant (equal tothe VS voltage minus the RON x IBUS current) for allcurrent values up to the ILIM.

If the current drawn by a portable device exceeds ILIM,the following occurs:

1. The port power switch will be turned off (Tripaction).

2. The UCS2114 will enter the Error state andassert the ALERT# pin.

3. The fault handling circuitry will then determinesubsequent actions.

TABLE 6-1: ILIM DECODE

COMM_ILIM Pulldown Resistor

(±1%)

PWR_EN1 and

PWR_EN2 Polarity

ILIM (A)Total ILIM

(A)(Note 1)

GND Active-High 0.53 0.53+0.53

10 kΩ Active-High 0.96 0.96+0.96

12 kΩ Active-High 1.07 1.07+1.07

15 kΩ Active-High 1.28 1.28+1.28

18 kΩ Active-High 1.6 1.6+1.6

22 kΩ Active-High 2.13 2.13+2.13

27 kΩ Active-High 2.67 2.67+2.67

33 kΩ Active-High 3.2 3.2+3.2

47 kΩ Active-Low 0.53 0.53+0.53

56 kΩ Active-Low 0.96 0.96+0.96

68 kΩ Active-Low 1.07 1.07+1.07

82 kΩ Active-Low 1.28 1.28+1.28

100 kΩ Active-Low 1.6 1.6+1.6

120 kΩ Active-Low 2.13 2.13+2.13

150 kΩ Active-Low 2.67 2.67+2.67

VDD Active-Low 3.2 3.2+3.2

Note 1: The total maximum current depends on power dissipation characteristics of the design (see Table 1-1).


UCS2114

Figure 6-1 shows operation of current limits in Tripmode with the shaded area representing the USB 2.0specified VBUS range. Dashed lines indicate the portpower switch output will go to zero (e.g., Trip) whenILIM is exceeded. Note that operation at all possiblevalues of ILIM is shown in Figure 6-1 for illustrative pur-poses only; in actual operation, only one ILIM can beactive at any time.

FIGURE 6-1: Current Limiting in Trip Mode.

6.1.4.2 Constant Current Limiting (Variable Slope)

Constant current limiting is used when the currentdrawn is greater than ILIM (and ILIM < 1.6A). In CCmode, the port power switch allows the attachedportable device to reduce VBUS output voltage to lessthan the input VS voltage while maintaining currentdelivery. The V/I slope depends on the user set ILIMvalue. This slope is held constant for a given ILIMvalue.

This mode is specifically provided for devices that relyon resistive means to reduce VBUS voltage for directbattery charging or to allow portable devices a meansto “test” charger capacity. See Figure 6-2.

FIGURE 6-2: Constant Current Example.

Figure 6-3 shows operation of current limits whileusing CC mode. Unlike Trip mode, once IBUS currentexceeds ILIM, operation continues at a reduced voltageand increased current. Note that the shaded area rep-resenting the USB 2.0 specified VBUS range is nowrestricted to an upper current limit of IBUS_R2MIN. Notethat the UCS2114 will heat up along each load line asvoltage decreases. If the internal temperature exceedsthe TTSD_LOW threshold, the corresponding powerswitch operating in constant current mode will open. Ifthe internal temperature exceeds the TTSD_HIGHthreshold, both power switches will open, regardlessof whether the power switch channels are in currentlimit. Also note that, when the VBUS voltage is broughtlow enough (below VBUS_MIN), the port power switchwill open.

FIGURE 6-3: Current Limiting in CC Mode.

5

4

3

2

1

0.53 1.07 1.6 2.67 3.2

5.25

4.75

IBUS (Amps)

VB

US (V

olts

)

Operating Current

0

00.96 1.28

1.281.070.960.53 1.6 3.22.13 2.67

= ILIM’s

2.13

Power Switch Voltage and Current Output go to Zero when ILIM is

Exceeded

Trip action (ILIM = 0.53A)

Trip action (ILIM = 3.2A)

ILIM (Amps)

Control Loop Temp

VS

GND

ILIM

PowerSwitch

DC5V

BatteryCharger

IC

VBAT

RSense

IBUS

Portable Device

VBUS << VS

UCS2114

5

4

3

2

1

0.53 1.6 2.67 3.2

5.25

4.75

00

0.96 1.28

1.280.960.53 1.6

IBUS_R2MIN

2.13

2.13 2.67 3.2

IBUS (Amps)

V BU

S (V

olts

)

ILIM (Amps)

= ILIM’s

Constant resistance IBUS operation line 1

(ILIM = 0.53A)

Constant resistance IBUS operation line 4

(ILIM = 1.6A)

CC mode - Power switch current increases as voltage decreases when ILIM is exceeded following constant resistance lines


UCS2114

6.2 USB Port Power Profiles

The UCS2114 combines the qualities of traditionalUSB port power switches with USB port power profilesset forth in the USB-IF BC1.2 specification. USB portpower profiles consist of distinct voltage-currentoperation regions defined by “keep-out” and“operation” regions.

While operating in the CC mode of operation, theUCS2114 provides voltage-current output operatingprofiles that are specified by two keep-out regions.

If the current reaches the IBUS_R2MIN setting for longerthan tMASK, the UCS2114 enters the Error state and anOvercurrent event is flagged.

If the VBUS voltage ever goes below the no-operationlower-voltage keep-out (VBUS_MIN) value for longerthan tMASK, the port power switch is disabled and akeep-out violation is flagged (by setting theMIN_KEEP_OUT status bit). This will cause the deviceto enter the Error state.

Figure 6-4 illustrates the relationship between theseUSB port power profile parameters.

6.2.1 OPERATION WITHIN A USB PORT POWER PROFILE

An attached device may be constrained to operatewithin the boundaries of a USB port power profile bysetting the value of ILIM less than the USB port powerprofile IBUS_R2MIN value. In this case, the port powerswitch will be in Trip mode up until ILIM is exceeded, atwhich point, the switch will transition into CC mode. Ifthe attached device reduces the output voltage to lessthan VBUS_MIN, the switch will trip and terminatecharging.

FIGURE 6-4: ILIM < IBUS_R2MIN Example.

6.2.2 OPERATION OUTSIDE OF A USB PORT POWER PROFILE

An attached device may be allowed to operate outsideof the boundaries of a USB port power profile bysetting the value of ILIM greater than the USB portpower profile IBUS_R2MIN value. This is the defaultoperation for all portable devices. In this case, theUSB port power switch will operate in Trip mode untilthe bus current reaches the ILIM value. Once the ILIMvalue has been exceeded, the port power switch willopen and terminate charging. Figure 6-5 illustrates anexample of current limiting in this configuration.

FIGURE 6-5: ILIM > IBUS_R2MIN Example.

5

4

3

2

1

0.53 1.6 2.67 3.2

5.25

4.75

0

0

Port Power Profile Operating Region

0.96 1.28

1.280.960.53 1.6

2.13

2.13 2.67 3.2

VBUS_MIN = 2.0V

IBUS (Amps)

V BU

S (V

olts

)

ILIM (Amps)

(Trip)

ILIM = 1.6A

IBUS_R2MIN = 1.6A

Note: The CC mode of operation is possible onlyup to 1.6A. As long as the value of ILIM isless than the fixed port power profileIBUS_R2MIN value, CC mode is possible.Otherwise, the USB port power switch willoperate in Trip mode operation.

5

4

3

2

1

0.53 1.6 2.67 3.2

5.25

4.75

0

0

Port Power Profile Operating Region

0.96 1.28

1.280.960.53 1.6

2.13

2.13 2.67 3.2

VBUS_MIN = 2.0V

IBUS (Amps)

V BU

S (V

olts

)

ILIM (Amps)

(Trip)

ILIM = 2.67A

IBUS_R2MIN = 1.6A


UCS2114

6.3 Thermal Protection

The UCS2114 utilizes two-stage internal thermalmanagement. The first is triggered when the dietemperature exceeds TTSD_LOW threshold, and thesecond is triggered when the die temperature exceedsTTSD_HIGH threshold.

6.3.0.1 THE FIRST THERMAL SHUTDOWN STAGE (TTSD_LOW)

The first stage turns off the individual power switchchannel when the die temperature exceeds TTSD_LOWthreshold and a power switch operates in ConstantCurrent mode. It also causes the correspondingchannel to enter in error state and the correspondingALERT# pin to be asserted.

When an overcurrent condition appears, the powerswitch operates in Constant Current mode for theduration of tMASK time. Because of the increasedvoltage drop across the switch, the die temperatureincreases. If the die temperature exceeds TTSD_LOWthreshold before the expiration of the tMASK time, thenthe power switch will open immediately.

If the TTSD_LOW threshold has been exceeded, but thedie temperature has not decreased below theTTSD_LOW recovery threshold, then the power switchcannot be closed when commanded by the PWR_EN1or PWR_EN2 controls in the following situations:

• PWR_EN1 and/or PWR_EN2 controls transition from inactive to active.

• it is a power-up situation and PWR_EN1 and/or PWR_EN2 pins are active.

In these situations, the corresponding channel willenter in error state and the corresponding ALERT# pinwill be asserted.

The first thermal shutdown stage allows the two portsto work independently, by preventing the dietemperature to increase during overcurrent conditionsand to exceed the maximum allowable temperature(TTSD_HIGH).

The error state will persist and the power switches cannot be closed until the temperature is belowTTSD_LOW - TTSD_LOW_HYST.

6.3.0.2 THE SECOND THERMAL SHUTDOWN STAGE (TTSD_HIGH)

The second thermal protection stage turns off bothpower switches when the die temperature exceedsTTSD_HIGH threshold, regardless of whether the powerswitch channels are in current limit. It also causes bothchannels to enter in error state and both ALERT#1 andALERT#2 pins to be asserted.

The error state will persist and the power switchescannot be closed until the temperature is belowTTSD_HIGH - TTSD_HIGH_HYST.

6.4 VBUS Discharge

When the EN_VBUS_DISCHG bit from GeneralConfiguration 2 register is set (by default it is not set),the UCS2114 will discharge VBUS through an internal100 resistor when at least one of the followingconditions occur:

• The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control).

• The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to be disabled.

• When commanded into the Sleep power state.

• Upon recovery from the Error state.

• When commanded via the SMBus in the Active state.

When the automatic VBUS discharge circuitry isactivated, the UCS2114 will confirm that VBUS wasdischarged at the end of the tDISCHARGE time. If theVBUS voltage is not below the VTEST level, a dischargeerror will be flagged (by setting the DISCH_ERR(1/2)status bit) and the UCS2114 will enter the Error state.

When the EN_VBUS_DISCHG bit from GeneralConfiguration 2 register is not set (default setting), theautomatic VBUS discharges described above aredisabled. In this case, the SMBus master must set andclear bits DISCHG_LOAD1 and DISCHG_LOAD2 fromthe Current Limit Behavior registers, to discharge theVBUS1 and VBUS2. Setting the DISCHG_LOAD1 andDISCHG_LOAD2 bits connects the internal 100resistor to discharge the corresponding VBUS path.This functionality doesn't use any timers. Thedischarge time is controlled by the SMBus master,which must clear this bit when its internal timer expires.


UCS2114

6.5 Charge Rationing Interactions

When charge rationing is active, regardless of thespecified behavior, the UCS2114 will function normallyuntil the charge rationing threshold is reached. Notethat charge rationing is only active when the UCS2114is in the Active state. Changing the charge rationingbehavior will have no effect on the charge rationingdata registers. If the behavior is changed prior toreaching the charge rationing threshold, this change

will occur and be transparent to the user. When thecharge rationing threshold is reached, the UCS2114will take action as shown in Table 6-2. If the behavioris changed after the charge rationing threshold hasbeen reached, the UCS2114 will immediately adoptthe newly programmed behavior, clearing the ALERT#pin and restoring switch operation respectively (seeTable 6-4).

TABLE 6-2: CHARGE RATIONING BEHAVIOR

RATION_BEH(1 or 2) <1:0> Behavior Actions Taken Notes

1 0

0 0 Report ALERT# pin asserted.

0 1 Report and

Disconnect (default)

1. ALERT# pin asserted.

2. Port power switch disconnected.

All bus monitoring is still active. Toggling the PWR_EN control will cause the device to change power states as defined by the registers; however, the port power switch will remain off until the rationing circuitry is reset.

1 0 Disconnect and

Go to Sleep

1. Port power switch disconnected.

2. Device will enter the Sleep state.

All VBUS and VS monitoring will be stopped. Toggling the PWR_EN control will have no effect on the power state until the rationing circuitry is reset.

1 1 Ignore Take no further action.

TABLE 6-3: CHARGE RATIONING RESET BEHAVIOR

Behavior Reset Actions

Report 1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Release the ALERT# pin.

Report and Disconnect 1. Reset the Total Accumulated Charge registers.



4. Check the PWR_EN controls and enter the indicated power state if the controlschanged.

Disconnect and Go to Sleep

1. Reset the Total Accumulated Charge registers.


3. Check the PWR_EN controls and enter the indicated power state if the controlschanged.

Ignore 1. Reset the Total Accumulated Charge registers.



UCS2114

If the RATION_EN control is set to ‘0’ prior to reachingthe charge rationing threshold, rationing will bedisabled and the Total Accumulated Charge registerswill be cleared. If the RATION_EN control is set to ‘0’after the charge rationing threshold has been reached,the following additional steps occur:

1. RATION status bit will be cleared.

2. The ALERT# pin will be released if asserted bythe rationing circuitry and no other conditionsare present.

3. The PWR_EN controls are checked todetermine the power state.

Setting the RATION_RST control to ‘1’ willautomatically reset the Total Accumulated Chargeregisters to 00_00h. If this is done prior to reaching thecharge rationing threshold, the data will continue to beaccumulated restarting from 00_00h. If this is doneafter the charge rationing threshold is reached, theUCS2114 will take action as shown in Table 6-3.

TABLE 6-4: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED

Previous Behavior

New Behavior Actions Taken

Ignore Report Assert ALERT# pin

Reportand

Disconnect

1. Assert ALERT# pin.

2. Open port power switch. See the Report and Disconnect (default) inTable 6-2.

Disconnectand

Go to Sleep

1. Open port power switch.

2. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2.

Report Ignore Release ALERT# pin.

Reportand

Disconnect

Open port power switch. See the Report and Disconnect (default) in Table 6-2.

Disconnectand

Go to Sleep


2. Open the port power switch.


Report andDisconnect

Ignore 1. Release the ALERT# pin.

2. Check the PWR_EN controls and enter the indicated power state if thecontrols changed.

Report Check the PWR_EN controls and enter the indicated power state if the controlschanged.

Disconnectand

Go to Sleep



Disconnect andGo to Sleep

Ignore Check the PWR_EN controls and enter the indicated power state if the controlschanged.

Report 1. Assert the ALERT# pin.

2. Check the PWR_EN controls and enter the indicated power state if thecontrols changed.

Reportand

Disconnect

1. Assert the ALERT# pin.

2. Check the PWR_EN controls to determine the power state, then enter thatstate, except that the port power switch will not be closed.


UCS2114

6.6 Fault Handling Mechanism

The UCS2114 has two modes for handling faults:

• Latch (latch-upon-fault)

• Auto-recovery (automatically attempt to restore the Active power state after a fault occurs).

If the SMBus is actively utilized, Auto-Recovery FaultHandling is the default error handler as determined bythe LATCH_SET bit. Faults include overcurrent,overvoltage (on VS), undervoltage (on VBUS),back-voltage (VBUS to VS or VBUS to VDD), dischargeerror and maximum allowable internal die temperature(TTSD_HIGH) exceeded. Fault conditions also includethe situations when TTSD_LOW die temperature hasbeen exceeded and any of the following conditions aremet:

• a power switch operates in Constant Current mode.

• PWR_EN1 and/or PWR_EN2 controls transition from inactive to active.


Faults do not include:

• keep-out violations except VBUS_MIN.

• TTSD_LOW die temperature has been exceeded and any of the following conditions are met:

- the power switch is closed at the time when TTSD_LOW is reached and it is not in Constant Current mode.

- the power switch remains open (PWR_EN1 and/or PWR_EN2 controls are not active).

6.6.1 AUTO-RECOVERY FAULT HANDLING

When the LATCH_SET bit is low, Auto-Recovery FaultHandling is used. When an error condition is detected,the UCS2114 will immediately enter the Error stateand assert the ALERT# pin. Independently from thehost controller, the UCS2114 will wait a preset time(tCYCLE), check error conditions (tTST) and restoreActive operation if the error condition(s) no longerexist. If all other conditions that may cause theALERT# pin to be asserted have been removed, theALERT# pin will be released. Short-CircuitAuto-Recovery example in Figure 6-6.

FIGURE 6-6: Error Recovery.

6.6.2 LATCHED FAULT HANDLING

When the LATCH_SET bit is high, latch fault handlingis used. When an error condition is detected, theUCS2114 will enter the Error power state and assertthe ALERT# (1 or 2) pin. Upon command from the hostcontroller (by toggling the PWR_EN (1, or 2) pincontrol from enabled to disabled or by clearing theERR bit via SMBus), the UCS2114 will check errorconditions once and restore Active operation if errorconditions no longer exist. If an error condition stillexists, the host controller is required to issue thecommand again to check error conditions.

If the ALERT# pin is asserted and the interrupt statusregisters (addresses 03h or 04h) are not read, thecorresponding ALERT# pin remains asserted until thecorresponding PWR_EN pin is toggled.

If the ALERT# pin is asserted and the interrupt statusregisters are read, the ALERT# pin will deassert, butthe UCS will remain in error state until the ERR bit iscleared via SMBus or the PWR_EN pin is toggled.

tTST

VBUS

IBUS

SHORT applied.

ITEST

tDISCHARGE

ITEST

VTEST

Short Detected. VBUSdischarged. Enter

Error state.

Check short condition. Short

still present. Return to Error

State.

Wait tCYCLE. Wait tCYCLE.Check short

condition. Short removed. Return to normal

operation.

tCYCLE tCYCLEtTST


UCS2114

NOTES:


UCS2114

7.0 SYSTEM MANAGEMENT BUS PROTOCOL

In SMBus mode, the UCS2114 communicates with ahost controller, such as a Microchip PIC®

microcontroller or hub, through the SMBus. TheSMBus is a two-wire serial communication protocolbetween a computer host and its peripheral devices. Adetailed timing diagram is shown in Figure 1-1.Stretching of the SMCLK signal is supported; however,the UCS2114 will not stretch the clock signal.

7.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of theSMBus Data line from a logic ‘1’ state to a logic ‘0’state while the SMBus Clock line is in a logic ‘1’ state.

7.2 SMBus Address and RD/WR Bit

The SMBus Address Byte consists of the 7-bit clientaddress followed by the RD/WR indicator bit. If thisRD/WR bit is a logic ‘0’, the SMBus Host is writing datato the client device. If this RD/WR bit is a logic ‘1’, theSMBus Host is reading data from the client device.

The UCS2114 with the order code UCS2114-1-V/LXhas the SMBus address 57h - 1010_111(r/w).

Customers should contact their distributor,representatives or field application engineer (FAE) foradditional SMBus addresses. Local sales offices arealso available to help customers. A list of sales officesand locations is included in the back of this document.

7.3 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit firstand composed of 8 bits of information.

7.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes thatit receives. This is done by the client device pulling theSMBus Data line low after the 8th bit of each byte thatis transmitted. This applies to both the Write Byte andBlock Write protocols.

The Host will NACK (not acknowledge) the last data byteto be received from the client by holding the SMBus dataline high after the 8th data bit has been sent. For theBlock Read protocol, the Host will ACK (acknowledge)each data byte that it receives except the last data byte.

7.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of theSMBus Data line from a logic ‘0’ state to a logic ‘1’state while the SMBus clock line is in a logic ‘1’ state.When the UCS2114 detects an SMBus Stop bit and ithas been communicating with the SMBus protocol, itwill reset its client interface and prepare to receivefurther communications.

7.6 SMBus Time-out

The UCS2114 includes an SMBus time-out feature. Ifthe clock is held at logic ‘0’ for tTIMEOUT, the devicecan time out and reset the SMBus interface. TheSMBus interface can also reset if both the clock anddata lines are held at a logic ‘1’ for tIDLE_RESET.Communication is restored with a start condition.

The time-out function defaults to disabled. It can beenabled by clearing the DIS_TO bit in the GeneralConfiguration 3 register (see Register 8-9).

7.7 SMBus and I2C Compliance

The major difference between SMBus and I2C devicesis highlighted here. For complete complianceinformation, refer to the SMBus 2.0 specification andApplication Note 14.0.

• UCS2114 supports I2C fast mode at 400 kHz. This covers the SMBus maximum time of 100 kHz.

• The minimum frequency for SMBus communications is 10 kHz.

• The client protocol will reset if the clock is held low longer than 30 ms. This time out functionality is disabled by default in the UCS2114 and can be enabled by clearing the DIS_TO bit. I2C does not have a time out.

• Except when operating in Sleep, the client protocol will reset if both the clock and the data line are logic ‘1’ for longer than 200 µs (idle condition). This function is disabled by default in the UCS2114 and can be enabled by clearing the DIS_TO bit. I2C does not have an idle condition.

• I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).

• I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. The UCS2114 supports I2C formatting only.

7.8 SMBus Protocols

The UCS2114 device is SMBus 2.0-compatible andsupports Send Byte, Read Byte, Block Read, ReceiveByte as valid protocols, as shown below. TheUCS2114 device also supports the I2C block read andblock write protocols. The device supports Write Byte,Read Byte and Block Read/Block Write. All of thebelow protocols use the convention in Table 7-1.

TABLE 7-1: SMBUS PROTOCOL

Data Sent to Device Data Sent to the Host

Data sent Data sent


UCS2114

7.9 SMBus Write Byte

The Write Byte is used to write one byte of data to aspecific register as shown in Table 7-2.

7.10 SMBus Read Byte

The Read Byte protocol is used to read one byte ofdata from the registers as shown in Table 7-3.

7.11 Block Write

The Block Write is used to write multiple data bytes toa group of contiguous registers, as shown in Table 7-4.It is an extension of the Write Byte Protocol.

7.12 Block Read

The Block Read is used to read multiple data bytesfrom a group of contiguous registers, as shown inTable 7-5. It is an extension of the Read Byte Protocol.

TABLE 7-2: WRITE BYTE PROTOCOL

STARTSlave

AddressWR ACK Reg. Addr. ACK Register Data ACK STOP

1 → 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 → 1

TABLE 7-3: READ BYTE PROTOCOL

START Slave Address WR ACK Register Address ACK

1 → 0 YYYY_YYY 0 0 XXh 0

START Slave Address RD ACK Register Data NACK STOP

1 → 0 YYYY_YYY 1 0 XXh 1 0 → 1

Note: The Block Write and Block Read protocolsrequire that the address pointer be auto-matically incremented. For a write com-mand, the address pointer will beautomatically incremented when the ACKis sent to the host. There are no over orunder bound limit checking and theaddress pointer will wrap around from FFhto 00h if necessary

TABLE 7-4: BLOCK WRITE PROTOCOL

START Slave Address WR ACKRegister Address

ACKRepeat N Times

STOPRegister Data ACK

1 → 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 → 1

TABLE 7-5: BLOCK READ PROTOCOL

START Slave Address WR ACKRegister Address

ACK

1 → 0 YYYY_YYY 0 0 XXh 0

START Slave Address RD ACKRepeat N Times

Register Data NACK STOPRegister Data ACK

1 → 0 YYYY_YYY 1 0 XXh 0 XXh 1 0 → 1


UCS2114

7.13 SMBus Send Byte

The Send Byte protocol is used to set the internaladdress register pointer to the correct address location.No data is transferred during the Send Byte protocol asshown in Table 7-6.

7.14 SMBus Receive Byte

The Receive Byte protocol is used to read data from aregister when the internal register address pointer isknown to be at the right location (e.g., set via SendByte). This is used for consecutive reads of the sameregister as shown in Table 7-7.

7.14.1 STAND-ALONE OPERATING MODE

Stand-Alone mode allows the UCS2114 to operatewithout active SMBus/I2C communications.Stand-Alone mode can be enabled by connecting apull-down resistor greater or equal to 47 k on theCOMM_ILIM pin as shown in Table 5-3.The SMCLKpin should be tied to ground in this mode.

Note: The SMBus Send Byte command isexpected to be followed by the SMBusReceive Byte command. When twoSMBus Send Byte commands are sent ina row, the first command receives an ACKand will be processed by the UCS2114,but the second command receives aNACK and will be ignored.

TABLE 7-6: SEND BYTE PROTOCOL

START Slave Address WR ACK Register Address ACK STOP

1→0 YYYY_YYY 0 0 XXh 0 0 → 1

TABLE 7-7: RECEIVE BYTE PROTOCOL

START Slave Address RD ACK Register Data NACK STOP

1→0 YYYY_YYY 1 0 XXh 1 0 → 1


UCS2114

NOTES:


UCS2114

8.0 REGISTER DESCRIPTION

The registers shown in Table 8-1 are accessiblethrough the SMBus or I2C. An entry of ‘—’ indicatesthat the bit is not used. Writing to these bits will have noeffect and reading these bits will return ‘0’. Writing to areserved bit may cause unexpected results andreading from a reserved bit will return either ‘1’ or ‘0’ asindicated in the bit description. While in the Sleep state,the UCS2114 will retain configuration and chargerationing data as indicated in the text. If a register doesnot indicate that data will be retained in the Sleeppower state, this information will be lost when theUCS2114 enters the Sleep power state. TABLE 8-1: REGISTER SET IN HEXADECIMAL ORDER

Register Address

Register Name R/W FunctionDefault Value

Page No.

00h Port 2 Current Measurement R Stores the current measurement for Port 2 00h 38

01h Port 1 Current Measurement R Stores the current measurement for Port 1 00h 38

02h Port Status R Indicates Port and general status 00h 39

03h Interrupt Status2 See Text Indicates why ALERT# pin asserted for Port 2 00h 40

04h Interrupt Status1 See Text Indicates why ALERT# pin asserted for Port 1 00h 42

0Fh General Status2 R/R-C Indicates General Status for Port 2 00h 44

10h General Status1 R/R-C Indicates General Status for Port 1 00h 45

11h General Configuration2 R/W Controls basic functionality for Port 2 06h 46

12h General Configuration1 R/W Controls basic functionality for Port 1 02h 47

13h General Configuration3 R/W Controls other functionality 60h 48

14h Current Limit R/W Controls/Displays MAX Current Limit per port 00h 49

15h Auto-Recovery Configuration R/W Controls the Auto-Recovery functionality 2Ah 50

16h Port 2 Total Accumulated Charge High Byte

R Stores the total accumulated charge delivered high byte, Port 2

00h 51

17h Port 2 Total Accumulated Charge Middle High Byte

R Stores the total accumulated charge delivered middle high byte, Port 2

00h 51

18h Port 2 Total Accumulated Charge Middle Low Byte

R Stores the total accumulated charge delivered middle low byte, Port 2

00h 51

19h Port 2 Total Accumulated Charge Low Byte

R Stores the total accumulated charge delivered low byte, Port 2

00h 51

1Ah Port 1 Total Accumulated Charge High Byte

R Stores the total accumulated charge delivered high byte, Port 1

00h 52

1Bh Port 1 Total Accumulated Charge Middle High Byte

R Stores the total accumulated charge delivered middle high byte, Port 1

00h 52

1Ch Port 1 Total Accumulated Charge Middle Low Byte

R Stores the total accumulated charge delivered middle low byte, Port 1

00h 52

1Dh Port 1 Total Accumulated Charge Low Byte

R Stores the total accumulated charge delivered low byte, Port 1

00h 52

1Eh Port 2 Charge Rationing Threshold High Byte

R/W Sets the maximum allowed charge that will be delivered to Port 2

FFh 53

1Fh Port 2 Charge Rationing Threshold Low Byte


FFh 53

20h Port 1 Charge Rationing Threshold High Byte


FFh 53


UCS2114

8.1 Current Measurement Register

The Current Measurement register stores themeasured current value delivered to the portabledevice (IBUS). This value is updated continuously whilethe device is in the Active power state.

21h Port 1 Charge Rationing Threshold Low Byte


FFh 53

22h Ration Configuration R/W Controls Charge Ration Functionality 11h 54

23h Port 2 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC Mode Region 2) for Port 2

96h 55

24h Port 1 Current Limit Behavior R/W Controls the Current Limiting Behavior (CC Mode Region 2) for Port 1

96h 56

FDh Product ID R Stores a fixed value that identifies each product

E3h 57

FEh Manufacturer ID R Stores a fixed value that identifies Microchip 5Dh 57

FFh Revision R Stores a fixed value that represents the revision number

81h 57

TABLE 8-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Register Address

Register Name R/W FunctionDefault Value

Page No.

REGISTER 8-1: PORTS 2 AND 1 CURRENT MEASUREMENT REGISTERS (ADDRESSES 00H AND 01H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CM(x)<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CM(x)<7:0>: Port X Current Measurement, where x = 2 or 1 (address 00h for Port 2 and address 01h for Port 1).

Note 1: The bit weights are in mA,1 LSB = 13.3 mA (maximum value is 255 LSB corresponding to 3.4A).

2: This data will be cleared when the device enters the Sleep state. This data will also be cleared whenever the port power switch is turned off (or any time that VBUS is discharged).


UCS2114

8.2 Status Registers

The Status registers store bits that indicate the state ofthe ALERT# pins and if the ports operate in ConstantCurrent mode.

REGISTER 8-2: PORT STATUS REGISTER (ADDRESS 02H)

R-0 R-0 R-0 R-0 U-0 U-0 R-x R-x

ALERT1_PIN ALERT2_PIN CC_MODE1 CC_MODE2 — — — —

bit 7 bit 0

Legend:



bit 7 ALERT1_PIN: Reflects the status of the ALERT#1 pin. This bit is set and cleared as the ALERT#1 pin changes states.

1 = ALERT#1 Pin asserted (logic low)0 = ALERT#1 Pin not asserted

bit 6 ALERT2_PIN: Reflects the status of the ALERT#2 pin. This bit is set and cleared as the ALERT#2 pin changes states.

1 = ALERT#2 Pin asserted (logic low)0 = ALERT#2 Pin not asserted

bit 5 CC_MODE1: Port 1 Constant Current mode state

1 = Port 1 in Constant Current mode0 = Port 1 operating normally

bit 4 CC_MODE2: Port 2 Constant Current mode state

1 = Port 2 in Constant Current mode0 = Port 2 operating normally

bit 3-0 Unimplemented


UCS2114

REGISTER 8-3: INTERRUPT STATUS 2 REGISTER (ADDRESS 03H)

R/W-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

ERR2 DISCH_ERR2 RESET KEEP_OUT2 TSD_HIGH OV_VOLT BACK_V2 OV_LIM2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read


bit 7 ERR2: Error Port 2 - Indicates that an error was detected on the VBUS2 pin and the device has entered the Error state. Writing this bit to ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2114 returns to the Active state. This bit is set automatically by the UCS2114 when the Error state is entered. If any other bit is set in the Interrupt Status 2 register (03h), the device will not leave the Error state.

This bit is cleared automatically by the UCS2114 if the Auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN2 control is disabled (Note 1).

1 = Port 2 in Error state0 = Port 2 in Active state (no errors detected)

bit 6 DISCH_ERR2: Discharge Error Port 2 - Indicates the device was unable to discharge Port2. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.

1 = UCS2114 was unable to Discharge VBUS20 = No VBUS2 discharge error

bit 5 RESET: Indicates that the UCS2114 has just been reset and should be reprogrammed. This bit will be set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pins are not asserted when this bit is set. This data is retained in the Sleep state.

1 = UCS2114 has just been reset0 = Reset did not occur

bit 4 KEEP_OUT2: Port 2 Minimum Keep-Out region - Indicates that the V-I output on the VBUS2 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.

1 = VBUS2 < VBUS_MIN0 = VBUS2 > VBUS_MIN

bit 3 TSD_HIGH: Indicates that the internal temperature has exceeded TTSD_HIGH threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted and the device to enter the Error state.

1 = Internal die temperature has exceeded TTSD_HIGH0 = Internal die temperature has not exceeded TTSD_HIGH

bit 2 OV_VOLT: VS Overvoltage indicates that the VS voltage has exceeded the VS_OV threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted and the device to enter the Error state.

1 = VS > VS_OV0 = VS < VS_OV


UCS2114

bit 1 BACK_V2: Back-Bias Voltage Port 2 - Indicates that the VBUS2 voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.

1 = VBUS2 > VS, or VBUS1 > VDD by more than 150 mV.0 = VBUS2 voltage has not exceeded the VS and VDD voltages by more than 150 mV.

bit 0 OV_LIM2: Overcurrent Limit Port 2 - Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings for VBUS2. This bit will be cleared when read if the error condition has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the Error state.

1 = Current Limit for Port 2 exceeded0 = Current Limit for Port 2 not exceeded

Note 1: Note that the ERR2 bit does not necessarily reflect the ALERT#2 pin status. The ALERT#2 pin may be cleared or asserted without the ERR2 bit changing states.

REGISTER 8-3: INTERRUPT STATUS 2 REGISTER (ADDRESS 03H) (CONTINUED)


UCS2114

REGISTER 8-4: INTERRUPT STATUS 1 REGISTER (ADDRESS 04H)

R/W-0 R/C-0 R-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0

ERR1 DISCH_ERR1 VS_LOW KEEP_OUT1 TSD_LOW — BACK_V1 OV_LIM1

bit 7 bit 0

Legend:



bit 7 ERR1: Error Port 1 - Indicates that an error was detected on the VBUS1 pin and the device has entered the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS2114 returns to the Active state. This bit is set automatically by the UCS2114 when the Error state is entered. If any other bit is set in the Interrupt Status 1 register (04h), the device will not leave the Error state. This bit is cleared automatically by the UCS2114 if the auto-recovery fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN1 control is disabled (Note 1).1 = Port 1 in Error state0 = Port 1 in Active state (no errors detected)

bit 6 DISCH_ERR1: Discharge Error Port 1 - Indicates the device was unable to discharge Port1. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = Device was unable to Discharge VBUS10 = No VBUS1 discharge error

bit 5 VS_LOW: Indicates that the VS voltage has fallen below the VS_UVLO threshold and both VBUS1 and VBUS2 port power switches are held off. This bit is cleared automatically when the VS voltage is above the VS_UVLO threshold.1 = VS voltage has fallen below the VS_UVLO0 = VS voltage is above VS_UVLO

bit 4 KEEP_OUT1: Port 1 Minimum Keep-out region - Indicates that the V-I output on the VBUS1 pin has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = VBUS1 < VBUS_MIN0 = VBUS1> VBUS_MIN

bit 3 TSD_LOW: Indicates that the die temperature has exceeded the TTSD_LOW threshold and it is still abovethe TTSD_LOW - TTSD_LOW_HYST. This bit is cleared automatically when the die temperature is belowthe TTSD_LOW -TTSD_LOW_HYST. This bit will not cause the corresponding ALERT#1 and/orALERT#2 pins to be asserted and ERR1 and/or ERR2 bits to be set unless:

• a power switch operates in Constant Current mode

• PWR_EN1 and/or PWR_EN2 controls transition from inactive to active


1 = Internal die temperature has exceeded TTSD_LOW 0 = Internal die temperature has not exceeded TTSD_LOW

bit 2 Unimplemented: Read as '0'

bit 1 BACK_V1: Back-Bias Voltage Port 1 - Indicates that the VBUS1 voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = VBUS1 > VS, or VBUS1 > VDD by more than 150 mV0 = VBUS1 voltage has not exceeded the VS and VDD voltages by more than 150 mV


UCS2114

bit 0 OV_LIM1: Overcurrent Limit Port 1 - Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings for VBUS1. This bit will be cleared when read if the error condition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the Error state.1 = Current Limit for Port 1 exceeded0 = Current Limit for Port 1 not exceeded

Note 1: Note that the ERR1 bit does not necessarily reflect the ALERT#1 pin status. The ALERT#1 pin may be cleared or asserted without the ERR1 bit changing states.

REGISTER 8-4: INTERRUPT STATUS 1 REGISTER (ADDRESS 04H) (CONTINUED)


UCS2114

REGISTER 8-5: GENERAL STATUS 2 REGISTER (ADDRESS 0FH)

R/C-0 U-x U-x R-0 R-0 U-x U-x U-x

RATION2 — — CC_MODE2 PWR_EN2_CON — — —

bit 7 bit 0

Legend:



bit 7 RATION2: Indicates the state of Port 2 Rationing. This bit is cleared when read, or cleared automatically when the RATION_RST2 bit is set or the RATION_EN2 bit is cleared.

1 = Port 2 has delivered the programmed mAh of current0 = Port 2 has not delivered the programmed mAh of current


bit 4 CC_MODE2: Indicates whether Port 2 has entered CC mode.

1 = Port 2 is in CC mode0 = Port 2 not in CC mode

bit 3 PWR_EN2_CON: Reflects the PWR_EN2 control state. This bit is set and cleared automatically with the logic expression (PWR_EN2 pin OR PWR_EN2S).

1 = Port 2 Power Enable is set0 = Port 2 Power Enable is clear



UCS2114

REGISTER 8-6: GENERAL STATUS 1 REGISTER (ADDRESS 10H)

R/C-0 U-x U-x R-0 R-0 U-x U-x U-x

RATION1 — — CC_MODE1 PWR_EN1_CON — — —

bit 7 bit 0

Legend:



bit 7 RATION1: Indicates the state of Port 1 Rationing. This bit is cleared when read, or cleared automatically when the RATION_RST1 bit is set or the RATION_EN1 bit is cleared.

1 = Port 1 has delivered the programmed mAh of current0 = Port 1 has not delivered the programmed mAh of current


bit 4 CC_MODE1: Indicates whether Port 1 has entered CC mode.

1 = Port 1 is in CC mode0 = Port 1 not in CC mode

bit 3 PWR_EN1_CON: Reflects the PWR_EN1 control state. This bit is set and cleared automatically with the logic expression (PWR_EN1 pin OR PWR_EN1S).

1 = Port 1 Power Enable is set0 = Port 1 Power Enable is clear



UCS2114

8.3 Configuration Registers

The Configuration registers control basic devicefunctionality. The contents of these registers areretained in Sleep.

REGISTER 8-7: GENERAL CONFIGURATION 2 REGISTER (ADDRESS 11H)

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 U-1 U-0

ALERT2_MASK — DSCHG2 PWR_EN2S DISCHG_TIME<1:0> — —

bit 7 bit 0

Legend:



bit 7 ALERT2_MASK: Mask errors for all interrupts in Register 8-3 except OV_LIM2 and TSD.

1 = The ALERT#2 pin will only assert if a OV_LIM2 or TSD is detected0 = The ALERT#2 pin will be asserted if an error condition or indicator event is detected

bit 6 Unimplemented

bit 5 DSCHG2: Forces the VBUS2 to be reset and discharged when the UCS2114 is in the Active state and the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic ‘1’ will cause the port power switch to be opened and the discharge circuitry to activate and discharge VBUS. Actual discharge time is controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus master after the forced VBUS discharge.

1 = VBUS2 discharge initiated0 = Port 2 not in discharge

bit 4 PWR_EN2S: Power Enable Port 2 override - This bit is OR’ed with the PWR_EN2 pin. Thus, if the polarity is set to active-high, either the PWR_EN2 pin or this bit must be ‘1’ to enable the port power switch.

bit 3-2 DISCHG_TIME<1:0>: Discharge time - sets tDISCHARGE. The discharge time value is the same for both ports.

00 = 100 ms01 = 200 ms10 = 300 ms11 = 400 ms



UCS2114


R/W-0 U-0 R/W-0 R/W-0 U R/W-0 U-1 U-0

ALERT1_MASK — DSCHG1 PWR_EN1S — EN_VBUS_DISCHG — —

bit 7 bit 0

Legend:



bit 7 ALERT1_MASK: Mask errors for all interrupts in Register 8-4 except OV_LIM1 and TSD.

1 = The ALERT#1 pin will only assert if a OV_LIM1 or TSD is detected0 = The ALERT#1 pin will be asserted if an error condition or indicator event is detected

bit 6 Unimplemented

bit 5 DSCHG1: Forces the VBUS1 to be reset and discharged when the UCS2114 is in the Active state and the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic '1' will cause the port power switch to be opened and the discharge circuitry to activate to discharge VBUS. Actual discharge time is controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus master after the forced VBUS discharge.

1 = VBUS1 discharge initiated0 = Port 1 not in discharge

bit 4 PWR_EN1S: Power Enable Port 1 override - This bit is OR’ed with the PWR_EN1 pin. Thus, if the polarity is set to active-high, either the PWR_EN1 pin or this bit must be ‘1’ to enable the port power switch.

bit 3 Unimplemented

bit 2 EN_VBUS_DISCHG: Enables VBUS discharge circuitry.

If it is '0', it completely disables all the automatic VBUS discharges from happening and allows only manual VBUS discharges (the SMBus master must set and clear DISCHG_LOAD2 and DISCHG_LOAD1 bits from the Current Limit Behavior Registers 23h and 24h). Setting DSCHG2 and DSCHG1 bits from the General Configuration 2 and 1 registers 11h and 12h does not have any effect in this case (Note 1).

If it is '1', the VBUS is discharged automatically as described in Section 6.4 “VBUS Discharge”. The VBUS can be discharged manually by the SMBus master only by setting DSCHG2 and DSCHG1 bits from the General Configuration 2 and 1 registers 11h and 12h. Setting DISCHG_LOAD2 and DISCHG_LOAD1 bits from the Current Limit Behavior registers 23h and 24h doesn't have any effect in this case.


Note 1: When the automatic VBUS discharges are disabled (EN_VBUS_DISCHG is '0'), the UCS2114 will not check that the VBUS voltage is below the VTEST level after the manual VBUS discharges.


UCS2114


R/W-0 U-1 R/W-1 U-x U-x R/W-0 U-0 U-0

PIN_IGN RESERVED DIS_TO — — BOOST — —

bit 7 bit 0

Legend:



bit 7 PIN_IGN: Ignores the PWR_EN1 and PWR_EN2 pin states when determining the power state. This bit is retained in Sleep.

1 = PWR_EN1 and PWR_EN2 pin states are ignored.0 = Power state is determined by the OR'd combination of the PWR_EN1 and PWR_EN2 pins states

and the corresponding PWR_EN1S and PWR_EN2S bit states.

bit 6 Reserved: Do not change

bit 5 DIS_TO: Disable Time Out - Disables the SMBus time out feature.

1 = Time out disabled0 = Time out enabled


bit 2 BOOST: Indicates that the IBUS current is higher than IBOOST on VBUS1 or VBUS2 (bit is OR’ed).

1 = IBUS has exceeded IBOOST on either or both ports0 = IBUS is less than IBOOST on either port individually

bit 1-0 Unimplemented: Read as ‘0’


UCS2114

8.4 Current Limit Register

The Current Limit register controls the ILIM used by theport power switch. The default setting is based on theresistor on the COMM_ILIM pin and this value cannotbe changed to be higher than hardware set value. Thecontents of this register are retained in Sleep.

REGISTER 8-10: CURRENT LIMIT REGISTER (ADDRESS 14H)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — ILIM_PORT1<2:0> ILIM_PORT2<2:0>

bit 7 bit 0

Legend:




bit 5-3 ILIM_PORT1<2:0>: Sets the ILIM value for Port 1

000 = 0.53A001 = 0.96A010 = 1.07A011 = 1.28A100 = 1.6A101 = 2.13A110 = 2.67A111 = 3.2A

bit 2-0 ILIM_PORT2<2:0>: Sets the ILIM value for Port 2

000 = 0.53A001 = 0.96A010 = 1.07A011 = 1.28A100 = 1.6A101 = 2.13A110 = 2.67A111 = 3.2A


UCS2114

8.5 Auto-Recovery Register

The contents of this register are retained in Sleep.

The Auto-Recovery Configuration register sets theparameters used when the Auto-Recovery faulthandling algorithm is invoked. Once the Auto-Recoveryfault handling algorithm has checked theovertemperature and back-drive conditions, it will setthe ILIM value to ITEST and then turn on the port powerswitch and start the tTST timer. If, after the timer hasexpired, the VBUS voltage is less than VTEST, then it isassumed that a short-circuit condition is present andthe Error state is restarted for Auto Recovery.

REGISTER 8-11: AUTO RECOVERY CONFIGURATION REGISTER (ADDRESS 15H)

R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0

LATCHS TCYCLE<2:0> TTST<1:0> VTST_SW<1:0>

bit 7 bit 0

Legend:



bit 7 LATCHS: Latch Set - Controls the fault-handling routine that is used in the case that an error is detected.

1 = Error state will be latched. In order for the UCS2114 to return to normal Active state, the ERR bitmust be cleared by the user.

0 = The UCS2114 will automatically retry when an error condition is detected.

bit 6-4 TCYCLE<2:0>: Defines the delay (tCYCLE) after the Error state is entered before the Auto-Recovery fault handling algorithm is started as shown below.

000 = 15 ms001 = 20 ms010 = 25 ms011 = 30 ms100 = 35 ms101 = 40 ms110 = 45 ms111 = 50 ms

bit 3-2 TTST<1:0>: Retry Duration timer - Sets the tTST as shown below

00 = 10 ms01 = 15 ms10 = 20 ms11 = 25 ms

bit 1-0 VTST_SW<1:0>: Short-circuit voltage threshold VTEST that must be crossed during retries to declare the short removed

00 = 250 mV01 = 500 mV10 = 750 mV11 = 1000 mV


UCS2114

8.6 Total Accumulated Charge Registers

The Total Accumulated Charge registers store the totalaccumulated charge delivered from the VS source to aportable device. The bit weighting of the registers isgiven in mAh. The register value is reset to 00_00honly when the RATION_RST bit is set or if theRATION_EN bit is cleared. This value will be retainedwhen the device transitions out of the Active state andresumes accumulation, if the device returns to theActive state and charge rationing is still enabled.

These registers are updated every one (1) secondwhile the UCS2114 is in the Active power state. Everytime the value is updated, it is compared against thetarget value in the Charge Rationing Thresholdregisters. This data is retained in the Sleep state.

REGISTER 8-12: PORT2 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESSES 16H, 17H, 18H AND 19H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC2<25:18>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC2<17:10>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC2<9:2>

bit 15 bit 8

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

TAC2<1:0> — — — — — —

bit 7 bit 0

Legend:



bit 31-6 TAC2<25:0>: Total Accumulated Charge Port 2 - Each LSB of this 26-bit value equals 0.00367 mAh



UCS2114

REGISTER 8-13: PORT1 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESSES 1AH, 1BH, 1CH AND 1DH)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC1<25:18>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC1<17:10>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TAC1<9:2>

bit 15 bit 8

R-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

TAC1<1:0> — — — — — —

bit 7 bit 0

Legend:



bit 31-6 TAC1<25:0>: Total Accumulated Charge Port 1 - Each LSB of this 26-bit value equals 0.00367 mAh



UCS2114

8.7 Charge Rationing Threshold Registers

The Charge Rationing Threshold registers set themaximum allowed charge that will be delivered to aportable device. Every time the Total AccumulatedCharge registers are updated, the value is checkedagainst this limit. If the value meets or exceeds thislimit, the RATION(1/2) bit is set and action takenaccording to the RATION_BEH1<1:0> andRATION_BEH2<1:0> bits.

REGISTER 8-14: PORT 2 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESSES 1EH AND 1FH)


CT2<15:8>

bit 15 bit 8


CT2<7:0>

bit 7 bit 0

Legend:



bit 15-0 CT2<15:0>: Charge Rationing Threshold Port 2 - Each LSB of this 16-bit value equals 3.76 mAh

REGISTER 8-15: PORT 1 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESSES 20H AND 21H)


CT1<15:8>

bit 15 bit 8


CT1<7:0>

bit 7 bit 0

Legend:



bit 15-0 CT1<15:0>: Charge Rationing Threshold Port 1 - Each LSB of this 16-bit value equals 3.76 mAh


UCS2114

REGISTER 8-16: RATION CONFIGURATION REGISTER (ADDRESS 22H)


RTN_EN1 RTN_RST1 RTN_BEH1<1:0> RTN_EN2 RTN_RST2 RTN_BEH2<1:0>

bit 7 bit 0

Legend:



bit 7 RTN_EN1: Charge Ration Enable Port 1 - Enables Charge Rationing for Port 1.

1 = Charge Rationing enabled0 = Charge Rationing disabled. The Total Accumulated Charge registers for Port 1 will be cleared to

00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registershave already reached the Charge Rationing threshold, the applied response will be removed as ifthe charge rationing had been reset. This will also clear the RATION1 status bit (if set).

bit 6 RTN_RST1: Port 1 Ration Reset - Resets the charge rationing functionality for Port 1.

1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, theRATION1 status bit will be cleared and, if there are no other errors or active indicators, theALERT#1 pin will be released.

0 = Normal operation. This bit must be cleared to enable charge rationing

bit 5-4 RTN_BEH1<1:0>: Ration Behavior Control bits - Controls how the UCS2114 responds when the Ration Threshold has been exceeded (as shown in Table 6-2).

00 = Report01 = Report and Disconnect10 = Disconnect and SLEEP11 = Ignore

bit 3 RTN_EN2: Charge Ration Enable Port 2 - Enables Charge Rationing for Port 2.

1 = Charge Rationing enabled0 = Charge Rationing disabled. The Total Accumulated Charge registers for Port 2 will be cleared to

00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registershave already reached the Charge Rationing threshold, the applied response will be removed as ifthe charge rationing had been reset. This will also clear the RATION2 status bit (if set).

bit 2 RTN_RST2: Port 2 Ration Reset - Resets the charge rationing functionality for Port 2.

1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, theRATION2 status bit will be cleared and, if there are no other errors or active indicators, theALERT#2 pin will be released.

0 = Normal operation. This bit must be cleared to enable charge rationing.

bit 1-0 RTN_BEH2<1:0>: Ration Behavior Control bits - Controls how the UCS2114 responds when the Ration threshold has been exceeded (as shown in Table 6-2).

00 = Report01 = Report and Disconnect10 = Disconnect and SLEEP11 = Ignore


UCS2114

8.8 Current Limit Behavior Registers

The Current Limit Behavior register stores the valuesused by the applied current limiting mode (Trip or CC). The contents of this register are not retained in Sleep.

REGISTER 8-17: PORT 2 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 23H)


SEL_VBUS2_MIN<1:0> DISCHG_LOAD2 SEL_R2_IMIN2<2:0> Reserved Reserved

bit 7 bit 0

Legend:



bit 7-6 SEL_VBUS2_MIN<1:0>: Define the VBUS_MIN voltage for Port 2 as follows:00 = 1.50V01 = 1.75V10 = 2.0V11 = 2.25V

bit 5 DISCHG_LOAD2: Connects the internal 100Ω load to discharge VBUS2 (Note 1). The SMBus master must set this bit to discharge VBUS2 if the EN_VBUS_DISCHG bit from the General Configuration 1 register (address 12h) is '0'. This functionality doesn't use any timer. The discharge time is controlled by the SMBus master, which must clear this bit when its internal timer expires. The difference from DSCHG2 bit from the General Configuration 2 register (address 11h) is that, when that bit is set, the discharge time is controlled by the UCS2114 internal timer.

The state of this bit is ignored when the EN_VBUS_DISCHG bit from the General Configuration 1 register (address 12h) is '1'.

bit 4-2 SEL_R2_IMIN2<2:0>: Defines the IBUS_R2MIN current000 = 100 mA001 = 530 mA010 = 960 mA011 = 1280 mA100 = 1600 mA101 = 2130 mA

bit 1-0 Reserved: Do not change

Note 1: If the corresponding power switch is still turned on (PWR_EN2 control is active) while DISCHG_LOAD2 bit is set, the internal 100Ω load will be connected in parallel with the load on the VBUS2 pins.


UCS2114

REGISTER 8-18: PORT 1 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 24H)


SEL_VBUS1_MIN<1:0> DISCHG_LOAD1 SEL_R2_IMIN1<2:0> Reserved Reserved

bit 7 bit 0

Legend:



bit 7-6 SEL_VBUS1_MIN<1:0>: Define the VBUS_MIN voltage for Port 1 as follows:

00 = 1.50V01 = 1.75V10 = 2.0V11 = 2.25V

bit 5 DISCHG_LOAD1: Connects the internal 100Ω load to discharge VBUS1 (Note 1). The SMBus master must set this bit to discharge VBUS1 if the EN_VBUS_DISCHG bit from the General Configuration 1 register (address 12h) is '0'. This functionality doesn't use any timer. The discharge time is controlled by the SMBus master, which must clear this bit when its internal timer expires. The difference from DSCHG1 bit from the General Configuration 1 register (address 12h) is that, when that bit is set, the discharge time is controlled by the UCS2114 internal timer.

The state of this bit is ignored when the EN_VBUS_DISCHG bit from the General Configuration 1 register (address 12h) is '1'.

bit 4-2 SEL_R2_IMIN1<2:0>: Defines the IBUS_R2MIN current

000 = 100 mA001 = 530 mA010 = 960 mA011 = 1280 mA100 = 1600 mA101 = 2130 mA

bit 1-0 Reserved: Do not change

Note 1: If the corresponding power switch is still turned on (PWR_EN1 control is active) while DISCHG_LOAD1 bit is set, the internal 100Ω load will be connected in parallel with the load on the VBUS1 pins.


UCS2114

8.9 Product ID Register

The Product ID register stores a unique 8-bit value thatidentifies the UCS device family.

8.10 Manufacture ID Register

The Manufacturer ID register stores a unique 8-bitvalue that identifies Microchip Technology Inc.

8.11 Revision Register

The Revision register stores an 8-bit value thatrepresents the part revision.

REGISTER 8-19: PRODUCT ID REGISTER (ADDRESS FDH)

R-1 R-1 R-1 R-0 R-0 R-0 R-1 R-1

PID<7:0>

bit 7 bit 0

Legend:



bit 7-0 PID<7:0>: Product ID for the UCS2114

REGISTER 8-20: MANUFACTURER ID REGISTER (ADDRESS FEH)

R-0 R-1 R-0 R-1 R-1 R-1 R-0 R-1

MID<7:0>

bit 7 bit 0

Legend:



bit 7-0 MID<7:0>: Manufacturer ID for Microchip

REGISTER 8-21: REVISION REGISTER (ADDRESS FFH)

R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-1

REV<7:0>

bit 7 bit 0

Legend:



bit 7-0 REV<7:0>: Part Revision


UCS2114

NOTES:


UCS2114

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

Example 3 x 3 mm VQFN, 20-lead

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

U411707256


UCS2114

BA

0.05 C

0.05 C

0.08 C A B0.05 C

(DATUM B)(DATUM A)

CSEATING

PLANE

1

2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

1

2

N

0.10 C

0.08 C

Microchip Technology Drawing C04-421 Rev C Sheet 1 of 2

2X

20X

For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging

Note:

20-Lead Very Thin Plastic Quad Flat, No Lead Package (LXX) - 3x3x0.9 mm Body [VQFN]No Exposed Pad

D

E

(A3)

A

A1

e

20X b

L2

LTERMINAL 1

INDEX CHAMFER

4

5

6 7 9 10

11

12

L4

L5

L3


UCS2114

Number of Terminals

Overall Height

Terminal Width

Overall WidthTerminal Length

Terminal Thickness

Pitch

Standoff

UnitsDimension Limits

A1A

b

A3

e

LE

N0.50 BSC

0.203 REF

0.25

0.20

0.800.00

0.25

0.30

0.850.02

3.00 BSC

MILLIMETERSMIN NOM

20

0.35

0.30

0.900.05

MAX

REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1.2.3.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.Package is saw singulatedDimensioning and tolerancing per ASME Y14.5M

20-Lead Very Thin Plastic Quad Flat, No Lead Package (LXX) - 3x3x0.9 mm Body [VQFN]


Note:

No Exposed Pad

Overall Length D 3.00 BSC

Terminal Length L2 0.58 0.63 0.68Terminal Length L3 0.33 0.38 0.43Terminal Length L4 0.41 0.46 0.51Terminal Length L5 0.16 0.21 0.26


20-Lead Very Thin Plastic Quad Flat, No Lead Package (LXX) - 3x3x0.9 mm Body [VQFN]No Exposed Pad


UCS2114

1

2

20


Note:

20-Lead Very Thin Plastic Quad Flat, No Lead Package (LXX) - 3x3x0.9 mm Body [VQFNNo Exposed Pad

C1

X1

C3

X3

Y1

C4

Y3

SILKSCREEN

EXPOSED METAL SOLDER STENCIL OPENINGS

EV

X2

FILLED THERMAL VIAS OVERLAY

G1

CH

THERMALVIASØV

C12

C42

C32

CH

UNEXPOSEDTHERMALVIA PAD

C22

EV

Y2

PACKAGE FOOTPRINT

CONTACT PADS

C2

E E

HATCHED AREAS REPRESENTSOLDER STENCIL OPENINGS

ON EXPOSED METAL TRACES




UCS2114

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled to avoid solder loss duringreflow process

1.

2.


Note:

20-Lead Very Thin Plastic Quad Flat, No Lead Package (LXX) - 3x3x0.9 mm Body VQFNNo Exposed Pad

RECOMMENDED LAND PATTERN & SOLDER STENCIL OPENING

Dimension LimitsUnits

C2Contact Pad Spacing

Contact Pitch

MILLIMETERS

0.50 BSCMIN

EMAX

2.90

Contact Pad Length (X19)Contact Pad Width (X20)

Y1X1

0.500.25

NOM

C1Contact Pad Spacing 2.90

Solder Stencil Opening Y3 0.45

Thermal Via Diameter (X6) VThermal Via Pitch EV

0.350.60

Contact Pad to Center Pad (X10) G1 0.20Chamfer (X8) CH 0.10

Solder Stencil Opening X3 0.25

Thermal Via Pad WidthThermal Via Pad Length Y2

X21.132.00

C3Solder Stencil Opening SpacingC4Solder Stencil Opening Spacing 2.85

2.85


UCS2114

APPENDIX A: REVISION HISTORY

Revision A (June 2017)

• Original Release of this Document.


UCS2114

NOTES:


UCS2114

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: UCS2114: USB Dual-Port Power Switch and Current Monitor

Tape and Reel Option:

T = Tape and Reel(1)

Version: 1 = SMBus address 57h

Temperature Range: V = -40°C to +105°C (Various)

Package: LX = Very Thin Plastic Quad Flat, No Lead Package - 3x3x0.9 mm (VQFN), 20LD

PART NO. –X /XX

PackageTemperatureRange

Device

[T](1)

Tape and Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identi-fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

Examples:

a) UCS2114-1-V/LX: SMBus address 57h,Various temperature, 20LD 3x3 VQFN package

b) UCS2114T-1-V/LX: Tape and Reel,SMBus address 57h,Various temperature, 20LD 3x3 VQFN package

–X

Version


UCS2114

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

== ISO/TS16949==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2017, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-1793-4

DS20005743A-page 68


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11/07/16

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Documents

UCS2114 USB Dual-Port Power Switch and Current …ww1.microchip.com/downloads/en/DeviceDoc/20005743A.pdf• Configurable Per-Port BC1.2 VBUS Discharge Function • Wide Operating Temperature