7/23/2019 UCSD CSE140 HW1 FA2015

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Homework #1

CSE140 Fall 2015

Prof. Tajana Simunic Rosing

1. In class we talked about how two-input NAND gate works at the CMOS level. In this

assignment you will analyze two-input CMOS gate the same way. Fill out the tablebelow. PA, PB are pMOS transistors whose gates are connected to signal A & B,

respectively, while NA, NB, are the nMOS transistors with A & B gate connections. For

each transistor indicate if it is ON or OFF for a given input combination A & B, and also

provide the logic output. Note that in the figure below Vdd = logic 1, Gnd = logic 0, and

output Y is connected to PB, NA & NB, while PA is connected to Vdd and PB.

A B PA PB NA NB Y

0 0

0 1

1 0

1 1

7/23/2019 UCSD CSE140 HW1 FA2015

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2. Simplify the following boolean expressions using Boolean algebra.

Label each step with the name of the Boolean theorem that you applied.

i) xy + zy + zy + xii) (xy)(x + x)(y +x)

3. Design a logical function X1 * X2 + (X3 * X4) * X5using NAND gates and inverters only.

Your NAND gates can only have 2 inputs. Do not simplify.

4. Design a logical parity checker circuit: The circuit receives 3-bit data input (a2, a1, a0)

and produces 1-bit output y which represents the parity of the input data. The output

should be equal to zero if the number of ones in the input data is even, and it should be

equal to 1 otherwise. For example,

If (a2, a1, a0)=(1,0,1) then y=0

If (a2, a1, a0)=(1,0,0) then y=1

Show the truth table, boolean equation for the circuit and draw your circuit.

Dont simplify the boolean equation. You can usegates with multiple inputs.