ULTIMATE Design Review

ULTIMATE Design Review

Outline STAR Pixel Sensor Evolution

MIMOSA-26 Design

ULTIMATE Design & Optimisation Pixel, Discriminator, Auxilliary Functional Blocks

Analog Characterization

Summary

Designers : G. Bertolone, C. Colledani, A. Dorokhov, W. Dulinski, G.Dozière, A. Himmi, Ch. Hu-Guo, F. Morel, H. Pham, I. Valin, J. Wang Test engineers : G. Claus, M. Gelin, M. Goffe, K. Jaaskelainen, M. Specht

IPHC [email protected] 206/12/2010 Design ReviewSTARSTAR

STAR PIXEL Detector

A 3 (+ 1) steps evolution: 2007: A 3 plans telescope has been constructed

Sensor:MimoSTAR-2, 5x5 mm2, analogue outputSubmitted Q2 2005

2012: A engineering prototype detector with limited coverage will be installedSensor: PHASE-1: 2x2 cm2, binary output, NO Zero suppression Submitted Q3 2008 + V2 in Q3 2009

2010: EUDET Telescope DeliverySensor: Mimosa26: 1x2 cm2, binary output, Zero suppression Submitted: Q4 2008 + HRes Q4 2009 Toward ULTIMATE

2013: The pixel detector composed with 2 layers will be installedSensor: ULTIMATE: 2x2 cm2, binary output, Zero suppression


MIMOSA-26: Sensor for EUDET Beam Telescope

IRFU - IPHC [email protected] 821-25/09/2009 TWEPP 2009

MIMOSA26: 1st MAPS with Integrated Ø

Pixel array: 576 x 1152, pitch: 18.4 µm

Active area: ~10.6 x 21.2 mm2

In each pixel:

Amplification

CDS (Correlated Double Sampling)

1152 column-level discriminators

offset compensated high gain preamplifier followedby latch

Zero suppression logic

Memory management

Memory IP blocks

Readout controller

JTAG controller

Current Ref.

Bias DACs

Row sequencer

Width: ~350 µm

I/O PadsPower supply PadsCircuit control PadsLVDS Tx & Rx

CMOS 0.35 µm OPTO technology

Chip size : 13.7 x 21.5 mm2 Testability: several test points

implemented all along readout path

Pixels out (analogue)

Discriminators

Zero suppression

Data transmission

Reference Voltages Buffering for 1152 discriminators

PLL, 8b/10b optional

Main characteristics of MIMOSA26 sensor: Column // architecture with in-pixel Amp & CDS and end-of-col. discrimination, followed by Ø

Active area: 21.2×10.6 mm² ,1152 x 576 pixels, pitch: 18.4 µm sp. < ~ 4 µm

Read out time < ~100 µs (104 frames/s) suited for ~ 5 105 particles/cm²/s Yield ~ 90% (75% fully functional sensors thinned to 120 µm + 15% (showing one bad row or column)) Thinning yield to 50 µm ~ 90%

Collaboration with IRFU/Saclay


ULTIMATE based on MIMOSA-26 sensor

Half reticle 1152 x 576 pixel matrix Integration time ~ 100 µs

Pixel Pitch: 18.4 µm Temperature ~ 20 °C Light power consumption constrains: power

consumption ~ 270 mW/cm2

Space resolution < ~ 4 µm No constrains on radiation tolerance

Full reticle 960 x 928 pixel matrix Longer integration time ~ 200 µs

Pixel pitch: 20.7 µm Temperature: 30 - 35 °C Power consumption: target ~ 100 mW/cm² Space resolution < 10 µm 150 kRad / yr & few 1012 Neq /cm² /yr

Optimisation

20240 µm

2271

0 µ

m

3280

µm

21560 µm

1378

0 µ

m MIMOSA26 ULTIMATE


ULTIMATE Design and Optimization (1)

Reduction of power dissipation Optimisation of pixel pitch v.s. non ionising radiation tolerance

Larger pitch: 18.4 µm 20.7 µm Shorter integration time: 185.6 µs

Validated by the small prototype MIMOSA-22AHR Optimisation of power consumption

Power supply voltage reduced from 3.3 to 3 V in ULTIMATE simulation Design of pixel tested at 3V (in MIMOSA-22TER) with adjusted Vcl= 1.9 V:

7% increased ENC, 15% decreased gain

Estimated simulation power consumption ~ 150 mW/cm² (at 3.3 V )135 mW/cm2 (at 3 V)

Pixel improvement: charge collection, radiation tolerance High resistivity EPI substrate and radiation tolerance design

Validated by the small prototype MIMOSA-22AHR

Discriminator timing diagram optimization Threshold non-uniformity reduction

On-chip voltage regulator design for pixel clamping voltage Interferences minimisation on critical nodes

Zero suppression circuit (SuZe) adapted to STAR condition Higher hit density larger memories Higher output frequency (80 160 MHz)

Enhanced testability

MIMOSA-22AHR


ULTIMATE Design and Optimization (2)

- level Discriminators

Zero

Pad Ring

3280

µm

20240 µm

Pixel Array

Zero Suppression

PLLJTAGBias-DAC Seq.Ctrl

Ro

w S

equ

ence

r ~

365

µm

wid

th

2271

0 µ

m

Column-level Discriminators

Mem.1Mem. managementVDDA

REG.VDDA REG.

Re

f.Buf

.

Temp

Outputs PadsAnalog read-out ~ 220 µm width

Mem.2

928 rows x 960 columns

Pitch: 20.7 µm

Active area: ~ 3.8 cm2

Functional block diagram

Pixel array: 928 rows x 960 columns 20.7 µm square pixels Pre-amplification and CDS inside each pixel Column-level offset compensated discriminators Zero-suppression circuit Two output memories

Provided by the AMS foundry Frequency distribution:

Input LVDS clock at 160 MHz All column are readout in parallel at 5 MHz

200 ns /row (16 x 80 MHz)

Two LVDS sparsified data out at 160 MHz On-chip programmable bias-DACs via a JTAG

controller Optional blocks (individuals test blocks)

Internal PLL at 10 MHz On-chip voltage regulator for analogue power supply


ULTIMATE Optimization of Pixel (1)

Pixel Design

For binary readout, it is extremely important to have a correlated double sampling (CDS) and amplification inside pixel

Reduced discriminators threshold variation Noise contribution from clamping voltage

Only NMOS transistors can be used in Pixel Any additional NWELL used to fabricate PMOS

transistor would compete with sensing diode for charge collection

One need to obtain higher amplifier gain Maximized signal-to-noise ratio For standard common source amplifier, special

biasing with transistor M3 for the load transistor M2 increased AC gain by about ~ 2

Adaptive feedback can be used to stabilize the operating point of the amplifier

Working conditions garanteed for every pixel in changing temperatue, irradiation…

Smaller variation of pedestals caused by the CMOS process parameters variation

See Ref. A. Dorokhov et al., ULTIMATE Design Review Documentation, Part I, “Optimisation of Pixel Amplifier Design”

4 digital control signals per row: PWR_On, Slct_Row, Slct_Gr, Clamp

Slct_Row (16CK), PWR_On (2x16CK), Slct_Gr (16x16CK): power activate signals

Clamp: signal for CDS (3CK)

1 column split into 58 groups of 16 pixels Reduced SW capacitances

Current consumption: < ~ 60 µA/pixel

N_Well Diode

amplifier CDS

Output Buffer

Slct_Row

16 p

ix

Slct_Gr

Slct_Row

16 p

ix

Slct_Gr

Slct_Row

Slct_Row

Slct_Row

Column-levelDiscriminator

RD

CALIB

LATCH

Slct_Row

~ 2 cm long!!!



Pixel Optimization Different pixel amplifiers and sensing diodes were implemented in MIMOSA-22AHR

The pixel layout is optimized to have better radiation tolerance The feedback transistor (M4) is replaced by its ELT variant

Common source amplifier Cascode amplifierTwo stage amplifier

Biasing via diode

Two stage amplifier

Biasing via transistor

Amplifiers implemented in MIMOSA-22AHR (clamping not shown)



Different classes of amplifiers:1. Cascode 2. Common source3. two stage (source follower AC coupled

to cascode)4. amplifiers with load in source (without

feedback)

Geometry variation:1. Nwell diode2. Pitch3. Length of transistors' gate4. ELT transistors

MIMOSA-22AHR contains:

Different substrates:- epi layer of 14 µm and low resistivity (< 20 Ω.cm)- epi layer of 10, 15 and 20 µm and high resistivity (< 400 Ω.cm)



Calibration peak for different chips, implemented in different substrate, measured at different clock frequencies, temperatures and irradiation

S7 (blue line, common source) has quite small gain variation for all measurements compared to green line (cascode)


Track reconstruction efficiency as function of fake hit rate, measured at 20C and 100 MHz

Track reconstruction efficiency as function of fake hit rate, measured at 30C and 100 MHz

Beam test results

Optimized layout:

reduced parasitics and cross-talk

MIMOSA-26 layout


Pixel schematic S7 has been chosen for ULTIMATE


ULTIMATE Optimization of Discriminator (1)

Discriminator design

Small input signal Offset compensated amplifier stages

A/D conversion time = row readout time (200 ns)

Low current consumption ~ 70 µA/discri

See Ref. Y. Degerli et al, IEEE, Trans. Nucl. Sci. vol.52, No. 6, pp. 3186-3193, Dec. 2005

During the RD phase: Sample the pixel signal (VRD) and its offset voltage Sample the threshold voltage (VRef1) Sample the offset voltage of the gain stages A2 and A3 (both input offset and output offset storage)

During the CALIB phase: Sample the pixel voltage (VCALIB) and correct its offset Sample the common-mode voltage of the threshold voltage (VRef2) Amplify the signal (VRD-VCALIB) and the threshold voltage (VRef1-VRef2) and feed to the latch

During the LATCH phase: Compare the pixel signal (VRD-VCALIB) to the threshold voltage (VRef1-VRef2), then give a logic level

RDVclp_d

LATCH

RD

RD

CALIB

CALIB

VRef1

VRef2

To Pixel

Vclp_d

RD

RD

RDLATCH

Q

Q

A1 A2 A3

Column-level Double Sampling (DS)

reduce pixel to pixel dispersion (FPN)

Clamp

PWRON

RD (Ф1)

CALIB (Ф2)

fCK

200 ns

LATCH (Ф3)

Pixel readout sequence


ULTIMATE Optimization of Discriminator (2)d

isc

rim

inat

or

dis

cri

min

ato

r

dis

cri

min

ato

r

960 discriminators

Pixel Array

~2 cm

buffers

Reference voltages (threshold) and clamping voltage are applied to 960 discriminators (~ 2 cm long)

Have to consider RC distribution line + successive charge rejections Even an ideal source cannot provide stable references

Need stable voltages during “RD“ and “CALIB” periods (~ 30 ns) The discriminator row is divided into 4 groups 4 bias DACs to compensate process dispersions of discriminators

Group of 240 discris

A


B


D


C

Reference buffers

V_disc_ref1DV_disc_ref1CV_disc_ref1BV_disc_ref1A

V_disc_ref2

Pixel array

V_disc_clp

See Ref. I.Valin et al., ULTIMATE Design Review Documentation, Part II, “Optimisation of Discriminator Design”



Discriminator timing diagram optimisation Threshold non-uniformity reduction

S1’

S2

S2’

S1

Vref1

Vref2

S4’ _b

S4

_b

C1’

C1

A

Vin

S3

_b

S3'

A A A

SF

Vr 2

Vr2

+

- + -

+

- + -

+

- + -

+

- - +

_b

Vx Vz Vy- +∆V1

+ -

Vc1

+-∆V2

+-C2

C2’

-+∆V3

Vc2

1 (RD)

(RD) 1_b

Delay = trRD - tfRD

Obtained timing diagram due to long track:

- Mimosa26 test results: Threshold dispersion of 1152 discriminators (divided in 4 groups)

- It doesn't disturb chip operation if threshold is set to be higher than the dispersion

Due to the delay, ex. charge injections by S3, S4 cannot be compensated by the auto 0 phase

No. of discriminators

1 (RD)

2 (CALIB) 3 (LATCH)

(RD) 1_b

Ideal timing diagram:

1 (RD:S1-S1')

2 (CALIB) 3 (LATCH)

(RD:S3-S3')1a_b

(RD:S4-S4')1b_b

Optimised timing diagram: (validated by a proto)

Sub-array/Freq.=80 MHz

TN (µV) FPN (µV)

A 422 140

B 401 323

C 398 723

D 404 535



Optimized discriminator timing diagram Validated in the small prototype MIMOSA-22AHR

128 discriminators Additional functionality

RD signal is delayed of 3 ns compared to RD signal RD signal is delayed of 3 ns compared to RD signal No delay

Threshold dispersion as a function of the discriminator number

for three different pixel rows

When RD signal is delayed compared to RD signal, the threshold dispersion can be reproduced in the small prototype

In Ultimate sensor, the RD signal will be delayed compared to the RD signal to remove the systematic threshold dispersion

RD

RD


ULTIMATE Auxilliary Functional Blocks (1)

Pixel Array

VDiscriRef1A VDiscriRef1B VDiscriRef1C

PADS

Mu

ltip

lexe

r R

ow

Pix

Analog readoutB

uffe

rsP

ow

er

Pul

se

LVDS Rx LVDS Tx

VDiscriRef2A VDiscriRef2B VDiscriRef2C

VDiscriRef1D

VDiscriRef2D

Discriminators

A B C D

VT

ES

T1

VDiscriClp

i_ana_buf

i_lvds_rx

i_lvds_tx

Sources of Pixel SFi_pix

i_pwrs_bias

i_bufbias

Clamping Voltage

V_

pix

_cl

p

Inte

rfa

ces

i_disc_pwrs2

i_disc_pwrs1

i_disc1

i_disc2

V_disc_ref1DV_disc_ref1CV_disc_ref1BV_disc_ref1A

V_disc_ref2

V_tst1

V_tst2

V_disc_clp

VDiscriRef1AVDiscriRef1BVDiscriRef1CVDiscriRef1D

VDiscriRef2AVDiscriRef2BVDiscriRef2CVDiscriRef2D

IDIS1

IDIS2

Current Ref.

DAC+ interfaces

i_pix

i_disc1

i_disc2

V_tst1

V_tst2

V_disc_ref1A

V_disc_ref1D

V_disc_ref1C

V_disc_ref1B

V_disc_ref2

V_disc_clp

i_bufbias

i_disc_pwrs2

i_disc_pwrs1

i_pwrs_bias

i_lvds_rx

i_lvds_tx

Bias-DACs

V_pix_clp

Ctrl Pixel + SuZe

VTEST2

i_ana_buf

Bias synthetic block diagram

On-chip programmable bias-DACs via a JTAG controller

8 bit current DAC Range: 0 - 255 µA, Step= 1 µA Good linearity

Current Reference IRef = 1 µA PSRRVDDA < - 50 dB, Power consumption ~ 300 µA

Temp. variation = 7.3 nA/°C Reference voltages circuit for the discriminator

VRef2 DAC range: 0.5 V – 1.5 V, Step = 10 mV VRef1 DAC range: -32 mV / +32 mV, Step = 250 µV

On-chip voltage regulator for pixel clamping Adjustable output voltage by an internal 4 bit DAC No external compensation scheme

LVDS Pads LVDS transmitter

Can be set at high impedance by JTAG access The current can be adjusted by DAC

LVDS receiver Can be disable by JTAG access The current can be adjusted by DAC

Most of these blocks have already been implemented and tested in many successive chips as PHASE1, MIMOSA-26…

See ULTIMATE Design Review Documentation, Part III, “Auxilliary Functional blocks”



Reference voltages circuit

The VRef1 voltage is built from the VRef2 voltage

Reduced process dispersions

Monte-Carlo simulation Sigma of the threshold voltage (VRef1-

VRef2) ~ 4 mV Sigma of the threshold voltage after

buffer ~ 7 mV Near 100% of the chips could be

adjustable by the DAC

IRef2*R2VREF2

A1

1

IRef1R1VREF2VREF1

Iref2

V_disc_ref2

R2

R1

Iref1A

V_disc_ref1AReference

buffer

+

-

A+

-VDiscriRef1A

R1

Iref1B

V_disc_ref1BReference

buffer

+

-

A+

-VDiscriRef1B

R1

Iref1C

V_disc_ref1CReference

buffer

+

-

A+

-VDiscriRef1C

R1

Iref1D

V_disc_ref1DReference

buffer

+

-

A+

-VDiscriRef1D

Reference buffer

+

-

VDiscriRef2B

Reference buffer

+

-

VDiscriRef2C

Reference buffer

+

-

VDiscriRef2D

Reference buffer

+

-

VDiscriRef2A

DAC

DAC

DAC

DAC

DAC



cz

RA

RB

c1

Vbg

Vbias

Vdd

Vclamp

Mz

Msf2

Error amplifier Series RC network

Level shift buffer

Output stage

mc

MpwVfb

Ib Iv

Vv

To Pixel Array & Column-level Discriminators

VDDD

Bias DAC

Regulator

V_clp

VDDA

Digital circuit

Bias-DAC

Regulator

V_clp

Digital circuit

Schematic of regulator INT_LN : Low Dropout (Vin = 3 - 3.3 V)Characteristics: Dropout voltage: ~ 0.3V, PSRR: ~ 40 dB, Noise: < 1 µV/sqrt(Hz) (at 10 KHz), Power consumption: <~ 1mW Absolute noise contribution from buffer as a function of pixel noise

with external Vcl

The voltage Vcl can be supplied externally (EXT) or generated in the chip

On-chip voltage regulators for pixel clamping have been implemented in MIMOSA22-AHR Two different versions of circuits have been tested: INT and INT_LN The contribution if noise from internal buffer has small value (<10%) and can be reduced using filter

capacitance of few nF (estimated parasitic capacitance on the Vcl line)

ENC for different amplifier structures (S#)


ULTIMATE Analog Characterization

Mode 1: Analog readout of entire matrix at low frequency (20 MHz)

The matrix is divided in stripes of 8 columns and fully scanned at each frame, then swapped with the next block of 8 columns at right and so on until all the columns are analyzed.

Mode 2: Analog readout of 8 pre-

selected columns at nominal speed (80 MHz)

8 pre-selected columns are chosen in the middle of the chip and connected directly to the 8 output pads.

8 output pads


Summary The design of ULTIMATE has been optimized:

Pixel design (schematic + layout): cross-talk, parasitic capacitances, radiation tolerance beam-test and lab test to choose the optimal version

Discriminator timing diagram: Reduced threshold dispersion

Digital control circuit: power consumption speed

Design Status: Simulation of all blocks performed and functionalities verified Schematic and Layout: DRC and LVS passed Mixed-Simulation to verify whole chip (Analogue + Digital Part) Layout parasitic extraction to estimate possible degradation in worst case due to under estimated

parasitic interconnects between blocks In case of not sufficient performance, interconnect will be easily optimized to finalize the chip

Preliminary verification (DRC and Size for fabrication) made by CMP

Submission Plan: The 9 th of December: Modifications following the common design review recommandations Until the 17th of December: Verification at IPHC and at CMP From 18th of December to 3nd of January: Laboratory is officially closed Until the 14th of January: Verification The 17th of January: Submission


BACKUP


Actual Status

Functional verification full chip Analog block


Power Dissipation

M26 Current

A 170 mA

D 60 mA

LVDS 20 mA

Pixel pitch (µm)

Pixels Discris Buffer Ref.

DAC Digital LVDS Total Power (mW/cm2)

20.7

(960 col.)

At 3 V

57.6 mA 67.2 mA 18 mA 7 mA 50 mA 20 mA

170 mW 200 mW 50 mW 20 mW 150 mW 60 mW* 650 140

Chip area: 4.6 cm2

*4 transmitters, 1 receiver

ULTIMATE Current

A 142 mA

D 50 mA

LVDS 20 mA

Total current: 212 mA 152 mW/cm2 at 3.3 V 138 mW/cm2 at 3.0 V


MIMOSA-22AHR

calibration peak

400

500

600

700

800

900

1000

1100

(9) S

TD 1

5°

(12)

STD 6

.101

2 15

°

(2) H

R10 1

5°

(13)

HR10

6.1

012

15°

(10)

HR15

15°

(6) H

R15 1

5°

(6) H

R15 3

0°

(7) H

R15 3

.101

2 15

°

(7) H

R15 3

.101

2 30

°

(11)

HR15

3.1

012

15°

(20)

HR15

1E13

15°

(11)

HR15

3.1

012

30°

(20)

HR15

1E13

30°

(11)

HR15

3.1

012+

150k

15°

(11)

HR15

3.1

012+

150k

30°

(8) H

R15 1

5°

(8) H

R15 3

0°

(8) H

R15 1

50k 1

5°

(8) H

R15 1

50k 3

0°

(14)

HR15

15°

(14)

HR15

30°

(14)

HR15

300

k 15°

(14)

HR15

300

k 30°

(4) H

R20 1

5°

(16)

HR20

6.1

012

15°

(16)

HR20

6.1

012

30°

S6

S7

S8

S9

S10

S11

S12

S13

S14


Discriminator


Discriminator

Vin- Vin+

Vo+ Vo -

ib=10µA

VDD

R=1/gm

Vi1

LATCH

Vi2

LATCH

LATCH

X Y YX

VDD

Moderate gain ~ 4 Well defined output common-mode non linear gain

Dynamic latch No static power consumption Good speed, switching time ~ 2ns Dedicated lines and pads for the

supply and ground voltages

42

5 µ

m

20.7 µm


Current Reference


Reference Voltages Circuit


LVDS Transmitter


LVDS Transmitter

Process tm ws wp

Delay (ns) 1.45 1.87 1.10

Duty cycle (%) 49.8/50.2 49.5/50.5 49.9/50.1

Current consumption (mA) 4.6 4 5.9

Common-mode voltage(V) 1.184 1.182 1.1715

Differential swing (mV) +/- 300 +/- 265 +/- 400

Main characteristic in nominal condition T= 30°C, VDD = 3V, ilvds_tx= 40 µA, Cload = 10 pF)


Nominal condition, T= 30°C, VDD=3V, tm, Vdiffpp = 200 mV, vcm = 1.2 V

T= 125°C, VDD = 2.7 V, Vdiffpp = 200 mV

Nominal condition 30 °C, 3V, tm

Ilvds_rx (#UDAC) (µA) 32

Rise time (ns) 0.89

Fall time (ns) 0.60

Delay (ns) 2.5

Duty-cycle (%) 52-48

Vhyst (mV) 29.4

process tm ws wp

Ilvds_rx (#UDAC) (µA) 22 21 22

Vhyst (mV) 32.8 37 29.2

Duty-cycle (%) 46-54 49-51 50-50

Delay (ns) 3.45 4.32 2.4

Range of vcm (V) 0.5-2.2 0.85-1.9 0.25-2.4

LVDS Receiver

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ULTIMATE Design Review