Ultra Low Power General Purpose Microcontroller

Dale G. Wilson, Richard L. Chaney, and Douglas R. Hackler American Semiconductor, Inc.

3100 S. Vista Ave., Ste 230, Boise, ID, USA, Phone: 208-336-2773 www.americansemi.com

Abstract: An ultra low power general purpose microcontroller platform is designed to operate at 0.5V with 50MHz performance. The potential dynamic power savings can be up to 13X of similar microcontrollers operating at 1.8V. The power and performance improvements are achieved using the 130nm Flexfet double gate CMOS process.

Keywords: ultra low power, CMOS, Flexfet, microcontroller, Space Plug-and-Play

Introduction Microcontrollers are among the most versatile products in the semiconductor market. The microcontroller market was forecast to exceed $16 billion in worldwide sales in 2011. Also, compound annual growth is predicted to be above 9 percent over the next five years. [1] Within the microcontroller markets, ultra low power (ULP) has become increasingly important in both the commercial and military/aerospace markets. Reduced power consumption creates new opportunities for applications that must operate for long periods on small batteries or alternatively operate from solar cells or other energy scavenging methods.

Commercial microcontrollers have been built to operate at low voltage. However, these typical offer relatively low performance - for example, limited to 1MHz at 0.9V [2]. Or, alternatively, they use internal boost converters to translate the low supply voltage up to higher voltage for internal operation – for example, 0.7V is translated up to 3.0V [3]. Limitations in the voltage and performance are largely driven by the physics of the single gate CMOS processes employed to build these microcontrollers.

Flexfet Double Gated CMOS Development of an ultra low voltage, low power, and high performance microcontroller requires a breakthrough in the underlying technology. American Semiconductor’s patented double gate Flexfet SOI CMOS process provides opportunities for these breakthroughs. [4] The double gate Flexfet transistors have a steeper subthreshold slope which enables higher performance at lower operating voltage. [5]

Figure 1 illustrates the significant power and performance advantages the 130nm Flexfet process provides over a comparable 130nm bulk CMOS process. Simulations of ring oscillators were used to enable direct comparisons of the underlying technology. In this figure, it can be seen that the 130nm Flexfet double gate process technology provides lower voltage and power while also operating at higher frequencies.

Figure 1: Comparison of Flexfet Power and

Performance versus Bulk

American Semiconductor has demonstrated the ultra low power capabilities of Flexfet double gate CMOS with an energy scavenging application that required no external power supply as shown in Figure 2. The waveform on the oscilloscope is created by a Flexfet ring oscillator on the wafer power only by the ambient room light. [6]

Figure 2: Flexfet Ultra Low Power CMOS Demo

ULP Microcontroller Platform Architecture The block diagram of Figure 3 demonstrates an ULP general purpose microcontroller platform enhanced with some specified blocks required to implement a SPA-1 ASIC. While targeted primarily to meet the needs of satellites employing the SPA-1 communication protocol, this microcontroller will be suitable for a wide range of other general purpose applications, particular for space environments due to the radiation hardening employed.

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DG Flexfet IDG Flexfet - HP Bulk CMOS

Lower Voltageand Power

Faster

Figure 3: Block Diagram of General Purpose Microcontroller Platform Configured for SPA-1 ASIC

The Space Plug-and-play Avionics (SPA) initiative is designed to improve the ability of the US military to rapidly respond to changing operational needs. The goal is creation, integration, and launch of new spacecraft in less than one week. [7] This would provide major benefits to war fighters on the ground, in the sky, and at sea. SPA was named a 2010 Hot Technology Contest Winner for the Air Force. [8] A SPA-based satellite requires plug-and-play capabilities that extend from the hardware down to the interface electronics as illustrated in Figure 4. For the Air Force to fully benefit from the SPA initiative, new microelectronics that implement the SPA protocols and standards must be developed to address the low power, high performance and radiation requirements of space.

The SPA system is based on an interface-driven set of standards intended to promote the rapid development of spacecraft busses (platforms) and payloads. SPA is an open systems framework. It combines commercial standards, such as USB and I2C, with specific hardware and software extensions to support real-time embedded systems (e.g. fault tolerance, power delivery, and self-description). [7]

The ideal SPA-1 ASIC is a general purpose microcontroller that also implements the SPA protocols are fundamental building blocks for development of these plug-and-play satellites. In the SPA satellite framework, the SPA-1 devices provide a fully integrated solution to the lowest layer of network connection (Figure 5).

Figure 4: CubeSat Employing SPA Networks [7]

The SPA-1 components using I2C as the transport interface will likely be the most proliferated endpoint for connection to the satellites’ many sensors and actuators. Thus, the implementation of these SPA-1 devices must minimize size, weight and power without sacrificing performance. The versatility and small form factor of a microcontroller are also obviously beneficial for the SPA-1 applications.

SPA CubeSat

SPA Plug-and-Play Component

SPA Interface Module

Figure 5: SPA-x Distribution of Components

within a Satellite [9]

Low Power PIC CPU The PIC Low power (picL) CPU is a modified version of a PIC16F84A microprocessor core implemented in the 0.5V Flexfet library. Synthesis of the microprocessor core using Incentia DesignCraft and targeting the 130nm Flexfet double gate standard cell library indicated that high performance was achievable for the picL CPU. Figure 6 illustrates the typical CPU frequency as a function of supply voltage.

Figure 6: Synthesis Performance Results for picL

CPU in ULP Flexfet

For final implementation, the picL CPU has been upgraded with an improved memory interface, the ability to support the single cycle peripheral access via the Wishbone bus interface, and the addition of a Watch Dog Timer (WDT) instruction. Furthermore, debug capability has been integrated into the CPU core for on chip debugging and code development. This will allow easy code modification via a debug interface which interfaces to any personal computer with a serial interface.

Peripheral Features All microcontroller peripherals are accessed through the Wishbone interface bus. Wishbone Bus is open source bus protocol. [10] Within this microcontroller platform, the Verilog Wishbone bus generator supports a multi-layer, multi-master system architecture with up to 16 slave peripherals. Single cycle master access to peripherals including SRAM is supported via the Wishbone bus.

During Phase I of the SBIR program, a preliminary version of the SPA-1 ASIC architecture including picL CPU core was synthesized at 50MHz into the 130nm Flexfet double gate standard cell library. Using only 3 metal layers for interconnect, the digital section of the design was only 1.4mm x 1.4mm as shown in Figure 7. The design included 14,504 standard cell components and 14,987 signal nets. Silvaco Spider was employed for the place and route and Silvaco AccuCore was used for the static timing analysis.

Figure 7: Synthesis Performance Results for picL

CPU in ULP Flexfet During the current Phase II SBIR program, American Semiconductor has developed both low voltage SRAM and ROMs. Figure 8 shows the corner details of the SRAM. For radiation hardening against single event upset, the SRAM has 8k x 16 data bits plus 5 parity bits for error detection and correction (EDAC). The EDAC using Hamming coding supports automatic correction of single bit errors and detection of 2 bit errors. Each bit within a word is separated by 114μm to minimize the likelihood of single radiation events affecting multiple bits in a single word. The total size of the SRAM is 2540μm x 3350μm. The SRAM with EDAC will be the critical timing path for CPU operation.

Very low data rate (< 10 kilobit/sec)SPA ‐1 

low data rate (< 1 Mbit/sec) SPA‐U

high data rate (< 620 Mbit/sec)

SPA‐ S

Very high data rate “SPA‐ Optical”

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Figure 8: ULP Radiation Hardened Flexfet SRAM - View of Corner Showing Details

The 1k x 16-bit ROM is 375μm x 450μm and is shown in Figure 9. The ROM does not include EDAC.

Figure 9: Flexfet ROM

Summary Building microcontroller prototypes using high levels of integration with the ultra low power Flexfet technology will allow design methodologies to be established for a wide variety of applications. Besides space applications, the ultra low power benefits offered by the Flexfet technology and the range of size/power/performance supported by the proposed prototypes would lend themselves to other military and commercial applications, especially those that are powered via batteries or environmentally derived power sources such as solar cells or other energy scavenging mechanisms. The platform based approach will allow American Semiconductor to efficiently create future microcontroller derivatives targeted to meet specific program needs for both terrestrial and space applications.

Acknowledgements American Semiconductor, Inc. would like to acknowledge the support of Air Force Research Laboratory for this on-going work under the “High Performance, Ultra Low Power SPA-1 ASIC for Space Plug-and-Play Avionics” Phase II SBIR program.

References 1. “Microcontroller Market Forecasted to Reach Over

$16 billion worldwide in 2011,” electronics.ca publications, Jan. 18, 2011. http://tinyurl.com/6p9slyq

2. MSP430L092 datasheet, Texas Instruments, http://www.ti.com/lit/ds/symlink/msp430c092.pdf

3. ATtiny43U datasheet, Atmel, http://www.atmel.com/dyn/resources/prod_documents/doc8048.pdf.

4. US Patents 6580137, 6919647, 7015547, 7019342, 7154135, 7154135, and 7518189. Other US and foreign patents pending.

5. B. Meek, et al, “Flexfet CMOS for ULP Electronics,” GOMACTech 2009, 16-19 March 2009.

6. “Flexfet Ultra Low Power (ULP) CMOS Demo,” http://www.youtube.com/watch?v=xm_nA03oEb0

7. J. Lyke, et al, “Space Plug-and-Play Avionics,” 3rd Responsive Space Conference, April 2005.

8. 2010 Hot Technologies Contest Winners, DoD Tech Match, http://www.dodtechmatch.com/DOD/TECHAD/INDEX.ASPX

9. J. Lyke, “Bringing the Vision of Plug-and-play to High-Performance Computing on Orbit” HPEC 2009, Sept. 2009.

10. “Wishbone B4: WISHBONE SoC Interconnection Architecture for Portable IP Cores,” OpenCores, 2010. http://cdn.opencores.org/downloads/wbspec_b4.pdf