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6/5/2008 1

Understanding the new '5xx Integrated Power Management Module (PMM)Stefan Schauer

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Agenda

• Introduction into the PMM System• Technical Data, specified Values• Software controlled PMM configuration• Power considerations• System Protection• Summary

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Power Management Module (PMM)• 5xx-Core (CPU, Memory, …) uses a low voltage – can’t accept the higher

voltage range required at system level (Unlike pre-5xx)• Therefore an internal LDO generates VCORE rail from DVcc• Modules reside primarily in DVcc or VCORE domains• DVcc:

– 1.8 - 3.6V (Same input range as 2xx/4xx)• VCORE:

– System-programmable to 1.35V/1.55V/1.75V/1.85V according to MCLK requirements

– Only external Capacitor is required for VCORE(470nF)

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PMM Highlights

• PMM has sub-units that provide “supervision” and “monitoring”– “Supervision” generates POR if low-voltage event

occurs– “Monitoring” provides interrupts on event occurrence

• VCC is the “high-side” of LDO, VCORE is “low-side”• Still have zero-power BOR, similar to 4xx• Accurate voltage supervision for cost of 100nA!

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PMM Supervision Features

• DVCC and VCORE both have:– Programmable supervision/monitoring (SVS/SVM) levels– Software-selectable POR and power-fail conditions

• SVM (Supply Voltage Monitor)– Generates interrupt if voltage goes above/below programmable

threshold– Applies to both DVcc and VCORE

• SVS (Supply Voltage Supervisor)– Generates POR if voltage goes below programmable threshold– Applies to both DVcc and VCORE

• BOR (BrownOut Reset) – Minimum VCORE threshold reset– Less precision than SVS, but also less power

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BOR / POR / PUC

• BOR– Resets all SFR bits associated

with BOR [-0,-1]

• POR– Resets all SFR bits associated

with POR (-0,-1)

• PUC– Resets all SFR bits associated

with PUC -0,-1

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5xx Operational Modes

• LPM0/1/2/3/4 are the same as previous families• LPM5

– Same as LPM4, except LDO/core are powered down– RAM/register contents are not retained– Wakeup with RST/NMI pulse– Future 5xx Devices will also get wakeup for Port pins

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Supervision/Monitoring

• Flags automatically set/cleared according to rail state• SVM, SVS, BOR are working hand in hand• POR event generated as well

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Agenda

• Introduction into the PMM System• Technical Data, specified Values• Software controlled PMM configuration• Power considerations• System Protection• Summary

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High side SVS/SVM

• The high side SVS/SVM is used for system voltage observation• SVM provides an early warning and gives the system some time to go

into a safe state– Shut down critical tasks– Reduce current consumption so that the system may recover– Save parameters

• Default operation:– SVSH on in Active and LPM0 mode– SVSH off in LPM2/3/4

1.5

1.6

1.7

1.8

1.9

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2.1

2.2

2.3

2.4

2.5

SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM

Vcore = 0 Vcore = 1 Vcore = 2 Vcore = 3

Min/Max

TypDVcc(Min)

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Low side SVS/SVM

• The low side SVS/SVM is mainly used safe change of VCORE

• SVM generates flag to indicate when the VCORE level is sufficient high for desired MCLK frequency

• SVS could be used to reset the system in critical applications and ensure only proper execution of instructions

• Default operation:– SVSL on in Active and LPM0 mode– SVSL off in LPM2/3/4

1.2

1.4

1.6

1.8

2

2.2

2.4

SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM SVS- SVS+ SVM

Vcore = 0 Vcore = 1 Vcore = 2 Vcore = 3

Min/Max

TypDVcc(Min)

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BOR / POR / PUC Sources

• BOR– Sources:

• Power on / Brownout• RST/NMI• Security violation (protected Memory)• Software (Bit in PMM)• LPM5 wake up

• POR– Sources:

• SVS low/high• Software (Bit in PMM)

• PUC– Sources:

• WDT• Key Violation (WDT, Flash, PMM, …)• Fetch out of Peripheral Area • Software (Bit in PMM)

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LDO for VCORE

• The LDO supplies the required current for the CPU and the digital parts of the device.

• LDO is trimmed for optimized power consumption• Switched mode is automatically used in Low

Power modes to further reduce the power consumption in standby

• Note: It is not allowed to use the VCORE LDO for application purposes!!

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PMMCOREV Levels

Most applications can operate at lowest setting, with no need to alter default PMM configurations

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Typical Voltage Profile on VCORE

• Phase 1: 0sec - 25secCPU : switch between LPM and Active mode

• Phase 2: 25sec - 55secADC measurements are done

• Phase 3: 55sec - 90secCPU active all the time

• LDO continuously adapts to the power required by the system

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Agenda

• Introduction into the PMM System• Technical Data, specified Values• Software controlled PMM configuration• Power considerations• System Protection• Summary

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Access to PMM registers (Password)

• PMM Registers are password protected !!!• “General” Password is located in the PMMCTL register• Open PMM with

• Lock PMM with

• When PMM is open all PMM registers are open for write access

• Also for clearing the PMM interrupt flags the PMM needs to be opened (except read of IV Register (e.g. SYSSNIV)

PMMCTL_H = 0xA5;PMMCTL_H = 0xA5;

PMMCTL_H = 0x00;PMMCTL_H = 0x00;

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Recommend Software flow to change VCORE

• Ensures a safe transition of the VCORE voltage during operation mode.

• Set and check the required VCORE Voltage before increasing the CPU frequency

• Increase/decrease VCORE only step by stepVoltage

VCORE

time

SVML

SVSL

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Example: Increasing MCLK from Default to 20MHz• For MCLK>12MHz, must increase VCORE to support higher

speed– Unlock PMM registers– Set SVM to minimum threshold for chosen speed– Change LDO output– Poll SVM output until voltage OK– Disable SVM (if not used) and lock PMM registers

PMMCTL0_H = 0xA5; // Open PMM modulePMMCTL0 = 0xA500 + level; // Set VCoreSVSMLCTL = SVMLE + (level * SVSMLRRL0);// Set SVM new Level while ((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled (Delay)PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flagsif ((PMMIFG & SVMLIFG)) while ((PMMIFG & SVMLVLRIFG) == 0); // Wait till level is reached

PMMCTL0_H = 0x00; // Lock PMM module registers

// Change DCO speed here

PMMCTL0_H = 0xA5; // Open PMM modulePMMCTL0 = 0xA500 + level; // Set VCoreSVSMLCTL = SVMLE + (level * SVSMLRRL0);// Set SVM new Level while ((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled (Delay)PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flagsif ((PMMIFG & SVMLIFG)) while ((PMMIFG & SVMLVLRIFG) == 0); // Wait till level is reached

PMMCTL0_H = 0x00; // Lock PMM module registers

// Change DCO speed here

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Use of provided Macros and Function

• Make your life easy by using the provided functions for setting the PMM

SetVCoreUp (1); // Handles Vcore up………SetVCoreUp (1); // Handles Vcore up………

SetVCore (3);………SetVCore (3);………SetVCore (3); // Handles Vcore up and down………SetVCore (3); // Handles Vcore up and down………

SetVCoreDown (0); // Handles Vcore down………SetVCoreDown (0); // Handles Vcore down………

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Available Flags and interrupt sources

• Status flags from SVS/SVM on low and high side are available

• SVS/SVM provides a Delay interrupt flags which shows that the SVS/SVM has settled after a change (easier software handling)

• Separate Flags for Resets (BOR, POR, PUC) and their sources are available to allow individual power up handling– Different system initialization, e.g. RTC– Power up – System Violation error

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__interrupt void SYSNMI_ISR(void){

PMMCTL0_H = 0xA5; // Open PMMswitch( __even_in_range(SYSSNIV , 0x12)){

case 0x00: break; // No Int. pendingcase 0x02: mSVMLIFG_HANDLER();

break;case 0x04: mSVMHIFG_HANDLER();

break;…case 0x12: mSVMHVLRIFG_HANDLER();

break; default: break;

}PMMCTL0_H = 0x00; // Lock PMM

}

__interrupt void SYSNMI_ISR(void){

PMMCTL0_H = 0xA5; // Open PMMswitch( __even_in_range(SYSSNIV , 0x12)){

case 0x00: break; // No Int. pendingcase 0x02: mSVMLIFG_HANDLER();

break;case 0x04: mSVMHIFG_HANDLER();

break;…case 0x12: mSVMHVLRIFG_HANDLER();

break; default: break;

}PMMCTL0_H = 0x00; // Lock PMM

}

Interrupt Vector Generator Registers

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Agenda

• Introduction into the PMM System• Technical Data, specified Values• Software controlled PMM configuration• Power considerations• System Protection• Summary

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Performance Settings

• SVSH, SVSL, SVMH, SVML each operate in fast or slow modes (individually controllable)

• “Fast” = continuous operation• “Slow” = slower duty cycle driven (switched mode)

– Default– Slower response to under-voltage– Very fast under-voltage spikes may go uncaught (proper

decoupling necessary to catch very fast under-voltage spikes)

100nA~150us / 200usSlow20uA~1usFast

Current drawResponse timeMode

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SVS/SVM Performance Control Mode

• Slow/Fast Mode could be controlled by software or automatically– Default is Slow mode– In Automatic mode the operation mode switches between the

different performance levels of the SVS/SVMSlow: Switched mode of SVS/SVM (slower reaction)Fast: full-performance mode

Manual Mode

Automatic Mode

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Current consumption of separate functions

20 uA100 nA0 nASVM low side

20 uA100 nA0 nASVM high side

20 uA100 nA0 nASVS low side

0 nA(incl. Active/LPMx Modes)BOR

~ 2 uALDO

20 uA100 nA0 nASVS high side

FullSlowOff

Typical Values

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Power Considerations of PMM Modes

• The default setting (slow mode) gives a high reliability with low power consumption.

• Applications requiring highest power reliability could switch the SVS into full performance mode -> continuous observation

• Application less sensitive may switch off the SVS/SVM to get the lowest possible power consumption

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Low Power Modes with LDO switched mode

• No high current is required at the LPM• Decoupling could buffer all the required current

peaks• VCORE is increased automatically to give more

headroom.• For critical application (esp. high Temperature)

keep the quality of the Capacitors in mind.

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Low Power Mode 5 (LPM5)

• LPM5 is LPM4 (same as in 1xx/2xx/4xx) + regulator off• More gates = more leakage, therefore LPM4 current

higher– F449 (60K/2K) LPM4 @ 25C, typ: 0.1uA– FG4619 (120K/4K) LPM4 @ 25C, typ: 0.4uA– F5438 (256K/16K) LPM4 @ 25C, 3V, typ, PMMCOREV=0: 1.0uA

• LPM5 shuts down regulator (and core): 0.1uA (25C, typ)– No RAM retention– Wake up by RST or one of a few I/Os (F5438 is RST only)– I/Os become hi-Z “inputs”– Wake up issues a BOR reset, so execution starts over

Code must handle accordingly!

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Entering LPM5

• LDO operates in all modes except LPM5• LDO shuts off when LPM4 entered while PMMREGOFF bit

set (entering LPM5)• Active clock request delays LDO shutdown• Interrupt occurring between PMMREGOFF=1 & entering

LPM4 clears PMMREGOFF– Especially possible if clock request delays LPM4 entry– Even possible with no clock request unless handled properly!

__disable_interrupt(); // Clears GIEPMMCTL_H = 0xA5; // Open PMMM PMMCTL_L |= PMMREGOFF; // Disable LDO on LPM4 entry__bis_SR_register(LPM4+GIE); // Sets GIE while entering LPM5

__disable_interrupt(); // Clears GIEPMMCTL_H = 0xA5; // Open PMMM PMMCTL_L |= PMMREGOFF; // Disable LDO on LPM4 entry__bis_SR_register(LPM4+GIE); // Sets GIE while entering LPM5

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Agenda

• Introduction into the PMM System• Technical Data, specified Values• Software controlled PMM configuration• Power considerations• System Protection• Summary

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Protect from changing the PMM settings

• A bit in the SYSCTL registers allows the PMM module to be locked, preventing write access

• After setting this bit there is no user write access allowed to the PMMSYSCTL |= SYSPMMPE;

• PMM could still be accessed via the protected BSL segments

• Reset of the PMM protection is only possible with BOR

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I/O Port Behavior in LPM 5

• All I/Os become hi-Z “inputs” when regulator shuts down

• On F5438, wakeup only from RST; edges on I/Os have no effect

• All registers - including port registers - get reset when exiting LPM5

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Summary

• The PMM module is able to provide the required power at the right time

• Default system configuration will meet most of the application requirements

• But for higher system security or lower power consumption the system could be modified by Software

• PMM provides the highest system security ever available in an MSP430

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Thank you