Upload
nguyendang
View
216
Download
1
Embed Size (px)
Citation preview
1
�
Shyama P. Das Department of Electrical Engg.
IIT KanpurE-mail: [email protected]
Unified Power Quality Unified Power Quality Conditioner (UPQC) for Conditioner (UPQC) for
Power Distribution SystemsPower Distribution Systems
�
�� Introduction
� Motivation
� Design, Simulation and Hardware Implementation of
Unified Power Quality conditioner (UPQC)
(Single phase and Three phase)
� Optimum UPQC
� Conclusion and Scope of future research
2
�
Power QualityPower Quality: Measure of proper utilization of power by customers
“Electrical Pollutant” vs “Clean Utility”
� Advent of wide spread use of high power high frequency
switching devices
� Additional System required to maintain quality
� Deregulation, tariff
�
Power Supply Authority
Consumer
Power Quality
�������� ����������
� ������������ ������������������
�� ������� �� ���
3
!
PCC
LOAD
Line Impedance
Polluting Load
VoltageVoltage
���������� ����������� ������������
"����� �#�������#���������������$$���� �%�&���'��������
(
������������������
)��$����#�������*���������#����������� �#�+
, ��%����%��-������+
4
.
Harmonic Polluting Loads
• Computers
• Computer controlled machine tools
• Photo-copying machines
• Various digital controllers
• Adjustable speed drives
• PLCs
• Uncontrolled or phase controlled rectifiers
/
Some Important Observations of Power Quality(PQ) Surveys
� More low r.m.s. voltage sag occur at the PCC
� Majority of voltage sag are 10-20%
� More disturbances occur above 70% of nominal line
voltage
� The occurrence of most severe sag events are least
frequent.
5
0
�"1 ��2345678��74�-4�-�
�+!�4�*���(��9,
�+!�+!��!�:�(��9,
!�(0�9,��#��� �
��;�$�$�7)-
&<'
��;�$�$�6#�*�#�� �)��$���
�$�����&<'
����, ��%��&����, ��%�'
IEEE 519 Voltage Limits
�=
LocalSolution
Load/Equipment
Load/Equipment
Global Solution(Series/Shunt)
PCC
PCC
OTHER LOADS
���������� ������������������
6
��
(a) Providing ‘ride-through’ capability to the equipment so that they can be protected against certain amount of voltage sag and swell
(b) Equipment are provided with an arrangement so that they draw low reactive power and harmonics
(c) Disadvantage of this approach is that it cannot take care of existing polluting installations and further it is not always economical to provide the above arrangement for each and every equipment
��
(a) Here independent compensating devices are installed at PCC so that overall PQ improves at PCC.
(b) Advantages of this approach are
�Individual equipment need not be designed according to PQ standards
�Existing Polluting installations can be taken care of.
7
��
�#���� �����
a)Shunt (parallel) Active Filter (STATCOM)
b) Series Active Filter (DVR)
��
STATCOM ����������������$������
�$��������>�
? ������*��������
? )��$���������
8
�!
STATCOM
�(
9
�.
�747�"��
�/
�747�"�
10
�0
STATCOM Control Strategy
�� ������3���������>����
�=
DVR (Dynamic Voltage Restorer)
����
���
���
��
��
��������>�
? , ��%����%
? , ��%�����$���
11
��
Reactive Power Transfer
Vs2=VL
2-2VLVdvr Sin� +V dvr2
��
In-Phase Compensation
12
��
Phase cum Magnitude Compensation
��
������������� ��� ������ ���������� �����
� Load harmonic and VAR compensation
� Voltage sag mitigation and unbalanced voltage
correction
� Fast dynamic response, and steady state accuracy
� ������������ ���������������� �� ��� ������������ ���������������� �� ��
13
�!
Unified Power Quality Conditioner (UPQC)
�(
�Inverter-I compensates for sag through a tuned filter and voltage transformer
�Inverter-II (SLCVC) Synchronous Link Converter VAR Compensator provides VAR to the load, isolates load current harmonics, makes input power factor unity
�SLCVC maintains the charge of the dc link capacitor
Low PassFilter
Load
SynchronousLink Inductor
Inverter- I Inverter- II
Cdc
Utility supplyInjection
Transformer
is i_load
ic
LSLC
Vinj
14
�.
Phasor diagram of UPQC-Q for fundamental power frequency, when θθθθ <ΦΦΦΦ
Quadrature Compensation UPQCQuadrature Compensation UPQC--QQ
�/
Quadrature Compensation UPQCQuadrature Compensation UPQC--QQ
Where, x is p.u. sag
m = Modulation Index (max MI=1)
and transformer ratio 1:1
1
21
.)2(.22
2/2
22
s
dcinj
ssinj
Vxxm
mVV
VVV
−=
=
−=
��
���
�=θφ
coscos
22 ls II
From power balance
15
�0
�������,4�5�#�%���3�2�:2
Series VA loading of UPQC-Q
0
0.2
0.4
0.6
0.8
1
0 0.1 0.2 0.3 0.4
p.u. Sag
VA
p.u
.
p.f.=0.25
p.f.=0.5
p.f.=0.6
p.f.=0.7
p.f.=8
p.f.=0.9
�=
�����,4�5�#�%���3�2�:2
Shunt VA loading of UPQC-Q
0
0.2
0.4
0.6
0.8
1
1.2
0 0.1 0.2 0.3 0.4
p.u. Sag
VA
p.u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
16
��
�$���#�,4�5�#�%���3�2�:2
Combined Loading of UPQC-Q
00.20.40.60.8
11.21.41.6
0 0.1 0.2 0.3 0.4
p.u. Sag
VA
p.u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
.
��
17
��
Four Modules
� ����������������������������� �����
��!�����������"�����
� � ����������������# $ �%������
& �����"�����'��������� ���������
� ������"������������
(�����������������!�"�"�����"��!����
� �) �������������������# �����%������
& �����������
��Fig.3.15 Block diagram of hardware implementation
Computer
PCL-208Vdc
Vs_peak
v75
vsecv90
DA0DA1
pwmmodulatingsignal ( m3)
is*
[ADC, DAC,Timer, DIO]
AD0AD1
AD2AD3AD4
Vs
SPWM
GateDrive
N-L Load
HysteresisControl
Vs_peak
PeakDetector
Ckt. Filter
Vinj
GateDrive
is
is*
DA0
DA1
is
18
�!
Fig. 3.22 Simulation result of supply and load current corresponding to Fig. 3.21X axis = 5 ms/div Y axis = 5 A/div
Supply current ( is)
Load current (iL)
Fig. 3.21 Experimental result of supply current and load currentX axis : 5 ms/divY axis: 5 A/div
�(
Fig. 3.23 Load current (i_load) spectra (Experimental)0
20
406080
100120
1 5 9 13 17 21 25 29 33 37 41 45 49
Harmonic Number
Rel
ativ
e Pe
rcen
tage
Fig. 3.24 Supply current ( is) spectra (Experimental)
0
20
40
60
80
100
120
1 5 9 13 17 21 25 29 33 37 41 45 49
Harmonic Spectrum
Rel
ativ
e Pe
rcen
tage
19
�.
Fig. 3.25 Experimental results of supply current (is) and supply current reference (is*)X axis : 5 ms/div Y axis: 10 A/div
Fig. 3.26 Simulation results of supply current (is) and supply current reference (is*)X axis : 5 ms/div Y axis: 10 A/div
�/
Fig. 3.27 Experimental result of vL, vs and vsecTrace-1: Load voltage (vL)
y axis : 50 v/divTrace-2: Supply voltage (vs)
y axis : 50 v/divTrace-3: Series injected voltage
(vsec) /38. y axis : 1 v/divx axis : 20ms/div
Fig. 3.28 Simulation result of vL, vs and vsecTrace-1: Load voltage (vL)
y axis : 50v/divTrace-2: Supply
voltage(vs) y axis : 50v/divTrace-3: Series injected
voltage ( vsec) /38. y axis : 1v/div
Load voltage
Source voltage
Injected voltage
20
�0
Fig. 3.29 Load voltage (vL) spectra
0
20
40
60
80
100
120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Harmonic Number
Rel
ativ
e Pe
rcen
tage
THD = 3.6%
�=
Fig. 3.30 Steady state experimental results of DC link voltage (Vdc), supply ( is) and load current ( iL)X axis : 50ms/div Y axis : vdc20V/div, is, iL 5A/div
Dc link voltage (vdc)
Supply current (is)
Load current (i_load)
Fig. 3.31 Steady state simulation results of DC link voltage (Vdc/1000), supply (is) and load current ( iL)X axis : 50 ms/div Y axis : Vdc .1 V/div, iL = 2 A/div , is = 10 A/div
21
��
3-φAC
Source
3-φNon-linearLoad
is
ic
i_load
Vdc
SLCVCSeriesCompensator
Low PassFilter
secv
LSLC
��
Computer
PCL-208 PCL-726
DA0 DA1
vdc
Vs_peaksecv_a
secv_c
secv_bv90-A
v90-B
m1-A m1-BPI-outA(m2-A)
PI-outB(m2-B)
PI-outC(m2-C)
isa* isb
*
ADC,DAC,COUNTERTIMER, DIO
6 ch-DAC, DIO
AD0
AD1AD2AD3AD4AD5
AD6DAC1 DAC2 DAC3
DAC4 DAC5
N Vsb
Vsa
Vsc
SPWM
GateDriver
3-φN-L Load
HysteresisControl
Vs_peak
PeakDetector
Ckt. Filter
secv_a
secv_b
secv_c
GateDriver
isa
isb
isc
isa
isb
isc
m3-( A B C)
5 kHz
isa* isb
* isc*
22
��
isa
i_loada
Fig. 4.20a Experimental results of supply current and load current of phase-AX axis: 50 ms/div, Y axis: 5 A/div for isa, 2 A /div for i_loada
Fig. 4.20b Simulated results of supply current and load current of phase-A
��
Fig. 4.21b Simulated results of supply current and supply voltage of phase-A
Fig. 4.21a Experimental results of supply current and supply voltage of phase-AX axis: 50 ms/div, Y axis: 5A/div for isa, 20 V/div for vsa
23
�!
Load Current (A-phase) Supply current ( A-phase)Harmonicorder
Magnitude % fundamental Magnitude % fundamental
1st 1.645 A 100 2.652 A 100
5th 313.47 mA 19 38.989 mA 1.46
7th 204.86 mA 12.45 19.43 mA 0.73
11th 113.09 mA 6.87 23.4 mA 0.88
13th 80.05 mA 4.86 10.18 mA 0.38
17th 31.43 mA 1.91 16.68 mA 0.62
19th 28.13 mA 1.71 15.76 mA 0.59
23rd 13.674 mA 0.83 12.3 mA 0.46
25th 9.159 mA 0.5 10.1 mA 0.38
THD 23.28% 2.957%
DisplacementFactor
0.768 0.992
�(
Fig. 4.23a Experimental result of peak of supply voltage and load voltage of phase-AX axis: 100 ms/div, Y axis: 50 V/div for v_loada, 10.48 V/div for Vsa_peak,
Peak of supply voltage (A)
Load Voltage (a)
sag
Fig. 4.23b Simulated result of peak of supply voltage and load voltage of phase-A
24
�.
Fig. 4.24b Simulated result of peak of supply voltage and supply current phase-A
Fig. 4.24a Experimental result of peak of supply voltage and supply current of phase-AX axis: 100 ms/div, Y axis: 20.96 V/div for Vsa_peak, 2 A/div for i_loada
�/
Fig. 4.25a Experimental result of peak of supply voltage and injected voltage and supply voltage of phase A, X axis: 10 ms/div, Y axis: 10 V/div for secv_a,50 V/div for vsa, 52.4 V/div for Vsa_peak
Fig. 4.25b Simulated result of injected voltage and supply voltage of phase-A
25
�0
Fig. 4.26b Simulated result of injected voltage and supply voltage of phase-B
Fig. 4.26a Experimental result of peak of supply voltage and injected
voltage and supply voltage of phase-B, X axis: 10 ms/div, Y axis: 50
V/div for vsb, 10 V/div for secv_b,52.4 V/div for Vsa_peak
!=
�,�@����-,����������������������� ��* ��%�
�-,�����$�������*��������
��������%���5�#�,4����������747�"���#�-,�
�����$��������������* ��%����%��#����
Conventional UPQC-P
26
!�
"��������#�����%�&3�2�:�'
!�
�������,4�5�#�%���3�2�:�
Series VA loading of UPQC-P
00.050.1
0.150.2
0.250.3
0.350.4
0 0.1 0.2 0.3 0.4
p.u. Sag
VA
p.u
.
p.f.=0.25
p.f.=0.5
p.f.=0.6
p.f.=0.7
p.f.=0.8
p.f.=0.9
27
!�
�����,4�5�#�%���3�2�:�
Shunt VA loading of UPQC-P
0
0.2
0.4
0.6
0.8
1
1.2
0 0.2 0.4
p.u. Sag
VA
p.u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
!�
�$���#�,4�5�#�%���3�2�:�
Combined Loading of UPQC-P
00.20.40.60.8
11.21.4
0 0.2 0.4
p.u. Sag
VA
p.u
.
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
p.f.=0.5
p.f.=0.25
28
!!
5�$������ ��3�2�:2��
��������3�� ����$���%����* ��%����� ������$�%���#�
�3�� ����$���%����* ��%����� �����������������
�-������$����������* ��%�����
������������� �����$������%�����* ��%����%��#����
������ ����$���%���%�* ��%��$�%���#����� ����
�3�� ����$���%����* ��%����������� ���
!(
,4����$�A�������6@����%�, ��%�������"���$�$�4% �
29
!.
��������������������
-,����� ����#�����@����* ��%����������$�A�#��������% �+
!/
DVR Control Strategy
30
!0
Source voltages during normal and sag condition
Simulation Results
Sag end
Sag start
(=
Load voltages during normal and sag condition
Simulation Results
Sag end
Sag start
31
(�
Case Study (Optimized UPQC)
������������� �!�"�#$$ �%����&�������� '!�"�($)
������������ �!�"�(*$
������*���������������$�����%���$�����
,4�&3�2�:2'�B�=+.��+�+C�&� B��(+.='
� ,4�&3�2�:�'�B�=+(��+�+C�&� B�=='
� ,4�&3�2�:�����#'�B�=+�/��+�+C�&� B���='
(�
1. UPQC can mitigate voltage sag.2. Hybrid (combined analog and digital) control
implemented, the control scheme is applicable for both single phase and three phase.
3. No additional energy storage device required for sag compensation, long duration sags and under voltages can also be compensated.
4. Dynamic response is fast.
32
(�
5. UPQC can supply VAR to the load.
6. It isolates the load current harmonics from flowing to the utility.
7. It maintains input unity power factor at all conditions.8. Optimized UPQC leads to minimum VA loading of the
converters.
(�
� � �� ����$����$����� ����������
� �����������"����������
33
(!