Abstract—This paper presents two modulation methods for current source inverter both in SVPWM point of view: Discontinuous-PWM (DPWM) and Continuous-SVPWM (CSVPWM), and proposed the third method Pulse-Width-Amplitude-Modulation (PWAM), also based on SVPWM theory. Different switching sequences of DPWM are proposed and compared. The Double Fourier Series equations and integration limits for both DPWM and PWAM are given. A THD and switching loss comparison has been conducted between all methods. Simulation results are given for all methods to demonstrate the theory analysis.

Index Terms—Space vector PWM; current source inverter; CSVPWM; DPWM

I. INTRODUCTION

1S 3S 5S

4S 6S 2S

abcinV

3L

2L

2CTo AC Load or Source

Fig.1. Current source inverter

a

ß2 1 2( )I S S

3 2 3( )I S S

4 3 4( )I S S

5 5 6( )I S S

6 5 6( )I S S

1 6 1( )I S S

0

VI

III

III

IV V

8 3 6

3

( )

( )op

I S S

I S7 1 4

4

( )

( )op

I S S

I S

9 5 2

2

( )

( )op

I S S

I S

9 5 2

5

( )

( )op

I S S

I S

8 3 6

6

( )

( )op

I S S

I S

7 1 4

1

( )

( )op

I S S

I Sθ

Fig.2. Space vector PWM for current source inverter

This paper concentrates on the modulation of current source inverter, which is configured as Fig. 1. The space vector control strategy is utilized here which is described explicitly in some papers and the control diagram is shown in Fig.2. In the

0 5 10 3−× 0.01 0.015 0.020

0.5

1

S1 t( )

t Fig.3. Switching waveform of 1S

assumption of the three-phase balanced system, the output current synthesis equation is:

1 1 0 0ref s i i i iI T I T I T I T+ += + + (1) , where 1 0, ,i iT T T+ are the dwell times for the adjacent vectors iI , 1iI + and 0I respectively. And their expressions are as follows:

00 1

3 3sin(60 ) ; sin( ) ;2 2i s i s s i i opT m T T m T T T T T Tθ θ += − ⋅ = ⋅ = − − − (2)

II. DISCONTINUOUS SVPWM AND EQUIVALENT CARRIER-BASED MODULATION [6-17]

A. Selection of zero vector in terms of minimum switching times

TABLE I. SELECTION OF VECTORS IN EACH SECTOR

Sector Sector I Sector II Sector III Sector IV Sector V Sector VI

Vector1 I1 (S6S1) I2 (S1S2) I3 (S2S3) I4 (S3S4) I5 (S4S5) I6 (S5S6)

Vector2 I2 (S1S2) I3 (S2S3) I4 (S3S4) I5 (S4S5) I6 (S5S6) I1 (S6S1)

Vector0 I7 (S1S4) I9 (S2S5) I8 (S3S6) I7 (S1S4) I9 (S2S5) I8 (S3S6)

TABLE II. CONDUCTION TIME FOR S1 AND S4 IN EACH SECTOR

Sector I Sector II Sector III

S1 1 0

S4 0

Sector IV Sector V Sector VI

S1 0

S4 1 0

03 sin(60 )2

m θ−

031 sin(60 )23 sin( )

2

m

m

θ

θ

− −

−

3 sin( )2

m θ

031 sin(60 )23 sin( )

2

m

m

θ

θ

− −

−

03 sin(60 )2

m θ−

3 sin( )2

m θ

In every sector, except the two active vectors, there are three

zero vectors for selection. In order to reduce the switching

Unified Space Vector PWM Control for Current Source Inverter

Qin Lei, Bingsen Wang, Fang.Z. Peng Electrical and Computer Engineering Department,

Michigan State University, East Lansing, USA, leiqin@msu.edu

978-1-4673-0803-8/12/$31.00 ©2012 IEEE 4696

I1 I2 I7 I7 I2 I1

S2

S6S4

S1

S3

S5

I1 I2I7/2

I2 I1

S2

S6S4

S1

S3

S5

I7/2

I7/2

I7/2

I1 I2I7/2

I2 I1

S2

S6S4

S1

S3

S5

I7/2

I7/2

I7/2

Switching times

4

0

2

2

0

0

4

0

4

4

0

0

4

0

2

6

0

0

a b

c

Sector I

I1 I2 I7

S2

S6S4

S1

S3

S5

d

I1 I2 I7

Fig.3. Four different switching sequences in sector I

times, the zero vector with the common switch in two active vectors is selected. For example, in sector I, two active vectors are 6 1S S and 1 2S S , in which the common switch is 1S . So the zero vector 7I which contains 1S is selected so that 1S has no PWM switching in the whole 60 degree region. Similarly, each switch only does PWM switching in every other 60 degree, as shown in Fig. 3. The selection of vectors in each sector is shown in Table I, and the resultant conduction time is in table II.

B. Selection of switching sequence in each sector As long as the Ampere-seconds in one switching period

keeps constant, the sequences of vectors will not affect the output. However, it does affect the output THD and device switching loss. Taking sector I as an example, four switching sequences including symmetrical and unsymmetrical ones are shown in Fig. 3. In these sequences, type a is an unsymmetrical sequence. In order to get the same harmonic performance as the other symmetrical ones, the switching frequency has to be doubled. In this case, the benefits of less switching counts in one switching period can not be hold. Type b seems a good choice since the zero vector 7I connects together, and I1 also connects together with the previous switching period, which reduces the switching counts. However, the zero vectors are all allocated in the middle, so the active vectors are pushed to the edge, not in the middle of every half switching cycle, which may increase harmonics. It can be illustrated by the input current ripple which has been shown as the red line in Fig. 3. The input current will decrease in active state and increase in zero state. Since the zero vectors are connected together, as well as the active vectors, so the current ripple frequency is the same as switching frequency, which results in a double ripple amplitude. These low frequency and high amplitude harmonic contents are directly transferred into output current. Therefore, in the harmonics point of view, this sequence is not preferred. Type c makes an improvement for type b in terms of harmonics, by splitting the zero states into two parts, one of which is placed in the middle, and one of which is put at the side. The input current ripple amplitude changes to half of type b, and in addition, the ripple frequency is doubled, both of which decreases the size of the passive component, as well as lower the output harmonics. This is consistent with the statement

I II

III IV

V VI

t1 t2t0/2

I2 I1

S2

S6S4

S1

S3

S5

t0/2

t0/2

4

0

4

4

0

0

S3

S1S5

S2

S4

S6

4

0

4

4

0

0

S4

S2S6

S3

S5

S1

4

0

4

4

0

0

S5

S3S1

S4

S6

S2

4

0

4

4

0

0

S6

S4

S2

S5

S1

S3

4

0

4

4

0

0

S1

S5S3

S6

S2

S4

4

0

4

4

0

0

t0/2 t1 t2

t0/2

I2 I1t0/2

t0/2

t0/2

t1 t2t0/2

I2 I1t0/2

t0/2

t0/2 t1 t2

t0/2

I2 I1t0/2

t0/2

t0/2

t1 t2t0/2

I2 I1t0/2

t0/2

t0/2 t1 t2

t0/2

I2 I1t0/2

t0/2

t0/2

Fig.4. Switching state in 6 sectors for sequence c

C. Equivalent reference-carrier modulation for DPWM

0 0.005 0.01 0.015 0.02 0.025 0.03 0.03

-0.5

0

0.5

1

Fig.5. References for S1 and S4 and the output line current waveform

that the output harmonics can be minimized by putting the active state in the middle of half switching cycle. Type d inserts each active state into separate zero states. The switching counts maintain the same as type b, but the ripple is unevenly distributed due to the non-middle allocation of active vectors, because of which it doesn’t have the same effect as type c in terms of harmonic reduction. In the practical implementation, the SVPWM control could be transformed into equivalent carrier based control. The reference waveform instantaneous value of the switch is proportional to the corresponding conduction time at that moment t, as shown in Fig. 5, where one is for 1S and one is for 4S . The switching functions generates the output current

aoI in the form of

1 4( )*ao dcI S S I= − (3) For the same output current requirement, there are infinite choices for S1 and S4. The aforementioned references definitely generate a sinusoidal waveform, as the dotted line. However, the switching function characteristics are little bit different from the voltage source inverter modulation carrier. The upper switch and the lower switch on the same phase leg are not necessary complementary to each other, but the three switches on the same half leg must be, like 1 3 5, ,S S S . Thus the PWM generated from reference waveform can not follow the rules that be positive if reference exceeds carrier, and be

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0.0315 0.0317 0.0319 0.0321 0.0323 0.0325-1.5

-1

-0.5

0

0.5

1

T0

T0+T1+T2

T0

T0+T2

T2T2T1 T1

(a) Sequence b

0.04410.04410.04410.04420.04420.04420.04420.04420.04430.04430.044-1.5

-1

-0.5

0

0.5

1

T0/2

T2/2T1/2 T2/2T0/2T0/4 T0/4T1/2

T0/2+T2

T0/2+T2+T1

(b) Sequence c

0.015 0.0151 0.0151 0.0151 0.0151 0.0151 0.0152-1.5

-1

-0.5

0

0.5

1

T0/2

T0/2+T2

T0+T2

T0+T1+T2

(c) Sequence d

Fig.6. PWM implementation for three sequences negative if reference is below carrier. A new group of three references have been designed to generate the correct PWM for CSI, which are proportional to ( 0T ), ( 0T + 2T ) and ( 0 1 2T T T+ + ) respectively. The switches corresponding to the turn on time 0T , 1T and 2T are defined as 0Z , 1Z and

2Z respectively. The new rule is: if the carrier is below reference 0T , 0Z is turned on; if the carrier is between 0T and

0T + 2T , 2Z is turned on; if the carrier is between 0T + 2T and

0 1 2T T T+ + , 1Z is turned on, just like Fig.6(a). Different references and different placement sequences can be used for different switching sequence in Fig.4. But each PWM waveform is generated when the carrier is between two reference waveforms, which make the three PWM for the upper switches complementary. The implementation method for sequence b, c, d are shown in Fig. 6.

D. Numerical Spectrum analysis

1.9 10 4× 2 10 4× 2.1 10 4× 2.2 10 4× 2.3 1×0

0.2

0.4

0.6

Vpn_FFT→⎯ ⎯ ⎯ ⎯

fser (a) Sequence b 33.607 *10WTHD −=

1.9 10 4× 2 10 4× 2.1 10 4× 2.2 10 4× 2.3 10 4×0

0.2

0.4

0.6

Vpn_FFT→⎯ ⎯ ⎯ ⎯

fser (b)sequence c 32.663*10WTHD −=

1.9 10 4× 2 10 4× 2.1 10 4× 2.2 10 4× 2.3 10 4×0

0.2

0.4

0.6

Vpn_FFT→⎯ ⎯ ⎯ ⎯

fser (c)sequence c 33.306*10WTHD −=

Fig,7. Numerical FFT results for b, c, d at m=0.8 for switching frequency range

According to switching state assignment in Fig.4, switching time calculation from equation (2) and the switching waveform implementation in Fig. 6, the numerical switching waveform in one fundamental cycle could be obtained for each DPWM sequence by using equation (3). Set the parameters as: M=0.8,

of =100Hz, sf =20kHz. The spectrum distribution diagrams of each sequence at switching frequency are shown in Fig. 7 (a)(b)(c). The weighted THD has been used to be a criterion for evaluating the total harmonics distortion of each method. The definition of WTHD and results for each sequence are shown in the following:.

12 1 _ 2_ 1

2( ) /

mepn FFT kk

pn FFTkk

VWTHD V

kk

− −

== ∑ (4)

E. Analytical double Fourier analysis An analytical double Fourier series form could also be derived for each sequence in DPWM, according to the rising edge and falling edge time point according to the time duration for each switch at different sector in table II and the detailed PWM arrangement in Fig. 6. Take DPWM sequence b as an example. The double Fourier expression for the DPWM is a sum of the integrations in six sectors since no general equation for the rising and falling edges in terms of angle in six sectors exists, but does in one sector. Equation (5) gives the general double Fourier equation and table IV gives the integration upper limit and lower limit of 1S for sequence b in each sector. However, the FFT analysis target should be the line current, which can be represented by the subtraction of upper switching function to lower switching function in the same phase leg as shown in equation (3), which presents as an ac symmetric waveform. The coefficient of 1( )S t is shown in Table IV. The coefficient of 4 ( )S t is equal to the coefficient of 1( )S t in the sector of 180 degree apart. Thus the phase current double Fourier integration limit is derived and shown in table V. According to the symmetry, the integration could be conducted in the positive half cycle, two times of which is the final coefficient, as shown in equation (6).

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( )( )6( )

21 ( ) ( )

12

fe

s r

x iy ij mx ny

mn mn dcy i x i

A jB I e dxdyπ

++ = ∑ ∫ ∫ (5)

Tale IV. Integration limit of S1 for sequence b i ys(i) ye(i) xr(i) xf(i)

1 0 0

2

3 0 0

4

5 0 0

6

3π

2π

3π 2

3π 1

1

2

2 3 2( sin( ))2 2 3

2

fs

f

Tx m yT

x

π π π

π

= = −

=

23π π

π 43

π 1 22 3 2( ) ( sin( ))2 2 2 3s

T T m yTπ π π+ = − 1 22 3 2( ) 2 sin( )

2 2 2 3ss

T TT m yTπ π π π− − = − ⋅ −

43

π53

π

53

π 2π1

12 3 sin(2 )

2 2rs

Tx m yTπ π π= = − 1 2

12 3 4( ) sin( )

2 2 2 3fs

T Tx m yTπ π π= + = −

12

2 3( ) 2 sin(2 )2 2f s

s

Tx T m yTπ π π π= − = − −

1

12

0;

2 3 2( ) 2 sin( )2 2 3

r

r ss

x

Tx T m yTπ ππ π

=

= − = − ⋅ −

1 22

2 3 4( ) 2 sin( )2 2 2 3r s

s

T Tx T m yTπ π π π= − − = − −

Tale V. Integration limit for Ia(t) of sequence b

i Pulse ys(i) ye(i) xr1(i) xf1(i) xr2(i)

1 0 0

2 0

3 0

4 0

5 0

6

3π 0 2

2 S

TTππ − ⋅

3π 2

3π

23π π

π 43

π

43

π 53

π

53

π 2π

12 ( )2s

TTπ 12 ( )

2ss

TTTπ −

02 ( )2s

TTππ −

0 22 S

TTππ + ⋅

12 ( )2s

TTπ 1 22 ( )

2s

T TTπ + 1 222 ( )

2s

T TTππ +−

02 ( )2s

TTππ +

12 ( )2s

TTπ 122 ( )

2s

TTππ −

12 ( )2s

TTπ 1 22 ( )

2s

T TTπ + 1 222 ( )

2s

T TTππ +−

dcI

dcI

dcI

dcI−

dcI−

dcI−

F. Simulation results A current source inverter with the configuration of Fig.1 is constructed in simulation with the parameters:

100 , 1 , 30 , 1in in o rV V L mH C uF P kW= = = = , 100 ,of Hz= 20sf kHz= Fig. 8 shows the phase a current after the output

0.005 0.01 0.015 0.02-40

-20

0

20

40

t

Ia o

f se

quen

ce B

0.005 0.01 0.015 0.02-40

-20

0

20

40

t

Ia o

f se

quen

ce C

0.005 0.01 0.015 0.02-40

-20

0

20

40

t

Ia o

f se

quen

ce D

Fig.8. Simulated phase a current after the C filter for sequence b, c, d

I1 I2 I2 I1

S2S6S4

S1

S3

S5

Switching times

1

0

1

0

0

0

I

S3

S1S5

S2

S4

S6

Switching times

1

0

1

0

0

0

II

S4

S2S6

S3

S5

S1

Switching times

1

0

1

0

0

0

III

S5

S3S1

S4

S6

S2

Switching times

1

0

1

0

0

0

IV

S6

S4S2

S5

S1

S3

Switching times

1

0

1

0

0

0

V

S1

S5S3

S6

S2

S4

Switching times

1

0

1

0

0

0

VI

I2 I3 I3 I2 I3 I4 I4 I3

I4 I5 I5 I4 I5 I6 I6 I5 I6 I1 I1 I6

Fig.9. Switching state in 6 sectors for PWAM

1S 3S 5S

4S 6S 2S

abc

2L

2CTo AC Load or Source

Fig.10. Conventional CSI for PWAM

capacitor for sequence b, c and d respectively. It is observed that they have the same fundamental rms value, but different switching ripple. Sequence c has lower current ripple than sequence b and d.

III. PULSE-WIDTH-AMPLITUDE-MODULATION (PWAM)

A. Principle of PWAM

1 21 2 0

1 2 1 2' ' ' *(1 / )s s dc m s

T TT T T T I I T T

T T T T= ⋅ = ⋅ = −

+ +； ； (7)

, 1 2', 'T T are new time period for PWAM, 1 2 0, , , sT T T T are the old one from eq.(2); mI is the input current maximum value. PWM methods are all about zero vector selection and zero vector placement. In order to further reduce the switching times, at the same time not affect the output sinusoidal waveform, one method is to eliminate the zero state in each sector, as shown in Fig.9. All zero vectors are eliminated. The switching period for each switch reduces to only 120 degree per 360 degree. Take S1 as an example, it only has PWM switching in sector II and sector VI, so only for 120 degree. The elimination of zero state doesn’t affect the output waveform, but do affect the input current, which can not be a dc current but a dc current with 6ω ac ripple. ω refers to the fundamental frequency. Thus a dc-dc stage or an integrated dc-dc stage like the Z-source network has to be cascaded in front to generate this 6ω current on the dc link, instead of using of single stage inverter. The calculation for new T1’ and T2’ are shown in equation (7).

B. Example 1: PWAM for normal current source inverter with 6ω dc link current For the first example here an ideal 6ω ripple dc current source is utilized for conventional current source inverter as Fig.10. The simulation parameters are: 20 , 20dcm sI A f kHz= = ，

0 100f Hz= . Fig. 11 shows the simulation results for switching function, input and output current before and after

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the filter. It can be observed that, the output current directly utilizes the input current during two 60 degree sections, one positive and one negative. The current after the filter has a little phase shift with input dc current because of the capacitor.

(a)

0 0.005 0.01 0.015 0.02-15

-10

-5

0

5

10

15

(b)

0 0.005 0.01 0.015 0.02-15

-10

-5

0

5

10

15

(c)

Fig.11. Simulation results for PWAM CSI: (a) switching waveform (b) Input dc link current and output one phase current before the filter (c) input dc link

current and output three phase current after the filter

0 200 400 600

0.2

0.4

0.6

Vpn_FFT→⎯ ⎯ ⎯⎯

fser

2.9 104× 3 104× 3.1 104× 3.2 104× 3.3 104×

0.2

0.4

0.6

Vpn_FFT→⎯ ⎯ ⎯ ⎯

fser Fig.12. theoretical output line current in PWAM and Numerical spectrum of output current for PWAM ( 31.414 10WTHD −= × )

apS bpS cpS

anS bnS cnS

ab

c

1L

1C 2L

2C

1D

pnIinL1LI

2LI

inI

aIbIcI

inV

1I

Fig.13. Circuit configuration of current-fed Quasi-Z-Source-Inverter

The theoretical output line current could be calculated by equation (3), which is also shown in Fig.11 (b) the green waveform. A numerical FFT analysis is conducted based on this waveform and the results are shown in Fig. 12.

For the theoretical double Fourier Series form derivation for the output current, the same general equation as (5) has been adopted, but different integration limits are assigned for PWAM. Take 1S as an example. For sector I, the integration limit for x is [0,2 ]π ; for sector III, IV and V, the limit for x is [0,0]; for sector II, the integration limit for x is

1 1[0,2 / ] & [2 2 / ,2 ]s sT T T Tπ π π π− ; for sector VI, integration limit for x is 1 1[2 / , 2 2 / ]s sT T T Tπ π π− . The time range in a certain sector for 4S is the same with the time range of 1S in a sector which is 180 apart from the sector of 4S .The detailed closed-form expression will not be discussed here in detail.

C. Example 2: PWAM for current-fed quasi-Z-source inverter [1-4] The PWAM technique for grid-connected PV inverter can be easily applied in bidirectional current source HEV/EV motor drives. Take current-fed quasi-Z-source inverter [1-2] as an example. One third of inverter output line current is directly generated by the 6ω enveloped pulse-type dc link current through turning on the switches for a whole 60 degree. Instead of controlling the dc link current Ipn to have a constant average value, the open zero state duty cycle will be regulated instantaneously to generate a 6ω fluctuate dc average current, which is overlapped with the output three line current. It is also equivalent to control I1 to be a 6ω fluctuate dc current. The reason is that the average dc link current 1I shown in Fig. 13 is related to the input dc current inI by a transfer function:

11

1 2op

inop

DI I

D

−=

− (8)

Fig.14. PWAM modulation principle

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Fig.15. Simulation results

, in which opD is the open zero state duty cycle [1-2]. With

this transfer function, 1I can be controlled to be a 6ω varied waveform by regulating opD , resulting in a pulse type 6ω

waveform at the real dc link current pnI . The basic switching patterns for PWAM current-fed quasi-Z-source inverter are shown in Fig. 14. The red curve is the reference dc link current, which is also the envelope of the three-phase current because no zero state exists in the circuit. For each 60 degree range, only two switches are doing PWM modulation. It reduces the switching times of the original SPWM method by 2/3. In open zero state, only one switch is turned on; in non-open zero state, one switch in upper or lower half legs keeps on all the time, and another two switches in another half legs but in different phase legs are turned on and off complementarily, except some dead-time between them created by the insertion of the open zero state. Fig. 15 shows the simulated output current, dc link pn current, input average current Il, and also the switching waveforms of apS , bpS ,

cpS .

IV. COMPARISON BETWEEN DPWM B, C, D, CONTINUOUS SVPWM, AND PWAM

A. Spectrum and THD comparison

0.2 0.4 0.6 0.8 10

0.002

0.004

0.006

0.008

0.01

M

WT

HD

DPWM B

DPWM C

DPWM DContinuous

PWAM

Fig. 16 WTHD vs. M for different methods

0 0.005 0.01 0.015 0.02 0.025 0.03-1.5

-1

-0.5

0

0.5

1

1.5

t(s) Fig. 17. Switching voltage and current when pf=1

Fig. 18. CSI switching loss SVPWAM/SVPWM vs. power factor

The aforementioned five PWM methods for current source inverter can be compared in THD, by using the same average switching frequency. The DPWM only switches for half cycle, and PWAM only switches for 1/3 cycle, but continuous SVPWM switches for the whole cycle. Thus 20kHz, 30kHz and 10kHz are set for the switching frequency for them respectively in the comparison. The WTHD presents different value in different modulation index. So Fig. 17 shows the relationship between WTHD and the modulation index for each method. PWAM only has unity M, so it only shows one point. The plot indicates that PWAM has the smallest WTHD and DPWM C the second. Continuous SVPWM has the worst harmonic performance.

B. Switching loss reduction of PWAM on CSI In current source inverter, the current stress on the switch is equal to the dc link current, and the voltage stress is equal to output line to line voltage. The shadow area in Fig. 17 shows the switching current and voltage in Sector I. For a single switch, the switching loss is determined by

23

_3

12*2

a bcSW CSI SR sw

ref ref

i VP E f d t

V I

ππ ω

π⋅

= ⋅∫ (9)

This switching loss is similar to the one in voltage source inverter. But the comparison object switching loss in PWAM of CSI becomes only half of the SPWM. So the switching loss reduction relative to PWAM method can be plotted with power factor as shown in Fig. 18. The maximum switching loss reduction is 73.2% at unity power factor. The minimum switching loss reduction is 4.3% at power factor equal to zero. For conventional discontinuous SVPWM, in order to keep the output harmonics at the same level of SPWM, its switching frequency has to be doubled, which makes its switching loss reduction not obvious. Thus PWAM method can significantly reduce the switching loss at a equal output harmonic level compared to discontinuous SVPWM and continuous SVPWM.

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V. CONCLUSION This paper gives the general theory for three PWM modulation methods for current source inverter. The spectrum characteristics both in numerical and double Fourier equation are analyzed for each method. The results shows that for equal average switching frequency, PWAM has the lowest WTHD, DPWM c the second, and then DPWM b and d, and the worst one is CSVPWM. DPWM has almost equal switching loss with CSVPWM, but PWAM achieve 60% switching loss reduction.

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