UNIT 2: BASIC SEQUENTIAL CIRCUITS - Karnatakadte.karnataka.gov.in/Institutes/gptraichur/FileHandler/... · Flip Flops: Flip Flop is a bistable multivariate which has only two stable

DEPARTMENT OF COLLEGIATE AND TECHNICAL

EDUCATION

DEPARTMENT OF ELECTRONICS & COMMUNICATIONS ENGINEERING

STUDY MATERIAL ON

DIGITAL ELECTRONICS

(15EC32T)

UNIT 2: BASIC SEQUENTIAL CIRCUITS

Prepared by

SMT. SAVITA NAIK

LECTURER, E&CE DEPT

GOVERNMENT POLYTECHNIC, RAICHUR-117

DIST:-RAICHUR-584101

2020-2021

Digital Electronics (15EC32T)

Electronics and communication ,GPT Raichur Page 2

CONTENTS

S.NO CHAPTERS

Page no.

01 BASIC SEQUENTIAL CIRCUITS

2.1: Introduction to sequential circuits

3

2.1.1 . Comparison Between Combinational And Sequential

Logic Circuits

3

2.1.2. Definition of clock and triggering

4

2.1.3 . Introduction To Latches And Flip Flops

8

2.1.4 S-R Flip Flop

9

2.1.5 Unclocked S-R Flip-Flop Using NAND Gate 10

2.1.6 Unclocked S R Flip-Flop Using NOR Gate 11

2.1.7 Clocked SR Flip – Flops 12

2.1.8 Jk Flip_Flop 14

2.1.8 Race around condition of JK Flip Flop 14

2.1.9 Master-Slave JK Flip Flop 15

2.1.10 Applications

18

2.2 D Flip Flop 18

2.2.1 T FLIP – FLOP

20

2.2.2 Ic 7476 Dual Jk Flip-Flops 22

2.2.3 555 Timer Internal Circuit Diagram 25

2.2.4 Monostable Multivibrator using 555 Timer 28

2.2.5 Astable Multivibrator Using 555 Timer 32

2.2.6 555 Timer Flip-flop

37



UNIT-2

BASIC SEQUENTIAL CIRCUITS

2.1: Introduction to sequential circuits .

Digital electronics is classified into combinational logic and sequential logic.

Combinational logic output depends on the present inputs level, whereas sequential logic

output not only depends on the input levels, but also stored level (previous output history).

Fig: 2.1 Combinational circuit

SEQUENTIAL CIRCUITS

Fig: 2.2: block diagram of sequential circuit

There are many applications in which digital outputs are required to be generated in

accordance with the sequence in which the input signals are received. This requirement

cannot be satisfied using a combinational logic system. These applications require outputs to



be generated that are not only dependent on the present input conditions but they also depend

upon the past history of these inputs. The past history is provided by feedback from the

output back to the input.

Fig. 2.2 shows the block diagram of sequential circuit/finite state machine. As shown

in fig 2.2, memeory elements are connected to the combinational circuit as a feedback path.

The information stored in the memory at the given time defines the present state of the

sequential circuit. The present state and the external inputs determine the outputs and the next

state of the sequential circuit. Thus we can specify the sequential circuit by a time sequence

of external inputs , internal states (present states and next states ) and outputs. The countres

and registers are the common examples of sequential circuits.

2.1.1 . Comparison Between Combinational And Sequential Logic Circuits

S.No Combinational circuits

Sequential circuits

1 In combinational circuits, the output

variables are at all times dependent on the

combination of input variables.

In sequential circuits, the output

variables depend not only on the present

input variables but they also depend

upon the past history of these input

variables.

2 Memory unit is not required in

combinational circuits

Memory unit is required to store the past

history of input variables in the

sequential circuits.

3 Combinational circuits are faster in speed

because the delay between input and

output is due to propagation delay of gates.

Sequential circuits are slower than the

combinational circuits.

4 Combinational circuits are easy to design Sequential circuits are comparatively

harder to design

5 Parallel adder is a combinational circuit Serial adder is a sequential circuit

6 Examples of combinational circuits are

half adder ,full adder,nagnitude

comparator , multiplexer , demultiplexer

etc.

Examples of sequential circuits are flip

flop , register, counter etc.



7

A sequential circuits can further be categorized into Synchronous and Asynchronous.

Here is the difference between synchronous and asynchronous sequential circuits:

synchronous sequential circuits: Output changes at discrete internal of time . It is a circuit

based on an equal state time or a state time defined by external mean such as clock .

Examples of synchronous sequential circuit are flip flop , synchronous counter .

Asynchronous sequential circuits:Output can be changed at any instant of time by changing

the input . It is a circuit whose state time depends soely upon the internal logic circuit delays.

Example of asynchronous sequential circuit is Asynchronous counter .

2.1.2. Definition of clock and triggering

A clock signal is a particular type of signal that oscillates between a high and a low

state and utilized to co-ordinate action of circuits. It is produced by a clock generator.The

most common clock signal is in the form of a square wave with a 50% duty cycle , usually

with a fixed , constant frequency . Circuits using the clock signal for synchronization may

become active at either the rising edge , falling edge or in the case of double data rate , both

in the rising and in the falling edges of the clock cycle. The time required to complete one

cycle is called „clock period‟ or clock cycle. Ideally the clock signal should have sharp

transition from one level to other as shown in figure 2.2

Fig :2.3. Clock signal

Clock Pulse Transition

The movement of a trigger pulse is always from a 0 to 1 and then 1 to 0 of a signal.

Thus it takes two transitions in a single signal. When it moves from 0 to 1 it is called a

positive transition and when it moves from 1 to 0 it is called a negative transition. To

understand more take a look at the images below.



clocked flip-flops already introduced are

triggered during the 0 to 1 transition of the pulse, and the state transition starts as soon as the

pulse reaches the HIGH level. If the other inputs change while the clock is still 1, a new

output state may occur. If the flip-flop is made to then the multiple-transition problem can be

eliminated. The multi-transition problem can be stopped is the flip flop is made to respond to

the positive or negative edge transition only, other than responding to the entire pulse

duration.

Triggering

The output of a flip flop can be changed by bring a small change in the input signal.

This small change can be brought with the help of a clock pulse or commonly known as a

trigger pulse.

When such a trigger pulse is applied to the input, the output changes and thus the flip

flop is said to be triggered. Flip flops are applicable in designing counters or registers which

stores data in the form of multi-bit numbers. But such registers need a group of flip flops

connected to each other as sequential circuits. And these sequential circuits require trigger

pulses. The number of trigger pulses that is applied to the input of the circuit determines the

number in a counter. A single pulse makes the bit move one position, when it is applied onto

a register that stores multi-bit data.

In the case of SR Flip Flops, the change in signal level decides the type of trigger that

is to be given to the input. But the original level must be regained before giving a second

pulse to the circuit. If a clock pulse is given to the input of the flip flop at the same time when

the output of the flip flop is changing, it may cause instability to the circuit. The reason for

this instability is the feedback that is given from the output combinational circuit to the

memory elements. This problem can be solved to a certain level by making the flip flop more

sensitive to the pulse transition rather than the pulse duration. There are mainly four types of

pulse-triggering methods. They differ in the manner in which the electronic circuits respond

to the pulse. They are

1.High Level Triggering



When a flip flop is required to respond at its HIGH state, a HIGH level triggering

method is used. It is mainly identified from the straight lead from the clock input. Take a look

at the symbolic representation shown below.

2. Low Level

Triggering

When a

flip flop is required to respond at its LOW state, a LOW level triggering method is

used.. It is mainly identified from the clock input lead along with a low state indicator

bubble. Take a look at the symbolic representation shown below.

3. Positive Edge Triggering

When a flip flop is required to respond at a LOW to HIGH transition state,

POSITIVE edge triggering method is used. It is mainly identified from the clock input lead

along with a triangle. Take a look at the symbolic representation shown below.

4. Negative Edge Triggering



When a flip flop is required to respond during the HIGH to LOW transition

state, a NEGATIVE edge triggering method is used.. It is mainly identified from the

clock input lead along with a low-state indicator and a triangle. Take a look at the

symbolic representation shown below.

2.1.3 . INTRODUCTION TO

LATCHES AND FLIP FLOPS

Latches and flip-flops are the basic elements for storing information. One latch or

flip-flop can store one bit .There are basically four main types of latches and flip-flops: SR,

D, JK, and T.Latch is Pulse triggered memory device that checks all its inputs continuously

and change its output according to input at any period of time. They do not require Clock for

performing the operation.

Example of Latch

S-R Latch

Fig:2.4. S-R Latch

The S-R latch can be constructed by using either two NAND or two NOR Gates.

When two cross coupled NOR Gates as shown in the figure used then the resultant is

the S-R Latch.

Operation:

It has two Complementary outputs Q and Q‟as shown in the figure.

CASE-I: When Q Output is HIGH, the latch is in SET state.

CASE-II: When Q Output is LOW, the latch is in RESET state.



S-R Latch Truth Table

Condition for NAND GATE latch

When R‟=LOW and S‟=HIGH then Latch is in RESET state.

When S‟=LOW and R‟=HIGH then Latch is in SET state.

When both the inputs are HIGH then Latch is in no change.

When both the inputs are LOW i.e; Q and Q‟ both HIGH this is invalid state.

Draw backs of Latch:

Latch circuits are not preferred suitable for the synchronous logic circuits.

Flip Flops:

Flip Flop is a bistable multivariate which has only two stable states. Simply, Flip Flop

samples its input and change its outputs only at the time when it determine that clock signal is

activated. They are abbreviated as FF, a Edge-triggered memory element. They involves two

types of triggering procedure

Positive Edge-triggering when (ON = from 0 to 1; OFF = other time)

Negative Edge-triggering when (ON = from 1 to 0; OFF = other time)

Types of Flip Flop

S-R Flip Flop

D Flip Flop

J-K Flip Flop

T Flip Flop

2.1.4 S-R Flip Flop

The SR flip – flop is one of the fundamental parts of the sequential circuit logic. SR

flip flop is a memory device and a binary data of 1bit can be stored in it. SR flip flop

has two stable states in which it can store data in the form of either binary zero or

binary one. Like all flip flops, an SR flip – flop is also an edge sensitive device.

The S and R in SR flip flop means „SET‟ and „RESET‟ respectively. Hence it is also

called Set – Reset flip – flop. The symbolic representation of the SR Flip Flop is

shown below.

https://blog.oureducation.in/digital-electronics-jk-flip-flop/

https://i2.wp.com/blog.oureducation.in/wp-content/uploads/2013/10/NAND-GATE-S-R-Latch-Truth-Table.png?ssl=1



Fig: 2.5 .SR flip-flop Truth table of SR flip flop

Working

SR flip flop works during the transition of clock pulse either from low to high or from

high to low (depending on the design) i.e. it can be either positive edge triggered or

negative edge triggered.

For a positive edge triggered SR flip – flop, suppose, if S input is at high level (logic

1) and R input is at low level (logic 0) during a low to high transition on clock pulse,

then the SR flip flop is said to be in SET state and the output of the SR flip flop is

SET to 1

For the same clock situation, if the R input is at high level (logic 1) and S input is at

low level (logic 0), then the SR flip – flop is said to be in RESET state and the output

of the SR flip flop is RESET to 0.

The SR flip flops can be designed by using logic gates like NOR gates and NAND

gates. The two types of unclocked SR flip – flops are discussed below 2.1.5 Unclocked S-R Flip-Flop Using NAND Gate

SR flip flop can be designed by cross coupling of two NAND gates. It is an active low

input SR flip flop. The circuit of SR flip flop using NAND gates is shown in below

figure

Fig:2.6. Unclocked SR flip flop using NAND gate

Working

Case 1:

https://www.electronicshub.org/wp-content/uploads/2013/12/2.jpg





When both the SET and RESET inputs are high, then the output remains in previous state i.e.

it holds the previous data.

Case 2:

When SET input is HIGH and RESET input is LOW, then the flip flop will be in RESET

state. Because the low input of NAND gate with R input drives the other NAND gate with 1,

as its output is 1. So both the inputs of the NAND gate with S input are 1. This will cause the

output of the flip flop to settle in RESET state.

Case 3:

When SET input is LOW and RESET input is HIGH, then the flip flop will be in SET state.

Because the low input of NAND gate with S input drives the other NAND gate with 1, as its

output is 1. So both the inputs of the NAND gate with R input are 1. This will cause the

output of the flip flop to settle in SET state.

Case 4:

When both the SET and RESET inputs are low, then the flip flop will be in undefined state.

Because the low inputs of S and R, violates the rule of flip flop that the outputs should

compliment to each other. So the flip flop is in undefined state (or forbidden state).The table

below summarizes above explained working of SR Flip Flop designed with the help of a

NAND gates (or forbidden state).

2.1.6 Unclocked S R Flip-Flop Using NOR Gate

SR flip flop can also be designed by cross coupling of two NOR gates. It is an active

high input SR flip flop. The circuit of SR flip flop using NOR gates is shown in below

figure.



Fig:2.7: Unclocked S R Flip-Flop Using NOR Gate Truth table

Working

Case 1:

When both the SET and RESET inputs are low, then the output remains in previous state i.e.

it holds the previous data.

Case 2:

When SET input is low and RESET input is high, then the flip flop will be in RESET state.

Because the high input of NOR gate with R input drives the other NOR gate with 0, as its

output is 0. So both the inputs of the NOR gate with S input are 0. This will cause the output

of the flip flop to settle in RESET state.

Case 3:

When SET input is high and RESET input is low, then the flip flop will be in SET state.

Because the low input of NOR gate with S input drives the other NOR gate with 1, as its

output is 1. So both the inputs of the NOR gate with R input are 1. This will cause the output

of the flip flop to settle in SET state.

Case 4:

When both the SET and RESET inputs are high, then the flip flop will be undefined state.

Because the high inputs of S and R, violates the rule of flip flop that the outputs should

complement to each other. So the flip flop is in undefined state (or forbidden state).

The table above summarizes above explained working of SR Flip Flop designed with the help

of a NOR gate.

The problem with simple SR flip – flops is that they are level sensitive to the control

signal (although not shown in figure) which makes them a transparent device. In order to

avoid this, Gated or Clocked SR flip flops are introduced (whenever the term SR flip flop is

used, it usually refers to clocked SR flip – flop). Clock signal makes the device edge sensitive

(and hence no transparency).

2.1.7 Clocked SR Flip – Flops

Two types of clocked SR flip – flops are

possible: based on NAND and based on



NOR. The circuit of clocked SR flip – flop using NAND gates is shown below .

Fig:2.8. Clocked SR Flip – Flops

Truth table

This circuit is formed by adding two NAND gates to NAND based SR flip – flop. The

inputs are active high as the extra NAND gate inverts the inputs. A clock pulse is given as

input to both the extra NAND gates. Hence the transition of the clock pulse is a key factor in

functioning if this device. Assuming it is a positive edge triggered device, the truth table for

this flip flop is shown above.

2.1.8 JK FLIP_FLOP

A JK flip – flop is the modification of SR flip – flop with no illegal state. In this the J

input is similar to the SET input of SR flip flop and the K input is similar to the RESET input

of SR flip flop. The symbol of JK flip – flop is shown below.

Fig:2.9.JK flip flop Logic Diagram

JK flip – flop is a modified version of SR flip flop. Logic diagram consists of three

input NAND gates replacing the two input NAND gates in SR flip flop and the inputs are

replaced with J and K from S and R. The design of the JK flip flop is such that the three

inputs to one NAND gate are J, clock signal along with a feedback signal from Q‟ and the

three inputs to the other NAND are K, clock signal along with a feedback signal from Q. This

arrangement eliminates the indeterminate state in SR flip flop.

https://www.electronicshub.org/wp-content/uploads/2015/05/5.JK-Block-diagram.jpg

https://www.electronicshub.org/wp-content/uploads/2015/05/5.JK-Block-diagram.jpg



Fig:2.10. JK flip flop Logic Diagram Truth Table

Operation

Case 1 : When both the inputs J and K are LOW, then Q returns its previous

state value i.e. it holds the previous data.

When we apply a clock pulse to the J K flip flop and the J input is low then

irrespective of the other NAND gates, the NAND gate-1 output becomes HIGH. In the same

manner, if the K input is low then output of NAND gate-2 is also HIGH. So thus the output

remains in the same state i.e. no change in the state of flip flop.

Case 2 : When J is LOW and K is HIGH, then flip flop will be in Reset state i.e. Q = 0, Q’ = 1.

When we apply a clock pulse to the J K flip flop and the inputs are J is low and K is

high the output of the NAND gate connected to J input becomes 1. Then Q becomes 0. This

will reset the flip flop again to its previous state. So the Flip flop will be in RESET state.

Case 3 : When J is HIGH and K is LOW, then flip – flop will be in Set state i.e. Q

= 1, Q’ = 0

When we apply a clock pulse to the J K flip flop and the inputs are J is high and K is

low the output of the NAND gate connected to K input becomes 1. Then Q‟ becomes 0. This

will set the flip flop with the high clock input. So the Flip flop will be in SET state.

Case 4 : When both the inputs J and K are HIGH, then flip – flop is in Toggle

state. This means that the output will complement of the previous state.



2.1.8 Race around condition of JK Flip Flop

For high inputs of J K flip flop, only the lower NAND gates are triggered by the

outputs that are compliment to each other i.e Q and Q‟. So while high inputs are connected to

flip – flop, at any instant, one gate is enabled and other gate will be disabled. If the upper gate

is in disabled state, it will drive the flip flop to SET state, later when the lower gate is

enabled, it will drive the flip flop to RESET state which causes the toggling of output. This

will cause the Race around condition in J K flip – flop.

Steps to avoid racing condition

1. We can avoid the Race around condition by setting up the clock-on time less than the

propagation delay of the flip flop. It can be achieved by edge triggering.

2. By making the flip flop to toggle over one clock period. This concept is introduced in

Master Slave J K flip flop.

2.1.9 Master-Slave JK Flip Flop

The Master-Slave J K Flip flop is a “Synchronous” device which allows the data to

pass with the timing of the clock signal. A master – slave flip flop consists of two clocked

flip flops connected in series, which isolate the input from output and hence the terminology

“master – slave”. Apart from eliminating the race around problem in normal JK flip flops, a

master – slave JK flip flop can also imitate the functions of SR flip flop, clocked flip – flop,

D flip – flop and Toggle flipflop.

The Q and Q‟ outputs of the slave flip – flop are fed back to the master flip flop while

the outputs of the master flip flop are connected as one of the inputs to the slave flip flop.

When the clock input is high, the master is active and the slave is inactive. Depending on the

inputs, the output of the master flip – flop is set or reset and the output of the slave flip flop is

not changed and so it remains in previous state. As the slave flip flop become active at low

clock input, the outputs of slave flip – flop changes. When the clock is high, the output of the

master flip – flop are put on hold as the slave is inactive during this period. When the clock is

low, the output of the master flip – flop are seen by the slave flip flop and pass them to the

output. The output of the slave flip flop is the final output of the Master – Slave flip flop. The

final output is available at the end of the clock pulse.



Construction

A master slave JK flip flop is a cascaded combination of two SR flips flops with the

feedbacks from output of the slave to the input of the master. The circuit of master -slave flip

flop is shown below

Fig:2.11: Master-Slave JK Flip Flop

Positiveclock pulses are applied to the master flip flop and they are inverted before

applying to slave i.e. master flip flop is active during positive transition while slave flip flop

is active during negative transition. During the positive edge of the clock, the data from

inputs J and K are passed to the master flip – flop and are held there till the occurrence of

negative edge transition of the clock. Then the data or information is passed to the slave flip

flop, here the output is collected. The symbolic representation of a master – slave JK flip flop

with two JK flip flops is shown below.

Fig:2.12. The symbolic representation of a master – slave JK flip flop

The truth table of master – slave JK flip – flop along with preset and clear inputs is shown

below.

https://www.electronicshub.org/wp-content/uploads/2015/05/new.jpg

https://www.electronicshub.org/wp-content/uploads/2015/05/Symbolic-representation-of-Master-%E2%80%93-Slave-JK-flip-flop1.jpg

https://www.electronicshub.org/wp-content/uploads/2015/05/new.jpg

https://www.electronicshub.org/wp-content/uploads/2015/05/Symbolic-representation-of-Master-%E2%80%93-Slave-JK-flip-flop1.jpg



When the clock input is low, and the two inputs of master flip flop i.e. J and K inputs

will have no effect on the output of Master Slave flip flop. When the clock input is high

If J is low & K is low: No change in state.

If J is low & K is high: Master Slave flip flop will be in reset state.

If J is high & K is low: Master Slave flip flop will be in set state.

If J is high & K is high: Toggled state.

Timing Diagram


https://www.electronicshub.org/wp-content/uploads/2015/05/jk-ms-timing.jpg


https://www.electronicshub.org/wp-content/uploads/2015/05/jk-ms-timing.jpg



2.1.10 Applications

JK flip – flops are one of the most widely used flip flops in digital electronics. This is

because of their universal programmable feature.

Some of the applications of JK flip – flop include

• Shift Registers

• Frequency Dividers

• Switching Applications

• Parallel Data Transfer

• Serial Data Transfer

• Binary Counter

• Sequence Detector

2.2 D Flip Flop

D flip flops are also called as “Delay flip – flop” or “Data flip – flop”. They are used

to store 1 – bit binary data. They are one of the widely used flip – flops in digital electronics.

Apart from being the basic memory element in digital systems, D flip flops are also

considered as Delay line elements and Zero Order Hold elements. D flip flop has two

inputs , a clock (CLK) input and a data (D) input and two outputs; one is main output

represented by Q and the other is complement of Q represented by Q‟. The symbol of a D flip

flop is shown below.

Fig: 2.13: The symbol of a D flip flop

Construction

A D flip flop is constructed by modifying an SR flip flop. The S input is given with D

input and the R input is given with inverted D input. Hence a D flip flop is similar to SR flip

flop in which the two inputs are complement to each other, so there will be no chance of any

intermediate state occurs. The major drawback of SR flip flop is the race around condition

https://www.electronicshub.org/wp-content/uploads/2015/05/D-flip-%E2%80%93-flop-Symbol.jpg



which in D flip flop is eliminated (because of the inverted inputs). The circuit diagram of D

flip – flop is shown in below figure.

Fig: 2.14: The circuit diagram of D flip flop

Working

When we don‟t apply any clock input to the D flip flop or during the falling edge of

the clock signal, there will be no change in the output. It will retain its previous value at the

output Q. If the clock signal is high (rising edge to be more precise) and if D input is high,

then the output is also high and if D input is low, then the output will become low. Hence the

output Q follows the input D in the presence of clock signal.

Simply, for positive transition on clock signal,

If D = 0 => Q = 0 so flip flop is reset.

If D = 1 => Q = 1 so flip flop is set.

NOTE: ↑ indicate positive edge of the clock and ↓ indicate negative edge of the clock signal.

https://www.electronicshub.org/wp-content/uploads/2015/05/4.D-Logic-Diagram.jpg





Applications

D flip – flops are one of the most widely used flip – flops. Some of the many applications of

D flip – flop are

Data storage registers.

Data transferring as shift registers.

Frequency division circuits.

2.2.1 T FLIP – FLOP

T flip flop is also known as “Toggle Flip flop”. To avoid the occurrence of

intermediate state in SR flip – flop, we should provide only one input to the flip flop called

Trigger input or Toggle input (T). Then the flip flop acts as a Toggle switch. Toggling means

„Changing the next state output to complement of the present state output‟.

We can design the T flip flop by making simple modifications to the JK flip

flop. The T flip flop is a single input device and hence by connecting J and K inputs together

and giving them with single input called T we can convert a JK flip flop into T flip flop. So a

T flip flop is sometimes called as single input JK flip flop.The logic symbol of T flip – flop is

shown below. It has one Toggle input (T) & one clock signal input (CLK).

Fig:2.15 logic symbol of T-flip-flop

The simplest constructon of a D Flip Flop is with JK Flip Flop. Both the inputs of the

"JK Flip Flop" are connected as a single input T. Below is the logical circuit of the T Flip

Flop" which is formed from the "JK Flip Flop":

https://www.electronicshub.org/wp-content/uploads/2015/06/Symbol-of-T-flip-flop.jpg



FIG:2.16 : T-FLIP FLIOP Circuit diagram

Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when the

output Q To is set to 0. make the flip flop in "set state(Q=1)", the trigger passes the S input in

the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the

output Q is set to 1. The trigger passes the R input in the flip flop to make the flip flop in the

reset state (Q=0).

Operations of T-Flip Flop

The next statee of the T flip flop is similar to the current state when the T input is set to false

or 0. If toggle input is set to 0 and the present state is also 0, the next state will be 0.

o If toggle input is set to 0 and the present state is 1, the next state will be 1.

The next state of the flip flop is opposite to the current state when the toggle input is set to 1.


https://www.javatpoint.com/nand-gate-in-digital-electronics




The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by

the incoming trigger. The "T Flip Flop" requires two triggers to complete a full cycle of the

output waveform. The frequency of the output produced by the "T Flip Flop" is half of the

input frequency. The "T Flip Flop" works as the "Frequency Divider Circuit." In "T Flip

Flop", the state at an applied trigger pulse is defined only when the previous state is defined.

It is the main drawback of the "T Flip Flop". The "T flip flop" can be designed from "JK Flip

Flop", "SR Flip Flop", and "D Flip Flop" because the "T Flip Flop" is not available as ICs.

The block diagram of "T Flip Flop" using "JK Flip Flop" is given below:

Fig:2.17: T flip-flop using JK flip-flop

Appications

Frequency Division Circuits.

2 – Bit Parallel Load Registers.



2.2.2 IC 7476 DUAL JK FLIP-FLOPS

Features

Dual JK Flip Flop Package IC

Positive edge triggered Flip-Flop

Operating Voltage: 4.5V to 5.5V

Input Rise time at 5V : 16 ns

Input Fall time at 5V : 25 ns

Minimum High Level Input Voltage: 2 V

Maximum Low Level Input Voltage: 0.8 V

Available in 14-pin PDIP, GDIP, PDSO packages

The internal block diagram of a 555 timer is shown below. It consists of the following

Two Comparators

An SR flip-flop

Two transistors

A resistive network



The comparators are the basic Op-amps. The comparator 1, which provides the R

input, compares the threshold voltage with a 2/3 VCC reference voltage.

The comparator 2, which provides the S input to the flip-flop, compares the trigger

voltage with a 1/3 VCC reference voltage.

The resistive network of three resistors will act as a voltage divider circuit. The values

of these resistors are 5KΩ each. These three 5K resistors are responsible for the name

“IC 555”.

Out of the two transistors, one transistor is a discharge transistor. The open collector

of this transistor is connected to the discharge pin (Pin 7) of the IC. According to the

output of the flip-flop, this transistor either goes into saturation or cut-off.

When the transistor is saturated, it provides a discharge path to the capacitor that is

connected externally. The base of the other transistor is connected to the reset

terminal (Pin 4) which resets the timer irrespective of the other inputs.



555 Timer Working

The three 5KΩ resistors form a voltage divider network. This network provides two

reference voltages to two comparators 2/3 VCC to the inverting terminal of the upper

comparator (comparator 1) and 1/3 VCC to the non-inverting terminal of the lower

comparator (comparator 2).

The inverting terminal of the upper comparator is connected to the control input.

Generally, control input is not used and is connected to 2/3 VCC. The other input of

the upper comparator is threshold and its output is connected to the R input of the flip-

flop.

When the threshold voltage is greater than 2/3 VCC (i.e. the control voltage), then

the flip-flop is RESET and the output goes LOW. This will turn the discharge

transistor ON (transistor goes to saturation) and provides a discharge path to any

externally connected capacitor.

A trigger input is connected to the inverting terminal of the lower comparator. When

the trigger input is less than the reference voltage (1/3 VCC), the lower comparator‟s

output is high.

This is connected to the S input of the flip-flop and hence the flip-flop is SET and the

output goes HIGH and the timing interval starts. As the output is high, the discharge

transistor is turned OFF and allows charging of any capacitor connected to it

externally.

Hence, in order for the output to go HIGH, the trigger input should be less than the

reference voltage momentarily. The output is low when the threshold voltage is

greater than 2/3 VCC, which resets the flip-flop and hence the output.

Introduction to Time Constant RC

Meeting timing requirements is a high priority task in most of the operations. For

example, the heating process of a metal or a material in an industry is time limited. Hence



meeting the specific time requirements can be achieved by timer circuits. A basic timer

circuit is shown below. It consists of a charging circuit, a comparator and an output unit.

The charging circuit consists of a resistor and a capacitor. When a series combination

of an RC circuit is applied with a DC voltage, the time taken for the capacitor to

charge to the peak value is controlled by the resistor.

The charging time is proportional to the value of the resistance. The rate at which the

capacitor charges in an RC circuit is given by Time constant.

RC Time Constant, generally called Tau (represented by the symbol τ), is the time

constant of an RC circuit which is the time taken by the Capacitor to charge through

the Resistor by approximately 63.2 % of the difference between initial and the final

values.

It is also equal to the time taken by the capacitor to discharge to 36.8%. Time constant

of an RC circuit is equal to the product of R and C.

τ = RC

when the trigger input falls below 1/3 VCC, the output of the timer goes high and the

period for which this stays high is determined by the RC time constant.

The pulse width and the frequency of the output of the 555 timer are determined by

the RC time constant.

Choosing Timing Components for RC circuit in Timer

A 555 timer can provide delays from microsecond to hours depending on the values

of R and C in the charging circuit. Hence it is very important to choose appropriate

values for resistors and capacitors.

When the 555 timer is operating in Astable mode, then it requires an RC circuit

consisting of two resistors and a capacitor. And in case of monostable mode of

operation, the RC circuit comprises of a resistor and a capacitor.

Timing Capacitor



Choosing capacitors with large capacitances will be a problem. This is because

electrolyte capacitors with large capacitances often tend to have wider tolerance

limits. So the actual values and the marked values may have a significant difference.

Large capacitance electrolyte capacitors will have high leakage currents which can

affect the timing accuracy as the capacitor charges. When choosing capacitors with

large capacitance and low leakage current, Tantalum capacitors are a better option.

It is better to avoid electrolyte capacitors that have a high working voltage rating as

they do not work efficiently when operated at a voltage 10% less than their rated

voltage.

Hence, capacitors with working voltage greater than the VCC of the 555 timer should

be chosen.

Timing capacitors with capacitance less than 100pF in order to produce short output

pulses may also cause problems.

For capacitors with such low values, stray capacitance around the circuit might affect

the capacitance of the timing capacitor.

Timing Resistor

When operating the 555 timer as an Astable multivibrator , the value of the timing

resistor should be at least 1 Kilo Ohms. If the idea is to build a low power

consumption circuit, then it is better to have higher values for the timing resistors.

But there is a disadvantage in choosing resistors with higher resistances as they lead

to inaccuracies in timing. In order to minimize these inaccuracies, the value of the

timing resistor shouldn‟t be more than 1 Mega Ohms.

Trigger Pulses

The Pin 2 in the 555 timer is a trigger input. When the trigger input goes below the

reference voltage i.e. 1/3 VCC, the output of the timer is high and the timing interval

begins.

The trigger pulse should momentarily go below the reference voltage and the duration

is important as it should not be longer than the output pulse.

Trigger pulses are generally identified by a narrow negative going spike. A

differentiator circuit made from a capacitor and a resistor will produce two

symmetrical spikes but a diode is used to eliminate the positive going spike.

The duration of the pulse is determined by the differentiator circuit (i.e. it depends on

the capacitor and resistor).



Applications

Some of the important areas of applications of the 555 timer are:

Pulse Generation

Time Delay Generation

Precision Timing

Sequential Timing

Pulse Width Modulation (PWM)

The typical applications of a 555 timer can be differentiated by the mode of operation.

Depending on the mode in which it is operated i.e. either in astable or in monostable mode,

some of the applications of IC 555 are:

Frequency Divider

Linear Ramp Generator

Missing Pulse Detector

Pulse Position Modulation

Square Wave Generation

Pulse Width Modulation

Oscillator

Tone Burst Generator

Speed Warning Device

Regulated DC – to – DC Converter

Voltage – to – Frequency Converter

Low Cost Line Receiver

Cable Tester

2.2.4 Monostable Multivibrator using 555 Timer

The following figure is the schematic of IC 555 as a Monostable Multivibrator. This

is the basic mode of operation of the IC 555. It requires only two extra components to make it

work as a monostable multivibrator: a resistor and a capacitor.



As the name specifies, a monostable multivibrator has only one stable state. When a trigger

input is applied, a pulse is produced at the output and returns back to the stable state after a

time interval. The duration of time for which the pulse is high will depend on the timing

circuit that comprises of a resistor (R) and a capacitor (C).

The details of the connection are as follows. The pins 1 and 8 are connected to ground and

supply (VCC) respectively. Output is taken at pin 3. To avoid accidental reset of the circuit,

pin 4 is connected to the VCC. Pin 5, which is the control voltage input, should be grounded

when not in use. To filter the noise, it is connected to the ground via a small capacitor of

capacitance 0.01µF.

Operation

The monostable mode is also called “one-shot” pulse generator. The sequence of

events starts when a negative going trigger pulse is applied to the trigger comparator.

When this trigger comparator senses the short negative going trigger pulse to be just

below the reference voltage (1/3 VCC), the device triggers and the output goes HIGH.

The discharge transistor is turned OFF and the capacitor C that is externally

connected to its collector will start charging to the max value through the resistor R.

The HIGH output pulse ends when the charge on the capacitor reaches 2/3 VCC. The

internal connection of the IC 555 in monostable mode along with the RC timing

circuit is shown below.

https://www.electronicshub.org/wp-content/uploads/2015/06/Internal-Connection-in-Monostable-mode.jpg

https://www.electronicshub.org/wp-content/uploads/2015/06/Internal-Connection-in-Monostable-mode.jpg



The detailed operation can be explained as follows. Initially, the flip-flop is RESET.

This will allow the discharge transistor to go to saturation. The capacitor C, which is

connected to the open collector (drain in case of CMOS) of the transistor, is provided

with a discharge path. Hence the capacitor discharges completely and the voltage

across it is 0. The output at pin 3 is low (0).

When a negative going trigger pulse input is applied to the trigger comparator

(comparator 2), it is compared with a reference voltage of 1/3 VCC. The output

remains low until the trigger input is greater than the reference voltage. The moment

trigger voltage goes below 1/3 VCC, the output of comparator goes high and this will

SET the flip-flop. Hence the output at pin 3 will become high.

At the same time, the discharge transistor is turned OFF and the capacitor C will

begin to charge and the voltage across it rises exponentially. This is nothing but the

threshold voltage at pin 6. This is given to the comparator 1 along with a reference

voltage of 2/3 VCC. The output at pin 3 will remain HIGH until the voltage across the

capacitor reaches 2/3 VCC.

The instance at which the threshold voltage (which is nothing but the voltage across

the capacitor) becomes more than the reference voltage, the output of the comparator

1 goes high. This will RESET the flip-flop and hence the output at pin 3 will fall to

low (logic 0) i.e. the output returns to its stable state. As the output is low, the

discharge transistor is driven to saturation and the capacitor will completely

discharge.



Hence it can be noted that the output at pin 3 is low at start, when the trigger becomes

less than 1/3 VCC the output at pin 3 goes high and when the threshold voltage is

greater than 2/3 VCC the output becomes low until the occurrence of next trigger

pulse. A rectangular pulse is produced at the output. The time for which the output

stays high or the width of the rectangular pulse is controlled by the timing circuit i.e.

the charging time of the capacitor which depends on the time constant RC.

Pulse Width Derivation

We know that the voltage across the capacitor C rises exponentially. Hence the equation for

the capacitor voltage VC can be written as

VC = VCC (1 – e-t/RC

)

When the capacitor voltage is 2/3 VCC, then

2/3 VCC = VCC (1 – e-t/RC

)

2/3 = 1 – e-t/RC

e-t/RC

= 1/3

– t/RC = ln (1/3)

– t/RC = -1.098

t = 1.098 RC

∴ t ≈ 1.1 RC

The pulse width of the output rectangular pulse is W = 1.1 RC.

The waveforms of the monostable operation are shown below.

Applications of Monostable Multivibrator

1) Frequency Divider

2) Pulse Width Modulation

3) Linear Ramp Generator

4) Switching the Relay ON

5) Missing Pulse Detector

https://www.electronicshub.org/wp-content/uploads/2015/06/Waveforms-in-Monostable-Mode.jpg



2.2.5 Astable Multivibrator Using 555 Timer

Circuit and Operation

Astable multivibrator is also called as Free Running Multivibrator. It has no stable states and

continuously switches between the two states without application of any external trigger. The

IC 555 can be made to work as an astable multivibrator with the addition of three external

components: two resistors (R1 and R2) and a capacitor (C). The schematic of the IC 555 as

an astable multivibrator along with the three external components is shown below.

The pins 2 and 6 are connected and hence there is no need for an external trigger

pulse. It will self trigger and act as a free running multivibrator. The rest of the connections

are as follows: pin 8 is connected to supply voltage (VCC). Pin 3 is the output terminal and

hence the output is available at this pin. Pin 4 is the external reset pin. A momentary low on

this pin will reset the timer. Hence when not in use, pin 4 is usually tied to VCC.

The control voltage applied at pin 5 will change the threshold voltage level. But for

normal use, pin 5 is connected to ground via a capacitor (usually 0.01µF), so the external

noise from the terminal is filtered out. Pin 1 is ground terminal. The timing circuit that

determines the width of the output pulse is made up of R1, R2 and C.

Operation

The following schematic depicts the internal circuit of the IC 555 operating in astable mode.

The RC timing circuit incorporates R1, R2 and C.



Initially, on power-up, the flip-flop is RESET (and hence the output of the timer is

low). As a result, the discharge transistor is driven to saturation (as it is connected to Q‟). The

capacitor C of the timing circuit is connected at Pin 7 of the IC 555 and will discharge

through the transistor. The output of the timer at this point is low. The voltage across the

capacitor is nothing but the trigger voltage. So while discharging, if the capacitor voltage

becomes less than 1/3 VCC, which is the reference voltage to trigger comparator (comparator

2), the output of the comparator 2 will become high. This will SET the flip-flop and hence the

output of the timer at pin 3 goes to HIGH.

This high output will turn OFF the transistor. As a result, the capacitor C starts

charging through the resistors R1 and R2. Now, the capacitor voltage is same as the threshold

voltage (as pin 6 is connected to the capacitor resistor junction). While charging, the

capacitor voltage increases exponentially towards VCC and the moment it crosses 2/3 VCC,

which is the reference voltage to threshold comparator (comparator 1), its output becomes

high.

As a result, the flip-flop is RESET. The output of the timer falls to LOW. This low

output will once again turn on the transistor which provides a discharge path to the capacitor.

Hence the capacitor C will discharge through the resistor R2. And hence the cycle continues.

https://www.electronicshub.org/wp-content/uploads/2015/06/Internal-Connection-in-Astable-mode.jpg



Thus, when the capacitor is charging, the voltage across the capacitor rises exponentially and

the output voltage at pin 3 is high. Similarly, when the capacitor is discharging, the voltage

across the capacitor falls exponentially and the output voltage at pin 3 is low. The shape of

the output waveform is a train of rectangular pulses. The waveforms of capacitor voltage and

the output in the astable mode are shown below.

While charging, the capacitor charges through the resistors R1 and R2. Therefore the

charging time constant is (R1 + R2) C as the total resistance in the charging path is R1 + R2.

While discharging, the capacitor discharges through the resistor R2 only. Hence the discharge

time constant is R2C.

Duty Cycle

The charging and discharging time constants depends on the values of the resistors R1

and R2. Generally, the charging time constant is more than the discharging time constant.

Hence the HIGH output remains longer than the LOW output and therefore the output

waveform is not symmetric. Duty cycle is the mathematical parameter that forms a relation

between the high output and the low output. Duty Cycle is defined as the ratio of time of

HIGH output i.e. the ON time to the total time of a cycle.

If TON is the time for high output and T is the time period of one cycle, then the duty cycle D

is given by

D = TON/ T

Therefore, percentage Duty Cycle is given by

%D = (TON / T) * 100

https://www.electronicshub.org/wp-content/uploads/2015/06/Waveforms-in-Astable-mode-of-operation.jpg



T is sum of TON (charge time) and TOFF (discharge time).

The value of TON or the charge time (for high output) TC is given by

TC = 0.693 * (R1 + R2) C

The value of TOFF or the discharge time (for low output) TD is given by

TD = 0.693 * R2C

Therefore, the time period for one cycle T is given by

T = TON + TOFF = TC + TD

T = 0.693 * (R1 + R2) C + 0.693 * R2C

T = 0.693 * (R1 + 2R2) C

Therefore, %D = (TON/ T) * 100

%D = (0.693 * (R1 + R2) C)/(0.693 * (R1 + 2R2) C) * 100

%D = ((R1 + 2R2))/((R1 + 2R2)) * 100

If T = 0.693 * (R1 + R2) C, then the frequency f is given by

f = 1 / T = 1 / 0.693 * (R1 + 2R2) C

f = 1.44/( (R1 + 2R2) C) Hz

Selection R1, R2 and C1 for different ferquency range are as follow:

R1 and R2 should be in the range 1k to 1M . It is best to Choose C1 first (because capacitors

are available in just a few values) as per the frequency range from the following table.

Choose R2 to give the frequency (f) you require.

R2 = 0. (f C1)

Choose R1 to be about a tenth of R2 (1k min.)

Applications of Astable Multivibrator

Square Wave Generation

Pulse Position Modulation

Frequency Modulation



Bistable Multivibrator Circuit using 555 Timer

The circuit for a bistable multivibrator using the 555 timer is shown below

A bistable multivibrator is one of the easiest circuits that can be built using a 555

timer. It doesn‟t require a capacitor as the RC charging unit is not responsible for the

generation of the output. The generation of high and low outputs is not dependent on

the charging and discharging of the capacitor in the RC unit but rather it is controlled

by the external trigger and reset signals.

The explanation of the bistable mode of operation of the 555 timer is as follows. The

trigger and reset pins (pins 2 and 4 respectively) are connected to the supply through

two resistors R1 and R2 so that they are always high. In all the previous cases, the

reset pin is not used and in order to avoid any accidental reset, it is simply connected

to VCC.

Two switches are connected between these pins and ground in order to make them go

low momentarily. The switch at the trigger input will act as S (SET) input for the

internal flip-flop. The switch at the reset input will act as reset for the internal flip-

flop.

When the switch S1 is pressed, the voltage from VCC will bypass the trigger terminal

and is shorted to ground through the resistor R1. Hence, the trigger pulse will

momentarily go low and the output of the timer at pin 3 will become HIGH. The

output stays HIGH because there is no input from the threshold pin (pin 6 is left open

or better if connected to ground) and the output of the internal comparator

(comparator 1) will not go high.

When the switch S2 is pressed, the voltage from VCC will bypass the reset terminal

and is shorted to ground through the resistor R2. This pin is internally connected to



the RESET terminal of the flip-flop. When this signal goes low for a moment, the

flip-flop receives the reset signal and RESETs the flip-flop.

Hence, the output will become LOW and stays there until the trigger is applied. The

waveforms of the bistable mode of operation of the 555 timer are shown below.

2.2.6 555 Timer Flip-flop

Flip-flop

It is not a great choice to use a 555 timer as a flip-flop in computer applications. In

typical computer applications, the clock pulse is used to drive the trigger and reset

signals and the frequency of the clock signal is very high (generally in the order of

Giga Hertz). The output of the 555 timer is not responsive enough to match the speed

of the clock signals‟ frequency. Readily available flip-flop devices are preferable

when used in high speed operations.

The 555 timer in bistable mode i.e. as a flip-flop can be used in low speed, non-

computer applications like robotics. A simple application is a robot which moves

forward and backward every time it hits an object.

https://www.electronicshub.org/wp-content/uploads/2015/06/Waveforms-of-Bistable-mode-of-operation-of-555-timer.jpg



That being said, the circuit of a flip-flop using a 555 timer is shown below.

When the output at pin 3 is high, the capacitor C charges through the resistor R1 to

the peak value i.e. VCC. When the output at pin 3 is low, the capacitor discharges

through the same resistor to 0. In order to switch the output from high to low or low to

high, a switch is used at the junction of trigger and threshold pins.

The voltage divider formed by the resistors R2 and R3 will provide a voltage of VCC

/ 2 at the pins 6 and 2. When the switch is pressed, this voltage is interrupted and

triggers the internal flip-flop. This will allow the output to switch between the two

states.

https://www.electronicshub.org/wp-content/uploads/2015/06/Circuit-of-flip-flop-using-555-timer.jpg

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UNIT 2: BASIC SEQUENTIAL CIRCUITS - Karnatakadte.karnataka.gov.in/Institutes/gptraichur/FileHandler/... · Flip Flops: Flip Flop is a bistable multivariate which has only two stable