Unit 3_embedded system

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DEVICES & BUSES FOR DEVICES NETWORK [UNIT-III] V.V.C.E.T

Department of EEE Page 1

EMBEDDED SYSTEMS

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

UNIT III

DEVICES & BUSES FOR DEVICES NETWORK

I/O devices; timer & counting devices; serial communication using I2C, CAN, USB buses; parallel

Communication using ISA, PCI, PCI/X buses, arm bus; interfacing with devices/ports, device drivers in a

system Introduction

Prepared by

M.Sujith,

Lecturer,

Department of Electrical and Electronics Engineering,

Vidyaa Vikas College of Engineering and Technology.

HOD/EEE


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IO Port

Port

A port is a device To receive the bytes from external peripheral(s) [or device(s) or processor(s) or controllers] for

reading them later using instructions executed on the processor or

To send the bytes to external peripheral or device or processor using instructions executed on

processor

A Port connects to the processor using address decoder and system buses The processor uses the addresses of the port-registers for programming the port functions or

modes, reading port status and for writing or reading bytes.

Example

SI serial interface in 8051

SPI serial peripheral interface in 68HC11

PPI parallel peripheral interface 8255 Ports P0, P1, P2 and P3 in 8051 or PA, PB, PC and PD in 68HC11

COM1 and COM2 ports in an IBM PC

IO Port TypesTypes of Serial ports

Synchronous Serial Input

Synchronous Serial Output

Asynchronous Serial UART input

Asynchronous Serial UART output

Both as input and as output, for example, modem.

Types of parallel ports

Parallel port one bit Input

Parallel one bit output

Parallel Port multi-bit Input

Parallel Port multi-bit Output

Synchronous Serial Input Example Inter-processor data transfer, reading from CD or hard disk, audio input, video input, dial tone,

network input, transceiver input, scanner input, remote controller input, serial I/O bus input,

writing to flash memory using SDIO (Secure Data Association IO based card)

Synchronous Serial Input Device (Serial Bits and a clock signal used for synchronisation of a port

input)


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Synchronous Serial Input The sender along with the serial bits also sends the clock pulses SCLK (serial clock) to the receiver

port pin. The port synchronizes the serial data input bits with clock bits. Each bit in each byte as

well as each byte in synchronization

Synchronization means separation by a constant interval or phase difference. If clock period = T,

then each byte at the port is received at input in period = 8T.

The bytes are received at constant rates. Each byte at input port separates by 8T and data transfer

rate for the serial line bits is (1/T) bps. [1bps = 1 bit per s]

Serial data and clock pulse-inputs

On same input line when clock pulses either encode or modulate serial data input bits suitably.

Receiver detects the clock pulses and receives data bits after decoding or demodulating.

On separate input line When a separate SCLK input is sent, the receiver detects at the middle or

+ ve edge or ve edge of the clock pulses that whether the data-input is 1 or 0 and saves the bits

in an 8-bit shift register. The processing element at the port (peripheral) saves the byte at a port

register from where the microprocessor reads the byte.

Master output slave input (MOSI) and Master input slave output (MISO) MOSI when the SCLK is sent from the sender to the receiver and slave is forced to synchronize sent

inputs from the master as per the inputs from master clock.

MISO when the SCLK is sent to the sender (slave) from the receiver (master) and slave is forced to

synchronize for sending the inputs to master as per the master clock outputs.

Synchronous serial input is used for interprocessor transfers, audio inputs and streaming data

inputs.

Synchronous Serial Output Device (Device Serial Bits and synchronisation clock signal at a port

output)


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Example Synchronous Serial Output

Inter-processor data transfer, multiprocessor communication, writing to CD or hard disk, audio

Input/output, video Input/output, dialer output, network device output, remote TV Control,

transceiver output, and serial I/O bus output or writing to flash memory using SDIO

SYNCHRONOUS SERIAL OUTPUT Each bit in each byte sent in synchronization with a clock.

Bytes sent at constant rates. If clock period = T, then data transfer rate is (1/T) bps.

Sender either sends the clock pulses at SCLK pin or sends the serial data output and clock pulse-

input through same output line with clock pulses either suitably modulate or encode the serial

output bits.

Synchronous serial output using shift register The processing element at the port (peripheral) sends the byte through a shift register at the port

to where the microprocessor writes the byte.

Synchronous serial output is used for interprocessor transfers, audio outputs and streaming data

outputs

Synchronous Serial Input/Output


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Synchronous Serial Input/Output Each bit in each byte is in synchronization at input and each bit in each byte is in synchronization at

output with the master clock output .

The bytes are sent or received at constant rates. The I/Os can also be on same I/O line when

input/output clock pulses either suitably modulate or encode the serial input/output, respectively.

If clock period = T, then data transfer rate is (1/T) bps.

The processing element at the port (peripheral) sends and receives the byte at a port register to or

from where the microprocessor writes or reads the byte

Asynchronous Serial input RxD at UARTCOM Port

Asynchronous Serial port line RxD (receive data). Does not receive the clock pulses or clock information along with the bits.

Each bit is received in each byte at fixed intervals but each received byte is not in synchronization.

Bytes separate by the variable intervals or phase differences

Asynchronous serial input also called UART input if serial input is according to UART protocol

Example Serial Asynchronous Input

Asynchronous serial input is used for keypad inputs and modem inputs in computers

Keypad controller serial data-in, mice, keyboard controller, modem input, character send inputs on

serial line [also called UART (universal receiver and transmitter) input when according to UART

mode]


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Format of bits at UART protocol

UART protocol serial line format Starting point of receiving the bits for each byte is indicated by a line transition from 1 to 0 for a

period = T. [T1 called baud rate.]

If senders shift-clock period = T, then a byte at the port is received at input in period = 10.T or 11.T

due to use of additional bits at start and end of each byte.

Receiver detects n bits at the intervals of T from the middle of the start indicating bit. The n = 0, 1,

, 10 or 11 and finds whether the data-input is 1 or 0 and saves the bits in an 8-bit shift register.

Processing element at the port (peripheral) saves the byte at a port register from where the

microprocessor reads the byte.Asynchronous Serial Output

Asynchronous output serial port line TxD (transmit data).

Each bit in each byte transmit at fixed intervals but each output byte is not in synchronization

(separates by a variable interval or phase difference). Minimum separation is 1 stop bit interval

TxD Does not send the clock pulses along with the bits.

Sender transmits the bytes at the minimum intervals ofn.T. Bits receiving starts from the middle of

the start indicating bit, n = 0, 1, , 10 or 11 and sender sends the bits through a 10 or 11 -bit shift

register.

The processing element at the port (peripheral) sends the byte at a port register to where the

microprocessor is to write the byte.

Synchronous serial output is also called UART output if serial output is according toUART protocol


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Example Serial Asynchronous Output

Output from modem, output for printer, the output on a serial line [also called UART output whenaccording to UART]

Half Duplex Half duplex means as follows: at an instant communication can only be one way (input or output)

on a bi-directional line.

An example of half-duplex modetelephone communication. On one telephone line, the talk can

only in the halfduplex way mode

Full Duplex

Full duplex means that at an instant, the communication can be both ways.

An example of the full duplex asynchronous mode of communication is the communication

between the modem and the computer though TxD and RxD lines or communication using SI in

modes 1, 2 and 3 in 8051

Parallel Port single bit input Completion of a revolution of a wheel,

Achieving preset pressure in a boiler,

Exceeding the upper limit of permitted weight over the pan of an electronic balance,

Presence of a magnetic piece in the vicinity of or within reach of a robot arm to its end point and

Filling of a liquid up to a fixed level.

Parallel Port Output- single bit PWM output for a DAC, which controls liquid level, or temperature, or pressure, or speed or

angular position of a rotating shaft or a linear displacement of an object or a d.c. motor control

Pulses to an external circuit

Control signal to an external circuit

Parallel Port Input- multi-bit ADC input from liquid level measuring sensor or temperature sensor or pressure sensor or speed

sensor or d.c. motor rpm sensor Encoder inputs for bits for angular position of a rotating shaft or a linear displacement of an object

LCD controller for Multilane LCD display matrix unit in a cellular phone to display on the screen the

phone number, time, messages, character outputs or pictogram bit-images for display screen or e-

mail or

web page

Print controller output

Stepper-motor coil driving bits


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Parallel Port Input-Output PPI 8255 Touch screen in mobile phone

Ports or Devices

Communication and communication protocolsTwo Modes of communication between the devices and computer system

Full Duplex Both devices or device and computer system simultaneously communicate each other Half Duplex Only one device can communicate with another at an instance

Three ways of communication between the ports or devices

Synchronous

Iso-synchronous

Asynchronous

1. Synchronous and Iso-synchronous Communication in Serial Ports or DevicesSynchronous Communication

When a byte (character) or a frame (a collection of bytes) in of the data is received or transmitted

at the constant time intervals with uniform phase differences, the communication is called as

synchronous. Bits of a full frame are sent in a prefixed maximumtime interval

Iso-synchronous

Synchronous communication special case when bits of a full frame are sent in the maximum time

interval, which can be variable.

Synchronous Communication

Clock information is transmitted explicitly or implicitly in synchronous communication. The

receiver clock continuously maintains constant phase difference with the transmitter clock. Bits of a data

frame maintain uniform phase difference and are sent within a fixed maximum time interval

Example of synchronous serial communication

Frames sent over a LAN. Frames of data communicate with the constant time intervals between

each frame remaining constant.

Another example is the inter-processor communication in a multiprocessor system Optional

Synchronous Code bits

Optional Sync Code bits or bi-sync code bits or frame start and end signaling bitsDuring

communication few bits (each separated by interval T) sent as Sync code to enable the frame

synchronization or frame start signaling.

Code bits precede the data bits.


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Second characteristics of synchronous communication

2. A clock ticking at a certain rate has always to be there for transmitting serially the bits of all the bytes

(or frames) serially. Mostly, the clock is notalways implicitto the synchronous data receiver. The

transmittergenerallytransmits the clock rate information

2. ASYNCHRONOUS COMMUNICATION FROM SERIAL PORTS OR DEVICES

Asynchronous Communication

Clocks of the receiver and transmitter independent, unsynchronized, but of same frequency and variable

phase differences between bytes or bits of two data frames, which may not be sent within any prefixed

time intervalExample of asynchronous communication

UART Serial, Telephone or modem communication.

RS232C communication between the UART devices

Each successive byte can have variable time-gap but have a minimum in-between interval and no

maximum limit for full frame of many bytes

Two characteristics of asynchronous communication

1. Bytes (or frames) need not maintain a constant phase difference and are asynchronous, i.e., not

in synchronization. There is permission to send either bytes or frames at variable time intervalsThis

facilitates in-between handshaking between the serial transmitter port and serial receiver port

2.Though the clockmust ticking at a certain rate always has to be there to transmit the bits of a single byte

(or frame) serially, it is always implicitto the asynchronous data receiver and is independent of the

transmitter

Clock Features

_ The transmitter does not transmit(neither separately nor by encoding using modulation) along with the

serial stream of bits any clock rate information in the asynchronous communication and receiver clock thus

is not able to maintain identical frequency and constant phase difference with transmitter clock

Example: IBM personal computer has two COM ports (communication ports)

COM1 and COM2 at IO addresses 0x2F8-0xFF and 0xx38-0x3FF


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Handshaking signalsRI, DCD, DSR, DTR, RTS, CTS, DTR

Data BitsRxD and TxD

Example: COM port and Modem Handshaking signals

When a modem connects, modem sends data carrier detectDCD signal at an instance t0.

Communicates data set ready(DSR) signal at an instance t1 when it receives the bytes on the line.

Receiving computer (terminal) responds at an instance t2 by data terminal ready (DTR) signal.

After DTR, request to send(RTS) signal is sent at an instance t3

Receiving end responds by clear to send(CTS) signal at an instance t4. After the response CTS, the

data bits are transmitted by modem from an instance t5 to the receiver terminal.

Between two sets of bytes sent in asynchronous mode, the handshaking signals RTS and CTS can

again be exchanged. This explains why the bytes do not remain synchronized during asynchronous

transmission.

COM port and Modem Signals

3. Communication Protocols

1. Protocol

protocol is a standard adopted, which tells the way in which the bits of a frame must be sent from a device

(or controller or port or processor) to another device or system [Even in personal communication we

follow a protocol we say Hello! Then talk and then say good bye!]

A protocol defines how are the frame bits:


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1) sent synchronously or Iso synchronously or asynchronously and at what rate(s)?

2) preceded by the header bits?

3) How the receiving device address communicated so that only destined device activates and receives

the bits?

[Needed when several devices addressed though a common line (bus)]

4) How can the transmitting device address defined so that receiving device comes to know the source

when receiving data from several sources?

5) How the frame-length defined so that receiving device know the frame-size in advance?

6) Frame-content specifications Are the sent frame bits specify the control or device configuring or

commend or data?

7) Are there succeeding to frame the trailing bits so that receiving device can check the errors, if any in

reception before it detects end of the frame ?A protocol may also define:

8) Frame bits minimum and maximum length permitted per frame

9) Line supply and impedances and line-Connectors specifications

Specified protocol at an embedded system port or communication device

IO port bits sent after first formatted according to a specified protocol, which is to be followed when

communicating with another device through an IO port or channel

Protocols

HDLC, Frame Relay, for synchronous communication

For asynchronous transmission from a device port RS232C, UART, X.25, ATM, DSL andADSL

For networking the physical devices in telecommunication and computer networks Ethernet and

token ring protocols used in LAN Networks

Protocols in embedded network devices

For Bridges and routers

Internet appliances application protocols and Web protocols

HTTP (hyper text transfer protocol),

HTTPS (hyper text transfer protocol Secure Socket Layer),

SMTP (Simple Mail Transfer Protocol),

POP3 (Post office Protocol version 3),

ESMTP (Extended SMTP),


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File transfer, Boot Protocols in embedded devices network

TELNET (Tele network),

FTP (file transfer protocol),

DNS (domain network server),

IMAP 4 (Internet Message Exchange Application Protocol) and

Bootp (Bootstrap protocol).

Wireless Protocols in embedded devices network

Embedded wireless appliances uses wireless protocolsWLAN 802.11, 802.16, Bluetooth, ZigBee, WiFi,

WiMax,

Exemplary Protocol HDLC

HDLC (High-level Data Link Control) is a standard protocol for the data link network.

For synchronous communication between two data link layers on a network.

Formats of bits in a HDLC frame

There are two formats Standard HDLC and Extended HDLC for 28 and 216 destination devices or

systems, respectively .

Sequence of bits in a HDLC frame

Frame start signaling flag bits;

Compulsory- Flag bits at start are (01111110) Address bits for destination compulsory;

8 bits in Standard HDLC Header format and 16 bits in extended format

Control bits Case 1: Information Frame; Compulsory as per case 1 or 2 or 3First bit 0, next 3-bits N(S),

next bit $P/F and last 3-bits N(R) in standard format

Note: N(R) and N(S) = 7-bits each in extended format

Control bits Case 2: Supervisory Frame; First two bits (10), next 2- bits# RR or RNR or REJ or SREJ, next

bit P/F and last 3-bits N(R) instandard format. Note: N(R) and N(S) = 7-bits each in extended format

Control bits Case 3: Un-numbered Frame; First two bits (11), next 2-bits ^M, next bit P/F and last 3-bit

remaining bits for M. [8-bits are immaterial after M bits in extended format]

Data bits; Compulsory; m frame bits transmitted; Each bit is at the serial line for time T or, each frame is

at the line for time m.T. [Note: Five consecutive 1s when present, then one additional 0 is stuffed in the


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data. This is to distinct the data from the start and ending bytes at the header and at the end. Number of

frame bits extend.]

FCS (Frame Check Sequence) bits; Compulsory; 16 bits in standard format and 32 in extended format

Frame End flag bits; Compulsory; Flag bits at end = (01111110)

NOTES

P/F when 1 then it means a primary (command) device is polling a secondary station. Polling

means to

detect through an acknowledgement from that; when 0 then receiving device has no data to

transmit; it is just responding.

N(R) sequence number of frame received earlier from a device to which this HDLC frame is being

sent N(S) sequence number of frame sending now to that device

This facilitates indirectly an acknowledgement of the past in the new frame sending now.

RR- A message in control bits in case 2, which conveys Receiver Ready

RNR - Receiver Not Ready

REJ Reject (Sent when a message rejects). Note there is no Accepted message as HDLC follows

negative

ACK protocol method. Like a child, who cries when milk not received, if given no need to cry!

SREJ Selectively Reject Frame received out-of-sequence, repeat suggested.

EXEMPLARY PROTOCOL RS232C

For asynchronous communication between two data serial links on a network,between a data

communication equipment and data terminal equipment

RS232C a standard protocol used in IBM PC COM ports, keyboard, computer mice and

For the data serial link network in UART bit format

DTE and DCE

RS232C communication is between a DTE (computer) COM (communication) port and a DCE

(modem) port.

DTE stands for 'Data Terminal Equipment'.


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DCE stands for 'Data Communication Equipment'.

RS232C is a standard for interfacing signals between DCE and DTE.

Sequence of serial bits in an RS232C Byte

Data BitsRxD and TxD lines

_ As per UART standard formats on RxD and TxD lines

Voltage Levels at TxD and RxD lines in RS232C

logic 1Receiver end voltage level

from 3 V to 25 V

logic 0 Receiver end voltage level

from + 3 V to + 25 V

logic 1

Transmitter end voltage levelfrom 5 V to 15 V

logic 0 Transmitter end voltage level

from + 5 V to + 15 V

opposite to that of TTL logic

wider noise margin to enable long distance

Communication

RS232C Connector

9 pin and 25-pin in case of IBM COM port

Can be simpler

Handshaking signals on 9 Pin connector

_ Handshaking signalsRI, DCD, DSR, DTR, RTS, CTS, DTR

Voltage levels at Handshaking signals

_ TTL standard

Example: 9-pin Connector Handshaking signals

RI to indicate ring available at data communication equipment receiving end

When a modem connects, modem sends data carrier detectDCD signal at an instance t0.

Communicates data set ready(DSR) signal at an instance t1 when it receives the bytes on the

line.

Receiving end responds at an instance t2 by data terminal ready (DTR) signal.


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Example: COM port and Modem Handshaking signals

After DTR, request to send(RTS) signal is sent at an instance t3

Receiving end responds by clear to send(CTS) signal at an instance t4. After the response CTS, the

data bits are transmitted by modem from an instance t5 to the receiver terminal.

Between two sets of bytes sent in asynchronous mode, the handshaking signals RTS and CTS can

again be exchanged. This explains why the bytes do not remain synchronized during asynchronous

transmission.

RS232C port in a computer Used up to 9600 baud per s asynchronous serial transmission rate with UART mode

communication.

Generally baud rates set at 300, 600, 1200, 4800 and 9600.

When transmitting upto 0.25 m or 1 m on cable (untwisted) the maximum baud rate can be 115.2 k

or 38.4k baud per s, respectively

RS232C port for keyboard serial communication

Communication at 1200 baud per s asynchronous serial transmission rate with UART mode

communication at IBM PC COM port.


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The signals used are RTS, CTS, TxD and RxD for keypad communication.

A mice port RS232C COM in the computer

A mice port can also be RS232C COM port in the computer (Alternative USB)

Handshaking bits are RTS, CTS and data bits are at TxD

Draws power from RTS and ground line

Voltage levels: TTL logic 1 derived from RTS line itself ground

COM Port Emulation

Assume a mobile smart phone Bluetooth device for personal area wireless network.

Bluetooth device protocol provides for emulation as DCE serial port, which can now communicate

in UART mode When computer on the other hand has a serial port called COM port

Mobile device placed on a cradle

The mobile device port data-pins connects the cradle pins. The cradle connects the computer or

laptop COM port.

The mobile emulated COM Bluetooth and computer serial port communicate. The data (for

example, pictures or address book data) between them synchronizes between COM and emulated

Bluetooth serial device ports

2. UART

UART Bits

Idle StateA linenon-return to zero (NRZ) state. It means in idle state the logic state is 1 at the serial line.

Byte start signaling flag bit Compulsory- Start bit 1 to 0 transition, which receiver detect at

the middle of bit interval T [T1 = prefixed baud rate.]


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Data bits

After start bit; 8 bits transmitted on TxD line and received on RxD line during period of 8 T

(receiver detect at the middle of each bit interval T ), In earlier circuits, the number of data bits

could also be set 5,

6 or 7 in place of 8

Full or half duplex

Address bits for destination

Not provided Can be indirectly sent by setting a programmable bit P = 0 or 1 as per receivers processing circuit

or ProgrammingControl or error detect bitOne bit- P-bit optional

Present in 11T mode

P bit can be used to detect parity error

P-bit can be used to interpret the preceding byte not as data but as address or command or parityas per the processing circuit for serial bits at receiver

Byte end flag bit

Compulsory- Minimum one stop bit at Logic 1 [In earlier circuits, the number of stop bits could also be set

1 or 2 in place of 1]

Disconnected State

Zero (Z) state

Disconnected serial line logic state is 0UART 8250

UART 8250 includes a 8-bit one byte buffer only and was used earlier in original IBM PC COM port, which

had 8-bit register UART port and did not include any FIFO buffer for the receiving or transmitting

bytes.

UART 16550

UART 16550 includes a 16-byte buffer and is nowadays used more commonly as compared to earlier

original IBM PC COM port, which had 8-bit register UART port, was based on 8250 and did not include

FIFO buffer.

The Handshaking Protocol

Strobe Protocol


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1. Master asserts req to receive data

2. Servant puts data on bus within time taccess3. Master receives data and deasserts req4. Servant ready for next request

Handshake Protocol

1. Master asserts req to receive data

2. Servant puts data on bus and asserts ack3. Master receives data and deasserts req4. Servant ready for next request

The Strobe & Handshake combined


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Fast-response case1. Master asserts req to receive data2. Servant puts data on bus within time t

access(wait

line is unused)3. Master receives data and deasserts req4. Servant ready for next request

Slow-response case1. Master asserts req to receive data2. . Servant cant put data within t

access,

asserts waitack3. Servant puts data on bus and deassertswait

4. Master receives data and deasserts req5. Servant ready for next request

TIMING AND COUNTING DEVICESTimer

Timer is a device, which counts the input at regular interval (T) using clock pulses at its input.

The counts increment on each pulse and store in a register, called count register

Output bits (in a count register or at the output pins) for the present counts.

Evaluation of Time

The counts multiplied by the interval T give the time.

The (present counts initial counts) T interval gives the time interval between two instances when

present count bits are read and initial counts were read or set.Timer

Has an input pin (or a control bit in control register) for resetting it for all count bits = 0s.

Has an output pin (or a status bit in status register) for output when all count bits = 0s after

reaching the maximum value, which also means after timeout or overflow


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Counter

A device, which counts the input due to the events at irregular or regular intervals.

The counts gives the number of input events or pulses since it was last read.

Has a register to enable read of present counts

Functions as timer when counting regular interval clock pulses Has an input pin (or a control bit in

control register) for resetting it for all count bits = 0s.

Has an output pin (or a status bit in status register) for output when all count bits = 0s after reaching

the maximum value, which also means after timeout or overflow.

Timer or Counter Interrupt

_ When a timer or counter becomes 0x00 or 0x0000 after 0xFF or 0xFFFF (maximum value), it can

generate an interrupt, or an output Time-Out or set a status bit TOV

Free running Counter (Blind running Counter)A counting device may be a free running (blind counting) device giving overflow interrupts atfixed intervals


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A pre-scalar for the clock input pulses to fix the intervals

Free Running CounterIt is useful

for action or initiating chain of actions, processor interrupts at the preset instances

noting the instances of occurrences of the events

processor interrupts for requesting the processor to use the capturing of counts at the inputinstance comparing of counts on the events for future Actions

Free running (blind counting) device Many Applications Based on

comparing the count (instance) with the one preloaded in a compare register [an additional

register for defining an instance for an action]

capturing counts (instance) in an additional register on an input event. [An addition input pin for

sensing an event and saving the counts at the instance of event and taking action.]

Free running (Blind Counts) input OC enable pin (or a control bit in control register)

For enabling an output when all count bits at free running count = preloaded counts in thecompare register.

At that instance a status bit or output pin also sets in and an interrupt OCINT of

processor can occur for event of comparison equality.

Generates alarm or processor interrupts at the preset times or after preset interval from

another event


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Free running (Blind Counts) input capture -enable pin (or a control bit in control register) for

Instance of Event Capture

A register for capturing the counts on an instance of an input (0 to 1 or 1 to 0 or toggling) transition

_ A status bit can also sets in and processor interrupt can occur for the capture event

Free running (Blind Counts) Pre-scaling

Prescalar can be programmed as p = 1, 2, 4, 8, 16, 32, .. by programming a prescaler register.

Prescalar divides the input pulses as per the programmed value ofp.

Count interval = p T interval

T = clock pulses period, clock frequency = T 1

Free running (Blind Counts) Overflow

It has an output pin (or a status bit in status register) for output when all count bits = 0s after reaching

the maximum value, which also means after timeout or overflow Free running n-bit counter overflows after p 2n T interval

Uses of a timer device

Real Time Clock Ticks (System Heart Beats). [Real time clock is a clock, which, once the system

starts, does not stop and can't be reset and its count value can't be reloaded. Real time endlessly

flows and never returns back!] Real Time Clock is set for ticks using prescaling bits (or rate set bits)

in appropriate control registers.

Initiating an event after a preset delay time. Delay is as per count value loaded.

Initiating an event (or a pair of events or a chain of events) after a comparison(s) with between the

pre-set time(s) with counted value(s). [It is similar to a preset alarm(s).].

A preset time is loaded in a Compare Register. [It is similar to presetting an alarm].

Capturing the count value at the timer on an event. The information oftime(instance of the event) is

thus stored at the capture register.

Finding the time interval between two events. Counts are captured at each event in capture

register(s) and read. The intervals are thus found out.

Wait for a message from a queue or mailbox or semaphore for a preset time when using RTOS.

There is a A predefined waiting period is done before RTOS lets a task run.

Watchdog timer. It resets the system after a defined time.

Baud or Bit Rate Control for serial communication on a line or network.


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Timer timeout interrupts define the time of each baud Input pulse counting when using a timer,

which is ticked by giving non periodic inputs instead of the clock inputs. The timer acts as a counter

if, in

place of clock inputs, the inputs are given to the timer for each instance to be counted.

Scheduling of various tasks.

A chain of software-timers interrupt and RTOS uses these interrupts to schedule the tasks.

Time slicing of various tasks. A multitasking or multi-programmed operating system presents the

illusion that multiple tasks or programs are running simultaneously by switching between

programs very rapidly, for example, after every 16.6 ms.

Process known as a context switch. [RTOS switches after preset time-delay from one running task

to the next. task. Each task can therefore run in predefined slots of time]

Time division multiplexing (TDM) Timer device used for multiplexing the input from a number of channels.

Each channel input allotted a distinct and fixed-time slot to get a TDM output. [For example,

multiple telephone calls are the inputs and TDM device generates the TDM output for launching it

into the optical fiber.

TIMER STATES


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Software Timer A software, which executes and increases or decreases a count-variable (count value) on an

interrupt from on a system timer output or from on a realtime clock interrupt.

The software timer also generate interrupt on overflow of count-value or on finishing value of the

count variable.

System clock In a system an hardware-timing device is programmed to tick at constant intervals.

At each tick there is an interrupt

A chain of interrupts thus occur at periodic intervals.


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The interval is as per a presetcount value

The interrupts are called system clock interrupts, when used to control the schedules and timings of the

system

Software timer (SWT)

SWT is a timer based on the system clock interrupts The interrupt functions as a clock input to an SWT.

This input is common to all the SWTs that are in the list of activated SWTs.

Any number of SWTs can be made active in a list.

Each SWT will set a status flag on its timeout (count-value reaching 0).

SWT Actions are analogous to that of a hardware timer. While there is physical limit (1, 2 or 3 or 4) for the

number of hardware timers in a system, SWTs can be limited by the number of interrupt vectors provided

by the user.

Certain processors (microcontrollers) also defines the interrupt vector addresses of 2 or 4 SWTs

WATCHDOG TIMER A timing device such that it is set for a preset time interval and an event must occur during that

interval else the device will generate the timeout signal on failure to get that event in the watched

time interval.


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On that event, the watchdog timer is disabled to disable generation of timeout or reset

Timeout may result in processor start a service routine or start from beginning

Example Assume that we anticipate that a set of tasks must finish in 100 ms interval.

The watchdog timer is disabled and stopped by the program instruction in case the tasks finish within100 ms interval.

In case task does not finish (not disabled by the program instruction), watchdog timer generates

interrupts after 100 ms and executes a routine, which is programmed to run because there is failure of

finishing the task in anticipated interval.

Watchdog timer application An application in mobile phone is that display is off in case no GUI interaction takes place within a

watched time interval.

The interval is usually set at 15 s, 20 s, 25 s, 30 s in mobile phone.

This saves power.

An application in temperature controller is that if controller takes no action to switch off the

current within preset watched time interval, the current is switched off and warning signal is

raised as indication of controller failure. Failure to switch off current may burst a boiler in which

water is heated.

Provisioning of watchdog timer

A software task can also be programmed as a watchdog timer

Microcontroller may also provide for a watchdog timer.

68HC11 microcontroller watchdog timer

There are two registers, CONFIG (system configuration control register) and COPRST (computer

operating properly and processor reset on failure).

They are for programming the interrupts of the watchdog timer. CONFIG has a bit, NOCOP. It

configures when processor writes the configuration word at the address 0x003F. NOCOP is the 2nd

bit of CONFIG If NOCOP is reset to 0 the COP facility is enabled.

[COP means computer (68HC11 watchdog timer operating properly]. COP facility provides for

keeping a watch on the user program execution time Computer-reset control register COPRST

When the user program takes a longer time in routine than planned or expected by the user

software the user provides for storing at desired intervals; firstly, the 0x55 and then the 0xAA at

the COPRST.

Watchdog timer overflows (time outs)68HC11 program counter is reset according to the 16 bits (lower and higher bytes) preloaded at the

addresses 0xFFFA and 0xFFFB, respectively. If these 16 bits are the same as the bits in 0xFFFE and


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0xFFFF, then the microcontroller executes instructions as when it resets on power up or else executes the

routine at the 16-bit address fetched from 0xFFFE and 0xFFFF on failure within the watched time interval

Option register,OPTION

The 0th and 1st bit of OPTION at the address 0x0039 are the CR1 and CR0 bits.

IF NOCOP resets (0) and CR1-CR0 =0-0, watchdog timer time out occurs after every 216 Eclockpulses.

As T = 0.5s for the processor E clock output at 2 MHz, the WDT time-out will occur every 16.384

ms (216 0.5s) unless the user software stores at desired intervals before a time out, first the

0x55and then the 0xAA at the computer reset control register COPRST. [After 215 pulses if CR1-

CR0 =0-1, 214 pulses for 1-0, 213 pulses for 1-1].

REAL TIME CLOCK A clock, which is based on the interrupts at preset intervals. An interrupt service routine executes

on each timeout (overflow) of this clock. This timing device once started never resets or never

reloaded with another value. Once it is set, it is not modified later.

Used in a system to save the time and date.

Used in a system to initiate return of control to the system (OS) after the set system clock periods

RTC Application

Assume that a hardware timer of an RTC for calendar is programmed to interrupt after every 5.15 ms

(=1 day period/ 224)

Assume each tick (interrupt) a service routine runs and updates at a memory location. Within one day

(86400 s) there will be 224 ticks, the memory location will reach 0x000000 after reaching the maximum

value 0xFFFFFF.

RTC with 5.5 ms tick

Within 256 days there will be 232 ticks, the memory location will reach 0x00000000 after reaching the

maximum value 0xFFFFFFFF.

A battery is used to protect the memory for long period

RTC for implementing a software timer

A hardware 16-bit timer ticks from processor clock after 0.5 s. It will overflow and execute an

overflow interrupt service routine after 215 s = 32.768 ms.

The interrupt service routine can generate a port bit output after every time it runs or can call a

software routine or send a message for a task. Ifn = 30, the RTC initiated software will run every 30

32.768 ms, which is close to 1 s.

68HC11 microcontroller RTC


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Pulse Accumulator Control Register, PACTL and two lowest significance bits, RT1-RT0 (1st and

0th).

PACTL is write only.

If the RT1-RT0 pair is set =0-0, an RTC interrupt can occur after 213 pulses of the E clock. If the E

clock pulses are of 2 MHz and Tis 0.5 s, the interrupt from a real time clock occurs after every

4.096 ms. If the RT1-RT0 pair is 01, an interrupt can occur after 214 pulses of the E clock, that is,

after 8.192 ms.

If the RT1-RT0 pair is 10, the interrupt can occur after 215 pulses of the E clock, that is after 16.384

ms.

If the RT1-RT0 pair is 11, an interrupt can occur after 216 pulses of the E clock, that is, after 32.768

ms.

The real time clock is based on a free running counter. RT1-RT0 bits control its rate factor RTC disabled or enabled by the I bit in the CC (clock control)

register

Interrupts from real time clocks are also locally masked by the 6th bit, RTI in timer interrupt mask

register2, TMASK2.

Unmask and reset to mask of real time interrupt

RTI is set to unmask and reset to mask the real time interrupt locally.

If RTI and I bits permit the interrupt request for real time, the microcontroller fetches the lower

and higher bytes of the interrupt servicing routine address from the addresses 0xFFF0 (higher

byte) and 0xFFF1 (lower byte)


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IO BUSAny device that is compatible with a system's I/O bus can be added to the system (assuming an

appropriate device driver program is available), and a device that is compatible with a particular I/O bus

can be integrated into any system that uses that type of bus.

I/O devices communicate with theprocessor through an I/O bus, which is separate from the

memory bus that the processor uses to communicate with the memory system.

Embedded systems Networking

Embedded systems connected internally on same IC or systems at very short, short and long

distances can be networked using a type of the I/O buses- CAN, I2C, USB, PCI,

IO Bus for Networking vs. direct connections

Use of I/O bus, as opposed to direct connections between the processor and each I/O device, very

flexible, allowing a system to support many different I/O devices depending on the needs of its users and

allowing users to change the I/O devices that are attached to a system as their needs change.

Main disadvantage of an I/O bus

A bus has a fixed bandwidth that must be shared by all of the devices on the bus.


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Even worse, electrical constraints (wire length and transmission line effects) cause buses to have less

bandwidth than using the same number of wires to connect just two devices.

Essentially, there is a trade-off between interface simplicity and bandwidth

Example

A bus has bandwidth of 2 Mb/s (can be used to transfer 2 Mb data in one s.

If 10 devices are connected, the 2 Mb/s is shared between the networked systems

SERIAL BUS1. A serial bus has very few lines and the number of lines as per the protocol

Serial Bus

1. A wide range of I/O devices without having to implement a specific interface for each I/O device. When

the I/O devices in the distributed embedded systems are networked at long distances of 25 cm and above,

all can communicate through a common serial bus.

Internet or intranet

Using Internet or intranet, a computer or controller or embedded system IO device interface and

globally network with computers and a wide range of devices in the systems

PARALLEL BUS

Using a parallel I/O bus allows a computer or controller or embedded system to interface with

number of internal systems at very short distances without having to implement a specific interface for

each I/O device.

Short distances Wireless Bus protocol

Up to 100 m using wireless personal area network (WPAN)

WPAN protocol without having to implement a specific wireless interface for each I/O device

Allows a handheld computer or controller or embedded system I/O device to interface and

network with number of handheld system I/O devices of other handheld

SPI, SCI, SI and SDIO Port/devices for Serial Data CommunicationMicrocontroller internal devices for SPI or SCI or SI

Synchronous Peripheral Interface (SPI) Port, for example, in 68HC11 and 68HC12 microcontrollers

Asynchronous UART Serial Connect Interface (SCI), for example, SCI port in 68HC11/12

Asynchronous UART mode Serial Interface (SI), for example, SI in 8051

SPI


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Full-duplex Synchronous communication.

SCLK, MOSI and MISO signals for serial clock from master, output from master and input to master,

respectively.

Device selection as master or slave can be done by a signal to hardware input SS. (Slave select when

0) pin

SPI signals

68HC11/12 SPI signals at Port PD

68HC11/12 SPI Features1. Programmable rates for the clock


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2. Programmable as slave or master or by SS input bit

3. Programmable for the instance of the occurrence of

negative or positive clock edge and positive edges

4. Programmable for open-drain output or totem pole output

Serial Connect Interface (SCI) Port

UART asynchronous mode port

Full-duplex mode

SCI programmable for transmission and for reception

68HC11 SCI signals at Port PD

68HC11/12 SCI Features

1.SCI baud rates are fixed as per rate and prescaling bits

2. T8 and R8 for the inter-processor communication in 11- bit format

3. receiver wake up feature programmable by RWU

4. Signals programmable for RxD or TxD using DDR


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Serial Interface (SI) Port UART 10T or 11T mode asynchronous port interface.

Functions as USRT (universal synchronous receiver and transmitter) also.

SI is therefore synchronous- asynchronous serial communication port called USART (universal

synchronous-asynchronous receiver and transmitter) port.

SI is an internal serial IO device in 8051.

SI Full duplex signals Mode 1, 2 or 3

SI Half duplex signals Mode 0


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SI Control bits programming Mode 0 Half- duplex synchronous mode of operation, called. When a 12 MHz crystal is at 8051,

and is attached to the processor, the clock bits are at the intervals of 1 s.

Mode 1 or 2 or 3 Full- duplex asynchronous serial communication.

Modes 1 and 3 baud rate programmed Using the timer bits.

Mode 2 baud rate programming using SMOD bit at an SFR called PCON, when is used, the rate is

programmable at 1/64 or 1/32 of oscillator frequency at 8051.

T8 and R8 programming, when using 11- bit format, provides the 10th bit for error detection or for

indicating whether the sent data byte is a command or data for the receiving SI device

8051 SI signals at Port P3.1 and P3.0

1. Mode 0 Half-duplex synchronous mode of operation

2. Mode 1 or 2 or 3 Full-duplex asynchronous serial communication

3. Signals not programmable for RxD or TxD no DDR in 8051

4. T8 and R8 for the inter-processor communication in 11- bit format

Secure Digital Association (SD) SD an association of over 700 companies started from 3 companies in 1999

Created a new flash memory card format, called SD format for IOs

SDIO card has become popular feature in handheld mobile devices, PDAs, digital cameras and embedded

systems.

SD card size just 0.14 cm 2.4 cm 3.2 cm.

Allowed to stick out of the handheld device open slot, which can be at the top in order to facilitateinsertion of the SD card

SDIO card host controller A processing element functions used SDIO host controller to process the IOs.

Controller may include SPI controller to support SPI mode for the IOs and also supports the needed

protocol functionality internally


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SDIO (Secure Digital Input Output) card

Can have upto eight logical functions.

provides additional memory storage in SD format

Functions include IOs with several protocols, for example, IrDA adapter, Ethernet adapter, GPS or WiFi,

Bluetooth, WLAN, digital camera, barcode or RFID code readers

SDIO Functions and Card1. SDIO (Secure Digital Input Output) up to eight logical functions

during communication

2. CRC checks on the transferred data and

3. Specifies capabilities for additional tries by retransmission on

error

4. Data communication 48-bit command/ request format for 48-bit

control register/ status register bits

5. Supports data transfer in block of bytes

6. Programmable or SPI (20 Mbps) or 1-bit SD (25 Mbps) or 4-bit

SD (100 Mbps by 4 serial bits in parallel) communication

SERIAL BUS COMMUNICATION PROTOCOLS I2C

Interconnecting number of device circuits, Assume flash memory, touch screen, ICs for measuring temperatures and ICs for measuring

pressures at a number of processes in a plant.

ICs mutually network through a common synchronous serial bus I2C

An 'Inter Integrated Circuit' (I2C) bus, a popular bus for these circuits.

Synchronous Serial Bus Communication for networking Each specific I/O synchronous serial device may be connected to other using specific interfaces, for

example, with I/O device using I2C controller

I2C Bus communication use of only simplifies the number of connections and provides a common

way (protocol) of connecting different or same type of I/O devices using synchronous serialcommunication

IO I2C Bus

Any device that is compatible with a I2C bus can be added to the system (assuming an appropriate

device driver program is available), and a I2C device can be integrated into any system that uses

that I2C bus.


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Originally developed at Philips Semiconductors Synchronous Serial Communication 400 kbps up to 2 m

and 100 kbps for longer distances

Three I2C standards

Industrial 100 kbps I2C,

100 kbps SM I2C,

400 kbps I2CDistributed Systems (ICs) on I2C Bus usingserial data line and clock


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I2C Bus The Bus has two lines that carry its signals one line is for the clock and one is for bi-directional

data.

There is a standard protocol for the I2C bus.

Device Addresses and Master in the I2C bus Each device has a 7-bit address using which the data transfers take place.

Master can address 127 other slaves at an instance.

Master has at a processing element functioning as bus controller or a microcontroller with I2C

(Inter Integrated Circuit) bus interface circuit.

Slaves and Masters in the I2C bus

Each slave can also optionally has I2C (Inter Integrated Circuit) bus controller and processing

element.

Number of masters can be connected on the bus.

However, at an instance, master is one, which initiates a data transfer on SDA (serial data) line and

which transmits the SCL (serial clock) pulses. From master, a data frame has fields beginning from

start bit

Bits as per I2C Bus Protocol


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Synchronous Serial Bus Fields and its length First field of 1 bitStart bit similar to one in an UART

Second field of 7 bitsaddress field. It defines the slave address, which is being sent the data frame

(of many bytes) by the master

Third field of 1 control bitdefines whether a read or write cycle is in progress

Fourth field of 1 control bitdefines whether is the present data is an acknowledgment (fromslave)

Fifth field of 8 bitsI2C device data byte

Sixth field of 1-bitbit NACK (negative acknowledgement) from the receiver. If active then

acknowledgment after a transfer is not needed from the slave, else acknowledgement is expected

from the slave

Seventh field of 1 bit stop bit like in an UART

Disadvantage of I2C bus

Time taken by algorithm in the hardware that analyzes the bits through I2C in case the slave hardware

does not provide for the hardware that supports it. Certain ICs support the protocol and certain do not.

Open collector drivers at the master need a pull-up resistance of 2.2 K on each line

=================================================================================

SERIAL BUS COMMUNICATION PROTOCOLS CAN

Distributed Control Area Network example - a network of embedded systems in automobile

Serial

CAN Serial Bus Communication for networking

CAN-bus line usually interconnects to a CAN controller between line and host at the node. It gives

the input and gets output between the physical and data link layers at the host node. The CAN controller has a BIU (bus interface unit consisting of buffer and driver), protocol

controller, status-cum control registers, receiver-buffer and message objects. These units connect

the host node through the host interface circuit


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Three standards: 33 kbps CAN, 110 kbps Fault Tolerant CAN, 1 Mbps High Speed CAN

CAN protocolThere is a CAN controller between the CAN line and the host node.

CAN controller BIU (Bus Interface Unit) consisting of a buffer and driver

Method for arbitrationCSMA/AMP (Carrier Sense Multiple Access with Arbitration on Message

Priority basis)

Each Distributed Node Uses:

Twisted Pair Connection up to 40 m for bi-directional data

Line, which pulls to Logic 1 through a resistor between the line and + 4.5V to +12V. :

Line Idle state Logic 1 (Recessive state)Uses a buffer gate between an input pin and the CAN line

Detects Input Presence at the CAN line pulled down to dominant (active) state logic 0 (ground ~ 0V) by a

sender to the CAN line

Uses a current driver between the output pin and CAN line and pulls line

Down to dominant (active) state logic 0 (ground ~ 0V) when sending to the CAN line


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Protocol defined start bit followed by six fields of frame bits Data frame starts after first detecting that

dominant state is not present at the CAN line with logic 1 (R state) to 0 (D state transition) for one serial

bit interval

After start bit, six fields starting from arbitration field and ends with seven logic 0s end-field

3-bit minimum inter frame gap before next start bit (RD transition) occurs CAN Protocol defined

frame bits

Protocol defined First field in frame bits

First field of 12 bits 'arbitration field.

11-bit destination address and RTR bit(Remote Transmission Request)

Destination device address specified in an 11-bit sub-field and whether the data byte being sent is a

data for the device or a request to the device in 1-bit sub-field.

Maximum 211 devices can connect a CAN controller in case of 11-bit address fiel standard 11-bit

address standard CAN

Identifies the device to which data is being sent or request is being made.

When RTR bit is at '1', it means this packet is for the device at destination address. If this bit is at '0'(dominant state) it means, this packet is a request for the data from the device.

Protocol defined frame bits Second field Second field of 6 bitscontrol field.

The first bit is for the identifiers extension.

_ The second bit is always '1'.

_ The last 4 bits specify code for data Length


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Protocol defined frame bits Third field Thirdfield of 0 to 64 bits Its length depends on the data length

code in the control field.

Protocol defined frame bits Fourth field Fourth field(third if data field has no bit present) of 16 bits

CRC (Cyclic Redundancy Check) bits.

The receiver node uses it to detect the errors, if any, during the transmission

Protocol defined frame bits Fifth field

Fifth field of 2 bitsFirst bit 'ACK slot'

ACK = '1' and receiver sends back '0' in this slot when the receiver detects an error in the reception.

Sender after sensing '0' in the ACK slot, generally retransmits the data frame.

Second bit 'ACK delimiter' bit. It signals the end of ACK field.

If the transmitting node does not receive any acknowledgement of data frame within a specified

time slot, it should retransmit.Protocol defined frame bits Sixth field

Sixth field of 7-bits end- of- the frame specification and has seven '0's

=================================================================================

SERIAL BUS COMMUNICATION PROTOCOLS USBUSB Host Applications

Connecting

flash memory cards,

pen-like memory devices,

digital camera,

printer,

mouse-device,

PocketPC,

video games,

Scanner

Serial transmission and reception between host and serial devices

The data transfer is of four types: (a) Controlled data transfer, (b) Bulk data transfer, (c) Interrupt

driven data transfer, (d) Iso-synchronous transfer

A bus between the host system and interconnected number of peripheral devices

USB Protocol Features

Maximum 127 devices can connect a host.

Three standards:

USB 1.1 (a low speed 1.5 Mbps 3 meter channel along with a high speed 12 Mbps 25 meter

channel),

USB 2.0 (high speed 480 Mbps 25 meter channel), and

wireless USB (high speed 480 Mbps 3 m)


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Host connection to the devices or nodes

Using USB port driving software and host controller,

Host computer or system has a host controller, which connects to a root hub.

A hub is one that connects to other nodes or hubs.

A tree- like topology


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Dual Role Devices (DRDs).

DRD device can be a USB device as well as limited capability host. For example, a wireless USB

digitalcamera is USB host when connected to printer and is USB device when connected to personal

computer.

The root hub connection to the hub (s) and node (s)

The root hub connects to the hub (s) and node (s) at level 1. A hub at level 1 connects to the hub (s) and node (s) at level 2 and so on.

Root hub and each hub at a level have a star topology with the next level.

Only the nodes are present at the last level.

USB Device features Can be hot plugged (attached), configured and used, reset, reconfigured and used

Bandwidth sharing with other devices: Host schedules the sharing of bandwidth among the

attached devices at an instance.

Can be detached (while others are in operation) and reattached.

Attaching and detaching USB device or host without rebootingUSB device descriptor

Has data structure hierarchy as follows:

It has device descriptor at the root, which has number of configuration descriptors, which has

number of interface descriptor and which has number of end point descriptor.

Powering USB device A device can be either bus-powered or self- powered.

In addition, there is a power management by software at the host for USB ports

USB protocol

USB bus cable has four wires, one for +5V, two for twisted pairs and one for ground.

Termination impedances at each end as per the device-speed.

Electromagnetic Interference (EMI)- shielded cable for the 15 Mbps USB devices.

Serial signals NRZI (Non Return to Zero (NRZI)

The synchronization clock encoded by inserting synchronous code (SYNC) field before each USB

packet

Receiver synchronizes its bits recovery clock continuously

A polled bus

Host controller regularly polls the presence of a device as scheduled by the software.

It sends a token packet.

The token consists of fields for type, direction, USB device address and device end-point number.

The device does the handshaking through a handshake packet, indicating successful or unsuccessfultransmission. A CRC field in a data packet permits error detection

USB supported three types of pipes

'Stream' with no USB- defined protocol. It is used when the connection is already established and the

data flow starts

'Default Control' for providing access.

'Message' for the control functions for of the device.

Host configures each pipe with the data bandwidth to be used, transfer service type and buffer sizes.


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Wireless USB Wireless extension of USB 2.0 and it operates at UWB (ultra wide band) 3.1 GHZ to 10.6 GHz

frequencies.

For short-range personal area network (high speed 480 Mbps 3 meter or 110 Mbps 10 meter

channel)

FCC has recommended a host wire adapter (HWA) and a device wire adapter (DWA), whichprovides wireless USB solution.

Wireless USB also supports the dual-role devices (DRDs).

DRD device can be a USB device as well as limited capability host. For example, a wireless USB

digital camera is USB host when connected to printer and is USB device when connected to

personal computer.

=================================================================================

FireWire IEEE 1394 Bus Standards for multimedia streaming DevicesConnecting FireWire IEEE 1394a port up to 400 Mbps

1394b up to 800 Mbps Serial iso synchronous data transfer Transfers data at a guaranteed rate Also used in real time devices, such as video device data transfersFireWire IEEE 1394 Applications

_ Multimedia streaming devices digital video cameras, digital camcorders, digital video disk (DVD), set-top boxes, music systems multimedia peripherals, latest hard disk drives, latest high speed printersIEEE 1394 Protocol Features

A single 1394 port can interface up to 63 external FireWire devices. Supports both plug and play and hot plugging. Provides self-powered and bus powered support on the bus.


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PARALLEL BUS DEVICE PROTOCOLS PCI BusParallel bus enables a host computer or system to communicate simultaneously

32-bit or 64-bit with other devices or systems, for example, to a network interface card (NIC) or graphic

card When the I/O devices in the distributed embedded subsystems are networked all can communicate

through a common parallel bus.

PCI connects at high speed to other subsystems having a range of I/O devices at very short distances

(


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PCI device identification

A sixteen16-bit register in a PCI device identifies this number to let that device auto- detect it.

Another sixteen16-bit register identifies a device ID number. These two numbers let allow the

device to carry out its auto-detection by its host computer.

Peripheral Component Interconnect (PCI) Bus

Independent from the IBM architecture.

Number of embedded devices in a computer system use PCI

Three standards for the devices interfacing with the PC

Peripheral Component Interconnect (PCI) Standards

PCI 32bit/33 MHz, and 64bit/66 MHz

PCI Extended (PCI/X) 64 bit/100 MHz ,

Compact PCI (cPCI) Bus

Two super speed versions

PCI Super V2.3 264/528 MBps 3.3V (on 64- bit bus), and 132/264 (on 32-bit bus) and

PCI-X Super V1.01a for 800MBps 64- bit bus 3.3Volt.

PCI bridge

PCI bus interface switches a processor communication with the memory bus to PCI bus.

In most systems, the processor has a single data bus that connects to a switch module PCI bridge

Some processors integrate the switch module onto the same integrated circuit as the processor to

reduce the number of chips required to build a system and thus the system cost.PCI bridge/switch

Communicates with the memory through a memory bus (a set of address, control and data buses), a

dedicated set of wires that transfer data between these two systems.

A separate I/O bus connects the PCI switch to the I/O devices.

Advantage of Separate memory and I/O buses

I/O system generally designed for maximum flexibility, to allow as many different I/O devices as

possible to interface to the computer

Memory bus is designed to provide the maximum-possible bandwidth between the processor and

the memory system.


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32-bit 33 MHz throughput = 133 MBps, full component level, Connector (94-pin connector with 50 signals)

64-bit bus, 66 MHz option

PCI-X (PCI extended)

133 MBps to as much as 1 GBps

Backward compatible with existing PCI cards

Used in high bandwidth devices (Fiber Channel, and processors that are part of a cluster and Gigabit

Ethernet) Maximum 264 MBps throughput, uses 8, 16, 32, or 64 bit transfers

6U cards contain additional pins for user defined I/Os

Live insertion support (Hot-Swap),

Supports two independent buses on the back plane (on different connectors)

Supports Ethernet, Infiniband, and Star Fabric support (Switched fabric based systems) Compact PCI

(cPCI)


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Each PCI device on Bus

Perform a specific function,

May contain a processor and software to perform a specific function.

Each device has the specific memory address-range, specific interrupt-vectors (pre-assigned or

auto configured) and the device I/O port addresses.

A bus of appropriate specifications and protocol interfaces these to the host computer system or

compute

PCI controller Features

Accesses one device at a time

All the devices within host device or system can share the I/O port and memory addresses, but cannot

share the configuration registers

Device cannot modify other configuration registers but can access other device resources or share thework or assist the other device

PCI driver Features

If there are reasons for doing it so, a PCI driver can change the default boot up assignments on

configuration transactions.

PCI Device Initialization

A device can initialize at booting time

Avoids any address collision

Device on boot up disables its interrupt and closes its door to its address space except to the

configuration registers space

PCI BIOS (Basic Input-Output System)

Performs the configuration transactions and then, memory and address spaces automatically map to the

address space in the device hosting system

PCI device Interrupt Handling

A uniquely assigned interrupt type (a number) handles an interrupt.

For example, interrupt type 3 has the interrupt vector address 0x0000C and four bytes at the

address specify the interrupt service routine address.

Interrupt type can be a number between 0x00 and 0xFF. 64 bytes at the standard device

independent configuration registers in a PCI device


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VID: Vendor ID.DID: Device ID.

RID: Revision ID.CR: Common Register.CC: Class Code.SR: Status Register.CL: Cache Line.LT: Latency Timer.BIST: Base Input Tick

HT: Header Type.BA: Base Address.CBCISB: Card Base CIS Pointer.

SS: Sub System.ExpROM: Expansion ROM.MIN_GNT: Minimum Guaranteed timeMAX_GNT: Maximum Guaranteed Time.

=================================================================================

PARALLEL BUS DEVICE PROTOCOLS ARM BUSAMBA (ARM Main Memory Bus Architecture)

AHB (ARM High Performance Bus)

AMBA-AHB interfaces the memory, external DRAM (dynamic RAM controller and on-chip I/O

devices

AMBA-AHB connects to 32-bit data and 32-bit address lines at high speed

AHB maximum bps bandwidthsixteen times ARM processor clock

AMBA (ARM Main Memory Bus Architecture)

APB (ARM Peripheral Bus)

AMBA -APB interfaces ARM processor with the memory AMBAAHB and external -chip I/O devices,

which operate at low speed using a bridge (AMBA-APB bridge)

AMBA-APB bridge

Switches ARM CPU communication with the AMBA bus to APB bus.


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ISA Signal Descriptions

SA19 to SA0 (SA for System Address)

System Address bits 19:0 are used to address memory and I/O devices within the system. These signals may be used

along with LA23 to LA17 to address up to 16 megabytes of memory. Only the lower 16 bits are used during I/O

operations to address up to 64K I/O locations. SA19 is the most significant bit. SA0 is the least significant bit. These

signals are gated on the system bus when BALE is high and are latched on the falling edge of BALE. They remain


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valid throughout a read or write command. These signals are normally driven by the system microprocessor or DMA

controller, but may also be driven by a bus master on an ISA board that takes ownership of the bus.

LA23 to LA17

Unlatched Address bits 23:17 are used to address memory within the system. They are used along with SA19 to SA0to address up to 16 megabytes of memory. These signals are valid when BALE is high. They are "unlatched" and do

not stay valid for the entire bus cycle. Decodes of these signals should be latched on the falling edge of BALE.

AEN

Address Enable is used to degate the system microprocessor and other devices from the bus during DMA transfers.

When this signal is active the system DMA controller has control of the address, data, and read/write signals. This

signal should be included as part of ISA board select decodes to prevent incorrect board selects during DMA cycles.

BALE

Buffered Address Latch Enable is used to latch the LA23 to LA17 signals or decodes of these signals. Addresses are

latched on the falling edge of BALE. It is forced high during DMA cycles. When used with AEN, it indicates a valid

microprocessor or DMA address.

CLK

System Clock is a free running clock typically in the 8MHz to 10MHz range, although its exact frequency is not

guaranteed. It is used in some ISA board applications to allow synchronization with the system microprocessor.

SD15 to SD0

System Data serves as the data bus bits for devices on the ISA bus. SD15 is the most significant bit. SD0 is the least

significant bits. SD7 to SD0 are used for transfer of data with 8-bit devices. SD15 to SD0 are used for transfer of data

with 16-bit devices. 16-bit devices transferring data with 8-bit devices shall convert the transfer into two 8-bit cycles

using SD7 to SD0.

DACK0 to DACK3 and DACK5 to DACK7

DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests on DRQ0 to DRQ3 and DRQ5 to

DRQ7.

DRQ0 to DRQ3 and DRQ5 to DRQ7DMA Requests are used by ISA boards to request service from the system DMA controller or to request ownership of

the bus as a bus master device. These signals may be asserted asynchronously. The requesting device must hold the

request signal active until the system board asserts the corresponding DACK signal.

I/O CH CK


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I/O Channel Checksignal may be activated by ISA boards to request than an non-maskable interrupt (NMI) be

generated to the system microprocessor. It is driven active to indicate a uncorrectable error has been detected.

I/O CH RDY

I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signalsnormal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices

using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an

active read or write command. The signal is release high when the device is ready to complete the cycle.

IOR

I/O Readis driven by the owner of the bus and instructs the selected I/O device to drive read data onto the data bus.

IOW

I/O Write is driven by the owner of the bus and instructs the selected I/O device to capture the write data on the databus.

IRQ3 to IRQ7 and IRQ9 to IRQ12 and IRQ14 to IRQ15

Interrupt Requests are used to signal the system microprocessor that an ISA board requires attention. An interrupt

request is generated when an IRQ line is raised from low to high. The line must be held high until the microprocessor

acknowledges the request through its interrupt service routine. These signals are prioritized with IRQ9 to IRQ12 and

IRQ14 to IRQ15 having the highest priority (IRQ9 is the highest) and IRQ3 to IRQ 7 have the lowest priority (IRQ7

is the lowest).

SMEMRSystem Memory Read instructs a selected memory device to drive data onto the data bus. It is active only when the

memory decode is within the low 1 megabyte of memory space. SMEMR is derived from MEMR and a decode of the

low 1 megabyte of memory.

SMEMW

System Memory Write instructs a selected memory device to store the data currently on the data bus. It is active only

when the memory decode is within the low 1 megabyte of memory space. SMEMW is derived from MEMW and a

decode of the low 1 megabyte of memory.

MEMR

Memory Readinstructs a selected memory device to drive data onto the data bus. It is active on all memory read

cycles.

MEMW


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Memory Write instructs a selected memory device to store the data currently on the data bus. It is active on all

memory write cycles.

REFRESH

Memory Refresh is driven low to indicate a memory refresh operation is in progress.

OSC

Oscillator is a clock with a 70ns period (14.31818 MHz). This signal is not synchronous with the system clock

(CLK).

RESET DRV

Reset Drive is driven high to reset or initialize system logic upon power up or subsequent system reset.

TCTerminal Countprovides a pulse to signal a terminal count has been reached on a DMA channel operation.

MASTER

Masteris used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a

device can pull -MASTER low which will allow it to control the system address, data, and control lines. After

MASTER is low, the device should wait one CLK period before driving the address and data lines, and two clock

periods before issuing a read or write command.

MEM CS16

Memory Chip Select 16is driven low by a memory slave device to indicate it is capable of performing a 16-bit

memory data transfer. This signal is driven from a decode of the LA23 to LA17 address lines.

I/O CS16

I/O Chip Select 16is driven low by a I/O slave device to indicate it is capable of performing a 16-bit I/O data transfer.

This signal is driven from a decode of the SA15 to SA0 address lines.

0WS

Zero Wait State is driven low by a bus slave device to indicate it is capable of performing a bus cycle without

inserting any additional wait states. To perform a 16-bit memory cycle without wait states, -0WS is derived from an

address decode.

SBHE

System Byte High Enable is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8).


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Types of bus-based I/O:Memory-mapped I/O and standard I/O

Processor talks to both memory and peripherals using same bus two ways to talk to peripherals

Memory-mapped I/O

Peripheral registers occupy addresses in same address space as memory

e.g., Bus has 16-bit address

lower 32K addresses may correspond to memory

upper 32k addresses may correspond to peripherals


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Standard I/O (I/O-mapped I/O)

Additional pin (M/IO) on bus indicates whether a memory or peripheral access

e.g., Bus has 16-bit address

all 64K addresses correspond to memory when M/IO set to 0

all 64K addresses correspond to peripherals when M/IO set to 1

Memory-mapped I/O vs. Standard I/O

Memory-mapped I/O

Requires no special instructions

Assembly instructions involving memory like MOV and ADD work with peripherals as well

Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and

memory

Standard I/O

No loss of memory addresses to peripherals

Simpler address decoding logic in peripherals possible

When number of peripherals much smaller than address space then high-order address bits can be

ignored

smaller and/or faster comparators

========================================================================================================================

Internet enabled embedded systemInternet enabled embedded systemInternet enabled embedded systemInternet enabled embedded system Communication to other on the Internet.

Use html (hyper text markup language) or MIME (Multipurpose Internet Mail Extension) type files

Use TCP (transport control protocol) or UDP (user datagram protocol) as transport layer protocol

addressed by an IP address

Use IP (internet protocol) at network layer Protocol

MIME

Format to enable attachment of multiple types of files

_ txt (text file)

_ doc (MSOFFICE Word document file)

_ gif (graphic image format file)

_ jpg (jpg format image file)

_ wav format voice or music file


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A system at one IP address

Communication with other system at another IP address using the physical connections on theInternet and routers

Since Internet is global network, the system connects to remotely as well as short range locatedsystem.

ETHERNET Inventor of Ethernet LAN- Robert Metcalfe About one third of the LANs in the world

Ethernet LANs.

Ethernet is a protocol for local network of computers, workstations and devices. LAN- Service sharing by the local computers, systems and sharing of local resources likerinters,

hard disk space, software and data

Each frame has a header like in a packet.

IEEE 802.2 (ISO 8802.2) Standard data-link MAC Media Access control) layer

Ethernet LAN Features Bus topology, Wired LAN in IEEE 802.3 physical layer standard

10 Mbps, 100 Mbps (Unshielded and Shielded wires) and 4 Gbps (in twisted pair wiring mode)

Broadcast medium Passive, Wired connections based.

Frame format like the IEEE 802.2

SNMP (Simple Network Management Protocol)

Open system (therefore allows equipment of different specifications)


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Each one connected to a common communication channel in the network listens and if the channel

is idle then transmits. If not idle, waits and tries again.

Multi access is like in a Packet switched Network

Wireless Personal Area Protocols IrDA (Infrared Data Association) Bluetooth 2.4 GHz 802.11 WLAN and 802.11b WiFi ZigBee 900 MHz

IrDA

Used in mobile phones, digital cameras, keyboard, mouse, printers to communicate to laptop

computer and for data and pictures download and synchronization.

Used for control TV, air-conditioning, LCD projector, VCD devices from a Distance

IrDA devices

Use infrared (IR) after suitable modulation of the data bits.

Communicates over a line of sight

Phototransistor receiver for infrared Rays


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Five levels of communication Level 1 minimum required communication.

Level 2 access-based communication. Level 3 index-based communication

Level 4 sync communication. Synchronisation s

Documents

Unit 3_embedded system