Unit III Mpmc Material

MICROPROCESSORS AND MICROCONTROLLERS MATERIALUNIT-III

PIN DIAGRAM OF 8086

The 8086 is internally a 16-bit MPU and externally it has a 16-bit data bus. It has the ability to address up to 1 MB of memory via its 20-bit address bus. In addition, it can address up to 64K of byte-wide input/output ports.

• It is manufactured using high-performance metal-oxide semiconductor (HMOS) technology, and the circuitry on its chip is equivalent to approximately 29,000 transistors.

• The 8086 is housed in a 40-pin dual in-line package. The signals pinned out to each lead are shown in figure.

The address bus lines A0 through A15 and data bus lines D0 through D15 are multiplexed. For this reason, these leads are labeled AD0 through AD15. By multiplexed we mean that the same physical pin carries an address bit at one time and the data bits at another time.

P SREEKANTH SVEW, DEPT OF ECE

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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL• The 8086 can be configured to work in either of two modes:

• The minimum mode is selected by applying logic 1 to the MN/MX input lead. It is typically used for smaller single microprocessor systems.

• The maximum mode is selected by applying logic 0 to the MN/MX input lead. It is typically used for larger multiple microprocessor systems.

• Depending on the mode of operation selected, the assignments for a number of the pins on the microprocessor package are changed. The pin functions specified in parentheses pertain to the maximum-mode.

• In minimum mode, the 8086 itself provides all the control signals needed to implement the memory and I/O interfaces. In maximum-mode, a separate chip (the 8288 Bus Controller) is used to help in sending control signals over the shared bus shown in figure.

MINIMUM MODE OF 8086

MAXIMUM MODE OF 8086


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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL• Address/Data Bus: The address bus is 20 bits long and consists of signal lines A0 (LSB) through A19 (MSB). However, only address lines A0 through A15 are used when accessing I/O.

• The data bus lines are multiplexed with address lines. For this reason, they are denoted as AD0 through AD15. Data line D0 is the LSB.

• Status Signals: The four most significant address lines A16 through A19 of the 8086 are multiplexed with status signals S3 through S6. These status bits are output on the bus at the same time that data are transferred over the other bus lines.

The status of the Interrupt Enable Flag (IF) bit (displayed on S5) is updated at the beginning of each clock cycle.

S4, S3: together indicates which segment register is presently being used for memory access. These lines float at tristate off during the local bus hold acknowledge.

S6: It is always low.

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of data over the higher order (D15-D8) data bus. It goes low for the data transfers over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, when- ever a byte is to be transferred on the higher byte of the data bus.

TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution will continue, else, the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.

RESET: This input causes the processor to terminate the current activity and start execution from FFFF0H. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized.

VCC: +5V power supply for the operation of the internal circuit. GND ground for the internal circuit.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL

• Control Signals:

• When Address latch enable (ALE) is logic 1 it signals that a valid address is on the bus. This address can be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.

• M/IO (memory/IO) tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 signals a memory operation and logic 0 signals an I/O operation.

• DT/R (data transmit/receive) signals the direction of data transfer over the bus. Logic 1 indicates that the bus is in the transmit mode (i.e., data are either written into memory or to an I/O device). Logic 0 signals that the bus is in the receive mode (i.e., reading data from memory or from an input port).

• The bank high enable (BHE) signal is used as a memory enable signal for the most significant byte half of the data bus, D8 through D15.

• WR (write) is switched to logic 0 to signal external devices that valid output data are on the bus.

• RD (read) indicates that the MPU is performing a read of data off the bus. During read operations, one other control signal, DEN (data enable), is also supplied. It enables external devices to supply data to the microprocessor.

• The READY signal can be used to insert wait states into the bus cycle so that it is extended by a number of clock periods. This signal is supplied by a slow memory or I/O subsystem to signal the MPU when it is ready to permit the data transfer to be completed.

• Interrupt Signals:

• Interrupt request (INTR) is an input to the 8086 that can be used by an external device to signal that it needs to be serviced. Logic 1 at INTR represents an active interrupt request.

• When the MPU recognizes an interrupt request, it indicates this fact to external circuits with logic 0 at the interrupt acknowledge (INTA) output.

• On the 0-to-1 transition of non maskable interrupt (NMI), control is passed to a non maskable interrupt service routine at completion of execution of the current instruction. NMI is the interrupt request with highest priority and cannot be masked by software.

• The RESET input is used to provide a hardware reset for the MPU. Switching RESET to logic 0 initializes the internal registers of the MPU and initiates a reset service routine.

• DMA Interface Signals:

• When an external device wants to take control of the system bus, it signals this fact to the MPU by switching HOLD to the logic level 1.

• When in the hold state, lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, WR, RD, DEN and INTR are all put in the high-Z state. The MPU signals external devices that it is in this state by switching HLDA to 1.


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SYSTEM CLOCK:

• To synchronize the internal and external operations of the microprocessor a clock (CLK) input signal is used. The CLK can be generated by the 8284 clock generator IC.

• The 8086 is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz.

MAXIMUM MODE SIGNALS:

S2, S1, S0 (Status lines): These are the status lines which reflect the type of operation, being carried out by the processor. These lines active during T4 of the previous cycle & remain active during T1 & T2 of the current bus cycle.

LOCK:

· This output pin indicates that other system bus masters will be prevented from gaining the system bus, while the LOCK=0.

· The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction.

· This floats to tri-state off during ‘hold acknowledge’.

QS1, QS0 (Queue status):

· These lines give information about the status of the code-prefetch queue.

· These are active during the CLK cycle after which the queue operation is performed.

· The 8086 architecture has a 6-byte instruction pre-fetch queue.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALAfter decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If it is single opcode byte, the next bytes are treated as data byte depending upon the decoded instruction length; otherwise, the next byte in the queue is treated as the second byte of the instruction opcode. The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least, two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

RQ/GT0, RQ/GT1 (Request/Grant):

These pins are used by other local bus masters, in maximum mode, to force the processor to release the local bus at the end of the processor’s current bus cycle. Each of the pins is bidirectional with RQ 0/GT0 having higher priority than RQ1/GT1.

Minimum Mode 8086 System

•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.

•In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system.

•The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.

•Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.

•Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals.

•They are controlled by two signals namely, DEN and DT/R.

•The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.


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MINIMUM MODE SYSTEM

•Usually, EPROMs are used for monitor storage, while RAM for users program storage. A system may contain I/O devices.

•The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.

•The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.

•The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation.

•At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2.

•The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.

•The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.

•A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.

•The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

•The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.P SREEKANTH SVEW, DEPT OF ECE

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MICROPROCESSORS AND MICROCONTROLLERS MATERIALMaximum Mode 8086 System

•In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information.

•In the maximum mode, there may be more than one microprocessor in the system configuration.

•The components in the system are same as in the minimum mode system.

•The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines.

•The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.

•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

•AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin.

•If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL•INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.

•IORC, IOWC are I/O read command and I/O write command signals respectively.

These signals enable an IO interface to read or write the data from or to the address port.

•The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals.

•All these command signals instructs the memory to accept or send data from or to the bus.

•For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.

•Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.

•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.

•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or

AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.

•The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

•If reader input is not activated before T3, wait state will be inserted between T3 and T4.

TIMING DIAGRAMS FOR 8086 IN MINIMUM MODE

BUS CYCLE AND TIME STATES

• A bus cycle or machine cycle defines the sequence of events when the MPU communicates with an external device, which starts with an address being output on the system bus followed by a read or write data transfer.

• Types of bus cycles:

Memory Read Bus Cycle Memory Write Bus Cycle

Input/output Read Bus Cycle Input/output Write Bus Cycle

One cycle of clock is called a state or t-state. The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four time states are called T1, T2, T3 and T4. This group of states is called a MACHINE CYCLE.

The total time required to fetch and execute an instruction is called an instruction cycle. An instruction cycle consists of one or more machine cycle.


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The following figure shows a memory read cycle of the 8086:

• During period T1,

o The 8086 outputs the 20-bit address of the memory location to be accessed on its multiplexed

address/data bus. BHE is also output along with the address during T1.

o At the same time a pulse is also produced at ALE. The trailing edge or the high level of this pulse is used

to latch the address in external circuitry.

o Signal M/IO is set to logic 1 and signal DT/R is set to the 0 logic level and both are maintained

throughout all four periods of the bus cycle.

• Beginning with period T2,

o Status bits S3 through S6 are output on the upper four address bus lines. This status information is

maintained through periods T3 and T4.

o On the other hand, address/data bus lines AD0 through AD7 are put in the high-Z state during T2.

o Late in period T2, RD is switched to logic 0. This indicates to the memory subsystem that a read cycle is

in progress. DEN is switched to logic 0 to enable external circuitry to allow the data to move from memory onto the microprocessor's data bus.


o The memory must provide valid data during T3 and maintain it until after the processor terminates the

read operation. The data read by the 8086 microprocessor can be carried over all 16 data bus lines.

• During T4,

o The 8086 switches RD to the inactive 1 logic level to terminate the read operation. DEN returns to its

inactive logic level late during T4 to disable the external circuitry.

MEMORY READ CYCLE FOR 8086 IN MINIMUM MODE


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The following figure shows a memory write cycle of the 8086:


o The address along with BHE is output and latched with the ALE pulse.

o M/IO is set to logic 1 to indicate a memory cycle.

o However, this time DT/R is switched to logic 1. This signals external circuits that the 8086 is going to

transmit data over the bus.

• Beginning with period T2,

o WR is switched to logic 0 telling the memory subsystem that a write operation is to follow.

o The 8086 puts the data on the bus late in T2 and maintains the data valid through T4. Data will be carried

over all 16 data bus lines.

o DEN enables the external circuitry to provide a path for data from the processor to the memory.

MAXIMUM MODE TIMING DIGRAMS


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WRITE CYCLE TIMING DIAGRAM FOR 8086MEMORY INTERFACING

Types of memories: There are two main types of memory i.e. RAM and ROM.

Read Only Memory (ROM): This memory is available only for reading purposes. The various types of

memories under this category are PROM, EPROM, EEPROM.

Programmable ROM (PROM): PROM writes data by application of current pulses through output terminal for

each address. A blown fuse defines a binary 0 state and intact fuse defines a binary 1 state once written, the data

will be permanent.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALErasable (EPROM): EPROM is, read and written electrically. Before writing data, all the storage cells must be

erased to the reset state by exposure of the chip to UV radiation. This erasure process can take approx. 20mins.

However, it has the advantage of multiple data capability.

Electrically Erasable (EEPROM): In EEPROM, we can do read and write at any time. In order to write data,

no need to erase prior contents. This is similar to RAM but the differences in write operation. It takes more time

than read and limited to million times only.

Ex: Storing port statuses, mal functions and failure history

Flash memory: In flash memory a sector of bytes can be erased at a time that can be from 256B to 16KB.

Ex: Storing pictures in digital camera.

Random Access Memory (RAM): It is a volatile memory RAM contains temporary data and software programs

for different applications.

Static RAM (SRAM): A static RAM holds the data as long as power supplied to it. Each memory cell consists of

6 to 8 MOS transistors, therefore packing density is low.

Advantages:

Very fast as access time is less.

No need of refreshing circuit.

Disadvantages:

Low packing density.

It is expensive.

Consumes more power.

Dynamic RAM (DRAM): In order to store data capacitor can be used, so the presence or absence of charge in a

capacitor is interpreted as a logic 1 or logic 0 but as capacitor has a tendency to discharge DRAMs require

refreshing circuit to maintain data storage. A DRAM needs one transistor per memory cell, so packing density

will be very high.

Advantages:

High packing density.

Power consumption is very less compared to SRAM.

Inexpensive.

Disadvantages:

Requires complex refreshing control circuit.

It is slow since access time is more.

Several chips have to be connected in parallel to obtain the required length as DRAMs can store 1-bit of data for

each cell.

Note 1: Access time is referred to as the time required read/write operation.

Note2: The refresh cycle refers to the contents of a memory’s cell being recharged. It helps to read data properly.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALBasic memory device: Any memory device can contain i/p, o/p lines, selection i/p, control i/p to perform rd/wr

operation. All memory devices have address i/ps that select memory location within the memory device i.e. A0 to

AN. “Number of address lines indicate the total memory capacity of a device”. Ex: 1K memory requires 10

address lines (A0 to A9)

The memory device can have I/O lines to perform read or write operation. The size of memory location is

dependent on the number of data bits. i.e. D0 to D7; D8 to D15. A memory device generated is indicated as 2N * M, N

represents number of address lines; M represents number of data lines. Memory devices can be selected by

control selection pins (CP SP ) and select RD/WR mode.

Memory Capacity Address lines

1K=1024(0400H)

2K=2048(0800H)

4K=4096(1000H)

8K=8192(2000H)

16K=16384(4000H)

32K=32768(8000H)

64K=65536(10000H)

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Simple Memory Device

Memory Interfacing:

Available memory for 8086 is 1MB. EPROM can be used as program memory and RAM as a data

memory.

EPROM and RAM can be placed anywhere in 1MB memory but EPROM can be placed at last memory

page so that starting address of program memory at FFFF0H.

For interfacing memory to 8086, provide odd and even banks of memory. Even bank is selected when

A0=0 and odd bank is selected when PBHE=0.


A0 I/00

. .

. .

AN I/ON

C̅S̅ R̅ W̅

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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL Memory interfacing requires:

Select the chip Identify the register Enable the appropriate buffer

In order to communicate with memory or I/O devices, microprocessor has to decode the address.

Address Decoding techniques:

Absolute Decoding: In absolute decoding technique, the memory chip is selected only for the specified

logic level on the address lines. Here in order to select an 8K memory chip, we are using 13 address lines for each

memory location and remaining address lines (A19 – A14) are used to generate unique chip select signal. However

this has a disadvantage that implementing this requires more hardware. It is used in large systems.

Absolute Decoding

Linear Decoding: This technique eliminates the hardware for decoding logic i.e. it uses less number of

lines for selecting the chip but it has a drawback that multiple same addresses can be provided for different chips.

This can be used in small systems.

Linear Decoding

Block decoding: In this technique, decoder can be used to select the chip logic. This can be used in

systems which uses array of memories.


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Block Decoding

1. Design an 8086 based system with the following specifications:

a. 8086 in minimum mode 2. 64KB EPROM 3. 64KB RAM. Draw the complete

schematic of the design indicating address map.

For interfacing memory module to CPU, it is necessary to have odd and even memory banks i.e. by using two

32KB EPROMs and two 32 KB RAMs, one for odd bank and another for even bank. 32KB requires 15 address

lines A1 to A15. A0 and BHE are used to select even and odd memory banks.

F0000 – FFFFE = FFFE (65534) EPROM EVEN ADDRESS

F0001 – FFFFF = FFFE (65534) EPROM ODD ADDRESS


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Ex 2: In an SDK – 86 kit 128KB SRAM and 64KB EPROM is provided on system and provision for

expansion of another 128KB SRAM is given. The ON system SRAM address starts from 00000H and that

of EPROM ends with FFFFFH. The expansion slot address map is from 80000H to 9FFFFH. The size of

SRAM chip is 64KB and EPROM chip is 16KB. Give the complete memory interface and also the address

map for individual chips.

Sol: Data for SRAM:

Starting address of SRAM is 00000H

Required SRAM is 128KB

Maximum size of SRAM is 64KB

To provide 128KB SRAM, it requires two 64KB SRAMs. Here we have to provide 64KB memory locations

(65535-FFFFH) for each chip.

The address map for SRAM chip1 is 00000H – 0FFFFH


Data for 64KB EPROM:

Required EPROM size is 64KB

Maximum EPROM size is 16KB

To provide 64KB EPROM, it requires four 16KB EPROMs.

Given that end address of EPROM is FFFFFH

Starting address will be F0000H

The address map for 64KB EPROM is F0000H – FFFFFH

The address map for EPROM chip1 is F0000H – F3FFFH

The address map for EPROM chip2 is F4000H – F7FFFH

The address map for EPROM chip3 is F8000H – FBFFFH

The address map for EPROM chip4 is FC000H – FFFFFH


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALNote: 16KB maximum capacity is 4000H (0000 – 3FFFH)

128KB SRAM (Expansion slot):

Starting address is 80000H, ending address is 9FFFFH

Required SRAM size is 128KB, maximum size is 64KB. To provide this two 64KB SRAM chips are required.



Memory Map:


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALEx 3: Generate chip select signals with the help of 74LS138 to six memory chips of size 16KB, with the

address map from 00000H to 17FFFH.

Sol: The capacity of the memory is 128KB

Size of the single memory chip is 16KB i.e. 0 – 16383 (0 – 3FFFH)

In order to represent 128KB, 8 chips are required but number of chips should be used is six.

Address map for chip1 is 00000H – 03FFFH


Address map for chip3 is 08000H – 0BFFFH

Address map for chip4 is 0C000H – 0FFFFH



EX 4: It is necessary to interface 128KB SRAM and 32KB EPROM to an 8086 based system. The size of

SRAM and EPROM chips is 16KB. Address map of SRAM is fixed from 00000H to 1FFFFH and that of

EPROM is from F8000H to FFFFFH. Design the entire memory interface? Give the address map of

individual chip?

Sol:

Data for SRAM:

Starting address of SRAM is 00000H and Ending address of SRAM is 1FFFFH

Starting address of EROM is F8000H and Ending address of EROM is FFFFFH

Required SRAM is 128KB

Maximum size of SRAM is 32KB

To provide 128KB SRAM with 16KB, it requires eight 16KB SRAMs. Here we have to provide 16KB memory

locations (16384-4000H) for each chip.

The address map for SRAM chip1 is 00000H – 03FFFH

The address map for SRAM chip 2 is 04000H – 07FFFH

The address map for SRAM chip 3 is 08000H – 0BFFFH

The address map for SRAM chip 4 is 0C000H – 0FFFFH



The address map for SRAM chip 7 is 18000H – 1BFFFH

The address map for SRAM chip 8 is 1C000H – 1FFFFH

Data for 32KB EPROM:

Required EPROM size is 32KB

Maximum EPROM size is 16KB

To provide 32KB EPROM, it requires TWO 16KB EPROMs.

Given that starting address of EPROM is F8000H and ending address of EPROM is FFFFFHP SREEKANTH SVEW, DEPT OF ECE

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MICROPROCESSORS AND MICROCONTROLLERS MATERIALThe address map for 32KB EPROM is F8000H – FFFFFH

The address map for EPROM chip1 is F8000H – FBFFFH

The address map for EPROM chip2 is FC000H – FFFFFH

Note: 16KB maximum capacity is 4000H (0000 – 3FFFH)

MEMORY MAP:


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Need for DMA, DMA data transfer Method:

Direct Memory Access is a method of transferring data between peripherals and memory

without using the CPU.

In some cases the CPU may not be fast enough to keep up with the peripheral or it may be desirable to

allow the CPU to do other useful work while the I/O is in progress. In this case a special-purpose processor called

a DMA controller (DMAC) can be used to transfer data between memory and I/O devices. The DMA controller

periodically takes over control of the system bus from the CPU, and, like the CPU, generates address, data and

control signals to transfer data between memory and I/O devices.

DMA - Direct memory access or autonomous transfer

Direct Memory Access (DMA) is a method of allowing data to be moved from one location to

another in a computer without intervention from the central processor (CPU). It is also a fast way

of transferring data within (and sometimes between) computer.

The DMA I/O technique provides direct access to the memory while the microprocessor is

temporarily disabled. The DMA controller temporarily borrows the address bus, data bus and

control bus from the microprocessor and transfers the data directly from the external devices to a

series of memory locations (and vice versa).P SREEKANTH SVEW, DEPT OF ECE

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Basic DMA Operation: Direct memory accesses normally occur between an I/O device and memory without the

use of the microprocessor. Two control signals are used to request and acknowledge a direct memory access

(DMA) transfer in the microprocessor-based system.

DMA OPERATION

The HOLD signal as an input (to the processor) is used to request a DMA action.

The HLDA signal as an output that acknowledges the DMA action. When the processor recognizes the

hold, it stops its execution and enters hold cycles. HLDA becomes active to indicate that the processor

has placed its buses at high- impedance state.

A DMA read transfers data from the memory to the I/O device. A DMA write transfers data from an I/O

device to memory. The system contains separate memory and I/O control signals. Hence the Memory &

the I/O are controlled simultaneously.

The DMA controller provides memory with its address, and the controller signal selects the I/O device

during the transfer.

Data transfer speed is determined by speed of the memory device or a DMA controller.

In bus master mode, the DMA controller acquires the system bus from the CPU to perform the DMA

transfers. Because the CPU releases the system bus for the duration of the data transfer, the process is

sometimes referred to as cycle stealing.

In bus slave mode, the DMA controller is accessed by the CPU, which programs the DMA controller’s

internal registers to set up DMA transfers. The internal register consist of source and destination address

registers and transfer count registers for each DMA channel, as well as control and status registers for

initiating, monitoring and sustaining the operation of the DMA controller.

8257 DMA Controller:Features of 8257:


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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL1. It is a 4-channel Direct Memory Access (DMAC) interface IC which allows data transfer between memory and up to 4 I/O devices, bypassing CPU.

2. A maximum of 16 KB of data (= 214) can be transferred by this IC sequentially at a time. When a DMA request comes from a peripheral, the DMAC 8257, via its HRQ (Hold Request) pin, requests the CPU on its HOLD pin. CPU then acknowledges this request via its HLDA pin which goes to HLDA pin of 8257. After this, DMAC generates the required MEMR, MEMW, I/OR, I/OW signals.

3. Initialization of the DMAC is done under program control for each channel. The parameters which need to be initialized for each channel are starting address, number of bytes of data to be transferred, mode of operation, etc.

4. DMAC can be operated in three modes: (a) DMA Read (reading from memory, writing into peripheral), (b) DMA Write (writing into memory, reading from peripheral), (c) DMA verify.

5. Priority for each of the 4 channels can be set in (a) fixed priority, (b) rotating priority.

6. A Terminal Count Register exists for each of 4 channels. The number of bytes of data to be transferred is stored in the D13–D0 positions of the 16-bit Terminal Count Register. On completion of data transfer, the Terminal Count (TC) pin goes high.

7. When the CPU is in control of its buses (address bus, data bus and control bus), it acts as master and DMA controller acts as the slave. When DMA controller takes control of the buses, it becomes the master and CPU becomes the slave.

Description of pins:

D0-D7:It is a bidirectional ,tri state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15). In the slave mode it is a bidirectional (Data is moving). In the Master mode it is a unidirectional (Address is moving).

IOR: It is active low, tristate, buffered, Bidirectional lines. In the slave mode it functions as an input line. IOR signal is generated by microprocessor to read the contents of 8257 registers. In the master mode it functions as an output line. IOR signal is generated by 8257 during write cycle.

IOW: It is active low, tristate, buffered, Bidirectional lines. In the slave mode it functions as an input line. IOW signal is generated by microprocessor to write the contents of 8257 registers. In the master mode it functions as an output line. IOR signal is generated by 8257 during read cycle.

CLK: It is the input line, connected with TTL clock generator. This signal is ignored in slave mode.

RESET: It is used to clear mode set registers and status registers.

A0-A3: These are the tristate, buffer, bidirectional address lines. In slave mode, these lines are used as address inputs lines and internally decoded to access the internal registers. In master mode, these lines are used as address outputs lines, A0-A3 bits of memory address on the lines.

CS: It is active low, Chip select input line. In the slave mode, it is used to select the chip. In the master mode, it is ignored.

A4-A7: These are the tristate, buffer, output address lines. In slave mode, these lines are used as address outputs lines.

In master mode, these lines are used as address outputs lines, A0-A3 bits of memory address on the lines.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALREADY: It is a asynchronous input line. In master mode, When ready is high it is received the signal. When ready is low, it adds wait state between S1 and S3. In slave mode,this signal is ignored.

HRQ: It is used to receiving the hold request signal from the output device.

HLDA: It is acknowledgment signal from microprocessor.

MEMR: It is active low, tristate, Buffered control output line. In slave mode, it is tristated. In master mode, it activated during DMA read cycle.

MEMW: It is active low, tristate, Buffered control input line. In slave mode, it is tristated. In master mode, it activated during DMA write cycle.

AEN (Address enable): It is a control output line. In master mode, it is high. In slave mode, it is low. Used it isolate the system address, data and control lines.

ADSTB: (Address Strobe) It is a control output line. Used to split data and address line. It is working in master mode only. In slave mode it is ignore.

TC (Terminal Count): It is a status of output line. It is activated in master mode only. It is high, it selected the peripheral. It is low, it free and looking for a new peripheral.

MARK: It is a modulo 128 MARK output line. It is activated in master mode only. It goes high, after transferring every 128 bytes of data block.

DRQ0-DRQ3(DMA Request): These are the asynchronous peripheral request input signal. The request signals are generated by external peripheral device.

DACK0-DACK3: These are the active low DMA acknowledge output lines. Low level indicates that, peripheral is selected for giving the information (DMA cycle). In master mode it is used for chip select.

BLOCK DIAGRAM OF 8257

It contains five main Blocks:

1. Data bus buffer 2. Read/Control logic 3. Control logic block


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MICROPROCESSORS AND MICROCONTROLLERS MATERIAL4. Priority resolver 5. DMA channels.

DATA BUS BUFFER: It contains tristate, 8 bit bi-directional buffer. Slave mode, it transfer data between microprocessor and internal data bus. Master mode, the outputs A8-A15 bits of memory address on data lines (Unidirectional).

READ/CONTROL LOGIC: It controls all internal Read/Write operation. Slave mode, it accepts address bits and control signal from microprocessor. Master mode, it generate address bits and control signal.

Control logic block: It contains, Control logic, Mode set register and Status Register.

CONTROL LOGIC: Master mode, It control the sequence of DMA operation during all DMA cycles. It generates address and control signals. It increments 16 bit address and decrement 14 bit counter registers. It activates a HRQ signal on DMA channel Request. Slave, mode it is disabled.

Register organization of 8257: The 8257 performs the DMA operation over four independent DMA channels. Each DMA channel has a pair of two 16-bit registers i.e. address register and terminal count register. Also there are two common registers for all the channels are Mode set register and Status register. The CPU selects one of these registers using address lines A0 to A3.

DMA address register: The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel.

Terminal Count register: The function of this register is to indicate the end of the data transfer after required number of DMA cycles. The low order 14-bits of the terminal count register are initialized with the number of DMA cycles minus one. After each DMA cycle this register content can be decremented by 1and becomes zero after all DMA cycles are over. The bits 14 and 15 indicate the type of the DMA operation.

Terminal Count Register

Mode Set Register: The function of mode set register is to enable the DMA channels individually and also to set the various modes of operation.

Note: A DMA channel should not be enabled till the DMA address and terminal count registers have valid data.


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Mode Set Register

The bits B0 – B3 enable one of the four DMA channels of 8257. The extended write bit extends the duration of MEMW and IOW signals. B4 provides rotating and normal priority. TC stop bit is set, the selected channel is disabled, so that it can be prevented for further DMA cycle on the channel. If auto load bit is set enables the same channel for the repeat block chain operations without software intervention between two successive blocks.

Status Register: The lower order 4-bits are used to indicate the terminal count condition for the four individual channels. These bits remain set till either the status is read by CPU or reset by 8257. The update flag can only be cleared by resetting 8257 or by resetting the auto load bit of the mode set register. If update flag register is set, the contents of channel 3 registers are reloaded to the corresponding registers of channel 2.

Status Register

8237 DMA CONTROLLER

8237 is a four – channel device compatible with 8086/8088, adequate for small systems. Expandable to any number of DMA channel inputs. It is capable of DMA transfers at rates up to 1.6MB per second. Each channel is capable of addressing a full 64K-byte section of memory and can transfer up to 64K bytes with a single programming.

The timing and control block, priority block and internal registers are the main components. The timing and control block derives internal timing from clock input and generates external control signals. The priority encoder resolves priority encoder block resolves priority between DMA channels requesting services simultaneously.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALPin Description:

DREQ0 – DREQ3 (DMA request): Used to request a DMA transfer for a particular DMA channel.

• DACK0 – DACK3 (DMA channel acknowledge): Acknowledges a channel DMA request from a device.

• HRQ (Hold request): Requests a DMA transfer.

• HLDA (Hold acknowledge) signals the 8237 that the microprocessor has relinquished control of the address, data and control buses.

A0 – A3 In idle cycle these can act as inputs and are used by 8237 to address the control registers to be read or written. In an active cycle, they provide the lowest 4 bits of the output addresses generated by 8237.

A4 – A7 These lines are activated only during DMA services to generate address bits.

DB0 – DB7 These lines are used to transfer data to / from I/O device or memory.

• AEN (Address enable): Enables the DMA address latch connected to the 8237 and disable any buffers in the system connected to the microprocessor. (Use to take the control of the address bus from the microprocessor)

• ADSTB (Address strobe): Functions as ALE to latch address during the DMA transfer.

• EOP (End of process): Signals the end of the DMA process.

• IOR (I/O read): Used as an input strobe to read data from the 8237 during programming and used as an output strobe to read data from the port during a DMA write cycle.

IOW (I/O write): Used as an input strobe to write data to the 8237 during programming and used as an output strobe to write data to the port during a DMA read cycle.

MEMW (Memory write): Used as an output to cause memory to write data during a DMA write cycle.

MEMR (Memory read): Used as an output to cause memory to read data during a DMA read cycle.

BLOCK DIAGRAM OF 8237


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALInternal registers:

• The current address register (CAR) is used to hold the 16-bit memory address used for the DMA transfer.

• The current word count register (CWCR) programs a channel for the number of bytes (up to 64K) transferred during a DMA action.

• The base address (BA) and base word count (BWC) registers are used when auto-initialization is selected for a channel. In this mode, their contents will be reloaded to the CAR and CWCR after the DMA action is completed.

• Each channel has its own CAR, CWCR, BA and BWC.

• The command register (CR) programs the operation of the 8237 DMA controller.

• The mode register (MR) programs the mode of operation for a channel.

• The request register (RR) is used to request a DMA transfer via software, which is very useful in memory-to-memory transfers.

• The mask register set/reset (MRSR) sets or clears the channel mask to disable or enable particular DMA channels.

• The mask register (MSR) clears or sets all of the masks with one command instead of individual channels as with the MRSR.

• The status register (SR) shows the status of each DMA channel.

The temporary register holds data during memory to memory data transfers. After completion of the data transfer, the last word remains in the temporary register till it is cleared by a reset operation.

COMMAND REGISTER MODE REGISTER


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BUS REQUEST REGISTER MRSR REGISTER

MSR REGISTER STATUS REGISTER

Transfer modes of 8237:

Single mode

In single mode only one byte is transferred per request. For every transfer, the counting register is decremented and address is incremented or decremented depending on programming. When the counting register reaches zero. The terminal count TC signal is sent to the card.

The DMA request DREQ must be raised by the card and held active until it's acknowledged by the DMA acknowledge DACK.

Block transfer mode

The transfer is activated by DREQ which can be deactivated once acknowledged by DACK. The transfer continues until end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.

Demand transfer mode

The transfer is activated by DREQ and acknowledged by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or external EOP may activate auto-initialization if this is programmed.


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MICROPROCESSORS AND MICROCONTROLLERS MATERIALMemory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It's used to repeat the last transfer.

Cascade Mode:

More than one 8237A together for simple system expansion. The HRQ and HLDA signals from the additional 8237A are connected to the DREQ and DACK signals of a channel of the initial 8237A. This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device.

Software Command: Three software commands are used to control the operation of the 8237. These commands do not have binary bit pattern as control registers in 8237. A simple output to the correct port number enables the software command. The function of the software commands are as follows:

Clear the first/last flip-flop Clears the first/last (F/L) flip-flop within the 8237. The F/L flipflop selects which byte (low or high order) is read/written in the current address and current word count registers. If F/L=0, the low order byte is selected; if F/L = 1, the high order byte is selected. Any read or write to the address or count register automatically toggles the F/L flip-flop.

Master clear – Acts exactly the same as RESET signal to 8237. This command disables all channels.

Clear Mask register – Enables all four DMA channels.

Programming 8237: The 8237 can act as a slave when interfaced to microprocessor and acts as temporary master during DMA operation. The programming of 8237 refers to sending software commands and various


SINGLE MODE DEMAND MODE BLOCK MODE

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MICROPROCESSORS AND MICROCONTROLLERS MATERIALcontrol words to 8237. At the start of programming all the DMA channels have to be disabled and then they are enabled at the end of programming. Also, the first – last flip-flop has to be cleared before sending 16-bit address/count value to 8237 in order to load low byte first and then high byte in address/count registers.

Steps in programming 8237:

First send‘master clear’ software to 8237, which mask/disable all DMA channels, clear first-last flip-flop and clear all internal registers, except mask register.

Send a command register to inform priority of DMA channels, normal/compressed timings, polarity of DREQ and polarity of DACQ signals.

Write a mode word to mode register of each channel to inform DMA mode and type of DMA transfer.

Send a ‘clear first-last flip-flop’ software command to reset it zero.

Comparison between 8257 and 8237 DMA controllers:


Documents

Unit III Mpmc Material