UNIVERSIDAD AUTONOMA METROPOLITANA UNIDAD …148.206.53.84/tesiuami/UAM5859.pdf · besicas para un sistema mínimo, el bus de Dentro de las localidades disponibles de direcciones

UNIVERSIDAD AUTONOMA METROPOLITANA UNIDAD ETAPALAPA

’CIENCIAS BASICAS E INGENIERIA

INGENIERIA BlOMEDlCA AREA DE INSTRUMENTACION MEDICA ELECTRONICA

SEMINARIO DE PROYECTOS I Y I/ REPORTE FINAL

1, SEÑALES EN UNA UNIDAD DE CRT. DESPLIEGUE ALFANUMERICO Y DE

SEMINARIO DE PROYECOS I Y 11.

-?

,* AVALOS FLORES JUAN MANUEL 88322549 BAUTISTA PARDO YESELlNE 90321556 COSS MORA ENRIQUE 88201478

2 ING. DONACIANO JIMENEZ

INDICE

CARATULA PROYECTO TERMINAL INTEGRANTES Y ASESOR DEL PROYECTO INDICE JUSTlFlCAClON DEL PROYECTO 80188 PROGRAMA PRINCIPAL PARA SISTEMA MINIM0 PROCEDIMIENTO DE ENSAMBLE DEL CODIGO PARA EL 80188 PROGRAMA MASM DE MICROSOFT. LISTADO DE LA MACRO UTILIZADA PROYECTO TERMINAL INTRODUCCION AL CONTROLADOR DE CRT

REFRESCO DE DISPLAY DE CR FORMATO DE LLENADO DEL GENERADOR DE CARACTERES PROCEDIMIENTO DE DESPLIEGUE COMANDOS DEL 8275

PROGRAMA PRINCIPAL CON CONTROL DEL 8275 (EL CODIGO ESTA ENTRE ). CODIGO DE ADQUlSlClON DE DATOS PROGRAMA FINAL DEL PROYECTO TERMINAL CONCLUSIONES, RECONOCdMlENTO Y RECOMENDACIONES BlBLlOGRAFlA APENDICE

i 1 2 3 4 6 11

19 20 26 26 28 29 32 33 38 51 53 69 71 72

Aplicaci6n del 80188

I JUSTIFICACION DEL PROYECTO

En los últimos años, en nuestro pais

la tecnologia propia cada vez msis encuentra

obstsiculos para desarrollarse, ya sea

porque hay qui& dice que para que

producir algo que ya esta hecho; Y tienen

razbn en cierta medida. Pero si no

empezamos a producir tecnología propia

como va hacer posible que la tengamos. Si

no somos capaces de diseñar y mejorar un

equipo tan simple como lo es un

electroestimulador, una centrifuga, una

diatennia , etc. Nunca vamos a tener en

nuestras manos la tecnología que queremos

en nuestro país, y sobre todo si no se

empieza a inculcar a la iniciativa privada la

importancia de crear una tecnología propia

no lo tendremos.

Nuestro proyecto no es complicado

pero no es simple y para muchos es buscar

el hilo negro de lo que ya existe. Pero

somos ingenieros no “cocineros” porque la

receta no es la misma ( véanse tantos

equipos de una misma aplicacibn que

aunque tienen el mismo principio la

tecnología aplicada es diferente y en

algunos casos superior a otras).

A demás la importancia de poder

estar en contacto con los problemas nos

hacen estar a un nivel mejor de aquellos que

prefieren esas usando tarjetas fabricadas y

Despliegue en una Unidad de CRT

solo colgarse para lograr su fin eso no es

ser un INGENIERO BlOMEDlCO desde

nuestro punto de vista. En lo siguiente se

dad

una breve introduccibn al microprocesador

que usamos. No es recomendable usarlo,

use un micro como el de Motorola de la

familia 68hll y si es posible utilice un micro

de tecnología RISC, más completo y mejor

diseñado para todo uso.

Es por ello que nuestro proyecto

terminal consiste en diseñar un sistema de

registro de señales fisiolt5gicas mediante el

uso de un sistema minimo construido por

nosotros mismos. Muchos nos didn que en

el mercado existen tarjetas de micro$ más

potentes y checadas listas para usarse,;

pero es que no es tecnología propia aunque

claro nos evitamos muchos problemas. Pero

sino somos capaces de resolver problemas

entonces estamos destinados a depender de

otra tecnologia que no es nuestra.

4

Se indicaran instrucciones sencillas para

poder programar un sistema minimo, la

manera de control de interfaces, como

f o m r palabras de control del

microprocesador y se mostrara la manera

de colgar las interfaces al micro en los

diagramas eléctricos del sistema completo

tomando en cuenta entre otras las

caracteristkas del monitor para desplegar la

información.

Se incluird en este trabajo

informaci6n t kn i ca del micro ; as¡ mismo

los diagramas de las interfaces usadas

como son el 8275 y la tarjeta de adquisición

de datos y otras informaciones

indispensables.

Seminario de Proyectos I y I1 5


80188

~ temporización ~

1 micropro i cesador 1 cpu

I

modulo

memoria

li L

almacenamiento masivo

DIAGRAMA A BLOQUES DE UN SISTEMA COMPLETO USANDO UN MICROPROCESADOR

El sistema minimo mostrado en el apendice de

El micropmesador proporciona senales diagramas, despierta en la parte mes alta (

besicas para un sistema mínimo, el bus de Dentro de las localidades disponibles de

direcciones direciona tanto a memoria como a programacidn mínima requerida para echar

perif6ricos direcionando a 20 bits, el bus de andar al sistema).

datos utiliza las senales de WR y RD para FFFFF

realizar transferencias o traer informaci6n para FFFFO ; De O a F hay 16 localidades para

procesar. programar ya que en FFFFO despierta el

Las instrucciones besicas del cpu son: micropmesador; por lo tanto se localiza el

l. Asignacidn y aritm6tica de expresiones BIOS.

2. Brincos condicionales Este micropmesador tiene un nivel de

3. brincos condicionales y operaciones ldgicas integraci6n que contiene: tres timers, un

4. ciclos (looping) controlador de interrupciones, 2 canales de

5. Arreglos y otras estructuras de datos acceso a memoria DMA, reloj integrado y

6. Subrutinas habilitaci6n de MAO.

Despliegue en una Unidad de CRT 6

SEÑALES DE CS.

oooo:o LCS

FFFF:O 6 SENALES DE PCS (para controlar

perifdricos) Y 4 MMCS

FFFF:F UCS (parte alta de selecci6n del chip)

siempre esta en espacio de //O,

estuviera activa en el momento de acceso a

FFFF:O

La forma de programar los UMCS es la

siguiente y tomando en cuenta la tabla 7 y fig.

10 y 11 del manual del 80188 en el apendice

de manual. Como nuestra memoria es de 8

kbytes tomamos el valor de la tabla 7 que

corresponde a la memoria de 8 kbytes que es

FE38H y como offset FFAOH en la figura 1 de

muestra el formato 1 ?.bits que conforman la

palabra de control de UMCS. R2, R1 y RO son

si no escogidos de acuerdo si se desean ciclos

de espera o sin la línea de control de ciclos de

espera adicionales , pero en este caso solo

tomaremos los ciclos de espera por defaul que

on 3 y R2, R1 y R O estan en 1. Por lo que el

resultado se muestra en la figura 2.

Las U s indican que debemos colocar

el valor asignado al tamaAo de la memoria, solo

tomando en cuenta los bits 13 al 6 del valor y

formar con ello la palabra de control de UMCS.

la palabra formada con esto es: OFE3FH y la

direcci6n es FFAOH por lo que:

MOV DX, OFFAOH

M0 V AX, OFE3FH

OUT DX,AX

Como consecuencia debemos

programar tambien la palabra de control de

LMCS que accesa a la parte mas baja de la

memoria y poder así accesar una tabla de

vectores de interrupci6n necesarios para el

control del 80188, de la misma manera que los

UMCS. Vease la tabla 8 y figura 12 del

manual del 80188. Con ello es claro que la

palabra de control para IMCS es OlFFH y su

direcci6n esta dada por OFFA2H.

entonces:

MOV DX,OFFAOH

MOV AX,OFE3FH

OUT DXAX

INC DX

INC DX

MOV AX,OFFA2H

OUT DX,AX

En este caso de LMCS tenemos que la

direcci6n inicial es la OOOOH pero se reservan

256 bytes para uso de los vectores de de

interrupcidn y utilizacidn en el manual del

801 88.

palabras de control de los timers O , 1, y 2. el

formatoes como se muestra en la figura 3.

El siguiente paso es programar los

timers del 801 88 y debemos formar las



figura 1.

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 O 1 1 U U U U U U U U l 1 l R 2 R l R O

figura 2.

1 5 1 4 1 3 1 2 7 1 1 0 9 8 7 6 5 4 3 2 1 O 1 1 u u u u u u u u 1 1 7 1 1 1

Bits figura 3. 15 EN Habilitamos la operachn d e l timer, si esta en O el timer no trabaja

14 INH Bit de inhibkk5n da la posibiiidad de tener todo preparado para mciar al timer, 1 b hab-

13 INT Nos permite habilitar las hterrupcbnes por timer que son capaces de interrumpir al 80188 en 1 bs

habilita.

12 RIU UtiAha uno de bs dos registros de cuenta m i m a o alternadamente un O Mica que el registro A

es el que se utiliza y un 1 indka que el registro b es el que se utiliza.

11 o

5 MC Indica que cuando el triner alcance la cuenta maxima deber& comenzar otra vez en O

4 RTG Es ut&& este bits cuando se &a el rebj interno del 801 88. En O el rebj mtemo active el timer y

el 1 le Mia que ser& disparado externamente.

3 P Es un preescalador con tres opciones: 1.- Contar con una sehal externa en la entrada to(in), 2.-

Usar el rebj interno, y 3.- Usar el timer 2 como preescalar. en O contara a 55 d e l rekq del 80188 y en

1 usara el timer2 como pmescalar.

2 D(T Selecciona entre un rebj hterno = O, contara a 55 del rebj interno y externo = 1

1 ALT Le indicamos si se &aran de manera altema bs registros de cuenta maxha en O sob utiliza el

registro A y en 1 UtXkara bs dos registros de manera alterna.

O CONT En 1 el timer trabajara de manera contmua y en 1 terminara de trabajar al terminar la cuenta.

De esta manera el programa queda de la siguiente manera.

PAGE 60,132 TITLE PROGRAMA PARA DESPERTAR AL 80188

8 Despliegue en una Unidad de CRT

.186

;Profesor.: AOUSTIN SUARU SILVER10 LEON

. t......"t.t.."t.t.**"***.****" , ; * DECLARACION DE VALORES CONSTANTES . .~.....H"..*..**.*t~***f*t I

PUMCS DUMCS PLMCS

DMPCS PM PCS

DPACS PPACS

3

,

I

IRWRIO DRWRIO DRRDIO

COMKEY WRDAT MODKEY PROCLK RWIFO CLRRAM DATKEY STSRAM

I

PCT2 DPCT2 MAXCAT2 DMAXCAT2 PCT1 DPCTI MAXCAT1 DMAXCATI STOPTl

t

EQU OFE3FH EQU OFFAOH EQU OOlFFH

EQU OFFA8H EQU 080BFH

EQU OFFA4H EQU WO3FH

EQU 00080H EQU 00081H EQU 00083H

EQU OOOOlH EQU 00002H EQU 00011000B EQU 00111111B EQU 0101oooO8 EQU 11OOOO1OB EQU OOOOOH EQU OOOOIH

EQU OCOOIH EQU OFF66H EQU OFFFFH EQU OFF62H EQU OCW8H EQU OFF6EH EQU OO66CH EQU OFF6AH EQU 0400AH

. .*.*****"H*H**. ; * SEGMENTO DE COMO0 . "**."...H*.*~** ,

CSEO SEGMENT PARA PÚBLIC 'CODE' ASSUME CS:CSEO

I

ORO

CLI MOV

MOV OUT DB Dw Dw

ORO

IFFOH ;Origina el programa en la memoria en ; l a dimccign dada

AX,PUMCS ;Carga la palabra de control del

DX,DUMCS ;Carga la direccign del registro de UMCS DX&( OEAH ;Codlgo objeto de la InstucciCn JMP OOOOOH ; m e t OFEWH ;S.gmentO da wig0

;registro de UMCS

,

OOWH ;Origina el resto del programa en la ;memoria en la direccl*n dada


Aplicaci6n del 8 0 1 8 8

S

MOV AX,PLMCS ;Carga la palabra de control del LMCS INC DX I N C DX OUT DX,AX

, MOV AX,lOOtl MOV SS- MOV SP,OFFFH

MOV AX,CS MOV DSa XOR A X , A X MOV ES,AX

,

I .. N-...-".....""".."....". "Iniciakaci$n del bloque de pwrtos"

*""""....t....."."".-.......

MOV DX,DMPCS ;Carga d l m i $ n del rogistro MPCS MOV AX,PMPCS ;Carga la palabra de control del

OUT DX,AX MOV DX,DPACS ;Carga la direcci$n de1 registro PACS MOV AX,PPACS ;Carga la palabra de control del

OUT DX,AX

;registro MPCS

;registro PACS

... .......N.rm.."*..-.**....-."..."

* "lnicializaci~ de k interlu de display H**.**.**..*H**.HHH......."."..."..

BUSY MOV MOV OUT

BUSY MOV MOV OUT

DXJRWRIO AL,00111000B DX,AL ;FUNCTION SET

, DXJRWRIO AL,00001110B DX,AL ;DISPLAY ON

I

MOV DX.COMKEY ;Carga palabra q w indica que se intro- ;dudr un comando. Pone pata de ;chip-seloct en bajo y Ao en alto

MOV AL,MODKEY ;Carga comando de modo de trabajo de ;teclado

OUT DX,AL MOV AL,PRGCLK ;Carga comando que indica sobre que valor

;debbra ser dividido el reloj interno del ;microprocesador para alimentar al 8279

OUT DX,AL MOV AL,CLRRAM ;Carga comando de limpiado de FIFO OUT DX,AL

...**.mmmH."."*..."...".""

Inlclaliuci$n del TIMER 2 y del TIMER 1 *


MOV MOV OUT MOV MOV OUT

MOV MOV

OUT MOV MOV OUT

END CSEG ENDS

DX,DPCT2 AX,PCT2 D X W DX,DMAXCAT2 AX,MAXCAT2 QXW

DX,DPCTI AX,STOPTI ;Esta palabra mantiene el TIMER 1 desha-

;bilitado, hasta que 80 de la palabra que ;lo habillto para que lnlcie la cuenta(PCT1)

D X W DX,DMAXCATI AX,MAXCATl D X M

Este es el programa que ham que programado pra interfasar con un teclado y despierte el sistema minimo del 80188 y su puede ser daptado a uno mas grande o mas

diagrama se muestra en el apendice de pequeno; el que usted desee.

diagramas y puede checar en el osciloscopio o incluye un listado explicado del funcionamiento

en el mismo desplay solo agregandole que pinte del sistema minimo 80188 y la manera o forma

un enunciado en el display, ademas ya esta de como ensamblarlo y ligarlo.

PAGE 60,132 TITLE PROGRAMA DE JUEGO DE ADIVINANZAS DE NUMEROS COMMENT * SISTEMAS DIGITALES 111 (se anexan rutinas de poyecto)

PRACTICA 2

Este programa inicializa la intertaz de teclado, 8279. Realiza la lectura del teclado por medio de interrupciones y revlsa los codigos validos proporcionados - por el usuario. Si adivina el numero dado manda un - mensaje de "YO PERDI" en caso contrario d mensaje es "YO GANE en un tiempo muimo de 6 minutos para encontrar eí numero valido. la tecla entar es 'F4 ' que sirve para valldar la entrada de los numeros los cuales 80 desplegaran a1 principio en formato de XX hasta XXXXXX (6 - bytes) y al adivinarlos .stoa "x" doscubriran el valor adivinado en la posicidn que le corresponde.

,

.I88 ;Instrucción del 80188 que sirve para asignar d i g o (tipo de ;codigo

;Necesario para que. el lenguaje sea valido por el ;ensamblador . *NI*** "..."mH....tr*

I

; INICIALIZACION DE LA LIBRERIA * ; * QUE CONTIENE LOS MACROS . t***.m***t*..* ".tcN...tH....

IF1

ENDIF INCLUDE a:\.rchivos\SD3PRAC2.LIB

;Estas intruciones Incluyen c6dlgo al principal a la hora de ensabhrlo por el MASM ;En oste se debo incluir la ruta de acceso d d arohivo y pude llevar cualquibr nombre ;no necesita un nombre on wpocial formato XXXXXXXXXXX . "*"****ff**..tmt*."*~"****.***".*


Apliacibn del 801 88

; DECLARACION DE VALORES CONSTANTES *

;Como cualquier otro lenguaje existe un bloque donde se detinen variables, y constantes ;las palabras aqul definidas y variables (direcciones) son tomadas del 80188 (manual).

* L.. tm..**H.H....W"*~.****

PUMCS EQU OFE3FH ; Palabra de control del b loqw de memoria superior DUMCS EQU OFFAOH ; Direcci6n del la palabra de control de memoria superior PLMCS EQU 001FFH ; Palabra de control de la memoria baja DMPCS EQU OFFAIH ; Direcci6n de la palabra de control de la memoria baja PMPCS EQU 080BFH ;Palabra de control de la memoria media DPACS EQU OFFA4H ; Direcclbn de la palabra de control de los periferical CS (donde

;podemos asignar ; bloques donde se pueden encontrar algunos perihricos que se ;pueden conectar al sistema

PPACS EQU 0003FH ; Palabra de control del los PACS.

IRWRIO EQU 00080H ; DRWRIO EQU 00081H ; DRRDIO EQU 00083H ;

~OMKEY EQU OOOOIH ; WRDAT EQU 00002H ; MODKEY EQU OOOllOOOB PRQCLK EQU OOlll l l lB RDFIFO EQU 0101OOOOB CLRRAM EQU 11OOOO1OB DATKEY EQU OOOOOH ; STSRAM EQU OOOOlH ;

~ADENA EQU OWH ; GODENT EQU OF4H

PCT2 EQU OCOOlH ; DPCTP EQU OFF66H ; MAXCAT2 EQU OFFFFH DMAXCAT2 EQU OFF62H PCTl EQU OC008H DPCTl EQU OFF6EH; MAXCATl EQU 0066CH DMAXCATl EQU OFF6AH STOPTI EQU WOAH

TAMRAM EQU 02000H TAMROM EQU 02000H

. t.m**.*H**f*H....Hm..~H**.***.

; " VARIABLES EMPLEADAS EN EL PROGRAMA * . .... Hm*HH.H".HtftH*H**.*

8

DIRNUMLIN EQU OlOOH 8

DIRPOS EQU 0102H ; DIRCAR EQU 0104H ; DIRCONTAB EQU 0106H DIRNUMCAR EQU 0108H DIRCONTCAR EQU OlOAH

DIRNUMALT EQU O200H t

DIRNUMX EQU 0210H; DIRCADENA EQU 0220H ,

DIRTABI EQU OFFSET TABLAI

,

. ........ HH***.H..iu

; * SEGMENTO DE CODIQO


9

CSEO SEGMENT PARA PUBLIC 'CODE ASSUME CS:CSEO

ORO

CLI MOV

MOV OUT DB MN MN

ORG

IFFOH ;Origina el programa en la memoria en ;la direeoi#n dada

AX,PUMCS ;Carga la palabra de oontrol del

DX,DUMCS ;Carga la diroeci#n del registro de UMCS DX,AX

OEAH ;Codigo objeto de la instucoi#n JMP OOOOOH ; O f f s e t OFEOOH ;Segmento de o#digo

;registro de UMCS

* IEFOH ;Origina las tablas en la memoria en la

;dirwcl#n dada

DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

, CADENA1 DB 'QUE LINEA?$' CADENA2 DB 'YO GANES

CADENA3 DB 'YO PERDIS'

ORO OOOOH ;Origina el resto del programa en la ;memoria en la dirwci#n dada ,

MOV AX,PLMCS ;Carga la palabra de aontrol del LMCS INC DX INC DX OUT DX,AX

MOV AX,IOOH MOV SS,AX MOV SP,OFFFH

MOV AX,CS MOV =,AX

* XOR AX,AX MOV ES,AX


Aplicach del 801 88

.m.mt".*****t.H."...............-

"Inicialkacign del bloque de puertos" * .H**..*H*Hm*.*Nm*~"....H*

MOV DX,DMFCS ;Carga direcclgn del registro MPCS MOV AX,PMPCS ;Carga la palabra de control del

OUT DX,AX MOV DX,DPACS ;Carga la d imc ign del registro PACS MOV AX,PPACS ;Carga la palabra de control del

OUT DX,AX

;registro MPCS

;registro PACS

.tCt."H"....***..H."..~......"...

* "Inkklizacign de la intetfaz de display H*...m.t**N.N-.."-.""".H*

BUSY MOV DX,IRWRIO MOV AL,00111000B OUT DX,AL ;FUNCTION SET

BUSY MOV DXJRWRIO MOV AL,00001110B OUT DX,AL ;DISPLAY ON ........... "t*...r.

* "Chequeo de memorlas" .N."ttt.Nt.t".N".H

I

CHECKRAM TAMRAM ;Llamado a macro para e1 chequeo de RAM CHECKSUM TAMROM ;Llamado a macro para el chequeo de EPROM

*******.***H*H*H*..****t.*..H*W****H.-*.*-.H.**H.

"lnicialkacign de la interfaz de teclado, 8279" *HH*t.*.*H*..tt.****.**"*.*H*H.H*.**.....*..*

MOV DX,COMKEY ;Carga palabra que Indica quo BO intro- ;duck un comando. Pone pata de ;chip-select en bajo y A0 en alto


OUT DX,AL MOV AL,PROCLK ;Carga comando quo indica sobre que valor

;debora ser dividido el reloj interno del ;mlcroproccrscldor para alimentar al 8279

OUT DX,AL MOV AL,CLRRAY ;Carga oomando de limpiado de FIFO OUT DX,AL

.".""H*t.t.t*.**"*H"**H.*****.*..."

* Inlcialiucign d d TIMER 2 y dd TIMER I .... *11........ N*rn.".~*........*.". MOV DX,DPCT2 MOV AX.PCT2 OUT D X W MOV DX,DMAXCAT2 YOV AX,MAXCAT2 OUT DX,AX

MOV DX.DPCT1 MOV AX.STOPT1 ;Esta palabra mantiene el TIMER 1 desha-

;bilitado, hasta que se de la palabra que


;lo habilite para que inicie la cusnta(PCT1) OUT DX,AX MOV DX,DMAXCATI MOV AX,MAXCATI OUT DX,AX

I

MOV M,DIRNUMLIN MOV BYTE PTR ES:[MI,OOH

ETIQI: LlMPlADSP CADENRAM CADENA1,DIRCADENA ESCCADENA DIRCADENA,03H

ETIQIA MOV DX.STSRAM IN AL,DX ;Obtiene 01 estado de la RAM del 8279 TEST AL,00000111B ;Mascara para ver el estado de la FIFO, JZ ETIQIA :

CALL

MOV MOV CMP JNE MOV MOV JMP

ETlQ2: CMP JNE MOV MOV

LEECAR

DI,DIRCAR AL,BYTE PTR ES:[DI] AL,'I' ETlQ2 DI,DIRNUMLIN BYTE PTR ES:[DI],OOH ;C#dlgo que indica la. linea ETIQ2A

AL,'2' ETlQl D1,DIRNUMLIN BYTE PTR ES:[m,OFFH

I

ETIQ2A: MOV DLDIRCONTAB MOV

ETiQ3: MOV MOV MOV MUL MOV ADD

MOV MOV MOV

MOV

BYTE PTR ES:[m,OOH I

AH,O8H ;Aqui se ajusta d contador de tabla DI,DIRCONTAB ;(CONTAB) para que sea un otket so- AL,BYTE PTR ES:[m ;bre la TABLA AH BX,OFFSET TABLA BX,AX

AL,BYTE PTR DS:[Ba ;Aqui se carga el nfmero de carade- DI,DIRNUMCAR ;res del nfmero aleatorio diremionado BYTE PTR ES:[MI,AL ;en la TABLA y es guardado en la va-

;riable NUMCAR ,

M,DIRNUMALT ;Aqui se'pasan los cgdlgos ASCII's de INC BX ;la cadena de caracteres direcdonada

ETIQ4: MOV AL,BYTE PTR DS:[Bx] ;en la TABLA, a la variable NUMALT, CMP AL," JNE ETIQS

;para aq, formar el nfmero aleatorio

INC BX ;(si cual es otra cadena do caracte-

JMP ETlW ;res pero localizada en la RAM y sin

;espacios en blanco)

CMP AL,'$' JE ETlQ6

;El caracter $ indica fin de la ca-

INC DI ;dona.

INC BX JMP ETlQ4

ETIQI: MOV BYTE PTR ES:[DI]AL ;Los espacios en blanco son hincados.

ETIQG: MOV M,MRNUMALT ;Aquí se forma en la RAM la cadena

ETIQ7: MOV AL,BYTE PTR ES:[DI] ;display MOV BX,DIRNUMX ;de X's que va a ser escrita en el


Aplicacib del 80188

CMP JE MOV INC INC JMP

ETlQ8 MOV

AL,'$'

BYTE PTR ES:[BA,'X' ETIQ8

DI BX ETiQ7 BYTE PTR ES:[BA,'$'

LIMPIADSP ESCCADENA WRNUMX,ObH

I

MOV D1,DIRCONTCAR ;Inicializa en cero un contador de MOV BYTE PTR ES:[MI,OOH ;ca&res aoertados, el cual wr-

;vir para determinar cuando w a ;acertado a la cantidad total.

MOV DX,DPCTI MOV AX,PCTI OUT DX,AX

ETIQS: MOV DX,DPCTI IN AX,DX CMP AX,0402AH JNE ETlQlO JMP GANE

I

;Aqui w pone d tiempo a correr.

I

;Aqui se choca si el d o . de la

;os 01 quo comaponde a cuando el ;palabra de control dd TIMER1

;TIMER1 a alcanzado la cuenta m xi- ;ma y si es aq, se brinca hasta la

;rutina que da el mensaje YO GANE.

ETIQIO: MOV DX,STSRAM IN AL,DX TEST AL,0000011 I B JZ ETIQS

I

CALL LEECAR

MOV DI,DIRCAR ;Aqui M ve si el carackr obtenido MOV AL,BYTE PTR ES:[DI] ;es un nfmero, si es as¡, respalda MOV AH,AL ;el cgdigo obtenido on AH, en caso AND AL,111 loo008 ;contrario regresa a obtener otro. CMP AL,SOH JNE ETIQS

XOR CX,CX ;Aqui 80 ve si el nfmwo tecleado

ADD DI,CX MOV AL,BYTE PTR ES:[DI]

;mero aleatorio.

CMP AL,'$' JNE ETIQ12 JMP GANE

ETIQ12: CMP AL,AH JE ETIQ13 INC CX JMP ETlQll

ETIQII: MOV DI,DIRNUMALT ;os uno de los que componen el nf-

ETIQIS: MOV DI,DIRCONTCAR ;Aqui se incrementa en uno d oon- MOV AL,BYTE PTR ES:pI] ;tador de oaraeteres, en caso de INC AL ;que d h e r o twloado se uno do MOV BYTE PTR ES:[DI],AL ;los que conforman el nfmero aloa-

;torlo (el cual no a sido atinado ;con anterioridad). ,

MOV DI,DIRNUMALT ;Aqui se cambja el cgdlgo ASCII del ADD W,CX ;nfmero atinado, q w w encuentra MOV BYTE PTR ES:[DI],"' ;on la varia- NUMALT, con el fin

;de que este no sea comparado de ;nuevo, con otro nfmero tecleado.

MOV D1,DIRNUMX ;Aqul se coloca en la variabk NumX ADD D1,CX ;el Ogdigo ASCII de la twla pro-


MOV BYTE PTR ES:pl],AH ;sionada. Esto 88 usado para el ;despliegue.

LlMPlADSP ESCCADENA MRNUMX,O6H

MOV D1,DIRCONTCAR ;Aqui se compara el nfrnero de ca- MOV AL,BYTE PTR ES:[Dl] ;raateres del nfmero aleatorio con MOV AH,AL ;el contador de caraateres atinados, MOV D1,MRNUMCAR ;para determinar si 80 han adivinado MOV AL,BYTE PTR ES:[DI] ;todos los nemeros que componen el CMP AL,AH ;nfmero aleatorio. JE PERDI JMP ETlQS

,

PERDI: CADENRAM CADENA3,MRCADENA ESCCADENA DIRCADENA,OIIH JMP ETIQ14

GANE: CADENRAM CADENA2,DiRCADENA ESCCADENA DIRCADENA.04H

ETlQ14 MOV DX,STSRAM ;Aqui se espora que se presione la IN AL,DX ;tecla de enter (F4) para continuar TEST AL,00000111 B ;con otra adivinanza. JZ ETIQl4

CALL LEECAR

MOV M,DIRCAR MOV AL,BYTE PTR ES:[DI] CMP AL,OF4H JNE ETIQ14

, ETIQIS: MOV DI,DiRCONTAB

MOV AL,BYTE PTR ES:[DI] CMP AL,l3H JNE ETIQ16 XOR AL,AL JMP ETlQ17

ETIQ16: INC AL ETIQ17: MOV BYTE PTR ES:[DI],AL

JMP ETlQ3 JMP ETlQ3 NOP

LEECAR PROC NEAR

MOV DX,COMKEY MOV AL,RDFlFO OUT DX,AL MOV DX,DATKEY IN AL,DX MOV BX,OFFSET TABLA1 XLAT MOV DI,DIRCAR MOV BYTE PTR ES:[DI],AL

RET

TABLAl DB 37H,38H,3SH,41H,OFlH,OOH,OOH,OOH ; 7, 8, 9, A, F l

;4, 6, 6, B, F3 DB 34H,36H,3SH,42H,OF2H,OOH,OOH,OOH


Aplicaci6n del 801 88

DB 31H,32H,33H,43H,OF3H,OOH,OOH,OOH

DB 30H,46H,46H,44H,OF4H,OOH,OOH,OOH ; 1, 2, 3, C, F3

; O, F, E, D. F4 t

LEECAR ENDP

, ESCCAR PROC NEAR

MOV DI,DIRWS MOV AL,BYTE PTR ES:[DI] AND AL,00111111 B MOV AH,AL MOV D1,DIRNUMLIN MOV AL.BYTE PTR ES:[DI] CMP AL,OOH JNE LINEA2 ADD AH,lOOOOOWB JMP DESPCAR

LINEAS:

DESPCAR ADD AH,llOOOOOOB

MOV AL,AH PUSH AX BUSY POP AX MOV DX,IRWRIO OUT DX,AL

MOV DI,DIRCAR BUSY MOV AL,BYTE PTR ES:[DI] MOV DX,DRWRIO OUT DX,AL

RET

ESCCAR ENDP

I

CSEG ENDS END

Como ve en el listado anterior se requiere de

tener una experiencia en lenguaje ensamblador

para llevar al micro a un buen funcionamiento,

el entender como se forman las palabras de

control y a donde direcionarlas es fundamental

para obtener un mejor aprobechamiento de

este, asignarle perifericos, controlar un

convertidor analogico-digital, desplegar

informacidn en un monitor mediante el enlace

de lenguaje de alto nivel como puede ser C 6

Pascal mediante la comunicacidn serial de una

PC normal. En fin si usted procede a ensamblar

este listado de la siguiente manera podra

grabarlo en una memoria EPROM y colocarla


en el sistema y vera el funcionamiento del

micro de manera muy simple:

C:\> en el simbolo del sistema teclee

“MASM y a continuaci6n le pedira que inserte

el nombre del archivo, no necesariamente es

indispensable asignarle la extensidn del archivo

si es ARCHIVO.ASM y si le indica la ruta donde

se encuentra, el programa lo ensamblara y ya

que le indico que no tiene ningún error

procedera a ligarlo:

A continuacidn se presenta el procedimiento

antes descrito.

D:\ELECTROMRCHIVOS>masm

Microsoft (R) Macro Assembler Version 5.10

Copyright (C) Microsoft Corp 1981, 1988. All

rights reserved.

Source filename [.ASMI: pruebal ; teclee el

nombre del

;archivo

Object filename [pruebal. OBJ]: pruebal

Source listing [NUL. LST]: pruebal

Cross-reference [NUL. CRF]: prueba 1

46980 + 356935 Bytes symbol space free

O Warning Errors O Severe Errors ; mensajes

macroensambler de que todo esta bien.

del

D:ELECTROMRCHIVOS>

Como el archivo se encuentra en la ruta

de acceso y el programa MASM esta

direcionado para llamarse de cualquier lugar

solo es necesario llamarlo. Para ligarlo es un

procedimiento igual:

D:ELECTRO\ARCHIVOS>/ink

Mkxosofi (R) Overlay Linker Version 3.64

Copyright (C) Microsoff Corp 7983-1 988. A l rights reserved.

Object Mduks [OBJ]: pruebal ; se teclea el nombre del

programa Run F k [PRUEBA I.€XE]: ; se le da enter si no se desea

;escribk

List File [NUL. MAP]:

Lbbrarias [ LIB]:

LINK : warning L4021: no stack segment

;mensaje del @&or de que no se b asbno un

segmento de pila, pem esto es irrelevante.

D:ELECTRO\ARCHIVOS>

Nuestro programa esta listo

para poder gravado en una memoria EPROM,

entonces podemos usar un gravador de

memorias como el RONMAX, EMP etc. Ya que

debemos tenerlo en extensi6n EX€.

El listado siguiente como el anterior son

tomados de los archivos fuente es necsario

porque es la macro que se incluyo en el listado:

IF1

ENDlF INCLUDE r:\prchivos\SD3PRAC2.LIB

; MACILIB - BIBLIOTECA DE MACROS NO. 1 (SWPRACPASM) ,

Esta biblioteca de macros contiene las rutinas para el chequeo da la RAM y de



I

la EPROM.

, CHECKRAM MACRO TAMRAM

LOCAL LLENADO,CHECADO,ETIQAUX,RA"AL,FCHKRAM, LOCAL RAM,BIEN,MAL,CHKRAM

PAL EQU 3AH

RAM DB 'RAMS BIEN DB "'BIEN'S' MAL DB "'MAL"$, CHKRAM DB "'CHECKRAM"$

MOV CX,TAMRAM PUSH CX

MOV BX,DIRNUMLIN ;* MENSAJE DE CHECKRAM * MOV BYTE PTR ES:[Bq,WH CADENRAM CHKRAM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,OBH RETARDO OFFH

POP cx XOR BX,BX MOV DI,BX

INC DI CMP DI,CX JNE LLENADO XOR BX,BX MOV DI,BX

CMP AL,PAL JE ETIQAUX JMP RAMMAL

CMP DI,CX JNE CHECADO

MOV BX,MRNUMLIN MOV BYTE PTR ES:[BX],OOH CADENRAM RAM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,OGH

MOV BX,DIRNUMLIN MOV BYTE PTR ES:[BX],OFFH CADENRAM BIEN,DIRCADENA ESCCADENA DIRCADENA,OBH

RETARDO OFFH JMP FCHKRAM

LLENADO MOV BYTE PTR ES:[DI],PAL

CHECADO: MOV AL,BYTE PTR ES:[DI]

ETIQAUX: INC DI

RAMMAL: MOV BX,DIRNUMLIN MOV BYTE PTR ES:[BX],WH CADENRAM RAM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,OSH

MOV BX,DIRNUMLIN MOV BYTE PTR ES:[BX],OFFH CADENRAM MAL,DIRCADENA ESCCADENA DIRCADENA,OBH

RETARDO OFFH

FCHKRAM:


RETARDO OFFH ENDM

CHECKSUM MACRO TAMROM LOCAL SUMLOC,ROMMAL,ETIQAUX,FCHKROM,EPROM,BIEN,MAL,CHKSUM

EPROM DB 'EPROMS' BIEN DB '"BIENS' MAL DB '"MAL"$ CHKSUM DB "'CHECKSUM"$'

MOV CX,TAMROM PUSH CX

MOV BX,DIRNUMLIN ;* MENSAJE DE CHECKSUM MOV BYTE PTR ES:[BW,OOH CADENRAM CHKSUM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,(WH RETARDO OFFH

POP cx DEC CX DEC CX XOR AX,AX XOR BX,BX MOV DI,BX

ADD BX,AX INC DI CMP DI,CX JNE SUMLOC MOV AH,BYTE PTR DS:[DI] INC DI MOV AL,BYTE PTR DS:[DI] CMP AX,BX JE ETIQAUX JMP ROMMAL

ETIQAUX: MOV BX,DIRNUMLIN MOV BYTE PTR ES:[BX],OOH CADENRAM EPROM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,OSH

MOV BX,DIRNUMLIN MOV BYTE PTR ES:(BW,OFFH CADENRAM BIEN,DIRCAMNA ESCCADENA DIRCADENA,OSH

RETARDO OFFH JMP FCHKROM

ROMMAL: MOV BX.DIRNUMLIN

SUMLOC: MOV AL,BYTE PTR DS:[Dl]

MOV BYTE PTR ES:[Bq,WH CADENRAM EPROM,DIRCADENA LlMPlADSP ESCCADENA DIRCADENA,MH

MOV BX,DIRNUMLIN MOV BYTE PTR ES:[Bq,OFFH CADENRAM MAL,DIRCADENA ESCCADENA DIRCADENA,MH

RETARDO OFFH


Aplicacidn del 80188

FCHKROM: RETARDO OFFH ENDM

CADENRAM MACRO CADENA,DIRCADENA LOCAL ETIQA

MOV BX,OFFSET CADENA MOV D1,MRCADENA

ETIQA: MOV AL,BYTE PTR DS:[Ba MOV BYTE PTR ES:[DI],AL INC BX INC DI CMP AL,’$ JNE ETIQA

ENDM

ESCCADENA MACRO DIRCAD,POSDSP LOCAL ETIQAfINESC

XOR CX,CX

MOV AL,POSDSP ADD AL,CL MOV DI,DIRPOS MOV BYTE PTR ES:[DI],AL MOV DI,DIRCAD ADD D1,CX MOV AL,BYTE PTR ES:[DI] CMP AL,’$ JE FINESC MOV DI,DIRCAR MOV BYTE PTR ES:[DI],AL CALL ESCCAR INC CX JMP ETIQA

ENDM

ETIQA:

FINESC:

9

LIMPIADSP MACRO

BUSY MOV DXJRWRIO MOV AL,00000001B OUT DX,AL ; DISPLAY CLEAR

ENDM

BUSY MACRO LOCAL REVISA

RDBSAC EQU 0082H

MOV DX,RDBSAC

AND AL,10000000B; JNZ REVISA

REVISA: IN AL,DX

ENDM


I

ESCRIBE MACRO CADENA LOCAL ESCRIBO

MOV AL,WH MOV BX,OFFSET CADENA XLAT XOR AHAH MOV CX,AX MOV SI,OlH

ESCRIBO BUSY MOV DX,DRWRIO MOV ALJBXIFU OUT DXAL INC SI LOOP ESCRIBO

ENDM ,

,

RETARDO MACRO TIME LOCAL RETARQ,RETARl

I

MOV AL,TIME

MOV CX,OBFFH

LOOP RETAR1 CMP AL,OOH JNE RETARO ENDM

RETARO: DEC AL

RETARl: NOP

DESPDlR MACRO BX,LCAL LOCAL CAPNlB,ASCLET,COLVARI

, ,

PUSH BX ,

BUSY MOV DXJRWRIO MOV AL , l lWWl lB OUT DX,AL ; SET DD RAM ADDRESS

ESCRIBE LCAL

POP BX ,

MOV

MOV MOV MOV MUL MOV SAR AND MOV CMP JAE MOV ADD JMP

CAPNIB DEC CH,04H CH

DX,BX AL,CH AH,04H AH CLAL DX,CL DX,OOOFH AH,OAH DL,AH

ASCLET AL,30H AL,= COLVARI

ASCLET: MOV AL,37H

Seminario de Proyectos I y 11 23


ADD AL,DL

COLVARI: MOV AH,AL BUSY MOV DX,DRWRIO MOV AL,AH OUT DX,AL CMP CH,OOH JNZ CAPNIB RETARDO 01H E N M

Esta completo y debe guardarse como sea interesada en este micro, ya que pueden

un archivo aparte y colocandola en la ruta utilizar cualquier micro de INTEL para conectar

adecuada para que el programa principal lo la interfaz que se anexo en el apendice al

encuentre. no proporcionaremos m& detalles finalque se utilizo en la aplicacibn que se eligio.

del funcionamiento del 80188 porque no es

parte del proyecto terminal, pero si podemos (se anexa el diagrama electrico del sistema

proporcionar infomaci6n a la persona que le minimo del 80188 en el apendice).


PROYECTO TERMINAL I Y I1

DESPLIEGUE DE CARACTERES ALFANUMERICOS EN UN TUBO DE RAYOS

CATODICOS Y DESPLIEGUE DE INFORMACl6N.

Para empezar a realizar esto tenemos

que tener el conocimiento de la interfaz que es

el controlador de CRT el 8275 de INTEL se

eligid este por razones obvias; ya que hemos

trabajado con INTEL (no recomendable ya que

presenta demasiadas equivocaciones en cuanto

a su arquitectura, aconsejamos trabajar con

MOTOROLA o Tecnología RlSC que es la mzis

adecuada y ademzis m& avanzada; las mejoras

de la industria que cada dia avanza m& y

mejor (es una advertencia de lo que debe hacer

usted si no se quiere quedar obsoleto en el

mundo de la electdnica de los sistemas

digitales).

INTRODUCCION AL CONTROLADOR DE

CR T.

Este controlador de CRT se puede

adaptar a cualquier micropmesador de la

familia 8080 de INTEL ya que presenta una alta

integraci6n; este es un medio para comunicarse

con un computador y poderlo ver visualmente

un una unidad de CRT, controlar el monitor (lo

que se despliega) y aplicarlo como si fuera un

monitor de cabecera que monitores los signos

vitales de un paciente.

Descripcidn del funcionamiento del una unidad

de CRT.

El raster scan de un CRT para

desplegar imzigenes es generalmente por una

serie de líneas (raster) a traves de la cara del

tubo. N haz de electrones usualmente

comienza del lado superior izquierdo

moviendose de izquierda a derecha, regresando

a la izquierda de la pantalla, movithdose un

rengldn hacia abajo y continuando hacia la

derecha. Esto es repetido hasta llegar a la parte

baja del lado demho de la pantalla escamada.


Aplicacidn del 801 88

El retorno del haz a la parte superior izquierda y

refrescando la pantalla. El haz realiza un patrdn

de Zig Zag como se muestra en la siguiente

Dos circuitos independientes controlan

el movimiento del haz a traves de la pantalla, El

primero es el circuito oscilador horizontal que

controla el movimiento de izquierda a la derecha

del haz, mientras el oscilador vertical controla el

movimiento del haz de amba hacia abajo. Este

circuito tambien se encarga de retomar el haz a

la parte superior izquierda o posici6n de inicio.

Así como el movimiento del haz de electrones a

traves de la pantalla; bajo el control del

oscilador horizontal. Un tercer circuito controla

el control del cafi6n del haz. este es el circuito

de vídeo Por variaciones en la comente la

imagen puede prvducime por medio de blancos

y negros que se deseen. Este circuito de video

es usado para retomar e/ haz a OFF o para

blanquear la pantalla.

Cuando el haz alcanza el lado derecho

de la pantalla este, no aparece en la pantalla (

no pinta) y retorna a el lado izquierdo. Este

retraso del haz es mas rdpido que el que genera

la imagen a traves de la pantalla. El tiempo de

búsqueda (SCAN) completo que le toma a la

pantalla (recomdo) para retomar a la posicidn

de inicio se llama cuadro (Frame); el CRT

puede operar de 18 Khz a 30 Khz; esto implica

mayor número de líneas por cuadro, este

incremento de líneas (Entre mayor número de

líneas mayor es la resolucibn), es necesario

para gdficos o editores de texto.

Hay un esttSndar de 25 líneas x 80

caracteres por linea que es el modo texto que

usaremos por el momento.

El CRT genera pulsos definidos por

tiempos tanto en horizontal como de vertical. En

el raster scan de CRT’s la frecuencia horizontal

puede variar en unos 500 Hz; esto provoca un

cambio en el numero de lineas horizontales

desde 256 a 270 por cuadro (frame). el

controlador de CRT debe hacer tambien un

corrimiento de la informaci6n a ser desplegada

serialmente por un circuito externo que controla

la intensidad del haz de scan a traves de la

pantalla. el circuito de control de tiempo

asociado con el com’miento de la informaci6n

es conocido como reloj de punto (dot clock) y el

reloj de carzicter (character clock) . Vease

apendice de diagramas al final. La frecuencia

del reloj de cardcter (character clock) es igual a

la frecuencia del reloj de punto dividida por el

numero de puntos que se toman a lo largo del

eje horizontal. La frecuencia del reloj de punto

es calculado como sigue:

Reloj de punto

(dot clock) (Hz) = (N+R)DLF

donde:

N es el número de caracteres desplegados por

rengl6n

R es el tiempo de cardcter por retraso

D es el número de puntos por caracter en el eje

horizontal


L es el número de lineas horizontales por

cuadro

F es la veloidad de cuadro en Hz que

normalmente es de 50 Hz (vertical).

En este diseno se consideran 80 caracteres por

linea, 20 retazos en el eje horizontal para

retorno, 7 puntos por caracter de ancho, 270

lineas horizontales por cuadro y 50 hz como

condicion del tipo de monitor que se usa que

nos da un reloj de punto de 12.5 MHz aplicamos

un reloj de 12 M comercial en el mercado y se

realizaran los ajustes por software

correspondientes. El número de retazos puede

variar en cada diseno a causa de los margenes

de diseno del CRT propios. El número de

puntos por caracter es elegido por el disenador

adecuado a las necesidades del sistema. En

este diseno se considera por las caracteristicas

del monitor una matriz de 5x7 puntos y 2

blancos entre cada caracter es decir D es de 7;

el número de lineas horizontales esta dado por:

L = (H xZ)+ V

donde:

H es el numero de lineas horizontales por

caracter

Z es el número de lineas de caracter por

cuadro.

V es el tiempo de retazo vertical en cada linea

hirizontal (retorno a la siguiente linea horizontal

a ser pintada)

En este diseno se consideran 7 lineas

horizontales por caracter mds tres puntos

blancos entre cada rengldn nos da como H =

10; Ademds si se considera que son 25 lineas

pero por calculos Z = 33.8857. El tiempo de

retrazo vertical puede ser ajustado de acuerdo a

los requerimientos del tipo de minitor y sus

caracteristicas especificadas. Dandonos esto el

número de lineas por cuadro a considerar.

El diagrama del controlador de CRT 8275 se

muestra en el apendie de diagramas al final.

REFRESCO DE DISPLAY DE CRT.

El 8275 debera ser programado para un

formato especifico en pantalla, generando una

serie de senales leidas del buffer. el rengl6n de

caracteres es transferido en este caso por un

sistema controlador (80188) desde la memoria

de despliegue (tamano y direcidn fijada por el

prugramador), hacia al buffer de rengldn del

8275. Cuando el buffer de renglbn es llenado se

deshabilita el CS de/ 8275 y se mantinen las

senales de WR y DACk (reconocimiento de

DMA (el DMA tiene como funcidn realizar

transferencias de acceso directo de memoria de

display ) )que es una linea por la cual le 8275

se le consede el derecho a tener el acceso a

memoria de despliegue. Entonces el 8275

presenta el &digo a un generador de

caracteres externo ( Este generador de

caracteres es una memoria 2716) ROM usando

para ello las lineas de salida CC, - CC6 .

Esta memoria debert) ser cargada con los

formatos de caracteres como se muestra a

continuacidn:



Addrees 00 O1 02 03 04 05 06 07 08 O9 OA OB O C OD O E OF 0000000: 00010000000000000000000000000000 0000010: 00000000000000000000000000000000 0000020: 00000000000000000000000000000000 0000030: 00000000000000000000000000000000 0000040: 00000000000000000000000000000000 0000050: 00000000000000000000000000000000 0000060: 00000000000000000000000000000000 0000070: 00000000000000000000000000000000 0000080: 00000000000000000000000000000000 0000090: 000000000000082AlCO31C2A03000000 00000a0: 00000000000000000000000000000000 OoooObO: O0000000000000000000000000000000 00000c0: 00000000000000000000000000000000 00000d0:00000000000000000000000000000000 00000e0:00000000000000000000000000000000 00000f0: 00000000000000000000000000000000 oooO100: 00000000000000000808080808000800 OOOOllO: 141414000000000014143E143E141400 oooO120: 08 3C OA 12 81 E O 80 00 O6 26 10 08 04 32 30 O0 oooO130: 04OAOA042A 122C000808080000000000 ooOo140: 08040202020408000810202020100800 oooO150: 082AlC0812AO08000008083E08080000 oooO160: 00000000000008040000003C00000000 oooO170: 00000000000018000020100804020000 oooO180: 1C 22 32 2A 26 22 1C 00 08 OC 08 08 08 08 1C 00 OOOO190: 1C 22 20 1C 02 02 3E 00 3E 20 10 18 20 22 1C 00 oooOla0: 10 18 14 12 3E 10 10 00 3E 02 1E 20 20 22 1C 00 00001b0: 380402lE22221C003E20100804040400 oooOlcO: 1C 22 22 1C 22 22 1C 00 1C 22 22 3C 20 10 O E 00 oooO1dO: 00000800000800000000080000808004 OOOOleO: 100804020408100000003E003E000000 ooOOlf0: 04081020100804001C22201008080008 0000200:1C222A3A lA023C00081422223E222200 0000210:lE24241C24241E00lC22020202221C00 oooO220: 1E 24 24 24 24 24 1E 00 3E 02 02 O E 02 02 3E 00 oooO230:3E02020E020202003C02023A22223C00 0000240:2222223E22222200fC08080808081C00 0000250:7020202020221C002212OA06OA122200 0000260:0202020202023E0022362A2A22222200 oooO270: 22 26 2A 32 22 22 22 00 1C 22 22 22 22 22 1C 00 oooO280: 1E 22 22 1E 02 02 02 00 1C 22 22 22 2A 12 2C 00 0000290: 1E 22 22 1E OA 12 22 00 3C 02 02 1C 20 20 1E 00 ooOo2aO: 3E 08 08 08 08 08 08 00 22 22 22 22 22 22 IC 00 ooOo2bO: 22 22 22 22 22 14 08 00 22 22 22 22 2A 36 22 00 00002c0: 22221408142222002222221408080800 00002dO:3E20100804023E00lC04040404041C00 00002d): 00020408102000003820202020203800 00002ID: 081C2A0808080800000000000000007E oooO300: 089011000000000000003C203C223C00 oooO310: 02021A2622221E0000003804B4043800 0000320:20202C3222223C0000003824BC84B800


62

80 X 80 X 80 X 80 X O0

80 X O0

8 P Z 1 8 P Z I

87N BSN

000680808080008000ZZZZZZ9Z V1 ZOZO :OP&OOOO

:an6!s ow03 tajsanw as A eajuap! ua 0 6 4 ~ ~ la a3npoJju! as se.uowaw ap ~opeqw6

sa aped epun6as el 9aptae3 un ap lewpapexay un ap Ja#nq lap aped wawud el ow03 !se s3

O0

zz X X ZZ X X zz X X 9z X x x VI x x x

BSMI 7 3 S3 Z 73 OSV3 31S3 N3 ZO X zo X

8 P Z 1 8 P Z I

87MI HSMI

000680808080008000ZZZZZZ9Z V l ZOZO~~OP&OOOO

do 30 U0 30 80 VO 60 80 LO 90 GO PO &O ZO 10 O0 SSaPPV

:!se sa e34w6 ewoi ua lapwe3 un ap uqpeuuo] el oldwara Jod

Aplicacih del 80188

x x 90

esto es un ejemplo de como se forma el

cahcter; despu& de tanto tiempo de consulta

de manuales y libros este es el formato que

funciona sino, nos creen introduscanlo en un

grabador y programen una ROM 2716 (la marca

de su preferencia). La salida de los datos por

estas salidas de la ROM son en forma paralela

y son convertidos dentro de esta a informaci6n

serial hasta el reloj externo de punto Ibgico,

hasta la entrada del circuito de video de la

unidad de CRT (amplificador de video). Los

renglones de caracteres son desplegados en

una línea del CRT a un tiempo considerando las

líneas de salida LCo a LC3 . Seleccionando

estas llneas de informaci6n hasta el generador

de caracteres ROM. El proceso de despliegue

es mostrado en la siguiente figura:

El proceso mostrado es repetido para

cada rengl6n de caracteres desplegados. Para

comenzar a desplegar un rengl6n, el 8275

genera una petici6n de intermpcidn colocando la

línea de salida INT en alto. La solicitud de

interrupci6n es aceptada por el 80188 y

reinicializando su carga del apuntador del buffer

para el pdximo ciclo de refresco del display. El

8275 deber4 ser programado para realizar un

refresco de CRT en la inicializaci6n del sistema;

El 8275 tiene dos tipos de registm internos; El

de cornando de solo escritura (CREG) y registro

de par4metros (PREG) y de solo lectura Status

Register (SREG). El 8275 espera recibir el

comando siguiente de O a 4 bytes dependiendo

el comando, las Instrucciones se describen a

continuaci6n:




1.- Comando de Reset.

Comand ejecuta una escritura al 8275

con A. en 1 es el comando de reset y su

palabra se escribe así:

MOV DX, DIR-COMAN-REG

MOV AL,OOOOOOOOB ; podriamos hacer

;MOV A L,OOH

OUT DX,AL

La accidn de este comando es realizar

una escritura de inicializaci6n del 8275,

solicitando este una solicitud de paro de DMA,

deshabilitando cualquier intermpcidn del 8275 y

usando la salida de VSP ( video supress ) del

8275 para blanquear la pantalla del monitor. Las

senales del 8275 HVRTC y VRTC cuando se le

aplica VCC al 8275 inician su conida sin

intermpcidn hasta que los parametros de

registros son mandados para tomar la velocidad

especificada por el programador o mejor dicho

para que los c¿9lculos activen a la unidad de

CRT. Estos tiempos por defaul son en un

principio aleatorios.

Este comando cuenta con cuatro

parametros a especificar de acuerdo a los

c¿9lculos previamente elegidos como son las

caractetfsticas del monitor y nuestro reloj de

punto (velocidad del cristal).

El primer pardmetro a mandar despues del

comando es:

MOV DX, DIR-PARAM-REG

MOV AL,SHHHHHHHB

OUT DX,AL

Despliegue en una Unidad de CRT

S Es el espaciado entre los renglones que

puede ser: S = O espaciado normal S = 1

espaciado de renglones en este caso es de un

rengldn sin pintar de caracteres.

HHHHHHH Son los caracteres horizontales por

rengldn especificados en el diseno que usted

elija:

H H H H H H H Número de caracteres por

rengldn.

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 2

0 0 0 0 0 1 o 3

1 O O 1 1 1 1 80 maxim0 lo que sigue no

esta definido.

El segundo pardmetro a especificar es:

MOV

MOV

OUT

DX, DIR-PARM-REG

AL, VVRRRRRRB

DX, AL

VV es el numero de retrasos verticales a

considerar en el diseno:

O 0 es 1 retraso vertical

o1 2

10 3

11 4 retrasos verticales

RRRRRR son el número de renglones verticales

por cuadro (frame).

000000 1 rengldn por cuadro

32

000001 2 o0001 o 3

171111 64 renglones por cuadro.

El formato de la pantalla en espaciado normal y maximop tomados en cuenta.

El tercer pardmetro de registro a

considerar es:

MOV DX,DIR-PARAM-REG

MOV AL,UUUULLLLB

OUT DXAL

UUUU Es la posici4n de subrayado del

caracter; es muy importante en este caso que si

se eligierdn 10 lineas por caracter entonces la

linea 11 es la de subrayado si se elige la 12

este subrayado no aparecera en el el

despliegue.

O000 1 en la linea 1 es la de

subrayado.

O001 2 0010 3

1111 16

LLLL Es el número de lineas a considerar por

caracter.

O000 1 linea por caracter

O001 2

O010 3

O011 4

11 1 1 16 lineas de caractel:

El último parametm de registro a considerar es

el siguiente:


MOV AL, MFCCZZZZB ;b indica que

introducimos



OUT DXAL ;c6digo binario. 1111 32

M Es el modo de conteo de linea.

O modo O, en este modo se

considera la linea de salida de conteo,

el número es el mismo que el número

de linea.

1 se considera un offset de cuenta.

F Es que el modo del atributo sea

visible o no para el expectador.

O es que sea transparente

1 no transparente.

CC Es el formato del cursor en el

despliegue.

O 0 que parpade en forma de video inverso

en bloque (esto no esposible en

nuestro diseno porque no se ha

cosiaérado esta linea de salida para el

CRT.

O1 Forma de parpadeo del cursor en

subrayado.

10 que no parpade en bloque de video

inverso.

11 no parpade en forma de

subrayado.

ZZZZ Se programa el número de retrazos

horizontales por cuadro.

O000 2 cuentas de caracter por cuenta

de retrazo horizontal.

o001 4

O 0 1 0 6

2..- Start display command. Este comando

indica al 8275 que debera empezar a realizar el

despliegue. No cuenta con parametros

adicionales y solo se indica en el número de

ciclos de tiempo de caracter que debera

esperar y el número de caracteres en cada

transferencia de DMA. Es un comando de

escritura como el comando anterior y debra Ao

estar en 1 y el formato es el siguiente:


MOV AL,OOlSSSBBH

OUT DX,AL

donde:

SSS es el número de tiempo de caracter entre

cada solicitud de DMA es decir un tiempo de

espera en el cual la solicitud de DMA hecha por

el 8275 debera ser dada al sistema de control en

este caso al 80188, y toma los siguientes

valores.

sss O00 O tiempos de reloj de caracter entre

cada solicitud de DMA

O01 7

O10 15

O11 23

100 31

101 39

110 47

111 55


88 es el numero de ciclos de DMA por apertura

es decir el número de

caracteres a transferir desde la memoria de

video a la unidad de CRT.

88

O0 1 caracter por apertura

o1 2

10 4

I I 8 caracteres por apertura de DMA.

En este comando al darse son

habilitadas las interrupciones del 8275, las

solicitudes de DMA se dan, la sena1 de video es

habilitada, las banderas del STATUS

REGISTER de intermpcibn y video son puestas.

3.- Stop display command.- Este comando esta

de escritura y no interfieree en la corrida de las

senales de HRTC y VRTC pero deshabilita la

sena1 de video, la bandera del registro de Status

register de video es reseteada y un nuevo

comando de Start debera ser dado para

comenzar a desplegar otra vez.


MOV AL,OlOOOOOOH

OUT DX,AL ;Pam del 8275

4. - Load cursor position. - Este comando permite

posicionar el cursor en el lugar que desee, por

defaul es posesionado en la parte superior

izquierda de la pantalla, si se desea llevar a un

lugar especifico deberan darse dos parametros

contiguos despues del comando.

MOV DX,DIR-COMAN-REG

MOV AL, 10000000H

OUT DX,AL

Si se desea llevar el cursor a una posicibn

deseada:


MOV AL,NUMERO DE CARACTER

;posicibn en el renglbn

OUT DX,AL

MOV AL,NUMERO DE RENGLON

OUT DX,AL

Como se indica no es necesario cargar

otra vez la dimci6n del registro de parametros

porque DX apunta a ella.

El 8275 cuenta como ya se menciono

anteriormente con regisro de escritura

(anteriores) y con registros de solo lectura que

es el registro de STATUS REGISTER. En el

cual podemos saber la condicibn en la cual cae

el 8275, como lo es:

Que el 8275 cayera en una condicibn de

comando impropio es decir que se diera un

comando equivocado por lo cual el 8275 no

opera, y espera a ser reseteado para que entre

un nuevo comando. Que cayera en un bajo

com'meinto de DMA, es decir que no se le de el

tiempo necesario para que los buffers de

caracteres se llenen adecuadamente. Que la

FIFO del 8275 cayera en un sobrecorrimiento;



en estos casos la bandera correspondiente es

puesta y el 8275 no opera hasa 9ue se reseteen

todas estas banderas.

El acceso a estos registros debra

tenerse en cuanta 9ue la sedal de CS debera

mantenerse a lo largo en conjuccibn con las

senales de WR o RD. El estado de la sena1 de

Ao determinara si el comando o parametro es

selecionado. El 8275 permite una flexibilidad de diseno en formato de despliegue como se

menciono anteriormente. El 8275 esta provisto

de salidas de tiempo para el control de la unidad

de CRT. Que son las sena1 de HRTC y VRTC

que controlan los circuitos osciladores

horizontales y verticales. La sedal de Video

Supress provee al circuito de video el tiempo de

punto para blanquear el video durante las

senales de retrazo horizontal y vertical.

LTEN: es usada para fonar la salida de

video en alto a pesar del estado de la sena1 de

Video Supress. Esta caracteristica es usada

para colocar el cursor sobre la pantalla y

controlar los atributos de funcibn.

RVV : Salida de video inverso; si es habilitada

causa 9ue la salida de video se invierta, 5 ciclos

de tiempos en la sena1 de salida, HLGT: Permite

la flexibilidad de incrementarse la intensidad del

haz de CRT para grandes niveles de lo normal..

El 8275 reconoce tambien 4 c6digos

especiales que pueden ser usados para reducir

memoria; software o un sistema controlador

superior. Los caracteres son desplegados en

cualquier lugar por el sistema controlador.

El 8275 desarrolla ciertas tareas cuando

estos c6digos son recibidos en el buffer del

renglbn de memoria de c6dgo.

111lOSS

SS

O 0 realizan la funcibn de indiarle al

8275 que el fin de renglbn llegb y

por lo cual debra brincar al siguiente

a desplegar.

FIN DE RENGLON.

O1 Le indica al 8275 9ue ha sido dado

un fin de renglbn y con paro de

DMA; es decir 9ue no se realizaran

mds transferencias de DMA en el

despliegue de este reglbn si no que

continuara con el proximo si no se ha

especificado lo contrario; es decir 9ue se de por

terminado el despliegue de la informacibn.

10 le indica al 8275 que un fin de pantalla

fue dado pero que continue desplegando lo

que se contega en los buffers de renglon.

11 le indica al 8275 9ue un fin de pantalla

y con paro de DMA es dado y con el cual no se

realizaran mds transferencias de DMA y se dara por terminado el

despligue de la informacibn por el cual

es retornado el despligue a la posicibn

inicial.

MOV DX,DIR-COMAN-REG

MOV AL, 11 1 lOOSSH

OUT DX,AL


A continuaci6n se proporcionara un para control del 8275.

listado del programa con la insercicln del cddigo

PAGE 60,132 ,

. I 86 IF1

ENDlF INCLUDE D\ELECTRO\ARCHNOS\SD3PRAC2.LlB

I

. ..t..**.t.HH*.**..tt.....H....~ I

; DECLARACION DE VALORES CONSTANTES * . *** ..,.t*)...t.H..*.,~..*...*)H*

PUMCS EQU OFE3FH DUMCS EQU OFFAOH PLMCS EQU OOIFFH

DMPCS EQU OFFA8H PMPCS EQU W B F H

DPACS EQU OFFA4H PPACS EQU OOO3FH

¡RWRIO EQU 00080H DRWRIO EQU 00081H DRRDIO EQU 00083H

COMKEY EQU OOOOIH WRDAT EQU 00002H MODKEY EQU 00011000B PROCLK EQU OOlll l l lB RDFIFO EQU OIOIOOOOB CLRRAM EQU IIOOOOIOB DATKEY EQU OOOOOH STSRAM EQU OOOOIH

CADENA EQU 0204H CODENT EQU OF4H

PCT2 EQU OCOOIH DPCT2 EQU OFF66H MAXCAT2 EQU OFFFFH DMAXCAT2 EQU OFF62H PCTI EQU OC008H DPCTI EQU OFF6EH MAXCATI EQU OO66CH DMAXCATI EQU OFFSAH STOPTI EQU 0400AH

. .*t....*..*. t*".H*"...+t*rr.nr. t

; VARIABLES EMPLEADAS EN EL PROGRAMA . ..*H*tm....t..*."..H..Ht.*H..t.

, DlRNUYLlN EQU OIOOH DIRPOS EQU 0102H DIRCAR EQU O I W DIRCONTAB EQU Ol06H DIRNUMCAR EQU 0108H DlRCONTCAR EQU OIOAH

DIRNUMALT EQU O2OOH


Aplicack5n del 801 88

DIRNUMX EQU 0210H DIRCADENA EQU 0220H

DIRTAB1 EQU OFFSET TABLA1 ,

DBMEMVID EQU 0400H DTMEMVID EQU OFFFH ASCllBLK EQU 20H INTllP EQU 0034H INTlCS EQU 0036H FlNLlNEA EQU 1111OOOOB FINPANT EQU 1111OOlOB FINLINEADMA EQU 11 1 lo001 8 ; paro de DMA FINPANTDMA EQU 1111OOIlB ; paro de DMA DACKDMA EQU 028FH

.......* rr*n+

;* DMAO .. .....n...*. DPCDMAO EQU OFFCAH DSOURCEO EQU OFFCOH

PCDMAO EQU 07666H ;M S do una transferenoia y sinc. por la fuente PC2DMAO EQU 07EA6H ;Solo una transferencia y sinc. por la fuente

DTCO EQU OFFCBH

DESTUW EQU OOOOH DESTO EQU 028FH

SOURCEUW EQU OOOOH SOURCE0 EQU 0400H

BASESCO EQU 0400H

TOPESCO EQU ODF6H

.*.H."*H..**.**

.* 1 -

;* INTlllNTAl * .*

DIMSKR EQU OFF28H PIMSKR EQU OOODDH

DIPMSKR EQU OFF2AH PIPMSKR EQU 00007H

DINTlR EQU OFF3AH PlNTlR EQU 00002H

DEOIR EQU OFF22H PEOllNTl EQU OOOODH

.. -..L..... ;* 8276 * ..........*. DPREG EQU 0202H DSREG EQU 0203H DCREG EQU 0207H


CRESET EQU OOOOOOOOb PI RESET EQU 001 11 101 b ;62 caracteres por linea P2RESET EQU OllOOOOOB :OO100001b P3RESET EQU 10001001b P4RESET EQU 1101 111 1 b ;20 carahrot3 por retrazo horizontal

CSTART EQU 001OOO11 b S T O P EQU OlOOOOOOb CLDCURSOR EQU 100000OOb CDlSlNT EQU 11000000b

.******H***.l**

;* VARIABLES ..**"H***** ,

ACTSCO EQU 0302H POSXCAR EQU O304H POSYCAR EQU 0306H BFINPANT EQU 0308H

. "*N*N****"***** ; * SEGMENTO DE CODIGO ' . ************-*e

CSEG I

SEGMENT PARA PUBLIC 'CODE ASSUME CS:CSEG

ORO IFFOH ;Origina el programa en la memoria en

CLI MOV AX,PUMCS ;Carga la palabra de control del

MOV DX,DUMCS ;Carga la dimcci$n del registro de UMCS OUT DX,AX DB OEAH ;Codigo objeto do la instuccign JMP DW OOOOOH ;met DW OFEOOH ;Segmento de W i g 0

;la direccidn dada

;registro de UMCS

I

ORO IEFOH ;Origina l a s tablas en la memoria en la ;direcci#n dada

CADENA1 DB 'EN QUE LINEA?$' CADENA2 DB 'Tu Perdiste$'


Aplicacidn dd 801 88

CADENA3 DB 'Yo perdis' I

I

ORO OOOOH ;Origina el resto del programa en la ;memoria en la direcoi@ dada

MOV AX,PLMCS ;Carga la palabra de control del LMCS INC DX INC DX OUT DX,AX

8

I

MOV AX,100H MOV SS,AX MOV SP,OFFFH

MOV AX,CS MOV DS,AX

XOR A X , A X MOV ES,AX

,

,

*.*........ t.t.rn~ttmm.t.N..Ntttt*****

"lnlcrialkaci$n del bloque de puertos" * 9.99.. Nt".tNt...*.*N.N*N***H*r

MOV DX,DMPCS ;Carga direcci$n del registro MPCS MOV AX,PMPCS ;Carga la palabra de aontrol del

OUT DX,AX MOV DX,DPACS ;Carga la dirscci$n del registro PACS MOV AX,PPACS ;Carga la palabra de control del

OUT DX,AX

;registro MPCS

;registro PACS

m*t".*L*~~*H*H.H..."N"~N.*

* "lnichliucign de la interfaz de display * ...tt********NX1*t..."N-...N*...*".**.

BUSY MOV MOV OUT

BUSY MOV MOV OUT

DX,IRWRIO AL,00111 OOOB DX,AL ;FUNCTION SET

DXJRWRIO AL,0000111OB DX,AL ;DISPLAY ON

I

, .*. H**HH**t.*.*..tN.NN*.**~H-...*N..

* "lnicialbi#n de la intorfaz de teclado, 8279" N** f.m*t.tNN...N**Nt...mHt.N..*mmH*H

MOV DX,COMKEY ;Carga palabra que indica que se intro- :duoir un comando. Pone pata de :chip-select en bajo y Ao en alto


OUT DX,AL MOV AL,PROCLK :Carga comando que indica sobre que valor

;debera ser dividido el reloj interno del :microprocesador para alimentar al 8279

OUT DX,AL MOV AL,CLRRAM :Carga comando de limpiado de FIFO


OUT DX,AL

, MOV DX,DPCT2 MOV AX,PCT2 OUT DX,AX MOV DX,DMAXCATZ MOV AX,MAXCATP OUT DX,AX

MOV DX,DPCTI MOV AX,STOPTI ;Esta palabra mantiene 01 TIMER 1 desha-

;bilitado, hasta que se de la palabra que ;lo habilite para q w inicie la cwnta(PCT1)

OUT DX,AX MOV DX,DMAXCATl MOV AX,MAXCATI OUT DX,AX

MOV DX,DSOURCEO MOV AX,SOURCEO OUT DX,AX

INC DX INC DX MOV AX,SOURCEUW OUT DX,AX

INC DX INC DX MOV AX,DESTO OUT DX,AX

INC DX INC DX MOV AX,DESTUPO OUT DX,AX

MOV DX,DTCO

OUT DXAL MOV AL,oan

MOV DX,DIPMSKR MOV AX,PIPMSKR OUT DX,AX

MOV DX,DINTIR MOV AX,PINTIR OUT DX,AX


Aplicaci6n dd 8 0 1 8 8 MOV MOV MOV MOV MOV MOV

BX,INTlIP AX,OFFSET INTI RUTINA WORD PTR ES:(BX],AX BXJNTICS AX,OFEOOH WORD PTR ES:[BX]W

MOV CX,DTMEMVID MOV AX,DBMEMVID SUB CX,AX MOV BX,DBMEMVID MOV AI,"

MOV BYTE PTR ES:[BX],AI I N C BX LOOP LIMPIAMEMVID

LIMPIAMEMVID

MOV BX,DBMEMVID

mov AL,'A' MOV BYTE PTR ES:[BX],AL INC BX mov AL,'A' MOV BYTE PTR ES:[BX],AL INC BX mov AL,'A' MOV BYTE PTR ES:[BX],AL

INC BX

MOV AL,'@ MOV BYTE PTR ES:[BX],AL INC BX

MOV AL,'# MOV BYTE PTR ES:[BX],AL

,

MOV MOV MOV

;RepPar: MOV MOV OUT

MOV

MOV OUT

BX,ACTSCO ;Iniciallza la variable de fuente actual AX,BASESCO WORD PTR ES:[Ba,AX

DX,DCREO AL.CRESET DXAL

DX,DPREO

AL,PIRESET DXAL


MOV AL,P?RESET OUT DX,AL

MOV AL,P3RESET OUT DX,AL


MOV DX,DCREG MOV AL,CLDCURSOR OUT DX,AL

MOV BX,POSXCAR MOV BYTE PTR ES:[BX],AL

MOV BX,POSYCAR MOV BYTE PTR ES:pXI,AL

. t g g ~ . ~ g ~ t ~ g g t ~ r n g g ~ ~ ~ g g g ~ ~ ~ ~ g ~ g g ~ - - ~ ~ m ~ ~ * ~ - ~ m m t

;* Habilitaei#n de canal de DMA O y w i g 0 de inicio del 8276 .** t t ~ ~ ~ * g * . t g ~ ~ . ~ m t ~ ~ ~ ~ * ~ r n ~ ~ ~ * ~ * ~ ~ * ~ ~ ~ ~ ~ ~ * ~ ~ n ~ N 5

MOV DX,DCREG MOV AI,CSTART OUT DX,AI

MOV DX,DCREG MOV AI,CDISINT OUT DX,AI

ST¡

,

MOV DI,DIRNUMLIN MOV BYTE PTR ES:[DI],OOH

ETiQ1: LIMPIADSP CADENRAM CADENA1,DIRCADENA ESCCADENA DIRCADENA,OBH

ETIQIA: MOV DX,STSRAM IN AL,DX ;Obtiene el estado de la RAM d e l 8279 TEST AL,00000111B ;Mascara para ver e1 estado de la FIFO, JZ ETIQIA ;

CALL

MOV MOV CMP JNE MOV MOV JM P

LEECAR I

DI,DIRCAR AL,BYTE PTR ES:[DI] AL,'I' ETlQ2 DI,DIRNUMLIN BYTE PTR ES:[DI],OOH $#dig0 que Indica IS. linea ETlQ2A

ETIQ2: CMP AL,'2' JNE ETIQI MOV DI,MRNUMLIN MOV BYTE PTR ES:[DI],OFFH

ETIQZA: MOV DI,MRCONTAB


Aplicacidn del 801 88

MOV

ETlQ3 MOV MOV MOV MUL MOV ADD

MOV MOV MOV

MOV INC

BYTE PTR ES:[DI],OOH ,

AH,08H ;Aqui se ajusta el contador de tabla DI,DIRCONTAB ;(CONTAB) para q w 80. un offset so- AL,BYTE PTR ES:[DI] ;bre la TABLA AH BX,OFFSET TABLA B X N

AL.BYTE PTR DS:[Bx] ;Aqui se carga el nfmero de cara&- M,DIRNUMCAR ;res del nfmero aleatorio dirwcionado BYTE PTR ES:[DII,AL ;en la TABLA y es guardado en la va-

9

;riable NUMCAR

D1,DIRNUMALT ;Aqq se pasan l o s c#dlgos ASCII's de BX :la cadena de caracteras direccionada

ETIQ4:~ MOV AL,BYTE h R DS:[Bx] ;en la TABLA, a la variable NUMALT, CMP AL," ;para aq, formar el M e r o aleatorio JNE ETIQ6 ;(el cual es otra cadenr de cara- INC BX ;res pero localizada en la RAM y sin JMP ETlQ4 ;espacios en blanco)

CMP AL,'$' ;El caracbr $ indica fln de la ca- JE ETIQG ;dena. INC DI INC BX JMP ETIQ4

ETIQ6 MOV BYTE PTR ES:[DII,AL ;Los espacios en blanco son blncados.

, ,

ETIQG: MOV DI,DIRNUMALT ;Aqui se forma en la RAM la cadena MOV BX,DIRNUMX ;de X's que va a ser escrlta en el

ETIQ7: MOV AL,BYTE PTR ES:[DI] ;display CMP AL,'$' JE ETIQ8 MOV BYTE PTR ES:[Bq,'X INC DI I N C BX JMP ETIQ7

ETlQ8: MOV BYTE PTR ES:[Bq,'$' I

LlMPlADSP ESCCADENA DIRNUMX,06H

MOV MOV

MOV MOV OUT

, D1,DIRCONTCAR ;Inicializa en cero un contador do BYTE PTR ES:tM],OOH ;caracteres acertados, e1 cual ser-

;vir para determinar cuando se a ;acertado a la cantidad total.

DX.DPCT1 AX,PCTl

;Aqq se pone el tiempo a correr.

DXSU(

ETIQS: MOV DX,DPCTl IN AX,DX

;Aqui se choca si el .do. de la :palabra de "rol del TIMER1

CMP AX,0402AH JNE ETlQlO

;es el que correspond. a cuando el

JMP GANE ;TIMER1 a alcanzado la cuenta m xi- ;ma y si es as¡, se brinca hasta la

;rutina que da el mensaje YO GANE.

ETIQIO: MOV DX,STSRAM IN AL,DX TEST AL,000001llB JZ ETIQS

CALL LEECAR


MOV DI,DIRCAR ;Aqui se ve si el caracter obtenido MOV AL,BYTE PTR ES:[DI] ; e s un &mero, si 08 as¡, respalda MOV AH,AL ;el cqdigo obtenido en AH, en caso AND AL,11110000B ;contrario regresa a obtener otro. CMP AL,30H JNE ETIQS

XOR cx,cx ;Aqui se ve s i el nfmero tooleado ETIQll: MOV D1,DIRNUMALT ; e s uno de los que componen el n f -

ADD DI,CX ;mero aleatorio. MOV AL,BYTE PTR ES:[DI] CMP AL,’$’ JNE ETIQl2 JMP GANE

ETIQl2: CMP AL,AH JE ETIQ13 INC CX JMP ETIQl l

MOV INC MOV

MOV ADD MOV

MOV ADD M OV

ETIQl3: MOV D1,DIRCONTCAR ;Aqui se incrementa en uno el con- AL,BYTE PTR ES:[DII ;tador de carautores, en caso de

AL ;que el n h e r o tecleado so uno de BYTE PTR ES:[DI],AL ;los que conlorman el nemero alea-

:tori0 (el cual no a sido atinado :con anterioridad).

DI,DIRNUMALT :Aqui se cambia el c$digo ASCII del DI,CX ;nPmero atinado, que se encuentra BYTE PTR ES:pU,”’ :en la variable NUMALT, con el fin


D1,DIRNUMX ;Aqui se coloca en la variable NumX DI,CX ;el cgdigo ASCII de la tecla pre- BYTE PTR ES:[DI],AH ;sionada. Esto es usado para el

;despliegue.

LlMPlADSP ESCCADENA DIRNUMX,OBH

MOV D1,DIRCONTCAR ;AqUi se compara el nfmero de ca- MOV AL,BYTE PTR ES:[DI] ;racteres del nfmero aleatorio con MOV AH,AL :el contador de caracteres atinados, MOV DI,DIRNUMCAR ;para determinar si so han adivinado MOV AL,BYTE PTR ES:[DII :todos los nfmeros que componen et CMP AL,AH JE PERDt

;nPrnero aleatorio.

JMP ETIQS

PERDI: CADENRAM CADENA3,DIRCADENA ESCCADENA DIRCADENA,WH JMP ETtQl4

GANE: CADENRAM CADENA2,DIRCADENA ESCCADENA DIRCADENA,WH

ETIQl4: MOV DX,STSRAM ;Aqui se espera que se presione la IN AL,DX ;tecla de enter (F4) para continuar TEST AL,00000111B ;con otra adivinanza. JZ ETIQl4

CALL LEECAR

MOV DI,DIRCAR MOV ALBYTE PTR ES:[DI] CMP AL,OF4H JNE ETlQl4

MOV DX,DEOiR MOV Ax,PEOIINTI OUT DX,Ax

POP SI POP DX POP BX POP Ax

IRET

INTIRUTINA ENDP

LEECAR PROC NEAR

MOV DX,COMKEY MOV AL,RDFIFO OUT DX,AL MOV DX,DATKEY IN AL,DX MOV BX,OFFSET TABLA1 XLAT MOV DI,DIRCAR MOV BYTE PTR ES:[Dl],AL

MOV DX,DCREG MOV AL,CLDCURSOR OUT DX,AL

MOV DX,DPREG

MOV BX,POSXCAR MOV AL,BYTE PTR ES:[BX] INC AL CMP AL,62 JB ACTPOSX MOV AL,OIH

ACTPOSX: MOV BYTE PTR ES:[BX],AL OUT DX.AL

MOV AH,AL

MOV BX,POSYCAR MOV AL,BYTE PTR ES:[BX] CMP AH,OIH JNE ACTPOSY INC AL CMP AL,33 JBE ACTPOSY MOV AL,OIH

ACTPOSY: MOV BYTE PTR ES:[BX],AL OUT DX,AL

I

Aplcac~dn del 80188

RET

TABLA1 DB 37H,38H,39H,41 H,OFl H,OOH,OOH,OOH ; 7, 8. 9, A, F1

;4, 6, 6, B, F3

; 1, 2, 3, C, F3

; O, F, E, D, F4

DB 34H,36H,36H,42H,OF2H,60H,OH,OOH,OOH

DB 31H,32H,33H,43H,OF3H,WH,OOH,OOH

DB 8OH,46H,4SH,44H,OF4H,OOH,00H,OOH

LEECAR ENDP

ESCCAR PROC NEAR

MOV DI,DIRPOS MOV AL,BYTE PTR ES:[DI] AND AL,00111111 B MOV AH,AL MOV DI,DIRNUMLIN MOV AL,BYTE PTR ES:[DI] CMP AL,OOH JNE LINEA2 ADD AH,IOOOOWOB JMP DESPCAR

LINEAZ:

DESPCAR: ADD AH,l1000000B

MOV AL,AH PUSH AX BUSY POP AX MOV DX,IRWRIO OUT DX,AL

MOV DI,DIRCAR BUSY MOV AL,BYTE PTR ES:[DI] MOV DX,DRWRIO OUT DX,AL

RET ESCCAR ENDP

CSEG ENDS END

El siguiente cbdigo es para la

adquisicidn de los datos (informaci6n

que es procesada por medio de un

;INTERRUPCIONES PINT2 EQU OOOOOH

convertidor analogico-digital, vease la

informacidn del convertidor en el

apendice de manuales de informacidn).

' I

DINT2 EQU Off3CH PPMR EQU OOOOOH DPMR EQU OFF2AH QE012 EQU OOOOEH DE01 EQU OFF22H

PINT? EQU OOOOOH DINT1 EQU OFF3AH PPMR EQU OOOOOH DPMR EQU OFFZAH PEOll EQU OOOODH

~IRNUMCAN EQU oioln DIRBANCO EQU 0106H

......................... " PROGRAMACICN DEL MA' ..........................

MOV DX,OFFBOH MOV AL,OOOOH OUT DX,AL

MOV DX,OFF34H MOV AL,OOOOH OUT DX,AL

MOV DX,OFF32H MOV AL,0001 H OUT DX,AL

MOV DX,OFFCIH MOV AX,OOFFH OUT DX,AX

MOV DX,OFFCGH MOV AX,OOOOH OUT OX,AX

MOV DX,OFFC4H MOV AX,0202H OUT DX,AX

MOV DX,OFFCPH MOV AX,OOOOH OUT DX,AX

MOV DX,OFFCOH MOV AX,OOOOH OUT DX,AX

;INTERRUPT STATUS

;DMA O CONTROL REGISTER

;TIMER CONTROL

;TRANSFER COUNT

;DESTINATION POINTER UPPER

;DEST. POINTER LOW

;SOURCE UPPER

;SOURCE LOW

MOV DX,OFFCAH ; TC=S,CHG=2 CON 11 JALA MOV AX,0001010001110110E OUT DX,AX ;CONTROL WORD

........................................ t

;INICIALIZACION DE LAS INTERRUPCIONES ...................................... MOV AX,OFFSET CONVERSION MOV WORD PTR ES:[0038H],AX MOV AX.OFEOOH

Apllcacidn del 801 88

MOV WORD PTR ES:[003AH],AX

MOV AL,PPMR MOV DX,DPMR OUT DXAL

MOV ALPINTI MOV DX,MNTI OUT DX,AL

MOV AL,PINT2 MOV DX,MNT2 OUT DX.AL

CALL AWUlSlClON

..... t.t.."......t..t..***~....*....t

;VECTORES DE INTERRUPCION .. t.*.....t......ttt.*.~*...".*..*..

CONVERSION:

MOV DX,WORD PTR ES:[0101H] IN AL,DX MOV BX,WORD PTR ES:[0103M MOV BYTE PTR ES:[BX],AL

MOV DX,DEOI MOV AL,PEOIZ OUT DX,AL

ADQUIRIR PROC NEAR

MOV AX,WORD PTR ES:[0106H'J ;DIRECCION INICIAL DEL BANCO DE ADD AX,lFFFH MOV WORD PTR ES:(0103H],AX ;ALMACENAMIENTO ELEGIDO

;COMIENZO DE UNA CONVERSION

SIGA: MOV DX,WORD PTR ES:[0101H] ;DIRECCION DEL CANAL ELEGIDO (0180H MOV AL,OOH ;DIRECCIONA CONVERTIDOR PARA EMPEZAR OUT DX,AL ;AWUISICION

OEC WORD PTR ES:[0103H] MOV AX,WORD PTR ES:[OI06H] CMP AX,WORD PTR ES:[OlOBH] JNZ SIGA

ALTO: HLT

LEA BX,CONVER CALL CADENA RETARDO OFFH

RET ADQUIRIR ENDP

1)csplicguc en una 1 inidad dc c ' l i 1

Cano se ve en el listado anterior; este es el

&go de adquisicibn y de conversion para

almacenarlo a la memoria de despliegue y de

aqui podemos mandar esta informaci6n al igual

de lo que hicimos cuando mandamos al 8275

para desplegar un letrero.

A continuaci6n se vera el listado final

del programa del proyecto terminal I y Il.

PAGE 60,132 TnLE PROGRAMA DE DESPLIOUE DE INFORMACION EN UNA UNIDAD DE CRT

COMMENT * PROYECTO TERMINAL I Y It

Este programa Inicialira la interfaz de teclado, 8279. Realiza Ir lectura del teclado por medio de interrupciones y revisa los oodigos validos proporcionados - por el usuario. SI adivina e1 numero dado manda un - mensaje de "YO PERDI" en caso contrario el mensaje es "YO GANE" en un tiompo maximo de 6 minutos para encontrar el numero valido. Is tecla enbr es 'F4 ' que sirve para validar la entrada de los numeros los cua- l e s se desplegaran al principio en formato de XX hasta XxXXXX (6 bytes) y al adivinarlos estos "x" descubriran el valor adivinado en la posici$n que le corresponde.

El procedimiento antes descrito solo es para estar seguros de que el sistema trabaja; no 8s impottante ya que lo que importa es b prograrnacidn de la Interface de adquisicien, conversi#n, almacenamiento en la memoria, mandando esta informacipn al 8276 para ser desplegada en la unidad de CRT.

AVALOS FLORES JUAN MANUEL BAUTISTA PARDO YESSELINE COSS MORA ENRIQUE

,186

.................................. ; lNlClALlZAClON DE LA LIBRERIA ; QUE CONTIENE LOS MACROS * ...................................

IF1

ENDIF INCLUDE D:\ELECTRO\ARCHIVOS\SD~PRAC~.LIS

...................................... ; DECLARACION DE VALORES CONSTANTES * ...................................... PUMCS EQU OFEBFH DUMCS PLMCS

EQU OFFAOH EQU O O I F F H

51

Aplicac16n del 80188

DM PCS PMPCS

DPACS PPACS

IRWRIO DRWRIO DRRDIO

COMKEY WRDAT MODKEY PRQCLK RDFIFO CLRRAM DATKEY STSRAM

CADENA CODENT

PCTP DPCT2 MAXCATP DMAXCAT2 PCTI DPCTl MAXCAT1 DMAXCATl STOPTl

TAMRAM TAMROM

EQU OFFAIH EQU OIOBFH

EQU OFFA4H EQU 0003FH

EQU OO080H EQU 00081H EQU 00083H

EQU OOOOlH EQU OOOO2H EQU O001 10008 EQU 00111111B EQU OlOlOOODB EQU 1lOOOOlOB EQU OOOOOH EQU OOOOlH

EQU 0204H EQU OF4H

EQU OC001H EQU OFF66H EQU OFFFFH EQU OFF62H EQU OCOOBH EQU OFFSEH EQU OO66CH EQU OFFSAH EQU 0400AH

EQU 02000H EQU 02000H

, t . ) . . . .~ .* . . . . t .~)t*" . . . . t t t . l

; VARIABLES EMPLEADAS EN EL PROGRAMA . ....*~*.*.*.. t.**.**.*.*.*..**"**...**

DlRNUMLlN DIRPOS DIRCAR DIRCONTAB DIRNUMCAR DIRCONTCAR

DIRNUMALT DIRNUMX DIRCADENA

DIRTABI

DBMEMVID DBMEMVIDl DBMEMVIDP

DTMEMVID ASCllBLK INTlIP INTICS FlNLlNEA FINPANT DACKDMA

EQU EQU EQU EQU EQU EQU

EQU EQU EQU

EQU

EQU EQU EQU

EQU EQU EQU EQU EQU EQU EQCJ

O1 OOH 0102H 0104H 0106H O1 08H OlOAH

0200H 021 OH 0220H

OFFSET TABLA1

0400H 0400H O6EOH ; se deja un margen un poco mayor para evitar

: traslapo de informaci#n ya que consideramos ; un espacio para el letrero de 400 lugares ; m S un margen de 80.

OFFFH 20H 0034H 0036H 11 11 O001 B ; Paro de DMA

OPBFH 11110011B ; Paro de DMA

I

!

.*.... **.f..*.

;* DMAO ..t. t.........

DPCDMAO EQU OFPCAH DSOURCEO EQU OFFCOH

PCDMAO EQU 07676H ;M S de una transferenoh y sinc. por la fuente ; TC=9, CHG= 2 CON 11 JALA ; TENIA 076A6H

DTCO EQU OFFCSH

DESTUPO EQU OOOOH DESTO EQU 028FH

SOURCEUPO EQU OOOOH SOURCE0 EQU 0400H

BASESCO EQU 0400H

TOPESCO EQU ODFSH

.*t.*..***..*..**.

.. 1 -

;* INTlIINTAl .. .... **t.....**.*.. DIMSKR EQU OFF28H PIMSKR EQU OOODDH

DIPMSKR EQU OFFZAH PIPMSKR EQU 00007H

DlNTlR EQU OFFBAH PlNTlR EQU 00002H

DEOlR EQU OFF22H PEOIINTI EQU OOOODH

PINT2 EQU OOOOOH DINT2 EQU OFFBCH PPM R EQU OOOOOH DPMR EQU OFF2AH PE012 EQU OOOOEH

PINT1 EQU OOOOOH DINT1 EQU OFF3AH PPMR EQU OOOOOH DPMR EQU OFF2AH PEOll EQU OOOODH

..*. "t.."...

;* 827s ..... t *...*. DPREO EQU 0202H DSREG EQU 0203H DCREG EQU 0207H

CRESET EQU OOOOOOOOb P l RESET EQU 00111101 b ;62 caracteres por linea

Ccminario dc I'roycctos I y I I


PZRESET EQU 00100001 b P3RESET EQU 10001 O01 b P4RESET EQU 1101 I I I1 b ;20 caracteres por retrazo horizontal

CSTART EQU 00100011 b CSTOP EQU OlOOOOOOb CLDCURSOR EQU IOOOOOOOb CDlSlNT EQU 11000000b CPRESET EQU I1 100000b

.t..*.**.*..*..*

;* VARIABLES ................ ACTSCO EQU 0302H POSXCAR EQU 0304H POSYCAR EQU 0306H EFINPANT EQU 0308H

....................... ; * SEGMENTO DE CODIGO ....................... CSEG SEGMENT PARA P u m c CODE'

ASSUME CS:CSEG

ORO 1FFOH ;Origina el programa en la memoria en

CLI MOV AX,PUMCS ;Carga la palabra de control del

;la direccien dada

;registro de UMCS MQV DX,DUMCS ;Carga la direccien del registro de UMCS OUT DX,AX DB OEAH ;Codigo objeto de la instucciCn JMP DW OOOOOH ;Offset DW OFEOOH ;Segmento de cedigo

QRG IEFOH ;Origina'las tablas en la memoria en la ;direcci$n dada

CADENA1 DB 'EN QUE LINEA?$ CADENA2 DB 'Tu Perd is te CADENA3 DB 'Yo perdis CONVER DB 'FIN CONVERSION,TSH TSPC DB 'CONVIRTIENDO',TBH

ORO

MOW INC INC OUT

MOV MOV MOV

MOV M OV

XOR MOV

OOOOH ;Origina el resto del programa en la ;memoria en la direccign dada

DX DX

AX,PLMCS ;Carga la palabra de control del LMCS

DX,AX

AX,lOOH ss,Ax SP,OFFFH

Ax,cs DS,AX

AX,AX ES,AX

.......................................... "InicializaciQn del bloque de puertos" * ..........................................

MOV DX,DMPCS ;Carga direcciqn del registro MPCS MOV AX,PMPCS ;Carga la palabra de control del

OUT DX,AX MOV DX,DPACS ;Carga la direcciCn del registro PACS MOV AX,PPACS ;Carga la palabra de control del

OUT DX,AX

;registro M PCS

;registro PACS

............................................. "InicialiraciQn de la interfaz de display

*t.*t....t.~....t..r*...**.~...*.."~...*..**

BUSY MOV DX,tRWRIO MOV AL,00111000B OUT DX,AL :FUNCTION SET

BUSY MOV DXJRWRIO MOV AL,00001110B OUT DX,AL :DISPLAY ON

.................................................... "lnicializaci$n de la interfaz de teclado, 8279" * ....................................................

MOV DX,COMKEY :Carga palabra que indica que se intro- ;ducir un comando. Pone pata de :chip-select en bajo y Ao en alto



OUT DX,AL MOV AL,PROCLK ;Carga comando que indica sobre que valor

;debera ser dividido el reloj interno del ;microprocesador para alimentar al 8279

OUT DX.AL MOV AL,CLRRAM ;Carga comando de limpiado de FIFO OUT DX,AL

.............................................. lniclrllzaci~n del TIMER 2 y del TIMER 1 ..............................................

MOV MOV OUT M OV M OV OUT

MOV MOV

OUT MOV MOV OUT

DX,DPCTZ AX,PCT2 DX.AX DX,DMAXCAT2 AX,MAXCAT2 DX,AX

DX,DPCTI AX,STOPTI ;Esta palabra mantiene el TIMER 1 desha-

;bilitado, hasta que se de la palabra que ;lo habilite para que inicie la cuenta(PCT1)

DX,AX DX,DMAXCATI AX,MAXCATI DX&(

........................................ ,* Inioiallzaci$n del DMA O ........................................

MOV DX,DSOURCEO MOV AX,SOURCEO OUT DX,AX

INC DX INC DX MOV AX,SOURCEUPO OUT DX,AX

INC DX INC DX MOV AX,DESTO OUT DX,AX

INC DX INC DX MOV AX,DESTUPC OUT DX,AX

MOV DX,DTCO MOV AX,OBH OUT DX,AX

...................................... 56

;INICIALIZACION DE LAS INTERRUPCIONES ...................................... MOV AX,OFFSET CONVERSION MOV WORD PTR ES:[OOBBH],AX MOV AX,OFEOOH MOV WORD PTR ES:[003AH],AX

MOV AL,PPMR MOV DX,DPMR OUT DX,AL

MOV AL,PINTI MOV DX,DINTI OUT DX,AL CALL ADQUIRIR

....................................... ;VECTORES DE INTERRUPClON ...................................... CONVERSION:

MOV DX,WORD PTR ES:[010lH] IN AL,DX MOV BX,WORD PTR ES:[Ol03H] MOV BYTE PTR ES:[BX],AL

MOV DX,DEOIR MOV AL,PEOIS OUT DX,AL IRET

.....................................

.* - ;* Inicializaci$n de INTlllNTlA ..

MOV DX,DIPMSKR MOV AX,PIPMSKR OUT DX.AX

MOV DX,DINTIR MOV AX,PINTlR OUT DX,AX

MOV BX,INTIIP MOV AX,OFFSET INTIRUTINA MOV WORD PTR ES:[BX],AX MOV BX,INTICS MOV AX,OFEOOH MOV WORD PTR ES:[BX],AX

................................... ;* Limpiado de memoria de video * ...................................

MOV CX,DTMEMVID

Seminario dc I’roycctos I y 11 57


MOV AX,DBMEMVID SUB cx,Ax MOV BX,DBMEMVID MOV AI,ASCIIBLK

MOV BYTE PTR ES:[BX],AI INC BX LOOP LlMPlAMEMVlD

LIMPIAMEMVID:

............................ ;* Colocamos el letrero ............................

MOV BX,DBMEMVIDl

MOV AL,FINLINEA MOV BYTE PTR ES:[Bq,AL INC BX

MOV AL," MOV BYTE PTR ES:[BX],AL INC BX

MOV AL,' ' MOV BYTE PTR ES:[BX],AL INC BX




MOV AL,' ' MOV BYTE PTR ES:(BX],AL INC BX

mov MOV INC

M OV rnov

INC mov MOV INC rnov M OV INC mov M OV INC rnov MOV INC mov M OV INC

ah,'F' BYTE PTR ES:[BX],AH

BX ah,'R' BYTE PTR ES:[BX],AH

BX ah;E BYTE PTR ES:[BX],AH

BX ah,'C' BYTE PTR ES:[BX],AH

BX ah,'U' BYTE PTR ES:[BX],AH

BX ah,'E' BYTE PTR ES:(BX],AH

BX ah,'N' BYTE PTR ES:[BX],AH

BX

mov ah,'C' MOV BYTE PTR ES:[BX],AH INC BX mov ah,'l' MOV BYTE PTR ES:[BX],AH INC BX mov ah,'A' MOV BYTE PTR ES:[BX],AH INC BX

MOV AL,FINLINEA MOV BYTE PTR ES:[BX],AL INC BX

MOV AL,FINLINEA MOV BYTE PTR ES:[BXl,AL INC BX

MOV AL,FINLINEA MOV BYTE PTR ES:(BX],AL INC BX

MOV AL,FINLINEA MOV BYTE PTR ES:[BXI,AL INC BX

........................................... ;* Colocamos LA INFORMACIPN ADQUIRIDA * ;* no es en tiempo real ...........................................

MOV CXDTMEMVID MOV AX,DBMEMVID2 SUB CX,AX MOV BX,DBMEMVIDS MOV A1,BYTE PTR ES:[OlOBH]

SIGUE-SACANDO:

MOV BYTE PTR ES:[BX],AI INC BX LOOP SIGUE-SACANDO

MOV AL,FINPANT MOV BYTE PTR ES:[BX],AL

.................................. ;* lnicializaci$n del 8276 * ..................................

MOV M OV MOV

RepPar: M OV M OV OUT

M OV

MOV OUT

MOV QUT

BX,ACTSCO ;Inicializa la variable de fuente actual AX,BASESCO WORD PTR ES:[BX],AX

DX,DCREG AL,CRESET DX,AL

DX,DPREG

AL,PlRESET DX,AL

AL,PZRESET DX,AL




.. ".....*t.*.....~*...*....."..*.~..*~.99*..~*.*******~...".*.**~

;* Habilltacign de canal de DMA O y c#digo de inicio del 8276 .. t.........t....t....~.**.9**.*.**99*.....~*~..*.*.*..9.9.99.9.

MOV DX,DCREG MOV AI,CSTART OUT DX.AI

MOV DX,DCREG MOV AI,CDISINT OUT DX.AI

mov dx,DSREG in al,dx and a1,00001OOOb jnz RepPar

MOV D1,DIRNUMLIN MOV BYTE PTR ES:[Dlj,OOH

ETIQI: LIMPIADSP CADENRAM CADENA1,DIRCADENA ESCCADENA DIRCADENA,03H

ETIQlA: MOV DX,STSRAM IN AL,DX ;Obtiene el estado de la RAM del 8279 TEST AL,00000111B ;Mascara para ver el estado de la FIFO, JZ ETIQlA ;

CALL LEECAR

MOV DI,DIRCAR MOV AL,BYTE PTR ES:[DI] CMP AL,'1' JNE ETIQ2 MOV DLDIRNUMLIN MOV BYTE PTR ES:[DI],OOH ;Cedigo que indica l a . linea JMP ETIQ2A

ETlQ2: CMP AL,? JNE ETlQI MOV D1,DIRNUMLIN MOV BYTE PTR ES:[DU,OFFH

ETIQ2A: MOV D1,DIRCONTAB MOV BYTE PTR ES:[D&OOH

I

I

ETIQ4:

ETIQ6:

ETlQ6:

ETlQ7:

ETIQS:

ETIQS:

M OV M OV M OV MUL MOV ADD

MOV M W M OV

MOV INC

MOV CMP JNE INC JMP

MOV CMP JE INC INC JMP

MOV MOV

MOV CMP JE M OV INC INC JMP

MOV

AH,OSH ;Aqui se ajusta el contador de tabla DLDIRCONTAB ;(CONTAB) para que sea un offset So- AL,BYTE PTR ES:[DIJ ;bre la TABLA AH BX,OFFSET TABLA BX,AX

AL,BYTE PTR DS:[BX] ;Aqui se carga el nfmero de caracte- D1,DIRNUMCAR ;res del n h e r o aleatorio dimionado BYTE PTR ES:[DQJL ;en la TABLA y OS guardado en lp Va-

;riable-NUMCAR

D1,DIRNUMALT ;Aqui s e ' pasan los c$digos ASCII's de Bx ;la cadena de caracteres d1mIon.d. AL,BYTE PTR DS:[BX] ;en la TABLA, a la variable NUMALT,

AL,' ' ;para as¡, formar el Mmero aleatorio ETlQ6 ;(el cual es otra cadena de caract6 BX ;res pero localizada en Ir RAM y sin ETIQ4 ;espacios en blanco)

BYTE PTR ES:[Dl),AL ;Los espacios en blanco son bincados. AL,'$

ETIQB ;El caracter S indica fin de la ca-

DI ;dona.

BX E f l W

D1,DIRNUMALT ;Aqui se forma en la RAM la cadena BX,DIRNUMX ;de X's que va a ser escrita en e1

AL,BYTE PTR ES:[DI] ;display AL,'$'

ETIQS BYTE PTR ES:[BX],'X

DI BX

BYTE PTR ES:[BX],'$ ETIQ7

LlMPlADSP ESCCADENA DIRNUMX,O6H

MOV D1,DIRCONTCAR ;Inicializa en cero un contador de MOV BYTE PTR ES:[DQ,OOH ;caracteres acertados, el cual ser-

;vir para determinar cuando se a ;acertado a la cantidad total.

MOV DX,DPCT1 $qui se pone el tiempo a correr. MOV AX,PCTl OUT DX,AX

MOV DX,DPCTl ;Aqq se checa si el edo. de la IN AX,DX ;palabra de control del TIMER1 CMP AX,0402AH JNE ETlQlO

;es el que corresponde a cuando el

JMP QANE ;TIMER1 a alcanzado la cuenta m xi- ;ma y si es asi, se brinca hasta la

;rutina que d a d mensaje YO GANE.

ETIQl0: MOV DX,STSRAM IN AL,DX TEST AL,000001llB JZ ETlQ3

CALL LEECAR

MOV DI,DIRCAR ;Aqui se ve si el caracter obtenido MOV AL,BYTE PTR ES:[DI] :es un nemero, si es psi, respalda MOV AH,AL ;el cedigo obtenido en AH, en caso

61

Aplicac16n del 80188

AND AL,lll10000B ;contrario regresa a obtener otro. CMP AL,30H JNE ETIQS

XOR CX.CX ;Aqui M) ve si el nfmero tecleado

ADD DI,CX ;mero aleatorio. MOV AL,BYTE PTR ES:[D(l CMP AL,'$ JNE ETIQl2 JMP GANE

ETIQl2: CMP AL,AH JE ETlQl3 INC CX JMP ETlQll

ETIQll: MOV DI,DIRNUMALT ;es uno de los que componen el ne-

ETlQl3: MOV D1,DIRCONTCAR ;AqUi se incrementa en uno el con- MOV AL,BYTE PTR ES:[DI] ;tador de caractere, en caso de INC AL ;que el nfmero tecleado se uno de MOV BYTE PTR ES:[DI],AL ;los que conforman el nfmero alea-

;tori0 (el cual no a sido atinado ;con anterioridad).

MOV DI,DIRNUMALT ;Aqui se cambia el c$digo ASCII del ADD DI,CX ;nCmero atinado, que se encuentra MOV BYTE PTR ES:[DI],'*' ;en la variable NUMALT, con e1 fin


MOV DI,DIRNUMX ;Aqui se coloca on la variable NumX ADD DI,CX ;el c#digo ASCII de la tecla pre- MOV BYTE PTR ES:[DI],AH ;sionada. Esto es usado para el

;despliegue.

LlMPlADSP ESCCADENA DlRNUMX,OIH

MOV MOV MOV MOV MOV CMP JE JMP

D1,DIRCONTCAR ;Aqui se compara el nEmero de ca- AL,BYTE PTR ES:[DI] ;racteres del nfmero aleatorio con AH,AL ;el contador de caracteres atinados, DI,DIRNUMCAR ;para determinar si se han adivinado AL,BYTE PTR ES:[DQ ;todos los nfmeros que componen el AL,AH ;nfmero aleatorio.

ETIQS PERDI

PERDI: CADENRAM CADENA3,DIRCADENA ESCCADENA DIRCADENA,04H JMP ETlQ14

GANE: CADENRAM CADENA2,DIRCADENA ESCCADENA DIRCADENA,04H

ETlQ14: MOV DX,STSRAM ;Aqui se espera que se presione la IN AL,DX ;tecla de enter (F4) para continuar TEST AL,0000011lB ;con otra adivinanza. JZ ETIQl4

CALL LEECAR

raov DI,DIRCAR MOV AL,BYTE PTR ES:[DI] CMP AL,OF4H JNE ETIQ14

ETIQl6: MOV D1,DIRCONTAB MOV AL,BYTE PTR ES:[DI] CMP AL.13H JNE ETIQIG

1)csplicguc cn una I hidad dc C'K I' 62

XOR AL,AL JMP ETlQll

ETIQ16: INC AL ETIQl7: MOV BYTE PTR ES:[DI],AL

JMP ETlQ3 JMP ETlQ3 NOP

lMlRUTlNA PROC NEAR

PUSH AX PUSH BX PUSH DX PUSH S1

mov dx,DSREO in al, dx and aL,01101001b jz Continua

Ciclo: jmp Ciclo jmp Ciclo

Continua:

MOV DX,DACKDMA MOV SI,ACTSCO MOV BX.WORD PTR ES:[SI]

CONTTRANSF:

MOV ALBYTE PTR ES:[BX] OUT DX,AL

INC BX

MOV AH,FINLINEA GMP AL,AH JE FINRENGLON

MOV AH,FtNPANT CMP ALAH JE FINPANTALLA

JMP CONTTRANSF

FINRENGLON: MOV WORD PTR ES:[SI],BX JMP FININTl

FINPANTALLA: MOV BX,DBMEMVID MOV WORD PTR ES:[SI],BX

FININTI: MOV DX,DEOIR MOV AX,PEOIINTf OUT DX,AX

POP SI

Seminario dc Proyectos I y I1 63 I

Aplicacibn del 80188

POP DX POP BX POP AX

IRE1

INTlRUTlNA ENDP

ADQUIRIR PROC NEAR

MOV AX,WORD PTR ES:[O6EOm ;DIRECCION INlClAL DEL BANCO DE ADD AX,lFFFH MOV WORD PTR ES:[OlO3Hj,AX ;ALMACENAMiEMO ELEGIDO

;COMIENZO DE UNA CONVERSION

CADENRAM TSPC,DIRCADENA ESCCADENA DIRCADENA,03H

SIGA:

ALTO:

ADQUIRIR

MOV DX,WORD PTR ES: [O lO l~ ;DIRECCION DEL CANAL ELEGIDO (OISOH MOV AL,OOH ;DIRECCIONA CONVERTIDOR PARA EMPEZAR OUT DX,AL ;AWUISICION

DEC WORD PTR ES:[OlO3w MOV AX,WORD PTR ES:[06EOH] CMP AX,WORD PTR ES:[O403H] JNZ SIGA

HLT

CADENRAM CONVER,DIRCADENA ESCCADENA DIRCADENA,OBH

RET ENDP

LEECAR PROC NEAR

MOV DX,COMKEY MOV AL,RDFIFO OUT DX,AL MOV DX,DATKEY IN AL,DX MOV BX,OFFSET TABLA1 XLAT MOV DI,DIRCAR MOV BYTE PTR ES:[DI],AL

RET

TABLA1 QB 37H,38H,39H,41H,OF1H,OOH,OOH,OOH

D8 34H,36H,36H,42H,OF2H,OOH,OOH,OOH

DB 31H,32H,33H,43H,OF3H,OOH,OOH,OOH

OB 30H,4%H,46H,44H,OF4H,OOH,OOH,OOH

; 7, 8, 9, A, F1

;4, 6, 6, E, F3

; 1, 2, 3, C, F3

; O, F, E, 0, F4

LEECAR ENQP

1)csplicguc cn una IJnidad dc C'K'I' 64

ESCCAR PROC NEAR

MOV DI,DIRPOS MOV AL,BYTE PTR ES:[DI] AND AL,OOll1lllB MOV AH,AL MOV D1,DIRNUMLIN MOV AL,BYTE PTR ES:[DU CMP AL,OOH JNE LINEA2 ADD AH,lOOOOOOOB JMP DESPCAR

LINEAS:

DESPCAR: ADD AH,110000008

MOV AL,AH PUSH AX BUSY

MOV DX,IRWRIO OUT DX,AL

MOV DI,DIRCAR BUSY MOV ALBYTE PTR ES:[Dq MOV DX,DRWRIO OUT DX,AL

RET

wp AX

ESCCAR ENDP

CSEG ENDS END

65


CONCLUSIONES, RECOMENDACIONES Y RECONOCIMIENTOS ...

I

incluirlos en los manuales de operacidn de la 1

Para realizar la interface con la

unidad de CRT tuvimos varios

problemas tanto en el disefio de

hadtware como en el software; Dado que la

informacMn que proporciona INTEL es en

ciertos puntos incierta y confusa.

Es recomendable que si desean

realizar una interface con una unidad de CRT

debedn usar otra tecnologia como es la

RlSC o si no tan avanzada como la familia

Motorola 68HXX, ya que se ha demostrado

que es una tecnologia superior y no es que

estemos dando lugar a echar a fuera INTEL

Pero con los problemas que tuvimos son

suficientes para desecharla y ademis

debemos considerar que la tecnologia que

usa motorola es completamente integrada es

decir que cuenta en sus integrados con

perifbricos que nosotros usamos y

adaptamos al sistema como lo es un

convertidor analogico-digital, puertos que

solo debemos inicializarlos. En suma los

problemas son a consecuencia que intel no

dice en ciertas ocasiones las modificaciones

que deberán tomarse en cuenta en diseño ya

que en la mayoría de los casos en una tarjeta

que se vende al mercado; esta conlleva una

serie de problemas resueltos, que en diseño

no muy profesional como lo somos nosotros

(sin duda alguna) tenemos los problemas

que a ellos tal vez les dieron solucibn sin

familia 80.

Se requiere que el diseñador tenga

un pleno conocimiento del manejo de

lenguaje ensamblador ya que si no lo

domina no podrsi realizar un buen proyecto,

se requiere tambien que se comprenda el

funcionamiento en primer lugar en

diagramas a bloques del funcionamiento del

integrado que se de una visidn muy general

del integrado a usar ya que con ello mejorara

el funcionamiento y con ello tendrd menos

problemas de los que ya se traen con el

integrado.

Tambih es importante que se tomen

en cuenta las características de la unidad de

CRT que se va a usar. Ya que la suma de

todos estos detalles nos llevo a que solo se

visualizara parte de la pantalla (la mitad de

ella ) solo se usaron 25 caracteres por 33

lineas(donde debeffan ser 80x33).

Despliegue tal vez por mal disedo de

Hadtwam o software.

Queremos agradecer al profesor de

proyectos por tener confianza y sobre todo

damos la confianza necesaria para lograr

realizar este proyecto, ya que este

ingrediente es un factor significativo. Por

que ademds de hacemos sentir personas

mds capaces nos hace sentir gente

preparada y calificada con una gran

confianza de realizar las cosas con ganas, no

con miedo por ellos '%RACIAS PROFESOR".

66


BIBLIOGRAFIA:

- Manual de operación del 80188 de INTEL Co.

- Hoja de datos de operación del 8275 de INTEL Co.

I_ Hoja de datos del convertidor Análogico - Digital

ADC0809 de INTEL Co.

- Hoja de datos del 8288 de INTEL Co.

- Hoja de datos del 8275 de INTEL Co.

Ilcspliegue cn una I Jnidad de CKI' 68

APENDICE I I

Seminario de Proyectos I y 11 69

. ..

I

1 ~

".

1 I ! i

. . . . . . .

I

~. ". 1 1

I I

/ / / I

I

II

C?

I

.. ". ................ . . . . . . . . . . . . . . . . . . . . . " - ." ." . . . .

S . " ... "" ........ - .....

1 ,""."--"

"" - . . . . .

8275 PROGRAMMABLE CRT CONTROLLER

m Programmable Screen and Character m Fully MCS-80TY end MCS-85TU

m 6 Independent Visual Field Attdbutes m ~~~l R~~ Buffers

m 11 Vlsusl Character Attrlbutes

Format Compatible

(Graphic Capabllity) B Programmable DMA Burst Mode

m Cursor Control (4 Types) m Slngie + SV Supply

m Light Pen Detection and Reglsters m 40-Pin Package

The lnler 8275 Programmable CAT Controller is a single chlp device lo interlace CRT raster scan Qi~plays wltn Inter microcompuler syslems. lls prlmsry lunctlon IS 10 relresh !ha dlsplay by bullermg the intormallon from main memory and keeplng track o1 ¶he Qlsplay posl¶lon O1 ¶he screen. The flexlbrllly designed Into the 8275 will allow aimple Interface to aJmos¶ any raster s a n CRT display wllh a mmmum ot external hardware and software overhead.

I

I

PIN CONFIGURATION

PIN NAMES

I"

BLOCK DIAGRAM

PIN DESCRIPTIONS

1 2 3 4

5

6

1

8

9

10

11

12 13 14 I5 16 17 18 19

20

FUNCTIONAL DESCRIPTION

Dots Bur Buffor This 3.1tate. bjd$rect!onal. abut buffer 8s used lo mterldca the 8275 10 the system Data Bus

Thls funnlonal bluck aCCeph knputs from the Svstrrn con trol Bus and qenerdles conirol rqnd l s for overdll devtce op?rateon I t contatns the Cornrnand. Parameter. and Status

devtce functional drlinrt~on Reglsters that store the vdrious C O n l r d formats lor the

RD(R..d) A ''low'' on rhrr mput mtorm, the 8215 thd! !ne CPU il reddtng data or s t d l ~ s m l o rma t~on l r om the 8275

WR (wrll,) A ''low'' on I h l S mput mlorms the 8275 that the CPU 15

wrtrlng ddta or control words to the 8275

(Chlp Selecb A "low" on thts mput selects the M215 No readgng or writ

mg w~ l l occur unless the devlce IS selycted. When CSts high. the Data Bus m the float state and R D and WR wcll have no ettect o n the chlp.

DRO (DMA Raqueat) A "high" on thn output mlorms the D M A Controller that the M275 deslrer a D M A translet

DACK (DMA Acknowledge) I __

A "low" on this mput tntorms the M215 that a CIMA cycle I S ~n progress

IR0 (Inlermpt Request) A "htgh" on lhls uutput tnlorms the C P U that the 8275 destres mterrupt rervtce

J 1

A g R ? ¿% O O I O Wvte 8275Parameter O 1 O O Read 0275Parameter 1 O 1 O Wrtte 8275Cornmand 1 1 O O Read 8215Status X 1 1 O ThreeState X X X 1 Three state

" -

8275 . .* ~ . , ' .

charactor Counter

,,& (o determnnc the number o1 characters to bs d w l a y e d por row and the length 01 the horlzontrl r e t r w i n l e r v d . f t ,, &,ven b y the CCLK (Character Clock¡ Input. h o u l d bs a derwatwe o1 the external dol clock.

The Ch,racter Counter 15 a prOVamm&bla CoutlWr thal $5

LIM Counter The Ltne Counter I S a programmable Counter that IS uud 10

&termlne the number of hor&¿ontal lines Isweemi PI

character row. I t s outputs are used to address the external character generator R O M .

R a Counter The R o w Counter I S a programmable counter that 1s used to dstcrmtns the numoer of character rows to be d w l a v e d Per trame and Ienqth of the vert>cal retrace Interval.

Light Pan Roglrtorr The L q h t Pen Reglsters are two regtsters that s t ~ e the con-

ever there IS a r w n g edge on the LPEN (L@l Pen1 Input. tents 01 the chardfter counter and the row counter when-

No,.: Soirwr.cor,rr,on IS rwulrld

Restor Tlmlnp end Vldoo Controls

H R T C (Horczontal Retrace) and VRTC (Verucal Retrace) The Raster Ttmlng cwcultry controls the fimlnp Of the

0 ~ 1 ~ ~ s . The Vldeo Control c,rcu~trv conlrols the genera. tlon 01 LAa-1 ( L m s Anrtbute). H G L T (H~ghlighll. R V V

Dress). and G P k t (General Purpose Anrlbuteb OutputS. (Reverse Vldeol. LTEN (Ltght Enable), VSP Wide0 SUP

Row Buffon The Row Bullerr are two 80 character bulters. They are

character codes to be dlrplayed. Whde one row buffer I S

Idled from the mtcrocomputer system rnemorv w t h the

do sp l ayq a row of characters, the other IS bemg Illled wlth the next row of characters.

Figura 2. 6275 Bloc& D W p m YHwlng Cwnler and R.pIrIw Funcllona

FlFOs There are two 16 character FlFOs m the 8275. They are ured to provade extra row buffer length In the Transparent Atlrlbute Mode (see Derailed Operathon senionl .

Buffer Inputtoutput Controllen

bemg placed In the row buffers. If the character 3s d charac The Bufler InDut/Output Controllers decode the characters

ter attribute. lteld artrtbute or speclal code, these con trollers control the appropriate actaon. (Examples: An "End o1 Screen-Stop DMA" spectal code wdl cause the Butler Input Controller 10 stop further D M A requests. A " H q W q h l " h i d attrjbute wtll c a u ~ the Butler Outuut Controller to actwate the U G L T output.1

I ., . . )I

SYSTEM OPERATION -1

MEMORIES

, \ SYSTEM BUS

r, M P M R no

0% 7 W R m €S IRa

8%) .o D U A

ORO Lfo-3 VIDEO SIGNAL

CmrnwLtR m 5 GENERATOR

' CHARACTER - m75 C C S 6 HORIZONTAL SYNC

CRT DOT

ANO .

'

CONTROLLER , '"lNG VERTICAL SYNC

CCLK c

INTENSITY INTERFACE

- - __1

VIDEO CONTROLS -

The 8115 dtrplays character rows one ¡me .t a lbme. read on command. [See Programmtng Sect8on.l

I W

: I

I I I

1 I

J

! - 1 . '

.- , . d 9Lrn

0 0 0 0

0 0 1 0 O O C l

0 1 0 0 0 0 1 1

o 1 10 o 1 1 1 1 o 0 0 1 0 0 1 1 0 1 0 1 0 1 1

a t o 1

0 0 0 0 loll

O 0 0 1 0 0 1 0 0 0 1 1

O 1 0 1 O I O O

O 1 1 0 o 1 1 1 toon 1 0 0 1 I O I C

wrmbr Lo.

O [I il n ci G O 0 0 0 0 O 1 1 1 1 o n m a m o LI 0 0 0 1 0 0 0 0

3 o m o n o m o 0 0 1 1 O O T O 2 m G o o m o o 0 1 0 0 0 0 1

The firat OMA request of t lp frame occurs one row tíme belore the end of vertrcd retrace DMA r@puCSU W n t l n w o p r o p m m e d . until the row buffer I S fllled. If the row txrfler is fil led in the msddle of a burst. tho 8175 fermrnates the bunt and rese!$ the burst counter. No mors OMA requests wrll occur untd the AWnnin# of the mxr row. A t that rime. SMA requesls are actrwated as programmed untll the other buffer I S fllled.

IRQ will go tnaclwe afler the 5bfu1 register ir read.

I

Flgurs 20. End of Intampl R l q W S l

VISUAL ATTRIBUTES AND SPECIAL CODES

Tho charmers procerred by the 8275 are 8.bt qumtrtr~. The character coda outputs orov~de the character generator wth 7 bits of address. The MMt Stpf rcanr Brt 1s the extra

charr tsr IMSB - 01. or I f It IS a Vrsual Anrlbute or Specral brt rP 11 IS used to d e t r r r n m 11 st ts a rmrrnal display

COJa IUSB = 11.

There are t w o rvpes of Vwal Atf r t tu te Coder. They are Charmer Anributn and Fleld Attrltutes.

".

8275 -.

H I 1 FOR HIGHLIGHTING B - 1 FOR BLINKING R I 8 FOR REVERSE VIDEO

1 FOR UNDERLINE GC - GPAt. GPAQ

8275 . . .-

8275 .i - I

Smcr the FIFO 8s 16 characten long. no more than 18 held attrlbutc characters n a y te used pel I l n e on thn modc.

characters m the FIFO are w r l t t m over and loll. I f more are used. a bl in the atatus word Is (61 and the flnl

I I " I i I j 1 2 3 4 5 6 7 8 9 J

~ ~~

F lgurr 22 Exsmplr of Ih. Vlslble Flrld Atlrlbulr Mode (Unb.rtLnr Allrtbutr)

I f the 8275 IS programmed m the invlslble held attribute node. the 8275 FIFO IS activated. 1 [ N O P O R S T U V

A E C D E F G H I J K L M

1 c- ;u FIrld an

Flpure 23. Block Diagram Showlnp FIFO A c t l d l O n

__ 8275

-

Rramoter - S Spaced Rows

S I FUNCTIONS

Parmeter - HHHHHHH Hormnlal CharactedRow

H H H H H H N

0 0 0 0 0 0 0 0 0 0 0 0 0 1

NO. OF CHARACTERS PER ROW

-

0 0 @ 0 0 1 0 I ! I

I i

1 0 0 1 1 1 1 1 80 1 O 1 O O O O 1 Undlhned

i

I

_" - 1 1 1 1 1 1 1 U"r)tIlncd

Parameter - V U Verrlcal Rerrace R o w Count

Parameter - R R R R R R Vertncal RowriFrame R R R R R R ROWSIFRAHE _" __ 0 0 0 0 0 0 1 o o o o u l 2 0 0 0 0 1 0 3

O O U l 1 4

0 0 1 0 I 6 I I

"

8275

S f 8 IIETWEENDMA REOUESTS M0 OF CMARACTER CLOCKS

l . Dtuble Interrupt Command:

I

i

* i

D.C. CHARACTERISTICS Tn - ooc to IOOC: vcc = 5v 1596

CAPACITANCE TA = 25'C; Vcc GNO = O\,

SYMBOL PARAMETER MIN. MAX. UNITS

Cllo I/O Capmtance 20 pF

TEST CONDITIONS

Input Capacitance 10 pF I,= 1 MHz

Unmeasured pans returned 10 Vss

!

. _ 8275

WAVEFORMS "

- . ... -

c 8275

I__L. - 8275 2,

LC. CHARACTERISTICS 0'C to 7dC; VE 5.0V t6%; G N D E 0'4

W r h nmlng

I I

clock Tlmlng Input Wmrolorms (For A.C. Toairl

_ _ . ". - __ --

N~mer i c Coprocesdng Capability Through 8007 Interface

w 00108 ~. - .- -

r- . ~ - " . _.._ ""-.__._I_ .. "_l - ~

Ccramlc Lcadlcaa Chip Csnior (JEDEC Type A ) Contacts Faclng Up Contacts Facing Down

~ "

Figure 2.80188 PlnOut Magram .. .. .

1.159

*m 80188

""-

w 80 188

r

OMA-mltated bus cycle. Durtng the same T-states. S 3 . a . and S5

ADDRESSXIATA BUS (0-7): Stgnals constrtute the llme mulhptexed memory (w I10 address ( T I ) and data lr2, T3, Tw. and AD6

AD5 I 110 , A M

AD3 A02 901

r15

At0 A l 1

A9 m . S7

ALElQSO

rn10Sl

i 17 l / O 1 O ADDRESSONLY BUS (6-15): Contalnrng valld address hr m T,-T, 3 O The bus IS ache HIGH. 5 O

- I

ntec 80188

ARDY

t- j !

80188

I

m 34 O

cc;s 33 O

I

Name and FuncUon HOLD: Indcates t h a t another bus master is requestrng the loca: bus. The HOLD input IS ache HIGH. HOLD may be asynchronous wlth respoct to the 80186 clock. The 80188 m11 issue a HLDA in respon%

!ssuance of HLDA. t h e 8 0 1 8 8 wll lioat the local bus and control to a HOLD request at the end of T. or T,. slrnultaneous wth t h e

I~nes. Atter HOLD is d e t e c t e d as bang LOW, Uw 801 88 wll lower HLDA. When the 801 88 needs lo run another bus cycle. 11 will agam

UPPER MEUUAY CHIP SELECT Is an actwe LOW outpul whenever a memory refe:snco is made lo lhe dolmd upper po-tron (1K-256K block) 01 memory. This llno IS not floated during bus HOLD. The address range actwatlng ÜCS is software programraa LOWER MEMORY CHIP SELECT Is active LOW-whenever a

Of memory. This line IS not floated during bus HOLD. The addre 5s mefnoty reference IS made to the d e f t n e d lower portion (1 K-25 jK)

range activating m is software programmable. WIDRAWGE MEMORY CHIP SELECT SIGNALS: Are active L )w when a memory reference is made to the deflned mad-range po lion )f memo~y (BK-512K). These lunes are n o t f l o a t e d durrng bust OLD. T h e address ranges activatlng MtZ5-3 are software programr 1% ~ERIPHERAL CHIP SELECT SIGNALS 0-4 Are ache LOW Lvhcn I reference is made to the defined peripheral area (64K byte 1/11 ipace). These lines are not floated dunng bus HOLD. The address anges activabng "4 am sobare programmable.

"

, dnve the local bus and contrd lines. -

'ERIPHERAL CHIP SELECT 5 or LATCHED Al: May be xogrammed to provide a sixth penpheral chlp select, or to provlde VI internally 4tched A l si nal The address ranga activating is oftware programmable. &%/Al does not float during bus HOLD. When programmed to provide latched Al, this p n wll retain Ihe weviousty latched value during HOLD. 'ERIPHERAL CHIP SELECT 6 or LATCHED U. May be nogranuned to provide a seventh peripheral chip select 01 In ovide M internally latched A2 ~ nal The address range activating bis s o - e - p m g r a m m / A 2 does not t b a t dww;g bus

HOLD. when programmed to provide latched A2, this pin w i l l retacn

through an extemal data bus transce~er. When LOW, data is transfend to the 60188. When HIGH the 801 88 places Write ciafa nn . - " - -. . the data bus.

m is ective LOW during each memory and I10 access. &TJ is HIGH whenever DT/R dranges stale. Dunng RESET, is driven HIGH for one dock. then Aoated. m also f l o a t s during bus HOLD.

39 O DATA ENABLE. Is provided 6s a data bus transceiver out t eoable.

FUNCTIONAL DESCRIPTION

Introduction The lollowing Functional Oascription describes the base architecture of the 80188. The 8 0 1 8 8 Is a Very high rntegratlon 8-bt microprocessor. It comhnes 15-20 of the most common mtcroprocessor system components onto one chip whlleproviding twice the performance of the standard 8088. The 80188 IS Ob- lec: code compatible wth the 8086,8088 mcroproc- CbSOfS and adds 10 new tnstruction types to the 8086, 8088 instruction set.

80188 BASE ARCHITECTURE T h 8086.8088,80186,80188 and 80286 f a m i l y all contam the same bltstc set of regrsters. rnstructmns. and addressing m d s . The 80188 pocesvx is up- ward compabble wlth the 8086. 8 0 8 8 , 8 0 1 B 6 . and 80286 CPUS.

GENERAL REGISTERS

Eight 16-brt general purpose registers may be used for artthmetlc and logical operands. Four of these (AX, EX, CX, and DX) can be used as 16-blt registers or spht into parrs of separate &bit registers.

BASE AND INDEX REGISTERS

Four oí the general purpose regislers may alSo be used to determrne offset addresses oí operands In memory. These reylsiiirj may contain base addresses or indexes to parttcular locations wtlhrn a segment The addresstng mode selects the SpeClfiC r e g isters for oparand and address calculatlons.

SlATUS AND CONTROL REGISTERS

Two 16-bit special purpose registers record o( alta cerbn aspects of the 80 t 88 processor state. TI" are the Instruction Pointer Regtster. which Contain! t h e otlset address of the next sequential instructioc to be executed. and the Status Word Register, whicl contains status and control flag bits (see Figures 3i and 3b).

STATUS WORD DESCRIPTION

The Status Word records specihc characteristics C the result of loglcal and arithmetlc instructions (M O. 2. 4, 6, 7, and 11) and controls the operatron C the 80188 within a y e n operating mode (bits 8. and 10). The Status Word Regtster is 16-bits mdc The function of the Status Word blts is Shown i Table 2.

r

Figuro 3b. Status Word Format

Tabla 2 S __

6 1 ZF

,tus Word Btt F u n c t i o ~

F uncth

Cany FlaQ-Set on highrder bl cany or borrow; cleared othermse

Parity Flag-Set d low-order 8 Ms ot result contain an wen

Othermse number of 1 "S; cleared

S e t on carry from 01 bonow to the low arder lour bits of AL: cleared otherwise

Zero Flag-Set it result is zero; cleared otherwise

Sign Flag-Set equal 10 high- order bR oí result (O if positive. 1 if negative)

Sngte Step Flag-Once set. a single step rnterrupl occurs after the next instruction executes. TF IS cleared by the slngle step inlermpt

Interrupt-Enable Flag-When

cause tha CPU to transfer set, maskable lntermpts will

control to an Interrupt vector spectfied location.

brection Flag-Causes strurg instructions to auto decrement

when set. Clearlng DF causes the approprrate index regster

auto Increment.

Overflow Flag-Set 11 the slgned result cannot be expressed wlthin the number o1 bits In the destlnatlon operand; cleared othenwse -____

Instruction Set The rnstruction se t is divided into m e n categories: data transfer, arithmew. sh¡/rotatellogical. string manipulation, control lransler. high-level instructions, and processor control. These categories we summarized in Figure 4.

An 80188 instruction can reference anywhere í?om zero to several operands. An operand can reside in a register. in the instruction itself. or in memory. Spe- cific operand addressing modes are discussed later in this data sheet

Memory Organization Memory IS organized in sets of segments. Each seg ment is a lrnear contiguous sequence of u2 to 64K (216) &bit bytes. Memory is addressed using a two- component address (a pointer) that conslsts of a 16- bit base segment and a 16-bil oftset. The 16brt base values are contained in one ot four internal segment registers (code, data. stack, extra). The physical address IS cakulated by shtfbng the tase value LEFT by lour btts and addrng the 16.bit offset value to yreld a 20-blt physical address (see Fqure 5). Thrs allows lor a 1 MByte physcal addr 3ss sue.

All instructions that address operands in memory must specily the base segment and the 16-bit clfset value. For speed and compact instruction tncodlng.

eratm IS rrnplml by the addressing mode sed (seo the segment reglster used for physical add ess yen-

wrrnen (see Frgure 6) as independent mocules the1 Table 3). These rules lollow the way prog.ams are

requlre areas for code and data. a stack. an3 accuas to external data areas.

Special segment overrlde rnstructlon prefixes allow

overndden for special cases. The stack, data, and the impllclt segment reglster selectton rules IO be

edra segments may ccuurloda Isr nmpk prwams

To access operands that do not resde in one of the lour immediately avadable segments, a lull 32" pointer can'be used to reload both the base ( S e g - ment) and onset vahres

Table 3. Segment Re

lmpllclt Segmml Selection Rule

lnstructlon prefetch and lmmedlate data. All stack pushes and POPS; any memory references whch use BP Reglster as a base reglstec. All stnng InStrUCtIon references w h r h use the DI reglster as an index. All other data relerencer __

Flgure 6. Segmented Memory Help. Structure Software ,/'

1-167 ,*' ,.5

4ddressing Modes

:hc $0 t 88 provldes elght categories of addressing nodes to spec~ty operands. Two addressng modes ire provlded for instructlons that operate on register Ir Irnrnedlate operands:

Regrsref operand Mde: The operand is located

/.nrned/ate Operand Mode: Th& operand is in- m one of the 8- or 16-bi? genera) registers.

c!uded 111 the inStrUCtIGn.

SIX ~ O ~ C S are provlded to specify the locatton of an operand in a memory segment. A memory Operand

rnent baso and an otfset. The segment base is SUP- address consists of two 16-blt components: a Seg-

plfcd by a 16-blt segment reglster either implicitly ChOScn by the addresslng mode or eXPllOtlY chosen w a seqment overrtde preflx. The offsel, also called

elluctwe address, is calculated by summlng any I ,j~iit~m!;sn 01 tho followlng three address el* t i t ; : ;1t5

the ~ C , V X C ~ J H J ! (an 8- or 16-blt immediate valU0

Itrc base (contents o! elther the EX or BP base

the mdex (contents o! erther the SI or DI index.

con1,urcd In the rnstructlon);

reylstcrs). and

rcg~sters)

h y cdrr, out from the 16-brt addrllon IS ignored. 1 . q r ; t t ' l t di:p!acements are sign extended to 16-bit 'ldlue3

Iornblnations o1 these three address elements de- line the SIX memory addressing modes, described below 0 Lhea Mode. The operand's offset is contarned In

the lnstructlon as an 8. or 16-blt displacement element Heglsfer lndlrecf Mode: The operand's offset is In one ot the reglsters SI. DI, BX, or BP. Based Mode; The operand's offset IS the sum Of an 8- or 16-brt dlsplacement and the Contents Of d base register (EX or EP). lndexed ,Mode: The operand's otfset is the Sum 01 an 8- or 16-bll drsplacement and the Contents 01 an Index regtster (SI or 00. &sed hdaxed Modee The operand's Offset 1s the sbrn 01 the contents of a base reglster and an Index rey I d

8ab& h d ~ x e d Mode wtfh Drsplacemenf: The O P mcld'5 ottsct 1s the sum 01 a base register's con- IC,! ,, a ~ ? Index rrgster's contents. and an 8- or 1 o 1 ~ 1 dlsplacemsnt.

Data Types

The 80188 dlrectly supports ¡he following data types:

/nregef; A wgned binary numeric Value contained In an 8-blt by% or a 16-blt word. All operations assume a 2's complemant representation. Signed 32- and 64-blt Integers are supported using an 8087 Numerlc Data Coprocessoc with the 80188. Ordm/: An unstgned %nary nuntenc value ccn- tained In an B-blt byte or a 16-b1t word. Pornlor: A 16- or 32-blt quantlty, cOmpoS€d Gf 3 t6-bll offset componen: or a 16-bit segment base component In addition to a 16-bit offset c o m p nent. Sfrmg: A contiguous sequence 01 bytes or words. A string may contam lrom 1 to 64K bytes. ASCN A byte representation of alphanumeric and control characters uslng the ASCII standard Of character representatlon. BCD: A byte (unpacked) representation 01 the decimal dlglts 0-9.

0 Packed BCD: A byte (packed) representatlon Of two declmal diglts (0-9). One dlgit is stored in each nibble (4-blts) of the byte. f-/oat/ng Poinf: A stgned 32.. 64-, or 80-bit red number representatton. (Floating point operands are supported using an 8087 Numerlc Data prDcessor wlth the 80188.)

In general, lndlvldual data elements must fit within defined segment Irmlts. Figure 7 yraphically rePr* sents the data types supported by the 80188.

I/O Space

The I/O space conslsts 01 64K &bit or 32K 16" ports. Separate rnstructions address the I10 space wlth elther an 8-blt port address, specifled in the Ir* structron. or a 16-blt port address in the DX registe. 8-brt port addresses are zero extended such that AI5-Ae are LOW. I/O port addresses OOF8(H) through OOFF(H) are reservad.

r " 80188

f

I

t

W c

Programs may cause an interrupt with an INT in-

usual conditron. whch prevents turther instruction structron. lnstructlon exceptions occur when an un-

Processing. IS detected whtle anemptmg to execute an instructlon. If the exceptlon was caused by eye- cutlngan ESC Instruction w~th t h e ESC.trap&t s e t In

relocatlcn reglster. the return lnstructlon wlll mint to the ESC Instruction. or to the segment over- '* prehx lmmadataty precdng the ESC mstruc- tlW I! the prefix was present. In all other cases, the

return address from an excepkn wll pant at tbe tnslrucbon lmmedlaleiy Iol!owmg Ihe WfUCbOn causing the excepbon.

A table containing up to 256 pointers defines the proper interrupt servlce routrne for each Interrupt. In- terrupts 0-31, some of which are used for instruction exceptions, are reserved. Table 4 shows Itw 80188 predefined types and default pnonly levels. For each Interrupt, an &bit vector must be supplied lo the 80188 whlch ldentlfies the appropriate table entry. Excopticns supply the interrupt vector Inter- nally. In audluon, Internal perlpheíals and noncas- caded extemal Interrupts w i l l generate thew own vectors through tha Internal cnrerrupt Controller. INT instructlons contarn or tmply the vector and allow access to all 256 Interrupts. Maskable hardware Ini- tiated Interrupts supply the &bit vector to the CPU durlng an interrupt acknowledge bus sequence. Non-maskable hardware rnterrupls use a predefined internally supplied vector.

Interrupt Sources

The 80188 can service interrupts generated by software or hardware. The software interrupts are gen. erated by spectfic Instructions (INT. ESC. unused OP, etc.) or the results of conditions specified by instructions (array bounds check, INTO, DIV. IDIV, etc.). All interrupt sources ara serviced by an tndtrect call through an element 01 a vector table. This vector table is indexed by using the interrupt vector type (Table 4). rnultiplled by four. All hardware-generated interrupts áre sampled at the end of each instruc-

first. Once Ihe servlce routine is entered and inter- tion. Thus. the software interrupts wlll begin service

priority can interrupt the service routine In progress. rupts are enabled, any hardware source of sutficml

Those pre-defined 80188 interrupts which cannot be masked by programmmg %e described below.

DIVIDE ERROR EXCEPTION (TYPE O)

Generated when a DIV or IDlV mstrucmn quofient cannot be expressed in the number of blts m the desknation.

SINGLE-STEP INTERRUPT (TYPE 1)

Generated after most lnstructlons tf the TF flag 15

structrons (e g., REP), lnstructlons whlch mod fy seg- sel. Interrupts wtll not be generated after pfefi m-

men1 reylstars (e.g., POP DS), or the WALT nstruc- tron.

NON-MASKABLE INTERRUPT-NMI (TYPE 2)

An external interrupt suulce whtch cam& be masked. ,

! . l W

... . - Overtlow E*cepbon

k r a v E O U ~ 14H 1 BOUND 1

-

I

1-1 70

80188

ESCAPE OPCOOE EXCEPTION (TYPE 7)

Generaled d execution is attempted o1 ESC opcodes (DBH-DFH). The exception wlll only be generated 11 a biI in the r e l o c a t i o n register IS set. The return address of this excepton wtll point lo the ESC instroc- tion causing the exception. If a segment override

dress will pranlb IJw s6gmenl override prefix. peflx pecebed the ESC instruction, the return ad-

Hardware-Qenereted interrupts are dtvided into two groups: maskable Interrupts and non-maskable interrupts . The 80148 provtdes maskable hardware interrupt request pins INTO-INT3. In addrtron, rnaska-

grated DMA controller and the Integrated timer urut Me Interrupts may be generated by the 80188 inte-

The vector &pes for these ~nterrupts are shorn, m

me Interrupt Flag bit ( I F ) In the Status Word. The hlerrupI controller is discussed in the peripheral section ot this data sheet.

Table 4. Software enables these Input8 by Wning

Further maskable interrupts are dlsabled while sew- icing an interrupt because the IF bat is reset as part of the response to an interrupt or exceptlon. The saved Stat~~s Word w i l l rellect the enable status of the process& prlor to the interrupt. The rnternrpt flag m11 remain zero unless speclfially set. The Interrupt

' r e s t o r i n g the original status of IF bit. I t the Interrupt return kbuction restores the Status Word, thereby

return re-enables interrupts. and another Interrupt is P e n d i n g , the 80188 mll irnmedlately service the hghestpMrity interrupt pending, 1.8.. no instructions Of the main line program w i l l be executed.

Non-Maskable Interrupt Request (NMI)

A non-maskable Interrupt (NMI) is also provided. Thrs intemLpt is serviced regardless o1 the Slate of

IF M. A tvplcar use of NMI wwld be to activate a Power failure routine. The actwation ot this hpul QUSes an interrupt with an internally s u p p l e d vector

9uence is pwfwmed. The IF blt IS cleared at the "Blue of 2. No externel interrupt acknowledge s e

beginning of M NMI Interrupt to prevent maskaMe mntermpts from beuq s e r v i c e d .

1.171

THE 80188 COMPARED TO THE 80186

The 80188 CPU is an &bn processor designed around the 80186 internal structure. Most internal functions of the 80188 are @!cal to the equwalent

bus the same way the 80186 does with the disbnc- 80186 funcbons. The Bot88 handles the external

wands are fetched or wmten in two consecutive bus lion of handl~ng only 8 bts at a time. Sixteen bit op-

cycles. Both processors WU appear idenbjcal to the sohare engineer. with thesxceplion of execution time. The internal regrster structure is identical and a l l ins t ruct tons have the same end resutt. The Mer- - ewes between the 80188 and the 801% are out- l~ned b e l o w . Internalty. there are three dillerences

related to me Sbt bus interlace. between the 80188 and the 8 0 1 8 6 . AH changes are

The q m iengtb is 4 bytes In the 80188. where- as the 80186 queue contains 6 bytes, cr three words. The was shatened to prevent overuse of the bus by the BIU when prefstching instructiw. This was requued because of the ad&W Itme neceswy to fetch instnrtrons 8 bits at a Limf To hvther opbmlze t h e q w w . the preletc!ung al- gonthm was changed. The 80188 BIU will fetch a new utStruc(l0n to l o a d tnto the queue each m e

queue. The 8 0 1 8 6 watts untd a &byte space IS

there M a 1-byte hole (space avarlable) in *e

aVa&le..

80188 Clock Generator Tho 80188 provides an on-chip clock generator f o r both Internal and external clock generation. The clock generator teatures a crystal oscillator. a divide- by-two counter, synchronous and asynchronous ready Inputs. and reset circuitry.

U 210708-8 J

Flgure 8. Rscommended 8 MHz 80188 Crystal Configuratlon

READY Synchronization The 80188 provides both synchronous and a s p chronous ready Inputs. Asynchronous ready S F chronizatlon IS accompllshed by circurtry which Sam ples ARDY In the middle of Tz, Tg, and again in middle ot each Tw unbl ARDY is sampled HIGH One-half CLKOUT cycle o! resolution bme is us8( lor full synchronimtion of a rising ARDY sisd high-to-low translbon on ARDY may be Used Bs indication o! the n o t ready condition but it mUSt performed synchronously to CLKOUT dthW in * mtddle of T ~ , 13, or T ~ , or at the falling edge of T: N Tw.

A second ready Input (SRDY) is provided 10 int@ face wlth externally synchronized ready Signals. TIu Input IS sampled at the end of T2, T3. and again the end of each Tw until it is sampled HIGH. using thts Input rather than the asynchronous r d input. the half-clock cycle resolution time penaltY' elimlnated.

Thts Input must satlsty set-up and hold times to 908 antee proper operation of the ctrcult.

1-172

.A

In addttion. t h e 80188. as part of the integrated chlp- @C. has the capabilily Io program WAIT

states for memory and peripheral blocks. Thls is dis- msed in the Chip %lect/Ready Log~c dascrtptlon.

T h e BO188 plowdes both a RES Input pin and a synchronized RESET outpan for use wlth other sys- t e m components. The RES Input pin on the 8OlBB is provded mth hysteresrs in order to facilltate power- on Reset generation via an RC network. RESET out- pat is guaranteed to remaln active for at feast five clocks given a m input nt at least SIX clocks. RE-

one-half clocks behrod HE-S. SET may be delayed ucto approrlmately two and

moqh the d Multiple 80188 ocossors may be synchronized r n p l t pm, slnce ths resets

both the processor and divide-by-two internal count-

&vide-by-two counters all begin counting at the 8( in the Clock gemrator. In order to ensure that the

Same time. the active golng edge of i%% must satisfy a 25 ns setup bme before the fallrig edge of the 801B8 clock input. In addition. In order to ensure t h a t 811 CPUs beyin executing In the Same clock cycle,

edge of the CLKOUT srgnal of all the proces- lfm reset must satisfy a 25 ns setup time before the

wrs.

LOCAL BUS CONTROLLER The 80188 provides a local bus controller to generate the local bus control stgnals. In addltlon. it em- Ploys a HOLD/HLDA protocol for relinquishing the local bus to other bus masters. It also provides wt-

bdirectthefkmofdataonandoff thelocalbus. Puts that can be used to enable external buffers and

Memory/Perlpheral Control The 80188 provides ALE. m, and bus control %nals. The m and signals are used to strobe

data from the 80188 to memory or 110. The ALE line Qta from memory or 1 1 0 to the 80188 or to strobe

Wid. The 80188 l o c a l bus controller does not pro- provides a strobe to latch the address when it is

slgnal (which will require external latching), make a memorylm ugnal. If this IS reqused. use the

be memory and I/O spaces moverlapping, or use the integrated chip-select circultry.

Transceiver Control The 8 0 1 88 generates two control stgnals for exrer-

transceiver chips. This capability allows the add¡- tQn of transceivers f o r extra buffering without adding

external lcgcc. These control lines. DTlR and b j , are generated lo control the flow of data through the transcervers. The operation of these signals IS shown !n Table 6,

Table 6. Transceiver Control SIgmIs Dsrcrlptlon I Pin Name Functbn @Ñ (Data Enable) Enables the outpul

drrvers of Ute transceivers. It is ac .tive

I/O. or INTA cycles LOW during memory,

DTlR (Data Transmit/ Determines the dirt clron Recelve) 01 travel through tho

transceivers. A HIGH level directs data away from the processor during write operations. while a LOW level c trects data toward the processor during a read operation.

Local Bus Arbitration The 80188 uses a HOLD/HLDA system of local bus exchange. Thrs provides an asynchronous bus ex-

utilizing t h e same bus can operate at separate clock change mechanism. This means multiple masters

frequencies. The 80188 provides a single HOLD/ HLDA pair through which all other bus masers may

arbitrate which external device wlll gain control of gam control of the local bus. External circuity must

bus master. When the 80188 relin uishes ccntrol of the bus when there is more than one alternate local

the local bus. it floats m, m, d, S&=. m, ADO-AD7, AB-Al9. w , and DT/A to dlow another master to dmre these lines dir ly

The 80188 HOLD latency time, ¡.e.. the time between HOLD request and HOLD acknowledge. is a function of the activity occumng m the processor when the HOLD request is received. A HOLD re-

the processor may racewe: higher than instruction quest is the lughest-priority activity request which

cycle is in progress, the 80188 wlll complete the fetching or internal DMA cycles. Kowever. if a DMA

transfer before relinquishing the bus. This implles that if a HOLD request is recervfid just as a DMA

great as 4 bus cycles. This will occurit a CIMA word transfer b e g m n s , the HOLD latency time can be as

dress to an odd address. This is a total of 16 clocks transfer -ation IS taklng place from an odd ad-

or more, if WAIT states are required. In addrtion. if locked transfers are performed, the HOLD latency time will be inueased by the length of the locked transier.

"it- ' *

i 1

..

.

8 0 1 8 8

Local Bus Controller and Reset

Curing RESET the loca l bus contrdler wll PWfm lho following acttons: 0 Drlve Di%, m, and m HIGH f o r one clock Cy-

cle, then float.

NOTE

to prevent Ihe processor from inadvertently enter- AD is also provided wrth an iniernal plli-up device

ing Oueue Status Mode during RESET. 0 Drlve ?%S to the inactlve state (all HIGH) and

Drive m K HIGH and ü m float. 0 Three-state ADO-7. AfJ-19. S?. DT/Ü.

Drlve ALE LOW (ALE is never floated). Drwe HLDA LOW.

-

then float.

INTERNAL PERIPHERAL INTERFACE

AII the 80188 integrated penpherals are controlled by 16-blt registers conmned wthm an internal 256 byle control block. The control block may be mapped Info either memory or 110 space. Internal loglc mll recognize control block addresses and r e spond to bus cycles. During bus cycles to internal registers. the bus controllerwill srgnal the operation externally (¡.e.. the m, WR. status. address, data. etc.. lines wll be driven as in a normal bus cycle). but D7-0, SRDY, and ARDY will be Ignored. The base address of the control block must be on an even 256-byte boundary (¡.e., the lower 8 bits of the base address are all zeros). All of me defined registers mthrn this control block may be raad or wnlten by the 80188 CPU at any time

The control block base address is programmed by a

block at offset FEH from the base address of the 16-blt relocation register contained within the control

control block (see Figure 9). It provides the upper 12 bits of the base address of the control block. Note that mappmg the control register block into an address range corresponding to a chipselect range is not recommended (the chip select circuitry is discussed later in this data sheet. In addition, bit 12 of this register determines whether the control block will be mapped into I10 or memory space. If this bit IS f . the control block wil l be l o c a t e d in memory

in I10 space. If the control register block is mapped space. If the bit is O, the control block WIII be located

into I 1 0 space. the upper 4 blts of the base address must be programmed as O ( s u m I h O addresses are only 16 blts wlde).

Whenever mapplng the 188 perrpheral mlrd blodr to another locallon. the programming Of the reka- ton rogrster should be done wth a byte wnte he. OUT DX,AL). Any access to the control Mock is done 16 btts at a tlme. Thus, internally. the tion reglster will got wrltten wlth 16 bits of the AX r-ster while externally. the BIU MU run MB 8-blt bus cycle. If a word tnslruction (8 used (¡.e. OUT DX,AX). the relocallon register will be written On It% list bus cycie. The Bus Interface Unit (BIU) wli then run a second bus cycle which is unnecessary. Ths

wthm the eontroi block (¡.e. the conUd block was address of the second bus Cycle will no longer be

m o d on the !:!S! cycle), and thercíoro. wiu require the gmaraboii o: an ahtarnal ready scgnal to cont plete the cycle. Far thls reason we recommend byte cqxralions to the relocation register. Byte inslfw-

control bbck and WIJI Climmnate haif of the bus CyCkS tlons may also be used lor the other registers in the

required it a word operation had been specified Byte operams are only vala on evBn 8dckesses though, and are undeftned on odd addresses.

In addltlon to ptmdlng relocatmn information f a r the control block, the relocatlon register contaurS W which place the Interrupt controller into W e Mode, and cause the CPU lo interrupt upon enatennO ESC instructlons. At RESET. the relocation register is set to 20FFH which maps the control block to Start at FFOOH in I10 space. An offset map Of the 256-byle control regtster block is shorn in F&W 1 o.

CHIP-SELECT/READY GENERATION LOGIC

The 80188 contalns log~c which provides program

peripherals. In addition. it can be programmed m mable chip-select generahon for both memories and

also provide latched address bits AI and M. provide READY (or WAIT state) generalion. It Can

chip-select lines are acbve for a l l memocy aod Yo cycles in thelr programmed areas, whether lh0Y be generated by the CPU or by the integrated CIMA U d

Memory Chip Selects The 80188 provides 6 memory CM select outpas f 6 r 3 address areas: upper memory, lower m e m Q Y 8

and midrange memory. One each is povided for Up per memory and lower memory. while four Ye @' vlded for mldrange memory.

The range f o r each chlp select is user-programme' ble and can be set to 2K. 4K. 8K. t6K, 32K. 64K- 128K (plus 1K and 256K for upper and lower drp selects). In addltlon. the beglnnlng or base M

1-1 74

80 188

r 1__7

Upper Memory

The u w limit of mamocy defined by this ctip select is always FFFFFH, while t h e lower l i is xogram- mable. By programming the lower limit the size of the select bbck is also defined Table 7 swws the relationship between t h e base address selected and Vle size of the memory Mock obtained.

LYCS Prog~

" Block siu

1K 2K 4K 8K 16K 32K 64K 128K 2%

Mdng Valuer

UMCS Value t-w

RO==Rl=R2=0)

FFF 8H FFWH FF38H FE38H FC38H F838H F038H E038H C038H

The lower llmit of this memory block is defined i n the

offset AOH in the internal conlrd block. The legal UMCS register (see Figure 11). This register is at

values f o r bits 6-13 and the resulting starting address and memory Mock sizes are given in Table 7. Any combination of bits 6-13 not shown in Table 7 wll result in undehned operation. After reset, the UMCS register is programmed for a 1 K mea. It m u s ~ be reprogrammed it a larger upper memory area is desired.

The ~nrernal generarion of any 20" address whose upper 16 bits are equal to o( greater than the UMCS value ( m t h btts 0-5 as "o") asserts CRS. U M ~ bts R2-RO speaty the r e a d y mode foc the area of memory defined by the chip select register. as exphned later.

Lower Memory The 80 188 provides a chlp select for low memory

tempt vector table. starttng at location 00000H. called m. The bottom of memory contains the IR

1-175

iw 80188 80 188

The lcwer Ilrn;t of memory dtlltned by this chrp ScII&Ct IS d!wvay: W . whtio the upper llrnlt 18 programmable. 9 y proqrammlng the upoer Imt. the sue Of the murnory block IS dellnod. Tabla 8 shows the relationship between the upper address salected and the SIZO of the memory block obtalned.

Table ~

____ - 003FFt1

j 007FFH OSFFFH i OlFFFH

1 03FFFH j 07FFFH

OtFFFH 1 lFFFFH I qFFFFH I "Y-

B. I r I

Memory Block Size I_-

1K 2K 4K 8K 16K 32K 64 K 128K 256K "" I

LMCS Programmlna Valuer ." "7- I

- LMCS Value I

0078H OOFBH O1 F8H 03F8H 07F8H OFFBH 1 FF8H

The t1ppc-r llrnlt o! thls memory block is deflned in the LMCS reglsier (sue Figure 12) at ollset A2H In the trlternal control block. Tho legal values for bits 6-15 and the resulttng upper address and memory block w e b ara g w n In Table 8. Any coniblrlatlon of bits 6 - 15 not shown IC Tablo 8 wlll result in unde!lned operatton. Alter RESET, Ctt-LMCS register value IS undefined However, the LCS ch!pselect llne will not become actlve untll the LMCS reglster IS accessed.

Any Internally generated 20-blt address whose upper 16 b ~ t s are less than or equal to LMCS (with blts 0 - 5 "1"; will assert m. LMCS reglster bits A2-RO spcclly the READY mode for the area of memory dallned by thts chip-select reglster.

Mid-Range Memory CS

The 80188 provtdes four ECx llnes which are active wlthln a user-locatable memory block. Thls block can be located wlthln the 80188 1M byte memory gd!ess space exciusIve 01 the areas defined by UCS and LcS Botn the base address and slze Of

thls memory block are programmable.

-

The size o! Ihe memory block deflned by the mdrange select !Inus. as shown In Table 9. IS deter- mlnod by bits 8- 14 of the MPCS register (see Figure 13). Thts register IS at locallon A8H in the internal control block. One and only one of bits 8-14 must be sot at a tlme. Unpredlctable operation of the i;i-ds lines will o:hem;se occur. Each of the four c h i p s 1x1 lines is acilva for one of the four equal mnbgu- ous dlvlstons of tho mid-range block. If the total block slze IS 32K. each chlp Selecl is aCbv9 f o r BK Of memory with McS% being actwe f o r the first range and MCS3 being active lor the last range.

The EX and M S In MPCS relate to penpheral fUnC- tionallg as descrlbed in a later SeCtlOn

Table 9. MPCS Programming Values

Total Block Individual MPCS Bit8 Sue Select SIze 14-8

8K 2K . COOOOOlB 16K 4K 32K. 8K

' 64K- 16K- 128K 32K 001OOOOB 256K 64K

5 1 2 K j 128K - "

The base address of the mdrange memory block is defined by bits 15-9 of the MMCS register (see Fig- ure 14). Thls rcglster IS at offset A6H in the interd control block. These bits correspond to bits A19-Al3 01 the 20-blt memory address. 811s A12-A0 of the base address are always O. The base address may be set at any integer multiple of the stze of the total memory block selected. For exam ple, 11 the mid-rango block sue is 32K (or the size of the block for which each m line is active is 8t0, the block could be Located al lOOOOH or 18000H.: but not at 14000H. slnce the first few integer ples o! a 32K memory block are OH. BOOOH. 10000H, 18000H, etc After RESET, the contents 01 both of these regtsters are undelmed. Howeva. none 01 the MCS llnes wlll be acuve untll both the MMCS and MPCS regtsters are accessed.

.

Figure 1 l. UMCS Register

. ~ "_ Flgure 12. LMCS Register

I Figure 14. MMCS Register

I

however 11 can only be a multlple of 1K bytes. ¡.e.. lhe least slgniflcant 10 bits of the starttng eddress are always O.

m and m can also be programmed to qovide latched address bits X1 and A2. If so programmed, they cannot be used as penpheral selects. These outputs can be connected directly to the A0 and Al pins used f o r selecting internal registers of 8-ht peripheral chlps.

The starting address of the penpheral chipselect block is defined by the PACS register (see Flgure 15). The register IS located at offset A4H in the internal control block. Etts 15-6 of this register correspond lo bits 19-10 of the 20-bit Programmable Base Address (PEA) of the penpheral chipselect block. Bits 9-0 o1 the PEA of the peripheral chip-se- lec1 block are all zeros. If the chipselect block is located in 110 space. bits 12-15 must be programmed zero, anca the 110 address is only 16 bits wide. Table 10 shows the address range of each peripheral chip Select w~th respect lo the PEA contained in PACS register.

r""" ' ".""""_I_ __I_____

Flgure 13. MPCS Reglster r

MMCS bis R2-RO speciíy READY mode of opera- ban tor all four mtd-range Lhtp saiects.

The 512K block slze for the mld-range memory chlp selects is a special case. When using 512K. the base address would have to be at either locations OOOOOH or 80000H. I f it were lo be programmed at OOOOOH when the ES line was programmed, there would be an internal confktbehveon the LCS ready generation loglc and the MCS ready generation logic. Likewise. if the base address were p r o g r ame at 8-H. there wwld be a confllctwlth the UCS ready generation logic. Since the LCS chip-select llne does nolbecome active until programmed, whlle the m llne IS active at reset. the memory base can be set orlly at 0 0 0 0 ~ ~ thls base address is selected, however. the LCS range must not be programmed.

Peripheral Chip Selects

The 80188 can generate chip selects for up to Seven Peripheral devices. These chip selects are acbve for Seven contiguous blocks of 128 bytes above a programmable base address. The base address may be bCated in either memory or I/o space.

Seven a lines called m - 6 are generated by the 80188. The base address is user-programmable;

-

I

L

Figure 15. PACS Reglster

.- -

1-177 1-116 i

"1

I

The lormat o1 t h e DMA Control Blocks is shown m Table 13. T h e Transler Count Register (TC) speci- 110s the number 01 DMA LTanslers to be perfwmed.

tordbc IermlnaWn. The Control Word delmos the Up to 64K byta transters can be performed with au-

channel's o(wraWn (see Flgure 17). All rqsters may be modlied or alterad duMg any DMA achiíy.

ed mnedlately m OMA opetam. Any changes made lo registers will be reflect-

The usar should program bits 15-6 to COrrOSPOnd to iho desrred penpheral baso locatlon. PACS bts 0-2 are used 10 spac~v REAOY mode tor P T ~ ~ - K S ~ .

Table 10. PCS Address Range.

ndng " 7

Table 12. READY 811s ProQr ar....

1 U2 ! A l 1 RO I Number ot WAIT S W u f ". . .. -

O

O

O

1

, I

jl

Active between Locstlona

" PBA - P E A C 127 PBA t 1 2 W B A + 255 PBA+ 256-PBA+ 383

PBA t 512"PBA+ 639 PEA + 646"PBA + 767 PBA f 760-PBA + 895

PBA -1- 384"PBA + 51 1 Table 13. DUA Control Block Format

f I Register Name

The mode 01 operationot the penpheral chip s e l e c t s IS deílned by the MPCS register (which is also used to s e t the sue 01 the mid-range memory chip-select block. sea Figure 13). The registor is l o c a t e d at oftset A8H in the Interna! conlrol block. Bit 7 is used 10 seiect the lunctlon of P335 and Pm, while blt 6 IS used to select whether the peripheral chip seleCtS are mapped Into memory or 110 space. Table 11 describes the programmtng 01 these hts. Alter RE- SET, the contents of both the MPCS and t h e PA= r tqsters are undefined. however none Of the lmes wJi tx, acWo unti! both of the MPCS and PACS regsters are accessed.

Table 11. MS. EX Programming ValWS

Deacrlplion

into memory space. O = Penpherals mapped Into I10 space.

1 = 7 ltnes. Al, A2 are not prov~ded. ¡ EX O = 5 m I~nes. Al, A2 provided.

MPCS blts 0-2 specity UW READY mode for m- m 6 as outllned below.

The internal REAOY generator operater, In parallel mth external READY, n o t in 88rI6s if the externa) READY is used (R2 = O). For exampk, it the internal generator IS s e t to insert two wait states. but acbvrty on the external REAOY lines will betl IOU wait states, the processor will oniy insert four wai( states, n o t YX. Ths IS because the two wait states genetated by the internal generator OvWkpPfjd lhe fvst two wait states generated by the extemal readv signal. Note that the external ARDY and SADY lines are always ignored durtng cycles accessing i n t d peripherals.

R2-RO of each control word specifies the READY mode lor the corresponding block. with the excw 60n of the rlpheral chip selects: R2-RO of PAG s e t the &-3 READY mode. R2-RO of MPCS set the w - 6 READY mode.

Chip Select/Ready Logic and Reset lnl Upon RESET. the ChipSelectlReady will perform the following actions:

All chip-select outputs will be driven HIGH. Upon leavlng RESET, the m line will be VU grammed to provtde chip selects lo a 1K M@ mth the accompanylng READY control bits set d O1 1 to insert 3 wait states in conjunction with eP terna1 READY (1% UMCS resets to FFFBH).

0 No other chip select or READY control r e g s 1 6 have any predefined values alter RESET. They will not become actlve until the CPU accesses thelr control reglsters. Both the PACS and M@ registers must be accessed before the I@ w11l become acttve.

READY Generation Logic The 80188 can generate a READY ?.¡=al internally tor each of the memory or peripheral CS lines. The number oí WAIT states lo be inserted lor each perlpheral or memory is programmable to provide 0-3 wall states for all accesses to the area lor which the chlp select is active. In addition. the 80188 may be programmed to elther ignore-external READY for each chlpselect range lndlvldually or lo factor external READY with the Integrated ready generator.

READY control conslsts of 3 bits lor each m line or group oí llnes generated by the 80188. The interpre- latcon oí !he READY blts IS shown in Table 12.

2107W-S c

Figuro 16. DUA Unlt Block Diagram

I 15 14 13 12 11 10 9 8 7

c J Figure 17. M I A Control Register

1-179

"

1-178

h 1

80 188

DMA Channel Control Word Register

Each DMA Channel Control Word delermlnes the mode of oparatron for the partlcular 80188 C" channel. This reglster spealies: O tha mode of synchronizatlsn; O whether interrupts w~ll be generated after the last

transfer; O whether DMA activity will cease after a prC-

grammed number of DMA cycles; the ralatlve prlority o1 the DMA channel ,with respect to the other DMA channel; whether the *ource polnicr WI!! be incrementsd, decremented, or malntained constant after each transfer;

O whether the source pointer addresses memory or I/O space;

O whether Ihe deslinalion pointer will be increment- ed, dacremuntcd. or malntatned constant afler each t:anslor; 3nd

whether tha destina!ton polnter will address memor/ or 110 space.

Tho DMA channel control reglsters may be changed whlle the channel IS operaung. However. any changes mad9 durlng operatton wlll aflect the current DMA transfer.

BMA Control Word Bit Descriptions DEST: M/D Destlnatlon pocnter is in

memory (1) or I lO (O) space. DEC Decrement des;ination point-

er by 1 after each transfer. INC Increment destlnatlon point-

er by 1 after each transfer. If both INC and DEC are speclfted. the polnter m11 not be changed after each cycle.

SOURCE. M / W Source polnter is In memory (1) or 110 (O) space.

DEC Decrement source pointer by 1 aller each transfer.

INC Increment source polnter by 1 after each transfer. I t both INC and DEC are specifled. the pointer will not be changed after each cycle

TC:

INT

SYN:

P:

TDAQ:

CHG/NOCHG:

ST / W P :

It set. DMA will terminate when

count reyster reach zero. The the contents of the transfer

S T / S ~ ~ P bit WIII atso be reset at thls polnt. If cleared, lhe DMA controiler will decrement the transfer count register f o r each DMA cycle, but DMA transfers will not stop when the lrMSfeC coirnt reglster reaches zero. Enable intempts to CPU upon transfer cwnt tefrfIiMtion. 00 No synchronization.

NOTE: When unsynchronued transfers are spclfted. the TC bil wll be ignored and the ST bit mll be cleared upon Me transfer CWnt reaching zero, stopping me channel. 01 Source Synchronization. 10 Destlnauon Synchronization.

11 Unused. Channel priority relative to other channei during simultaneous r e quests. O Low priority. 1 High priority. Channels wdl alternate Cycles if both are set at the same pnonty level. EnablelDisaMe (110) DMA re quests from Tlmer 2. ChangeIDo Not Change (110) the S T / m P bit. If this bit is Set when wntg-the control word, the ST/STOP bit wll be prC- grammed by the write to the Con- trol word. If this bit is cleared when wrltlnq the control word the ST/SWP blt will not be ak tered. Thls btt IS not stored; it wl always be read as O. Startlstop (110) Channel.

1.180

."

80 168

DMA Destination and Source Pointer Register8 Each DMA channel manlams a 20-bit source and a 20" destination pointer. Each 01 these potnters takes up hvo full 1 6 " reg~sters in the peripheral control W. The lower four bits of the upper register contain Me upper four bits of the 20-bit physical

v i d u a l i y i n a e m s n t e d of decremented after each address { s e e F i e 18). These poin!crs may be indi-

or I10 space. Snce Me DMA channels can perform transfer. Each pointer may point into either memory

transfers to or from odd addresses, there is no re striction on values for the pc;n:er reglsters.

DMA l'ransfer Count Register

Each DMA channel maintains a 16-bit transfer Cwnt

ery DMA cyde. regardless of the state of tha TC bit register CyC). The register is decremented after ev-

in ihe DMA Control Register. If the TC blt in the DMA control word is set or if unsynchronlzed transfers are programmed, DMA activity will termmate when the transfer Cwnt register reaches zero.

DMA Requests

Data transfers may be either source or destination synchronized. that is either the source of the data or the destination of the data may request the data transfer. In addition, DMA transfers may be unsyn-

chronized; that is. the transfer mll take place contin-

curred. When source or unsynchronaed transfers ually until the correct number of transfers has oc-

are performed. the DMA channel may begm another transler mnediately after the end of a pevious DMA transfer. Thts a W s a complete transfer IO take place every 2 bus cycles of q h t c lock cycles (assuming no wait states). When destination syn-

fetched from the soulc~ address until the desana. chronzed transfers are performed. data will not be

tion devlce slgnals t h a t it is ready to recerve it. A l s o . the DMA controller wdl relinquish control of the bus after every transfer. If M other bus activity is inmat- e d , another desttnatlon synchronaed DMA cycle w i l l begin after two processor clocks. This allows the destination device Dme to remove its request if another transfer is not desired. Svwxt the DMA m o l - ler will relinquish the bus. Me CPU can initiate a bus cycle. As a result. a complete bus cycle will often be inserted between destinaton synchronized transfers. Table 14 shows the mawimum DMA transfer rates.

Table 14. Maximum DMA Tranater Rates @ CMOUT = 8 U&

T Y P of SynchronhUon CPU Hatted CPU Runn~ng

Unwnchronized 1.0 MBytes/sec

0.80 MB!ltes/sec 0.67 MByteslsec Destination Synch 1.0 MBytes/sec 1.0 MBy(es/~ec S W h 1.0 MBytestsec

!jOlected

REGISTER HIGHER

m E S S LOWER

REGISTER ADORES

I

xxx A18416 xxx xxx

A 1 5 4 1 2 "M A 7 - M All-AB

15 O

xxx - Don'lcu0

Figure 18. DMA Pointer Reglater Format ~ J

1-181

DMA Acknowledge

No expllctt DMA acknowledge pulse IS provided. Since both source and desttnarm pmnters are

wrlte lo a requesttng desttnalion. should be used as malntatned, a read lrom a requesttng source, or a

the DMA acknowledge signal. Since the chipselea lines can be programmed lo b activo tor a w e n block of memory or 110 space, and the DMA pointers can be programmed to point to the same given block, a chlpselect llne could be ysed to indicate a DMA acknowledge.

aro programmed. a DRQ must also be V a t e d Therelore, tho source and destination transfer pointers, and the transtor count re tster (If used) must be programmed batore me ~ T ; & o B txt 19 set

Each DMA reglstor may be m o d i f i e d whde the C M ne1 IS opcratmg. If the C H G / N m M is &¿Ved when the cnntrcI reg~srer IS wrlnen, the S T / m bit 01 the control regtster WII~ n o t be Wied by the wnte. If multlple channel reglslers are IWdIf ied. it is recommended that a LOCKED stMg tranSfW be usad to prevent a DMA transfer from Occurring between s@a:as to tho c!idr.neI rogistcus.

DMA Priority

The DMA channels may be programmed to glve one channel prtorlty over the other. or they may be programmed to alternate cycles when both have DMA requests pendlng. DMA cycles always have prionv over Internal CPU cycles except between locked memory accesses or word accesses to odd memory

over an internal DMA cycle. Because an interrupt locations; also, an external bus hold takes priortty

request cannot suspend a DMA operation and the CP9 cannot access memory durtng a DMA cycie.

continuous DMA C~C~QS . An NMI request, however. Interrupt latency time w11I suffer durtng sequences 01

w l l cause all Internal DMA acbvtty to hall. This allows the CPU to qulckly respond to the NMI request

DMA Programming

DMA cycles wtll occur whenever the S T / W bit of the Control Reglster IS set . If synchrontzed transfers

DMA Channels and Reset

Upon RESET. the DMA channels mll perform the foliowtng acbons:

The ST/sfbP bit lor each channel will be r-1

Any transfer tn progress is aborted. to STOP.

TIMERS The 80188 provldes three internal 16-bit programmable tlmers (see Figure 19). Two ot these B T ~ high- ly llextble and are connected to t a u extemal pins (2 per timer). They can be used lo Count external events. tlme external events, generate n~mepem waveforms. etc. The thlrd trmer is no t Connected IO any external ptns, and IS useful lor real-time m and tlme delay appllcations. In addtlnn. the third tint er can be used as a prescaler to Ule other two. or 89 a DMA request source.

210706-10

Figure 19. Tlmer Block Diagram

1-lM2 ‘*

80108 i

Timer Operation The bmers are controlled by 11 16” rqsters n the. peripheral contrd block. The confgwatm of these registers is shown in Table 15. The count r e g -

read or written at any time independent of whether ister cocltains the current value of the timer. It can be

will be iroemented f o r each timar event Each of the tha timer is mng or not. The value of this register

timers is equipped with a MAX COUNT re(ystw.

reach. Afler reaching the MAX COUNT regtster val- which defines the maximum cwnt t h e timer WIII

ue, the bra count vaiuu mil reset to zero dwing that same dock. ;.e.. the matmum count value is nwer stored in t h e Munl register ttsetf. Timen O and 1 are. in addition. equipped mth a “J MAX COUNT register. which enables thrr timers to alter-

vatuea if a sh@e MAX COUNT regstet ie used. the nata them courd between two different MAX COUNT

timer outpul pin will switch LOW for a single dock. 2 ck&s after the maamum count vafue has been reached. In the dual MAX COUNT reQisler mode. the wlput pin dl indicate whch MAX COUNT register is currently in use. Vws allowtng complete fwdom in selecong waveform duty cycles. For (he

the Control re(j¡ster determines which is used for the timers with WO MAX COUNT registers. the AIU bit in

Stnco the cwnt regtsters and the m m m count

provided. Any Read or Wnte access to the Limers WIII registers are all 16 &S mdo. 16 bts of resoiumn are

cyclo. h o w e v e r . Thts IS needed to SynChrMlae and add one wat state M (he mum fwcbdc bus

coorchnate the internal data flows between the internal bmers and the nteml bus.

The timers have several programmable options.

All t h r e e bmers can be set to halt OT continus on a terminal a n t . Timers O and 1 can s e l e c t between internal and extemal clocks, alternate between MAX COUNT registers and be s e t to retneger on external events. The timers may be programmed -._ .. to cause an In- terrupt on termlnal W t .

contrd word. These options are selectable via the timer mode/

Timer Mode/Control Reglster The moddcontrd register (see Fmre 20) illlows

or check the current programmed status for any of the usar lo program the spedfIc mode of operanon

the three integrated timers. Table 15. TInm Control Block Fonnat

Register Name Register Offret Tmr. O Tmr. 1 Tm. 2 .

Max Count B Max Count A Count Regstet

Figure 20. Tbmr ModdContrd Register “J

II I*

EN

Tne enable bit provldes programmer control over

eriablod to lncrement subject lo the Input pin con- tt,e tmer's RUN/HALT status. When set. the me r IS

slralnts In the lnternal clock mode (discussed prw- o~sly). When cleared, the tlmer WIII be Inhlbted from countmg. All Input pan transltlons durlng the llme EN IS zero WIII be ignored. I1 CONT 13 zero, the EN bit IS automatically.cleared upon maxlmum count.

INH

The inhlbll blt allows lor selective updatlng of the enable (EN) b!!. !f INH IS a one du rq the wr!!e to the mode/control würd. th6n Ihe-gate of tho EN bit wdl bo modllled by the write. I1 INH IS a zero during the w m . the EN blt 1111 be unaffected by the operatton. Thls blt IS not stored; It wlll always be a O on a read.

INT

'Nhen set, the INT blt enables interrupts lrom the timor, whlch wlll be generated on every terminal cocnt I f !he llrner IS conllgured IC dual MAX COUNT ragster mode, an Intetrupl wlll b~ generated each tlme the value In MAX COUNT register A is reached, and each tlme the value in MAX COUNT register B is reached I 1 thls enable bit IS cleared afler the interrupt request has been generated, but before a pnd- lng Interrupt IS serviced, the Interrupt request will still be In lorce. (The request is latched in the Interrupt Controller.)

RIU

The Reglster In Use bll lndlcates which MAX COUNT reglster IS currently belng used lor compari-

reglster A. The RIU bit cannot be written, ¡.e., Its son to the llmer count value. A zero value indicates

value IS not allected when the control register IS written It IS always cleared when the ALT blt is zero.

MC

reaches ~ t s llnal maxlmum count value. I1 the me r is The Maximum Count blt IS set whenever the tlmer

conllgured In dual MAX COUNT reglster mode, thts tiir will be set each time the value In MAX COUNT register A IS reached, and each tlme the value In MAX COUNT reylster B IS reached. Thls blt IS set reqardless of the tuner's Interrupt-enable blt. The. MI: blt glves the u 5 ~ the abtlliy to monltor timer SLIIUS through soltware Instead of through Inter- r l ipfs Programmer tnlervunllon IS requtred to clear 1111> bit

RTG

Retngger blt IS only active lor internal clocking (EXT 2 O). In thls case 1 1 determines the control luncllon provlded by the Input pln.

If RTG =- O, the Input levol gates the internel clock on and off. I1 the Input ptn IS HIGH, t h e timer will Count; 1 the Input pin IS LOW. the timer will hold its value. As indtcated provlously. the input signal m y be asynchronous wlth respoct to the 80188 Cl&.

When RTG = 1, tho Input pln detects LOW-to-HIGH transitions. The llrst such transition starts the timer running, clearing the tmer value lo zero on lhe first clock, and then 1ncrement;ng thereafter. Further transltrons on the input pln wlll again reset t h e timer to zero, from whtch It WIII start counting up agam. ¡I CONT = O. whon the timer has reached maximum count. the EN blt will be cleared, inhibiting twther timer activity.

P

The prescaler bit IS ignored unless internal clocking has been selected (EXT - O). If the P bit is a zero, the tlmer will count at one-fourth the internal CPU clock rate. I 1 the P blt is a one. the output of timer 2 w11I be used as a clock lor the timer. Note that the user must Initialize and start timer 2 to obtain the prescaled clock.

EXT

The external bit selects between internal and external clocktng for the timer. The external signal may be asynchronous wlth respect to the 80188 clock. I 1 this bit is set. the timer will count LOW-tdiIGH transitlons on the input pin. If cleared, it will count an lnternal clock whlle uslng the input pin lor control. In this mode, the functlon of the extemal pin is defined by the RTG blt. The maximum input lo output tram sttion latency time may be as much as 6 clocks.

together as every 4 clocks without losing dock pul9 However, clock inputs may be plpelmed as closely

es.

ALT

The ALT blt determines whlch o1 two MAX COUNT registers is used lor count comparison. I1 ALT = O. reglster A lor that tlmer IS always used, whlle if ALT 2 1, the comparlson WIII alternate between reg lster A and reglster B when each maximum count is reached. Thls alternalton allows the user to change one MAX COUNT reglster whlle the other is belng used, and thus provldes a method o1 generating non-repetltlve waveforms. Square waves and pulse outputs o1 any duly cycle are a subset o1 available stgnals oblalned by no1 chanqlng Ihe llnal count P2g Istors. The ALT 011 albo delermlnes the lunctlon

1-184

- . .. - A

" 'G .. .

the timer output pin. If ALT is zero, the ourput pn mll go LOW lor one clock. t h e clock after the maxmum count is reached. I1 ALT 1s one, the output pin wdl reflect the w e n t MAX COUNT reglste; bemg used (0/1 f o r BIA).

CONT SetUng the CONT bit causes the associated timer to run continuously. while resetting it causes the timer to halt upon maximum count If CONT 2 O and ALT

1, the timer wiU count lo the MAX COUNT register A value, reset, cwnt lo the register B value, reset, and halt.

Not all mode bits are provided lor tlmer 2. Certain bits are hardwired as in0ica!ed below:

ALT = O. EXT 3 O. P = O. RTG = O. RIU = O

Count Registers Each of the three timers has a 16-bll count register. The contents of this register may be read or written by the processor at any time. I1 the register is Wntten while the omer is counting, the new value will take effect in the current count cycle.

Max Count Registers Timers O and 1 have two MAX COUNT registers. while timer 2 has a single MAX COUNT register. These contain the number o1 events the timer wil l count In timers O and 1. the MAX COUNT register used can alternate between the two max count values whenever the current maximum count is reached. A timer resets when the timer count register equals the max count value being used. I1 the timer count register or the max count register is Changed 50 that the max count is less than the timer Count, the timer does not immediately reset Instead. the timer counts up to OFFFFH. "wraps around" to zero. counts up to the max count value, and then resets.

Timers and Reset

actions: Upon RESET, the Timers wlll perform the following

All EN (Enable) bits are reset preventing timer Counting. For Timers O and 1, the FilU blts are reset lo zero and the ALT blts are set to one. This results In the Tlmer Out pins going HIGH.

INTERRUPT CONTROLLER The 80188 can receive nterrupts lrom a number Of sources, both Internal and external. The internal In- terrupt controller serves to merge these requests On a prlonly basts. lor indwidual service by t h e CPU.

Internal Interrupt sources (Timers and DMA chat" nels) can be disabled by theu own control registers or by mask b!ts within the Interrupt controller. The 80188 interrupt controller has its own control reglster that sets the mode of operalion lor the controller.

The interrupt controller wil l resolve pnority among requests that are pendmg simullaneously. Nesllng is provided so interrupt servce rwhnes f o r lower priok ty interrupts may be interrupted by higher priority interrupts. A block diagram of the interrupt controller is shown in Figure 2 l .

The 80188 has a special Slave Mode in which the internal interrupt controller acts as a slave to an external master. The controller is programmed Into this mode by setting bt 14 in t h e peripheral control block relocation reglster. (See Slave Mode section.)

MASTER MODE OPERATION

Interrupt Controller External Interface

One of these pins is NMI. the non-maskable inter- Five pins are provided lor extemal Interrupt .sources.

rupt NMI is generally used for unusual eve& such as power-la1 Interrupts. The other four pins may be configured in any of the I o l h n g ways:

As lour interrupt Input tines with internalb generated interrupt vectors. As an intermpt line and interrupt ackrkmledge

ed interrupt vectors plus two interrupt iryut lines line pair (Cascade Mode) with externally generat-

with internally generated vectors. As two pairs of intenupt/intefrupl acknmiedge llnes (Cascade Mode) mth externally generated interrupt vectors.

External sources in the Cascade Mode use c xternal- ly generated nterrupttors . When an intorrupl IS acknowledged. two INTA cycles are initiated and the vector is read into the 80188 on the second cycle. The capabdity to interface lo external 8253A programmable interrupt controllers is provided when the Inputs are configured in Cascade Mode.

1-185

80188

Interrupt Controller Modes of Operation

The bauc modes of operatton of the Interrupt controller In Master Mode are slmlar to t he 8259A. The Interrupt controller responds ldenltcally to internal interrupts In all three modes: the difference IS only VI the lnterpretatlon of function of the fwr external in-

these three modes by programmng t h e correct bits terrupt pins. The Interrupt controller is set into one of

In the INTO and INTl control registers. The modes of Interrupt controller operabon are as follows:

FULLY NESTED MODE

When in the fully nested mode four pins aro used as direct Interrupt requests as in Figure 22. The vectors

serv~e brt IS prended lor every Interrupt source. If a for these lour inputs are generated internally. An in-

lower-priority devlce requests an interrupt while the In-service bit (IS) is s e t , no interrupt will be generat- ea by Ihe lnlerrupt controller. In addttm, if another Interrupt request. occurs from the same interrupt source whlle the fn-semm blt is set. no interrupt w~ll be generated by the interrupt controller. This allows interrupt servlce routines to operate with interrupts enabled. yet be suspended only by interrupts of hrgher prlority than the In-service interrupt.

When a servlce roubne is completed, the proper IS bit must be reset by writing the proper panern lo the €01 register. This IS requlred to allow subsequent Interrupts from this interrupt source and lo allow servicing of lower-prionty interrupts. An E01 com-

I 210706-11

Figure 21. Interrupt Controller Block Dlagram

mana IS exccuttxi al the end of the bervice r w t i n e lust b l o w tho return !rom mterrupt tnstrucbun. I1 the frilly nested slruciura has boon upheld. the nexl highest-prlorlly source wth its IS bl set is then m- ced.

CASCADE MODE

The 80159 ha; !our in?empt pns art hM of them have dual functlons. In the fully n e s t e d mode Ihe f o u r pns are used as direct Interrupt mputs and MB conespondrng vectors are generated internally. In t h e Cascada Mode, the four pns are coofigured into Ir\lsrrupl mplli-rrrdlcated acknowl&Je s g n a l pairs. T n e lnterconncctlon IS shown In Fgure 23. INTO 18 En interyt wyv! In!erfaced to an 8259A. while INT2liNTAO serves as the dedlcated Ultmpl a e knowledge slgnal lo tha!.p-nphefal. The same is

tively be placed In t h e Cascade Mode by program- true fur INTI and INT3/1NTAl. Each pair can selec-

ming the proper value into INTO and INTI control registers. The use of the dedmted acknowledge srgnals eliminates-lhg-need for the use of extemal logic lo generate INTA and device select ugnals.

The primary Cascade Mode allows the capab~llty to sowe up to 128 external interrupt sources through the use of external master and dave 8259As. Three levels of prlorlty are ueated, reqocring prbfity re sdu - bon In the 80188 Interrupt controller. the master 8259As. and the slave 8259As. If an extemal interrupt is serviced. one IS bit is set at each 01 these levels. When the tnlermpt service routine is completed, up lo three end-of-interrupt commands must be issued by the programmer.

SPECIAL FULLY NESTED MODE

This mode is entered by setting the SFNM bit in INTO or INTI control register. I t enables complete nestability wth external 8259A masters. NcmalIy. an interrupt request lrom an interrupt source will not be recognized unless the in-service bit f o r that source IS reset. If mofe than one intermpt sour- is connected to an external interrupt controller. all of the interrupts w~l l be funneled through the same 80188 interrupt request pln. As a result. ¡I the external interrupt controller receives a hgher-priority in-

80188 controller until the 80188 in-service bt is re tempt, its Interrupt wll not be recogruzed by the

set. In Special Fully Nested Mode. the 80188 interrupt controller w11I allow interrupts from an e x t d pm regardless of the state of the in-service bit for Interrupt source In order to allow multiple Interrupts from a slngle pin. An In-service blt wrll cOnt!nue lo be set. however, to inhlblt Interrupts lrom other lowe priority 80188 interrupt sources.

1-186

spsccal procedures should be lollawed when r-I- m IS bts at the end of Interrupt seivtce rwtlnes. ~~f tware polling of the IS reglster In t h e external

mQe than one bt set. If s o . the IS brt m the 8 0 1 8 8 master 8259A IS requued lo de!ermrra if there IS

r m - m v e and the next lnterrupt seMce rwbne Is entered

Operation in a Polled Environment The cootroller may be used in a polled r%Je ¡I interrupts are undesirable. When polllng, t h e processof &sables Interrupts and then polls t h e mterrupt CM-

controller is accomplished by readrng the POn Word mler w m e r II IS convenient. Pollmg the lnterntpt

(Figore 32). Bit 15 In the poll word mdtcales lo the processor that an interrupt of hgh enough pioclty is requesting servlce. 8ils 0-4 indicate to the preces- go^ the type vector of the hghest-pmrty BOW- re questq service. Rea&ng the Poll Word causes the In-Service bit of the hghest pmly source to be set

It is desirable to be able to read t h e Pdl Word information without guaranlmng servm of any pend~ng interrupt. ¡.e.. not set the indicated in-service b L The 801 88 provides a Poll Status Word m addttmn lo t h e mentional Poll Word to allow Uus lo be done. Poll Word information is duplicated in t h e Poll Status Word. bul reading the Poll Status Word does not set lhe a s s o d a t e d in-service biL These words are located in hvo adjacent memory locakns In the regster fie.

IN13 F-' INTERRUPI SOUlKI

210706-28

Fbm 22. Fully Nested (Direct) M o d e Interrupt Controller Connections

L

Master Mode Features

PROGRAMMABLE PRlORtTY

The user can program the Interrupt sources into any 01 elght dllferent pnority levels. The programming is done by placlng a 3-bl prionty level (0-7) in t h e control rqster of each interrupt source. (A w c e with a prwlty level o1 4 has hgher pmty mer a l l prior~ty levels from 5 to 7. Priority reglsters containing values lower than 4 have greater prionty). All interrupt sources have prepogrammed default pfiorlty leve!s ( s e e Table 4).

I f two requests wllh the same programmed priorlty level are pending al once. the priority ordering scheme shown In Table 4 is usad. If t h e serviced Interrupt routine reenables Interrupts. other interrupt requests can be servlced. .

END-OF-INTERRUPT COMMAND

programmer lo reset the In-Servce (IS) bit when an The end-of-Interrupt (EOI) command is used by the

interrupt service rwtlne is completed. The EO1 command is lssued by wrltlng the proper pattern to the €01 regrster. There are two types of EO1 commands, speclflc and nonspeclfc. The nonspeafic command does not spectfy which IS brt is reset. When issued, t h e interrupt controller automatically resets the IS bit of the htghest prlority source with an active service routme. A speclfic EO1 command requires that the programmer send the interrupt vector type lo lhe interrupt controller rndicabng which source's IS bit is to be reset. Thus command IS used when the fully nested structure has been disturtmd or the hghest p m t y IS blt that was set does not belong to the secvlce routine in progress.

TRIGGER MODE

The f o u r external interrupt pins can be programmed in either edge- or level-tngger W. The ;ontrol register lor each external source has a level W i e r mode (LTM) bt. All interrupt in* are active HIGH. In the edge sense mode or the level-tngger mode, the interrupt request must r e m n active (HIGA) untll the interrupt request is acknowledged by the 801 88 CPU. In the edge-sense mode, il the Level remains hgh after the lnterrupt is acknowledged. the :nplt IS dtsaMed and no further requests will be generated The input level must go LOW f o r at least one d. :k cycle to re-enable the Input. In the level-trigger mode, no such provlvon is made: holding the interrupt Input HIGH WIII cause continuous interrupt re- guests.

1-187

‘W 80188 ”_

INTERRUPT VECTORING

The 80188 lnterrupl Controller wlll generate Interrupt voclors lor the Integrated DMA Channels and the In- tegrated Tlmers. In addltlon. the Interrupt Controller WI!~ generale Interrupt vectors for the external Inter- rupt llnes If they are not configured in Cascade or Special Fully Nested Modes. The Interrupt vectors generated are fixed and cannot be changed (w Ta- ble 4).

Interrupt Controller Registers

Tho Interrupt Contro!lcr reqster model 1s shewn II!

Flgure 24. It contams 15 reglsters. All registers can bath bc read or writ:en unloss spezifled othcnvlso.

IN-SERVICE REGISTER

Thts reglster can be read from or wnnen into. The format is shown In Flgure 25. It contains the In-Serv- Ice blt lor each ÚI tie Interrupt sources. The In-Serv- ice bit IS set lo Indicate that a source’s service rou- tlnc is in progress. When an In-Service bit is s e t . the Interrupt controller wlll not generate Interrupts to the CPU when 11 recelves Interrupt requests from devlc- es wcth a lower programmed priority level. The TMR blt IS the In-Servce bit for all lhree timers; the DO and Dl blts are the In-Servce bits for the two DMA channels; the 10-13 are the In-Servce bits for the external interrupt pins. The IS bit IS set when the processor acknowledges an interrupt request either by an Interrupt acknowledge or by reading the poll reycster. The IS bit IS reset at the end of the interrupt service routlne by an end-of-Interrupt command.

INTERRUPT REQUEST REGISTER

The Internal Interrupt sources have Interrupt requesl bts Inside the ~nlerrupl controller. The lormat of tha regls!cr IS shown In F!gure 25. A read hom Vus regis ter ylelds the status of these bits. The TMR bit is the loglcal OR of all tlmer Interrupt requests. W and DI are the Interrupt request bits for the DMA channels.

The stale 01 the external lnlerrupt input pies is ala Indicated. The state of the external intemrpt pins I n o t a stored condition inside the interrupt controller, therefore the external interrupt bits cannot be writ. ten. The external interrupt request bits are set wher an interrupt request IS given lo the interrupt control ler, M 11 edge-trlggered mode is selected, the bit ir lhe registar wiil be HIGH only after an inactivsto-ac tive transition. For internal interrupt sources, the reg ister bits are s e t when a request anives and are re set when the processor acknowledges the requests

Writes to lo the interrupt request register will affec the W and Dl Interrupt request bits. Setting eithe b ~ t will cause the corresponding intmqt requas whlle clearlng ellher bit will r e m e t he correspond ing Interrupt request. All other bits In the register ELI1 read-only.

MASK REGISTER

This is a 16-bit register that contains a mask bit f0 each interrupt source. The format for this reglster shown in Figure 25. A one in a bit position corra spondlng lo a particular source masks the SOurCc from generatlng Interrupts. These mask bits are trU exact sama blts whch are used in the individual con trol reglsters; programming a mask bit using th mask reglster wlll also change this bit In the indivldu al control reglsters, and vlce versa.

-

I I- INTERRUPT SOURCES

.

. -

INIERRUPT SOURCES 210706-12

! . . ~ ~~” ~ ~. ~” ~. ~. ~ ~ - _ _ _ - Figure 23. Cascade and Special Fully Nested Mode Interrupt Controller COntTeCtionS

1-188

INT3 COEtTRCL REGISTER

IN12 M N T R O L FiEGlSTEH

INTl CONTROL REGISTER

W 1 CONTROL HEGISltH

TIMER CONTROL REGISTER ~ . . _ I _ ” -

IN-SERVICE REGISTER

PRlORflY REGISTER

W S K REGISTER

POLL STATUS REGISTER

POLL REGffiTER

t01 REGISTER

Figure 24. Interrupt Controller Registers (Master Mode)

PRIORITY MASK REGISTER

Thts regrster masks all interrupts below a parttcular Interrupt priority level. The format of VIIS register is shown In Flgure 26. The code In t h e bwer three bits

higher prlonty number) than U” code spectfied. For of thls register inhtblts interrupts of priority lower (a

example, 100 minen into this reglster masks Inter- rupts of level five (101). six (110). and seven (111). The reglster is reset to seven (1 11) upon RESET so no Interrupts are masked due to priority number.

INTERRUPT STATUS REGISTER

This register contains (jensral interrupt COnt iOlh status informatmn. The format of this regster is shown in Figure 27. The bits in the status r6gister have the follmng funcbons: DHLT: DMA Halt Transfer; setting this bit halts all

DMA transfers. It is automatically set whenever a non-maskable interrupt occurs. and it is reset when an IRET instruction is executed. This bit allows prompt service of all non- maskable interrupts. This bit may also be set by the programmer.

IRTx: These three bits represent the individual timer interrupt request bits. These bits differen- bate between bmer interrupts, since the timer IR bit in the interrupt request register is the “OR” function of all timer interrupt r s quests. Note that semng any one of these three h t s initiates an interrupt request lo the interrupt controller.

~~~ ~

Figure 25. In-Service, lntmupt Request, and Mask Register Formats

1

- Figwe 26. Priority Mask Register Format

TIMER, DMA O. 1; CONTROL REGISTERS

Tnase reg~sters are the control words for al¡ the ID- tarnal Interrupt sources. The format for these mgls- trjrs IS shown in Flgure 28. The three b i t posltlons PRO, PRl, and PR2 represent the programmable prl- or8I-y level of the Interrupt source. The MSK bt tnhib- its Interrupt requests from the interrupt source. The MSK blts in the indtvidual control registers are the exact same blts as are In the Mask Registot; modlhi- mg them In the indtvidual control reglslers WIII also modlly them In the Mask Reglster. and vtce versa.

INTO-INT3 CONTROL REGISTERS

These registers am tha con!rol wcrds !cr !ho fcur extarnal Input pms. Ftgure 29 shows the format Of the INTO and lNTl Control registers: Flqure 30 shows the format of the INT2 and INT3 Control reg- Istex. In Cascade Mode or Specgal Fully Nested Mode, the control words f o r INT2 and INT3 are not used.

The btts In tho varmcns control registors are encoded as foilows: 2RC)-2 Prtortty programming Informalton. Highest

priority = 000, lowest prlorlty 2 11 l . LTM: Level-tngger mode M . 1 -= level-trtg-

gered; O = edge-tnggered. lntenupt InpUt levels are actwe h!gh Ir! level-trqgered mode, an Interrupt IS generated whenever the external llne IS hlgh. In edge-triggered mode, an Interrupt mll be generated only

€01 REGISTER

Tilt, mil o: ihd lr&;ra;: regstor IS a command r e g ter wncn can orliy bu wtttierl Into. The format of tcc: reyster 19 shown In Ftgure 31. I1 hbtates M EO commana when wntten lo by the 80188 CPU.

The bt:s In the €01 register are Oncodod as follow S,: Encodcd lnformation that @@S an ir

tcrrupt source vector lype as shown I Table 4. For example, to reset the Ir Service bd for DMA cham01 O, these M should De set to 01010. Woce the V d type for DMA channel O is 10.

NOTE: To reset :he single In-Service bit l o r my Of three trrners. tho vector type f o r ltw 0 (8) shall be wntten tn this rogtster. NSPEC/: A ixt that determines the tvpe of €01 COO SPEC rnand. Nonspecilic = 1, SWUfC = o.

Figure 28. Tlmer/DMA Control Register Formats #

15 14 7 6 5 4 3 2 1 e 1 o I o I i o (SFNM; c I L : M [ M S K I P R ~ I ~ ~ ! P R O ]

Figure 29. INTO/INTl Control Register Formats -

I

15 14 5 4 3 2 1 0 1 0 I 0 1 . . . . 1 o ) L T M I M S K I P A ~ [ P R ~ I P A O

Figure 30. INT2/INT3 Control Register Formats

/

1.190

. .. A

POLL AND POLL STATUS REGISTERS

These regcsten contain polling :n!crmatron. The f o r - mat of U- registefs is shown In Flgure 32. They can or3y be read. Readrng the Poll regeter mlt- Mes a Sohare poU. This will set the IS bit 01 the h@=I pronty penchng interrupt. Reading the poll status register will n o t s e t the IS M of the highest

kltemupts w be provided piority pmdmg intermpt; only the status of peodine

as follows: Encoding of t h e Poll and Poll Status regtster bits are

&: Encoded tnlonnatlcn that indlcatos tha

Wtng s o u r c e . Valid oniy when INTREQ v e c t ~ typo of tho h:ghest prrority inter-

= l . . INTREO Tius bt determines 11 an interrupt request

is present. Interrupt Request = 1; no I+ lenupt Request = O.

SLAVE MODE OPERATION When Slave Mode is used, the internal 80isS interrupt controller will be used as a slave controller lo an external master interrupt controller. The mtemal 80188 r e s o u r c e s wll be monitored by the internal

Interrupt u)ntro:ler. while the extemal contrdler funclms as the system mast@ intenupt controller. Upon reset. the 80188 wll be in Master Mode. To pwrde f o r slave mode operatum btt 14 of the relo- ca lm regtsler should be set

Because of pin IlnrrtatiOM caused by the need to interlaca to an external 8259A master. the mmal interrupt contrdler will no longer accept extemal in-

controller inputs (IntemalC) to dedicate one to each puts. There a:e however. eoouph €0188 intempt

its Own mask bit IS bit, and control word. timer. In ths m o d e , each timer lntermpt w c e has

In Slave Mode each penpheral must be assigned a

operation. Therefore. 11 1s the kbgrammer's respon- uruque priority to ensure proper interrupt controller

slbility to asslgn correct priorities and initialitre interrupt control regisers belcre enable intenupts.

Slave Mode External Interface

The configuration of t h e 80188 unth respect to an eaernal 8259A master is shown io Figure 33. Tha INTO (pin 45) Input is used as the 80188 CPu interrupt input. I R 0 (pin 41) tunctions as an wtput to send the 801 88 slave-mtenupt-request to one of h 8 master-PICt~ts.

I

Figure 31. EO1 Register Format J

I

Figure 32. Po4 and POW Status RogisterFormat 1

! 1-191

t "_ "

80 188

,_ ""

i

210756-13

L" "_ i

Figure 33. Slave Mode Interrupt Controller Connections

Interrupt Nesting

Slave Mode operation allows nesting of interrupt requests. When an Interrupt IS acknowledged. the prionty loglc masks OH all priority levels except those with equal or hlgher prlorlty.

Vector Generation in the Slave Mode

Vector generation in Slave Mode is exactly llke that of an 8 2 5 9 ~ or 82C59A slave. The Interrupt controller generates an &bit vector type number which the CPU multlpltes by four to use as an address into the vector table. The five most slgnltlcant bits Of this type number are user-programmable whlle the three least slgntficant blls are deflned according 10 Figure 34 The slgnlflcant flve blts of the vector are Pro- grammed by wrltlng to the Interrupt Vector register at olfset 20H.

Specific End-of-Interrupt

Interrupt Controller Registers in the Slave Mode

All control and command reglsters are bCated lnsidc the internal peripheral control block. Figure 5 shows tha offsets of these registers.

END-OF-INTERRUPT REGISTER

The end-ot-Interrupt register is a command reglstc whlch can only be wntteri. The format of ths reg1St.f is shown In Flgure 35. 11 initlates an €01 comman when wrltten by the 80188 CPU.

The bits In the EO1 register are encoded as follow U,: Three least-signlflcant vector Vpe bits Con'

spondlng to the source for which the IS blt to be reset. Flgure 34 indicates these btS.

80 188 "__

IFCSERVICE REGISTER

Thfs reglster can be read trom or wrltien Into. I t contains t h e In-seWcce btl for each of the mtcrnal interrupt sources. The format f o r thts reglster IS shoNn In Figure 36. 611 pouUons 2 and 3 correspond to the

t h e integral tcmers. The source's IS bit IS wt when DMA Channels; powtlons O, 4. and 5 correspond to

t h e processor acknowladges tis lnlerrupt request.

INTERRUPT REQUEST REGISTER

Thus register indicates which internal pgrtpherals have interrupt requesrs pt.?dt:?g. The format 01 this regster is shown in Figuro 36. The Interrupt request bits are set when a request arnves from an internal source. and ara reset when the processor acknowledges the requesl. As in Masler Mode, M) and O1 are readlwrite, all other bits are read only.

MASK REGISTER

Thls register contains a mask blt for each interrupt source. The format for this reglster IS shown In Fig- ure 36. If the bit in thls reglster correspondmg to a particular Intwrrupt s o w e IS set. any mierrupts trom that source wdl be masked. Thesc mask blls are exactly the,.same blts whlch aro used In tho lndlvidual Control registers. ¡.e.. changing the state of a mask bit in this register w~ll also change the state of the

mrrespondmg lo the b t mask bit in the indlvldual interrupt control reglster

CONTROL REGISTERS

These registers are the control words for all the m- ternal interrupt sources. The format of these registers is shown in Figure 37. Each of the timers and both of the DMA channels have their own Control Reglster. - I

Tho btls of the Control Registers are encoded as foliows: pr,: 3-blt encoded fleld indicating a prior ty level

msk: mask bit for the priority level indicatal by pr, for Ute source.

bits. "

XH

MASK REGISTER 28H

SPECIFIC EO( REGISTER 22H

Flgure 34. Interrupt Controller Reglaters (Slave Mode)

1

L

Figure 35. Spaclflc €01 Reglater Format

(5 14 13 e r e 5 4 3 2 1 0 I o . I o I o I I o I o I o I T M R Z ~ T M R I ~ o1 I DO 1 o ~ T M R O ~

Figure 36. In-Service. Interrupt Request, and Ma8k Register Format - - "

'

1-192 I. 1-193

f %

80 188

INTERRUPT VECTOR REGISTER

rupt vector address. The format of thts register IS Thls register provides the upper llve bits of the inter-

p:ovtdes the lower three blts of the interrupt vector shown in Figure 38. The Interrupt controller itself

as delormined by the pnority level of the interrupt request.

The format of the bits In this register is: 1,. 5-blt lield indicating the upper five bits of the

vector address. I

PRIORITY-LEVEL MASK REGISTER

This rogtster ind~cates the lowest priority-level inter- rupl whtch will be serviced.

The encoding of the blts in this register is:

m,. 3-blt encoded field indication priority-level value. All lovais of lower prlority wll be masked.

INTERRUPT STATUS REGISTER

Tilts regtster IS defined as in Master Mode excepl that DHLT IS not Implemented. (See Figure 27).

Interrupt Controller and Reset Upon RESET. tne interrupt controller mll perlorn the followmy actions:

All SFNM btts reset to O, imptying Fully Nest& Mode. A l l PR bits in the various control registers s e t lo 1 Thls places all sources ai lowest prioritv (leve 1 1 1). All LTM bits reset lo O. resu l t ry in edge-sen% mode.

0 All 1ntc:rupt Sowice bits rese: to O. All Interrupt Request bits reset to O. All MSK (Interrupt Mask) blts set to 1 (mask). All C (Cascade) bits reset to O (non-cascade). All PRM (Priority Mask) bits set lo 1, implyIIIg N

lnitiallred to Master Mode. levels masked.

Flgure 37. Control Word Format

I i 15 14 13 8 7 6 5 1 3 2 1 0

[ o l o l o i . ~ ~ o ~ : ~ ~ D ~ u ~ u ~ ~ / o ~ o ~ o ]

Figure 38. Interrupt Vector Register Format

r--

t Flgure 39. Prlorlty Level Mask Register

80188

1-194

.

210706-14

Figure 40. Tvplul O188 Computer

1-195

. lntel r"

80188

I 16 Y*'

I Flgure 41. Typical 80188 MultCMarter Bu8 Interface

1-196

.. . -,

! 3

1-197

i

80 188

." .. _" . !

1-198

ou IOU

PIN TIMINGS (Continued)

A.C. CHARACTERISTICS = IPC to + 70°C. V w = 5V * 10%) (Contmued) 60188 Master Interface Tbnlng Rasponus rCononued) ,

TCLRO Reset Gelay 60 ns

- _ L w o s V Queue status Delay 35 IlS

TCHOX Stplus tidd Time 10 ns TAVCH Address Valid to 10 ns

L I I 80188 CLKIN Requlrmants

CLKIN Period 82.5 250 M ~ TCKHL CLKIN Fall Time 10 ns 3.5 to 1.ov - TCKLH CLKIN R ~ s e Ttme 10 ns 1 .o to 3.5v . CLKIN Lorv Time 25 ns 1.5v

L TC4iCK CLKIN Htgh Tlme 25 ns 1.5v

I I 80188 CLKIN Requlrmants

~ TCKHL

~- - "_ CLKIN Fall Time

.- l o ns 3.5 to 1.ov - TCKLH CLKIN R ~ s e Ttme 10 ns 1 .o to 3.5v

. CLKIN Lorv Time 25 ns 1.5v

L TC4iCK CLKIN Htgh Tlme 25 ns 1.5v

Explanation of the AC Symbols Each tlmtng symbol has trom 5 lo 7 characters. Tho 11:st character IS always a "T" (stands for erne). The other characlers. depending or? lhetr poslbOnS, stand for the name of a signal or the IOgiCal S W U S Of that slqnal. The lollowlng IS a l~st of ail the charac- tars and what they stand for. A. ARY

c. CK: cs: C T

D: DE: H: IN:

Address Asynchronous Ready Input Clock Output Clock Input Chtp Select

Control (DT/R. m. . . . ) Data lnpul om Logic Level Hlgh Input (DROO, TIMO, . . . )

L: Log~c Level Low M ALE o output 0% Queue Status ( W l , OS21 R: m Slgnai. RESET Signal S: Status (3, S T . 5 2 )

SRY: Synchronous Ready lnpul V: Valid W: WR Signal X: No Longer a Vahd Logic Level 2: Float

Examples: TCU- Tlme from Clock Low Io Address Valid TF- Tlrne from Clock High to ALE High Tucsv- Time from Clock Lov'j lo Chp v i

80188

WAVEFORMS

1-200

L

SOfTWARt' iALT-DT/R=Vw. I " "_ RD.WR.INTA.DfN:Vw x INVALID ADDRESS I

PTS, T C U V

TCLCSV

ucs TCXCSX

¡E. f - ucs (NOTE 3)

...

a0708 22 __ 1-201

c

fi I I

I I

I I

N O "! r

... . . . - . . " , .... " .... l"__.l .

OD z

P

1

8 ?-

.&

i

80188

WAVEFORMS (Continued)

1 'Imer On 80188

' ' I 210706-26

80188 EXPRESS The Intel EXPRESS system offers enhancements lo

processor. EXPRESS products are designed to the operational specil~cat~ons of the 80188 micrc-

mg rwrements exceed commercial standards. meet the needs of t h o s e applications whose operat-

The EXPRESS program includes the commercial standard temperature range wlth burn-in and an extended temperature range wlthout burn-in.

Wtth the commercial standard temperature range,

temperature range of O'C lo 70'C. Wlth the extend- operatronal character~strcs are guaranteed over the

ed temperature range optlon. operational character- I S ~ I C S are guaranteed over the range of -4o'C to t %'C.

The optlonal burn-In 1s dynamlc. for a mlnimum time 01 160 hours al 125'C wlth VCC - 5.5% k0.25'4, toltowmg gulaellnes In MIL-STO-883. Method 1015.

Package types and EXPRESS versions are identifie by a one or two-letter prefix to the part number. Th prefixes are listed in Table 16. All AC and DC speal cations not mentioned In this section are the sam for both commercial and EXPRESS parts.

Table 16. Preflx Identlflcatlon I

Prefix Package Temperature Type Range

Bum-In

I A I PGA I Commercial I NO

PGA Extended

NOTE No1 all packagellemperature range comlnnahs are ava able.

1-206

go188 EXECUTION TIMINGS

A d e t e r m i n a t i o n of 80188 program execution timing m r ~ t convder the bw cycles necessary to prefetch ~ t r ~ ~ t m s as well as the number of execution unit

@les 'z timings represent the minimum ex- to execute instructtons. The I&

lomw m m tima in clock cycles for each Instruction. The brmogs gwen are bad on the following assump m: b The opcode, along with any data or dIsplacemen1

required for execution of a particular instruction, has been prefetched and resides in the queue at the bme It IS needed. No wait states or bus HOLDS occur.

All instructtons whch mvo:va memory accBsJBs Can &so require one or two addrtmal clocks abme the mtnimum timings shown due to the a s y n c h r ~ w s handshake between the Bus lntertace Unit (81U) and execution unit

All jumps and calls cnclude the time required to fetch the -ode of the next inslruction al the &stinatcon address.

The 80188 &bit BIU is noticeabiy limited in it3 performance relative to the execution unit. A sut'bent number of prefetched bytes may not reside n the prefetch queue much of the time. Therefore, lctual program execution bme may be substantially geater than that derived from adding the instruction tinlgs shown.

1-207

L

,

__ C m

12

2

2

2

2

3110'

4/10.

314

31 19'

4/18.

314

31 15'

3

3/10'

4/18'

314

31 IO'

4/10'

314

3/15'

3

31 1 O'

3110'

3/10'

314

3/10'

0

4

7

4 -

L INSTRUCTION SET SUMMARY _I_ "

! FurUon

a0C)l Fama1 Qdn I Q I

V12'

218'

2/13.

314

e.'

0.

2113

2/15

20 14

13

-u . ..# .

24

14

12

"#a

4/17

3

1 O'

0'

8'

7'

15

6

¿i

21

..

111OOlOW I pat

1 1 1 0 0 1 l W I w l

[m,

1 0 0 1 1 1 1 1 ]

[ ( o 0 1 1 1 1 0 1

1 -2CY

111-1

- . b + o

.*+m

.w t 9

.Ul1+9

.Y1 t s

. u a + S

.Wt8

. ti *L

.o1

..?I

.S1

.n

.*l

.OllE

* IC

.ell*

r O l l E

*IC

.911t

.011E

* IC

. O l I t

. O l l C

- urr3 p43 -

012-1

319011

88108 m!

QD Q1

O QD

v-

I

B

j O 0 " " - ~

r

1- 4r

" . . " _ . . . . , . . , . . , I ...- _"" -""""."-I"'r*...""n*r."rYL-F"

80188 "

FOOTNOTES

IS computed accordlng lo the mod and r/m flelds: Tho Ellectlve Address (EA) 01 the memory operand

d mod = 1 I lhen rlm IS treated as a REG leld

It mod = O0 lhen DlSP = O'. dSpW and dtsphrgh are a b s n l

r f mod = O1 lhm DlSP = displorv srgrreXlended lo 16-btls. dlsp-htgh IS absent

I I mcd -= 10 then DlSP - disc-hlgh: d~splo*,

L

4 1 r i l l l - OGO lhen E A (BX) t (S!) + DlSP

It r/m ~ 001 then EA (6x1 t (DI) + DISP '

11 r/m 2 O 1 0 Vlen E A (BPI t (SI) + OlSP

1 1 , / m : O11 lhon E A i (RP) + (DI) + DlSP

It ( / m 100 then EA = (SI) + DlSP

11 r /m ~ 1 0 1 lhen EA = (DI) t DlSP

)I # / m ~ 1 1 0 lhen E A = (BP) t DISP'

It r/m = 1 1 1 lhen E A - (BX) t DlSP

DlSP follows 2nd byte of instruction (before data it requlred)

'except I t mod = O0 and r/m = 110 then EA = disp-hlgh: dlsp-low.

EA calculatlon time is 4 clock cycles for all modes, and IS Included In the execution times glven Whenev- er appropriate.

Segment Override Profix

1 0 O I reg I t O ]

reg is assigned accordlng to the f o l hng : 9gmont

reg Reglrter O 0 ES O1 cs 10 SS 11 0s

REG is ass;gncd accord!ng lo the Iollow~ng table:

i5-Blt (W =-

O00 AX O01 cx O 1 0 DX o11 DX 1 00 SP 101 BP 110 SI 111 DI

1) &Bit (w = O) O00 AL O01 CL O 1 0 DL o1 1 BL 100 AH 101 CH l lODH 111 BH

The physlcal addresses 01 all operands address@ by the BP reglster are computed using the SS SW men1 register. The phystcal addresses of the desD nation operands of Ihe stnng primitive Operation! (those addressed by the DI regisler) are complta uslng the ES segment. whch may not be overridden

1-214

u0 1 bu

REVISION HISTORY ucUont JpnHlcsnUy revlsed rlnce verdon 410 are:

hn Description Table Added nole lo m pln requlnng poper RESET at power-up to COnfW re pln as Input. Renamed pin 44 to lNTl /m and pin 41 to I N T 3 / 1 ~ / I R O to bat- ter descrrbe U W Iunctrons in Slave Mode.

Initialization and Processor Reset Added reminder to drive pin LOW dunng powerup.

M a p Cycle Timing Waveform Clarified applicability o1 TCLCSV to latched Al and A2 In footnote. HOLD/HLDA liming Waveforms Redrawn to indicate conect relationship of HOLD inactive to HLDA inx-

instruction Set Summary Corrected clock count for ENTER instruction. Slave Moda Operation The three low order bits assoclated with vector generation and pertming

EO1 are not alterable; however. t h e Monty levels are programmable. Thts Informallon IS a clanticabon only.

live.

me sections 8IgnlficanUy revbed slnce verdon -009 are: Pin Description Table Various descriptions rewritten l o r danty. Interrupt Vector Table Redrawn tor clarity. A.C. Charactenstics Added reminder that T ~ Y C L and T C L ~ Y mUSt be met. Explanation of t h e A.C. Symbols New sectton. Major Cycle Txc,trtg Waveforms T C ~ O indicated.

The sectlot18 rignlncantly revised slnce verdon 408 are: Pin Description Table, Noted I%% to be law m e than 4 clocks. Connectlons lo X1 and X2

DMA Control Bit Descriptions Moved and clarified note concerning TC conditm lor S T I m clearing

Interrupt Controller. etc. Renamed IRMX Mode to Slave Mode. Interrupt Request Register Noted that M) and Dl are read/write. others read-only.

clarified.

during unsynchronáed transfers.

nn .4ctkn, 8bnHku1tty nvbd since version 401 M:

A.C. charecteristics Several timings changed in anticipation of test change (all listed in ns): TCUV (min.) at 10 MHz from 50 to 44; TCVCTV (m.) at 8 MHz from 10 to 5; T w c w (max.) from 70 to 50 at 8 MHz and 56 lo 40 at 10 MHz.

1-215

-. ". .

Documents

UNIVERSIDAD AUTONOMA METROPOLITANA UNIDAD …148.206.53.84/tesiuami/UAM5859.pdf · besicas para un sistema mínimo, el bus de Dentro de las localidades disponibles de direcciones