up to 10 Gbit/s with Bit-Rate Flexible Operation Sampling ... · PDF filewith Bit-Rate Flexible Operation up to 10 Gbit/s ... processor –memory interface ... cycle control loop

Sampling Receive Equalizer with Bit-Rate Flexible Operation up to 10 Gbit/s

ESSCIRC 2006, 21.09.2006, © Markus Grözing / INT1

Universität StuttgartInstitute of Electrical and Optical Communications Engineering Professor Dr.-Ing. Manfred Berroth

Universität StuttgartInstitute of Electrical and Optical Communications Engineering

Prof. Dr.-Ing. Manfred Berroth

Sampling Receive Equalizer

with Bit-Rate Flexible Operation up to 10 Gbit/s

Markus Grözing,

Bernd Philipp, Matthias Neher,

and Manfred Berroth




Outline

• Motivation

• Channel response

• Equalizer concept

• Circuit design

• Experimental results

• Conclusion




Motivation (1): Applications

Computer mass market, i.e.processor –memory interfaceDDR3 ~1 Gbit/s FBDIMM 4.8 Gbit/stomorrow: 7 to 10 Gbit/stransmission length: 2 to 20 cm

Optical networks, i.e.LAN, MAN and WAN today: 2,5 to 10 Gbit/stomorrow: 40 to 100 Gbit/stransmission length: 10 m to 1000 km

Backplanes, multi-chip modules, i.e. network cross connects, mainframes

today: few Gbit/s tomorrow: > 10 Gbit/stransmission length: up to 1m




Frequency Response of 50 Ω Trace on FR4

-50

-40

-30

-20

-10

0

0 1 2 3 4 5 6 7 8 9 10

frequency [GHz]

S21

[d

B]

173 cm

- 24 dB@ 3.5 GHz

90 cm - 18 dB@ 5.0 GHz

- 19 dB@ 3.0 GHz




-0.1

0.0

0.1

0.2

0.3

0.4

-5 -4 -3 -2 -1 0 1 2 3 4 5time [UI]

rela

tive

res

po

nse

-0.1

0.0

0.1

0.2

0.3

0.4

-5 -4 -3 -2 -1 0 1 2 3 4 5time [UI]

rela

tive

res

po

nse

precursor ISI postcursor ISI

Measured Single Symbol Time Domain Response

90 cm long trace at 10 Gbit/s

173 cm long trace at 6 Gbit/s




Equalizer Concept (1): Filter Structure

T

c-1

c-2

CLK

T TT

c1

c2

Din DoutS&H

Finite-Impulse-Response (FIR) Filter

removes precursor ISI

Decision Feedback Equalizer (DFE)

removes postcursor ISI

analog delays decision & digital delays

analog weightingand adding




T&H 1 T&H 2 T&H 3 FIR filter adder

D

DFE adder & decision latch D-Latch

CLKc-1

c-2

c-2

c-1 c1

c2

c1

c2

Din

to output drivers

Dout1

Dout2

2

Equalizer Concept (2): Half-Rate Structure

FIR-Filter DFE

full rate data inputhalf rate clock

half rate demultiplexeddata outputs




Circuit Design (1): Track & Hold Circuit

Vin,D

Vout,D

VSS

VDDCLK/2n _CLK/2p

I0

differential complementary transfer gate

optimized for minimum track time

unity gain buffer

optimized for large linear range

bootstrapped clock inputs




Circuit Design (2): FIR Filter Adder

Vout,D

V-2,D

VSS

VDD

I-1 I0I-2

1/2(I-2+I-1)

V-1,D V0,D

CLK/2n/p

transfer gates

weightedtrans-

conductors

connected to outputs of interleaved T&H delay chain

common pair of load resistors

current injectionto ensure constant CM-level

weightadjustment




Circuit Design (3): DFE Decision Latch with Adder

Vin,D

VSS

VDD

I0

CLK/2 _CLK/2

I1+ I1- I2+ I2-Vout,D

V1,D V2,D

connected to other row decision latch (V1,D)same row D-latch (V2,D)

cross coupled decision latchDFE analog adder

fromFIRadder

toD-latch

coefficient weighting & sign selection




Circuit Design (4): Clock Generation

÷ 2

CLK/2

_CLK/2p_CLK/2n CLK/2p CLK/2n

_CLK/2

(VDD-VSS)/2

Boot-

CLKin

CLK/2out

CML amplifier

CMLdriver

forCLK/2output

CML driver

CMOS driver

Bootstrap circuit

CML divider

CMOS clock duty cycle control loop




CL

Kin

VSS VSS

Din

_Din

Dout1

Dout2

VDDVDD VDD

VDD

VDD

VDD

VDD

CLK

in

coefficient contol current inputs

data output drivers

clock generation

clock output driver

CLK

/2ou

t

equalizer core

Chip PhotographInput:max. 10 Gbit/s

Output:max. 2x 5 Gbit/s

Chip area: 1400 µm x 600 µmCore area: 60 µm x 56 µm




Experimental Results (1): 7 Gbit/s over 173 cm FR4

7 Gbit/s7 Gbit/s 2x 3.5 Gbit/s

data

clock

pulse-patterngenerator oscilloscope,

error detector

PRBS 231-1

PRBS 231-10000000000001

coefficientcontrol

V1 V2 R1 R2

diff. traceFR4 173 cm

equalizerCMOS 130 nm

Loss: 24 dB @ 3.5 GHz




Experimental Results (2): 10 Gbit/s over 90 cm FR4

10 Gbit/s10 Gbit/s 2x 5 Gbit/s

data

clock

pulse-patterngenerator oscilloscope,

error detector

PRBS 231-1

PRBS 231-10000000000001

coefficientcontrol

V1 V2 R1 R2

diff. traceFR4 90 cm

equalizerCMOS 130 nm

Loss: 18 dB @ 5 GHz




Experimental Results: BER versus Sampling Phase

-12

-10

-8

-6

-4

-2

0

-0.5 0.0 0.5sampling phase [UI]

log

(BE

R)

PRBS

27-1

PRBS

231-1

equal. off

-12

-10

-8

-6

-4

-2

0

-0.5 0.0 0.5sampling phase [UI]

log(

BE

R)

PRBS

27-1

PRBS

231-1

equal. off

173 cm FR4 trace @ 6 Gbit/s 90 cm FR4 trace @ 10 Gbit/s

Loss: 19 dB @ 3 GHz Loss: 18 dB @ 5 GHz




Performance Summary

230 mVmin. Vpp,PPG for BER < 10-11, PRBS 27-1, 6 Gbit/s, 173 cm FR4

300 mVmin. Vpp,PPG for BER < 10-11, PRBS 27-1, 10 Gbit/s, 90 cm FR4

24 dBmax. poss. channel loss for BER < 10-12, PRBS 231-1, 7 Gbit/s

200 mWPDC total (with drivers)0.5 Gbit/sminimum bit rate fmin

33 mWPDC clock generator**10 Gbit/smaximum bit rate fmax

21 mWPDC equalizer core*1.3 Vsupply voltage VDD

*circuitry corresponding to slide 8; **circuitry in dashed box of slide 13.




Conclusion• Receive-Side FIR-DFE-Equalizer for up to 10 Gbit/s:

- small chip area (core: 60 µm x 56 µm)

- low power consumption (core: 21 mW, clock: 33mW )

- up to 24 dB channel loss compensation

- no spiral inductors

- realized in 130 nm standard CMOS

• Filter frequency characteristic can be shifted

continuously by external clock:

- bit-rate flexible operation

- especially suited for measurement equipment

• adaptive operation is topic of future work




References

[1] J. Liu, X. Lin, “Equalization in high-speed communication systems,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 4-17, April 2004.

[2] R. Payne et al, “A 6.25-Gb/s binary transceiver in 0.13-µm CMOS for serial data transmission across high loss legacy backplane channels,” IEEE JSSC, vol. 40, no. 12, pp. 2646-2657, December 2005.

[3] T. Beukema et al., “A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization,” IEEE JSSC, vol. 40, no. 12, pp. 2646-2657, December 2005.

[4] S. Reynolds, P. Pepeljugoski, J. Schaub, J. Tierno, D. Beisser, “A 7-tap transverse analog-FIR filter in 0.13µm CMOS for equalization of 10Gb/s fiber-optic data systems,” ISSCC 2005, pp. 330-331, February 2005.

[5] J. E. Jaussi et al., “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE JSSC, vol. 40 no. 1, pp. 80-88, January 2005.

[6] Y.-S. Sohn, S.-J. Bae, H.-J. Park, S.-I. Cho, “A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel,” 2002 Symp. on VLSI Circuits, pp. 92-93, February 2005.

Documents

up to 10 Gbit/s with Bit-Rate Flexible Operation Sampling ... · PDF filewith Bit-Rate Flexible Operation up to 10 Gbit/s ... processor –memory interface ... cycle control loop