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UPE Devices Theme
Prof Phil Mawby
06/07/2015 CPE Annual Meeting June 2015 1
“We aim to make a significant contribution to the state of the art in semiconductor power device technology performance, in a number of key strategic areas, whilst maintaining competitiveness with global leaders.
The selected areas range from power IC technology and advanced superjunction IGBT structures in silicon, through to wide bandgap devices in silicon carbide and gallium nitride.
By carrying out this work we aim to progress the performance of power electronic systems and applications across the power range, for the benefit of UK industry.”
06/07/2015 CPE Annual Meeting June 2015 2
Mission Statement
Research Challenge – Advanced superjunction Si device design Silicon Carbide Device Design Compact Models for electro-thermal device design
Devices Theme – WP1: Power Device and design and fabrication
06/07/2015 CPE Annual Meeting June 2015 3
Overview
Devices Theme – WP2: Interfaces and Materials
Research Challenges: 1. To achieve high quality power device interfaces
(in particular MOS interface) 2. To develop novel methods of interface
characterisation 3. To grow high quality thick epilayers on SiC
Outputs: To provide novel power devices to accelerate the development of distinctive UK products.
06/07/2015 CPE Annual Meeting June 2015 4
Devices Theme – WP3: Device Reliability
Research Challenge – Understand the physical degradation of SiC and GaN devices Provide the basis for building predictive device degradation models.
06/07/2015 CPE Annual Meeting June 2015 5
Devices Theme/WP4 - Power Integrated Circuits
• This workpackage aims to develop competitive, 700V-1200V rated lateral power devices suitable for integration and realisation of compact products for energy saving low power applications.
• The main challenge will be to 1. gain deep understanding of various performance trade-offs through
device simulations and measurements on fabricated chips 2. optimise devices for reliable performance in the package and robust
operation in the application
06/07/2015 CPE Annual Meeting June 2015 6
06/07/2015 CPE Annual Meeting June 2015 7
WP 1 & 4 Devices Theme - Cambridge University
06/07/2015 CPE Annual Meeting June 2015 8
WP 1.1:Superjunction IGBTs
• Devices designed and fabricated with local charge compensation
• 1.2 kV breakdown with 25% lower on-state losses.
• Results published at ISPSD 2015 and new results submitted to IEEE EDL
06/07/2015 CPE Annual Meeting June 2015 9
The floating p-ring FS+ IGBT 9
The p-ring concept is a form of RESURF (Reduced SURface Field effect). We use p-n regions to distribute the field more uniformly across the cathode side M. Antoniou et al. in ISPSD 2015
P-ring P-ring
P-well
N-injector
N-drift
06/07/2015 CPE Annual Meeting June 2015 10
10
The technology curve: p-ring FS+IGBT
Simulation results
Experimental results
06/07/2015 CPE Annual Meeting June 2015 11
WP 1 & 4 Devices Theme - Cambridge University
06/07/2015 CPE Annual Meeting June 2015 12
WP 4: Power Integrated Circuits (700V/1kV Bulk Si LIGBTs and LDMOSFETs, Drivers)
• Devices designed and fabricated in the MPW batch have been characterised
• Both 700V LIGBTs and 1000V MOSFETs were evaluated
• Testing was done on bare dies (on-state and Vbr only, at 25C) and on selected packaged parts
(on-state, Vbr, switching, 25C and 125C).
• All devices were tested using single-pulse tests with on-state pulse width of 10us
• Selected devices were used to start reliability testing as well (HTRB testing)
• Trade-off curves were generated for al tested LIGBTs (Von vs. Eoff at Tj=125C)
• Simulations have been performed to explain some unexpected characteristics as well as to fine
tune simulation models to get a better match between simulations and measurements
06/07/2015 CPE Annual Meeting June 2015 13
Design area with Cambridge Devices
MOSFETs
POLY Resistors for Chip Id
IGBTs Layout view of
the Batch 1 MPW
CHIP 01
CHIP 02
CHIP 03
CHIP 04
CHIP 06
CHIP 07
CHIP 08
CHIP 09
CHIP 11
CHIP 12
CHIP 13
CHIP 14
CHIP 16
CHIP 17
CHIP 18
CHIP 19
CHIP 05 CHIP 10 CHIP 15 CHIP 20
06/07/2015 CPE Annual Meeting June 2015 14
MOSFET On-state and off-state measurements (Tj=25C)
• On-state and breakdown characteristics for MOSFETs
06/07/2015 CPE Annual Meeting June 2015 15
Photograph of the fabricated die with LIGBTs
1m
m
1.5 mm
700V Lateral IGBT (LIGBT) – 5W design
700V Lateral IGBT (LIGBT) – 10W design
G
G
G
E
E
E
C
C
C
D
D
700V Depletion mode MOSFET
G S
G S
06/07/2015 CPE Annual Meeting June 2015 16
Measured LIGBT Breakdown Voltage
• The measured breakdown voltage at Tj=25C is >800V • The leakage current is very low: <1nA for a 300mA device • The leakage current of the device cannot be accurately measured because it is limited by
the leakage of the measurement system
Warwick Research Activities
Research team
Project Leaders: Prof. Phil Mawby, (Ms Leigh Murray) Research Associates: Dr V. A. Shah, Dr. D Martin
PhDs: Yegi Bonyadi, Dai Tianxiang
06/07/2015 CPE Annual Meeting June 2015 18
The surface of the 3kV layer produced by Warwick
AFM scan of the
surface of the
30 um layer.
Surface steps are
seen, but not
significant.
These layers are intrinsic (~1-
3e14 cm-3) and can be produced at
a safe working rate of 1 wafer per 2
days.
Less than 20 optically visible
defects
The surface roughness is measured
to be ~1.5 nm RMS. Demonstrating
the readiness of the wafers for
device fabrication.
3kV Layer Epitaxial Growth
Epi Thickness
The thickness of the epilayer gives the blocking voltage of the device
06/07/2015 CPE Annual Meeting June 2015 19
The surface of the 10 kV epilayer.
-10 0 10 20 3010
13
1014
1015
1016
1017
Nd(cm-3) vs Vbias
Vbias (V)
Nd(c
m- 3
)
The doping concentration from Hg-probe measurements. At Zero Bias, the concentration is 1e14cm-3 to 3e14cm-3
When compared to the only other
known supplier of 100 um epitaxial
layers, NORSTEL, the defect
density is a factor of 3 less than that
observed in one wafer,
demonstrating their superior quality.
10kV Layer Epitaxial Growth
HR-XRD scans of the 100 um layers
grown by Warwick and NORSTEL. The
Warwick layer is shown to have a
lower FWHM, indicating better
layer quality
06/07/2015 CPE Annual Meeting June 2015 20
-40 -20 0 20 40
0.00E+000
5.00E+013
1.00E+014
1.50E+014
2.00E+014
2.50E+014
Wa
rwic
k D
op
ing
(cm
-3)
X position (mm)
Warwick Doping
Warwick Doping
LPE Doping
LPE Doping
-60 -40 -20 0 20 40 60
98
99
100
101
102
103
Wa
rwic
k T
hic
kne
ss (
um
)
X position (mm)
Warwick Thickness
Warwick Thickness
LPE thickness
LPE thickness
The thickness variation of the 10 kV epilayer over the wafer.
The doping variation of the 10 kV epilayer over the wafer.
Doping concentration variations
shows a variation from 1e14cm-3
to 3e14cm-3 compatible with
industrial standards.
Thickness uniformity is <2%
thickness, consistent with
industrial standards
Contaminants N, O, Cl, Al, Fe and
Zr are all below detectable limits
(1e15 cm-3, 3e16 cm-3, 2e14 cm-3,
3e13 cm-3, 2e14 cm-3, 1-2e14 cm-
3, respectively) demonstrating
high purity growth.
Uniformity and Background Impurities in SiC layers
06/07/2015 CPE Annual Meeting June 2015 21
TEM sample preparation: Lift out process using FIB/SEM
(a) SEM image of TEM bars in different
angles (b) SEM image of a TEM bar
(b)
TEM imaging AFM
Development of Material characterisation
(a)
(c) a prepared TEM sample
(80nm thickness).
d) AFM Scans of 3kV and 10kV
layers
SiC Material is Hard to Characterise, Development Still in Progress!
06/07/2015 CPE Annual Meeting June 2015 22
0.0001
0.001
0.01
0.1
1
10
100
1000
0.9998 1.1998 1.3998 1.5998 1.7998 1.9998 2.1998
Cu
rren
t d
ensi
ty (
A/c
m2
)
Voltage (V)
1.00E-10
1.00E-08
1.00E-06
1.00E-04
1.00E-02
1.00E+00
1.00E+02
1.00E+04
0 1 2 3 4 5 6 7Cu
rren
t d
ensi
ty (
A/C
m2
)
Voltage (V)
10 kV 4H-SiC PiN diode structure.
4H-SiC fabricated PiN diode.
Fig top-right: The departures from the ideal I-V characteristic in the recombination current region are attributed to the presence of a parasitic Schottky diode in parallel with the pn junction which was eliminated using a thicker passivation oxide layer (Fig bottom-right).
Before passivation improvement (with double bumps)
After Passivation improvement! No double bumps!!
Schottky diode fabrication
06/07/2015 CPE Annual Meeting June 2015 23
Right-TOP: Id-Vds
RIGHT-BOTTOM Mobility Curve
@ 1300°C N2O direct growth
condition
Lateral MOSFET Oxidation
Mobilities up to 40 V s / cm2!!
06/07/2015 CPE Annual Meeting June 2015 24
P-well Implantation profile simulations
2 dose implantation profile, (200 keV Al with fluence of 5 x 1013
ions/cm2 and 350 keV with fluence of 8 x 1013 ions/cm2. Simulation using SUSPRE.
0
50000
100000
150000
200000
250000
0 1000 2000 3000 4000 5000 6000
Al
Ion
s (
AU
)
Depth (Å)
350 keV Al
230 keV Al
30 keV Al
30 + 230 + 350 keV Al
SiO2 SiC
Mo line
Substrate surface
Process step testing
Microscope image of Mo lift – off process.
Microscope image of Mo etch process.
Lettering is Molybdenum and
surface is SiO2.
Fabrication of 3.3 kV MOSFETS
3 dose implantation profile with thin SiO2 covering, simulation
using TRIM.
Calibration of high
voltage device fabrication in progress!
Newcastle Research Activities
Research team
Project Leaders: Prof. Nick Wright and Prof. Anthony O’Neill Research Associates: Dr. Amit K. Tiwari and Dr. Jesús Urresti
PhDs: Faiz Arith
1. SiC MOS interface engineering
• During conventional thermal oxidation process, C atoms (not necessary all C atoms) of consumed bulk SiC leaves as CO or CO2 through the growing oxide.
• Because of the residual carbon atoms, SiC/SiO2 interfaces exhibit unwanted deep level immobile carbon di-interstitial defects, such as (Ci)2, which are the prime cause of endemically poor channel mobility in SiC MOSFETs [1].
• Multilayer gate stacks (metal/Al2O3/SiO2/SiC), comprising ultra-thin (~1nm) SiO2, are found to be effective in terms of reducing the C atom defects, resulting in a substantially high channel mobility of 294 cm2/Vs [2].
• Newcastle University is leading the task of developing low temperature process using atomic layer deposition (ALD) technique to obtain low interface density novel gate stacks and subsequently high mobility SiC MOSFETs.
1. Shen, et al, APL 98, 053507 (2011). 2. Hatayama et al, IEEE TED V55, 2041 (2008). Schematic for a metal/insulators/SiC gate stack.
Extracted channel mobility from a multilayer gate stack SiC-MOSFET.
2. SiC Superjunction (SJ) Device
• Akin to Si, SJ devices can break the theoretical limit of conventional SiC devices, as described by following equation: RSP_ON = 1.32 x 10-11 x VBR
2.43. • SiC SJ devices are capable of achieving specific ON
resistance nearly 1 order of magnitude lower than those of conventional SiC counterparts; however SJ devices require vertical p- and n-type pillars in the blocking layer.
• Fabrication process for vertical p-n pillars on SiC substrate using multi-epitaxial growth has recently been debated, however, no comprehensive details on functional devices yet [1, 2].
• Newcastle University is undertaking the novel research of developing SiC SJ devices capable of blocking voltage in the excess of 10 kV, while having a very low ON resistance when compared with conventional SiC devices in the similar voltage range.
• In addition, research team is also developing TCAD models for accurate design/optimisation simulations of SiC devices.
≈ ≈ Substrate
Drift region
Device channel region
n- pillars
p- pillars
L
2D representation of the drift region of a SJ-device sandwiched between the substrate and active channel region
Device ON resistance and breakdown voltage of a SJ-device
1. Kosugi et al. 26th ISPSD (2014). 2. Ranbir Singh et al (GeneSiC Semiconductor), HiTEC (2012).
SiC MOS interface engineering updates: Realisation of ~nm SiO2 on SiC (@600-700 C) thickness on SiC
SiC
SiO2 (~nm)
Ni (~20 nm)
SiO2 (~nm) SiC
Ellipsometry result 1.284 nm
~1.1 nm
•Realisation of thin SiO2 layer is critical for improving the channel mobility in SiC MOSFETs. • Ni/SiO2/SiC samples were prepared for ultra-thin SiO2 growth measurements. •Ni-layer used as an identification mark and as a mask for SiO2 etching. •Physical characterisation performed using AFM and Ellipsometry experiments on an area which consists both SiO2 and SiC. Both experiments have yielded similar results.
SiC (SJ) Device updates: SJ device design/optimisation
•A number of lateral and vertical SJ devices (diodes, JFETs and MOSFETs) are designed and optimised for high voltage applications. •In addition, effect of device parameters, such as doping, thickness and width of p- and n- pillars in the drift layer, which would induce the charge imbalance and thus affect the breakdown voltage, are also examined •At present, research activities are focused upon the realisation of simple SJ test structures to use them into more sophisticated device structures.
0
2000
4000
6000
8000
10000
12000
-20 -15 -10 -5 0 5 10 15 20
Breakdown Voltage (Volt)
Variation in doping concentration of pillars (%)
Fixed N-pillar doping
Fixed P-pillar doping
Pillar doping induced charge-imbalance analysis to investigate the degradation in the breakdown voltage of a SiC vertical JFET.
Effect of doping and thickness of blocking layer on the breakdown voltage.
DEVICES Theme
WP3: Reliability WP Lead: Martin Kuball (Bristol)
Covering: • WP3.1 Testing methodology and test structure definition • WP3.2 Interface, surface and bulk traps induced device generation • WP3.3 Nanometre resolution non-invasive device imaging & probing • WP3.4 Breakdown mechanisms • WP3.5 Contact degradation
30 06/07/2015 CPE Annual Meeting June 2015
IEEE BCDM 2014
Material and device system focus
06/07/2015 CPE Annual Meeting June 2015 31
IEEE MW 2009
Example from: WP3.4 Breakdown mechanisms
Can we build models on how (e.g.) GaN devices fail?
06/07/2015 CPE Annual Meeting June 2015 32
Substrate
AlGaN/GaN
Vd = 40V
Vg = -15V
Vs = 0V
20120°C
1 10 100 1000 10000
1
10
100
Ga
te c
urr
en
t I g
(
A)
Stress time (s)
Gate leakage
Electroluminescence microscopy and spectroscopy
AFM – image surface pit defects
Off-state stress test
06/07/2015 CPE Annual Meeting June 2015 33
D
SG
(a)
(b)
100
101
102
103
104
105
106
100
101
102
103
100
101
102
103
107
108
Gate
curr
ent
(µA
)
Stress time (s)
Num
ber
of
EL s
pots
EL inte
nsity
(arb
. units)
• Direct correlation between leakage current and EL spot generation. • Number of generated EL spots saturates at long stress time.
Saturation of defect generation
Sun, Kuball et al. APL 2014
06/07/2015 CPE Annual Meeting June 2015 34
Saturation of defect generation
2 µm Gate
(a)
(b)
Short pairs Mixed pairs Long pairs
400
600
800
1000
1200
1400
Dis
tance b
etw
een
pairs o
f adja
cent pits (
nm
)
Two possible causes: 1. Formation of exclusion zone near each defect. 2. Statistically distributed pre-existing defects. However, similar density of
defects in saturation regime on GaN-on-GaN devices.
GaN-on-GaN device
Distance between neighboring pits correlates with sizes of the two pits.
long long short
short
1 m
APL 2014
06/07/2015 CPE Annual Meeting June 2015 35
Two parallel electronic and electrochemical processes: formation of gate leakage path and generation of surface pit defects.
SiNx
gate
AlGaN Initial leakage
2DEG
SiNx
gate
AlGaN Leakage path formation
2DEG
- +
SiNx
gate
AlGaN
2DEG
- +
Surface defect
Cross-sectional view
Top view
AlGaN
gate
-
+ +
drain + +
-
- - gate
drain
21°C
Room T
High T
120°C
+ +
- - -
+ +
- -
‘+’ species
- electrons
Degradation model
Sun, Kuball et al., ROCS 2014
06/07/2015 CPE Annual Meeting June 2015 36