Verification Requrirement Specification Template

USB3SS Verification Requrirement Specification TemplateSKELETONCompany confidential

Doc no.3/002 02-10/LXE 108 820 UenRevB 2014-08-01Reference

PreparedESSRJJNChecked

B PTZ/N/A [Nithin Maiya]

USB3SS Verification Specification (Requirement/Plan) USB3 SS - 7600Revision History

Table 1: Revision historyDateRevisionAuthorApprover(s)Changes

12/09/20140.1Sachin Kumar JainNithin Maiya KumarInitial version

12/09/20140.2Sachin Kumar JainRemoved FS and LS

Table 2: Reference DocumentsDocument NameDocument NumberVersion

USB3_r1.0_06_06_2011.pdfRevision r1.0_06_06_2011

DWC_usb3_databook.pdf

USB_30_PIPE_10_Final_042309.pdf

Table of Contents1Introduction41.1Glossary41USB3 SUBSYSTEM62USB3 SS Verification Environment72.1DATA TRANSFER AND SCOREBOARDING82.1.1IN DATA TRANSFER82.1.2OUT DATA TRANSFER82Alpha Maturity Scenarios/tests102.1Register Read write Test102.1.1USB30_SS DWC Controller Register read/write test102.2Data Transfer Tests102.2.1USB30_SS_BULK_IN_Test (BYPASS Enumeration)102.2.2USB30_SS_BULK_OUT_Test (BYPASS Enumeration)112.2.3USB30_SS_DATA_TRANS_TEST (With Enumeration)112.2.4USB20_HS_DATA_TRANS_TEST113BETA Maturity Scenarios/tests123.1USB30_Functional_LP_Test123.1.1USB30_U0_U1_U0_Test DSP (host) initiated123.1.2USB30_U0_U1_U0_Test USP (device) initiated123.1.3USB30_U0_U2_U0_Test DSP (host) initiated133.1.4USB30_U0_U2_U0_Test USP (device) initiated133.1.5USB30_U0_U3_U0_Test DSP (Host) initiated143.1.6USB30_U0_U3_U0_Test USP (Device) initiated143.1.7USB30_U0_U3_U0_Test DSP (Device) initiated - Hibernation153.1.8USB30_U1_U2_HRESUME163.1.9USB30_U1_U2_DRESUME163.1.10USB20_HS_L2SUSPEND_REMTWKUP163.1.11USB20_HS_L2SUSPEND_RESET163.1.12USB20_HS_L2SUSPEND_RESUME163.1.13USB20_HS_L1SUSPEND_REMTWKUP163.1.14USB20_HS_L1SUSPEND_RESET163.1.15USB20_HS_L1SUSPEND_RESUME163.1.16USB20_HS_L2SUSPEND_REMTWKUP_HIB173.1.17USB20_HS_L2SUSPEND_RESET_HIB173.1.18USB20_HS_L2SUSPEND_RESUME_HIB174Final Maturity Scenarios/tests184.1USB3 Warm Reset Test184.2USB3 DSP Disconnect Testcase184.3USB3 USP Disconnect Testcase194.4USB3 Hot Reset Test204.5USB3 U0_to_Recovery_to_U0 Test205Software Sequence Details215.1.1.1Test Steps:215.1.1.2Device Mode Sequence225.1.1.3Device Mode Initialization225.1.1.4EP_CONFIG - Start Configuration & SET EP CONFIGURATION225.1.1.5SET EP TRANSFER RESOURCE CONFIGURATION225.1.1.6Program the BULK_OUT TRANSFER236Low Power Scenario/Tests (MVSIM/QUESTANLP)247GLS Scenarios/tests25

1 IntroductionThe aim of the Subsystem verification is to focus on the integration tests and inter-operability tests. Further, the subsystem goes into SoC and SoC verification is performed to assess that the IP is correctly integrated at the top level and formerly developed tests shall be instrumental in achieving the objective. The verification plan is a specification document dedicated to: Identify the IP or subsystem interfaces Identify the IP or subsystem features Specify how the features are stimulated (coverage model) Specify how the features are checked (Self-checking capabilities) Identify the scenarios (tests) to stimulate the IP or subsystem Estimate the expected coverage provided by the scenarios1.1 GlossaryAHBAdvanced High-performance BusAMBAAdvanced Microcontroller Bus ArchitectureAPBAdvanced Peripheral BusAXIAdvanced eXtensible InterfaceBFMBus-Functional ModelDMADirect Memory AccesseDMAEmbedded DMADWDesign Ware (all Synopsys IP are called as DW)EPEnd PointGPIOGeneral Purpose Input OutputMPHYMIPI Alliance MPHY (Physical layer)RRAPRemote Register Access ProtocolUSB3SuperSpeed Inter-chipSoCSystem on ChipSOMASpecification of Modeling ArchitectureTLMTransaction Level ModelingVALVerification Abstraction LayerVRIVirtual Register InterfaceVIPVerification IPUVCUniversal Verification ComponentUSB3 SUBSYSTEM In this USB3 subsystem, USB3.0 device controller, USB2.0 device controller are implemented.USB3.0 IP as a bus master will directly access external system DRAM through the bus interconnection. In this subsystem, the USB3.0 (super-speed) PHY and USB2.0 (HS) PHY are included. This sub-system has the following features:Compliant with USB 2.0 specification (revision 2.0), and USB3.0 specification (rev. 1.0). Can have SS(5-Gbps), HS (480-Mbps), and operation modes.Support HS USB OTG PHY with ULPI interface and SS USB PHY with PIPE3 Interface.Support all kinds of transfer types: Control, Bulk, Isochronous, and interrupt.Transfer descriptor used for data transfer between this modules with system memory. Descriptor caching/data pre-fetching for high performance requirementThe block doesnt support USB2/USB3 working at the same time.Below is the functional diagram of the USB3SUBSYS

USB3.0 PHYUSB2.0 PHYPIPE3UTMI+Super Speed USB Device Controller

Figure 1 : USB3 Subsystem Block DiagramUSB3 SS Verification Environment AXI SLAVE EVCAHB MASTER EVC

64 bit AXI Master I/F32bit AHB Slave I/F

USB3 Device Controller

USB3.0 PHY USB2.0 PHY

Thin Modem Peripheralsasync

USB 3.0 HOST PIPE USB 2.0 HOST UTMI+

PHY EVC PHY EVC

USB 3.0 HOST Controller EVC

Figure 1 : USB3 Subsystem Block Diagram

Figure 2: USB3SS Verification Environment Block Diagram

DATA TRANSFER AND SCOREBOARDING IN DATA TRANSFERUSB3 Device Transmits data transfer from memory to VIP USB3 HostMemory -> TX buffer -> PHY -> VIP Host

A VIP emulates the USB3 Host which requests and receives the data from USB3 DEVICE IP. SV test shall verify that interrupt is generated at end of transfer and that event buffer is updated to report correct event notification, which depends on what events were enabled for notification.Note: Scoreboard mechanism is implemented in the SV-UVM Environment. SV triggers the Callback functions to recover the data received by host (VIP). SV Env has reference data available in the AXI Slave memory. Scoreboard compares consecutive packets of the reference data with the actual data. If either interrupt is not generated for correct event or there is data/type mismatch, error will be reported to indicate failure of the test.

Figure 3: USB3 SS Data IN Transfer Block Diagram OUT DATA TRANSFERUSB3 Device receives data transfer from VIP Host to external memory, following the path:

VIP Host -> PHY -> Rx buffer -> Memory

Figure 4: USB3SS Data OUT Transfer Block Diagram

A VIP emulates the USB3 Host which transmits data to the USB3 DEVICE SS. SV test shall verify that interrupt is generated at end of transfer and that event buffer is updated to report correct event notification, which depend on what events were enabled for notification.

Note: Scoreboard mechanism is implemented in the software. SV has reference data available in AXI Slave Memory. Scoreboard compares consecutive packets of the reference data with the actual data. If either interrupt is not generated for correct event or there is data/type mismatch, error will be reported to indicate failure of the test

2 Functional Requirements Functionality support for all layers (Protocol, Link and Physical).

Support to run Protocol layer transfers at Packet-level (Transaction Packet, Data Packet, Link Management Packet, and Isochronous Timestamp Packet).

Support to run link layer commands (LCRDx, LGOOD, etc.) and link layer Header Packets.

Full enumeration process handling capability (GET_DESCRIPTOR, SET_CONFIGURATION, SET_ADDRESS, etc.) through control transfers

Support of all kind of Endpoints (Control transfers, Bulk transactions, Interrupt transactions, and Isochronous Transactions)

Complete support of Burst Transactions and Flow Control Conditions

Complete support for Bulk Stream protocol state machines for both host and device (ISPSM/IMDSM and OSPSM/OMDSM)

Support of Link Training and Status State Machine (LTSSM)

Support for Cyclic Redundancy Check (CRC) error in Data Packet Payload (CRC-32), Header packets (CRC-16), and Link commands (CRC-5)

Support for Link error detection/injection and recovery

Support for Framing Error in Header Packet, DPP and Link Command

Support for injection and detection of Header sequence number error.

Flexibility for injecting other types of Link Errors (like, Header Packet Error, ACK Tx Header Sequence Number Error etc.)

Support Link Recovery and Header Packet Retransmission

Supports Link Power Management Support for running LGO_Ux link command U1/U2/U3 state transitions Support for LFPS signaling for Ux State Exit to U0. Low power state transition can be initiated by any end

Low power state exit transition can be initiated by any end

Supports data scrambling/descrambling, 8b/10b encoding/decoding, and electrical/logical idle.

All types of Training Sequence Ordered Sets (for example, TSEQ, TS1, TS2, etc.) supported

Supports loopback mode and lane polarity inversion

Support for Low Frequency Periodic Signaling (LFPS) Configurable delays to control timing in transfers at different layers Configurable timers to control LTSSM transitions Configurable Initial LTSSM state Configurable number of TSEQ Ordered Sets in LTSSM Configurable number of Polling.LFPS in LTSSM Configurable support for skipping

Polling.LFPS and TSEQ ordered sets.3 Functional Coverage BinsItemRemarks

Upon Data packet end, samples packet fields The coverage group name is: cover_in/out_data_pkt

pkt_kindPacket KindProtocol Layer (TL) packet or Link Layer(DLL) packet

data_pkt_lenPacket Length

payload_lenPacket Payload Length

sopSOP of Packet

eopEOP of Packet

pkt_errPacket Error Type if any

cross pkt_kind, pkt_err

ItemRemarks

LTSSM state transition (Passive upstream port) The coverage group name is: Cover_ltssm_state

state_nameCurrent state of the agent

next_state_nameNext state of the agent

succeeded_conditionExit condition of the statetransition

directed_modeMode of the agent, Directed etc.

loopback_modeLoopback mode of agent

cross state_name, next _state_name, succeeded_condition

state_transition_kindTransition from state to state

4 Alpha Maturity Scenarios/tests4.1 Register Read write Test

This test performs all the read only, write only and read-write tests on the registers of USB3. These checks are performed in a C test, which is generated from IPXACT xml. These tests are automatically generated by the spirit2regtest tool.4.1.1 USB30_SS DWC Controller Register read/write testXML of DWC USB3 controller is used. The test will verify the AXI slave interface, implicitly verifying the XML of the Synopsys IP,will verify the PIPEW register wrt to the XML released

1. DWC_REG 2. PIPE_MIPHY_REG 3. USB2_REG

Register Access for the DWC Module

1). Check the reset value of all the registers.2). Check all the registers for read write accesses.4.2 Data Transfer Tests4.2.1 USB30_SS_BULK_IN_Test (BYPASS Enumeration)This scenario performs the bulkin test. USB3 Device DUT enters into U0 LTSSM state after initialization. These data packets are prepared in the memory first and then send to the VIP. With the help of VRI, comparison is done in software. This scenario will perform basic IN data transfers in the super speed mode. Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer (SetAddress request).4) Endpoints are configured and resources are allocated accordingly.5) CPU stores the data into the system memory. 6) Initialize the device registers. Predetermined device address is programmed in core.7) CPU waits for the connect-done event.8) Endpoint start transfer command fetches the data TRB. It decodes TRB and then fetches data from the system memory to internal buffer of core.9) Program the Denali host model via VRI to start bulk transfer10) CPU waits to complete the bulk transfer event.11) CPU uses the VRI function call to implement the scoreboard mechanism12) Based on packet comparison, test case Pass/Fail. 4.2.2 USB30_SS_BULK_OUT_Test (BYPASS Enumeration)This scenario performs the bulkout test. USB3 Device DUT enters into U0 LTSSM state after initialization. CPU triggers the VIP via VRI to send the data. With the help of VRI, comparison is done in software. This scenario will perform basic OUT data transfers in the super speed mode.Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) CPU passes data to the VIP through VRI function call.8) CPU triggers the VIP to start the bulk transfer through VRI9) Endpoint start transfer command fetches the data TRB. 10) CPU waits to complete the bulk transfer event.11) CPU uses the VRI function call to implement the scoreboard mechanism12) Based on packet comparison, test case Pass/Fail. 4.2.3 USB30_SS_DATA_TRANS_TEST (With Enumeration)1) Verify the USB 3.0 data path of the XHCI Controller with the PIP3 PHY along with USB 3.0 I/F2) Will include initial USB enumeration sequence in SS mode3) Will include 1 data transfer in OUT and IN direction4) DUT in Device mode only"The Interrupter Target changed to 1 from the default 0, Hence all the EP related interrupt would trigger on INT_1 line4.2.4 USB20_HS_DATA_TRANS_TEST1) Verify the USB 2.0 data path of the XHCI Controller with the ULPI PHY along with USB 2.0 I/F2) Will include initial USB enumeration sequence in HS mode3) Will include 1 data transfer in OUT and IN direction4) DUT in Device mode only

5 BETA Maturity Scenarios/tests5.1 USB30_Functional_LP_TestThese tests check the functional low power feature of the USB3 SS.5.1.1 USB30_U0_U1_U0_Test DSP (host) initiatedIt exercises the LTSSM state transition U0 to U1 (entry to U1) and U1 to U0 (exit from U1). Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Host initiated U1 Exit after U1 Entry (LTSSM Transition U0 > U1 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail.

5.1.2 USB30_U0_U1_U0_Test USP (device) initiatedIt exercises the LTSSM state transition U0 to U1 (entry to U1) and U1 to U0 (exit from U1).

Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Device initiated U1 Exit after U1 Entry (LTSSM Transition U0 > U1 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail.

5.1.3 USB30_U0_U2_U0_Test DSP (host) initiatedIt exercises the LTSSM state transition U0 > U2 > U0

Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Host initiated U2 Exit after U2 Entry (LTSSM Transition U0 > U2 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail. 5.1.4 USB30_U0_U2_U0_Test USP (device) initiatedIt exercises the LTSSM state transition U0 > U2 > U0Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Device initiated U2 Exit after U2 Entry (LTSSM Transition U0 > U2 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail. 5.1.5 USB30_U0_U3_U0_Test DSP (Host) initiatedIt exercises U3 LTSSM state. The transition sequence is U0->U3->U0

Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Host initiated U3 Exit after U3 Entry (LTSSM Transition U0 > U3 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail.

5.1.6 USB30_U0_U3_U0_Test USP (Device) initiatedIt exercises U3 LTSSM state and hibernation mode is also checked. The transition sequence is U0->U3->U0

Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Device initiated U3 Exit after U3 Entry (LTSSM Transition U0 > U3 > Recovery > U0)9) CPU passes data to the VIP through VRI function call.10) CPU triggers the VIP to start the bulk transfer through VRI11) Endpoint start transfer command fetches the data TRB. 12) CPU waits to complete the bulk transfer event.13) CPU uses the VRI function call to implement the scoreboard mechanism14) Based on packet comparison, test case Pass/Fail. 5.1.7 USB30_U0_U3_U0_Test DSP (Device) initiated - HibernationIt exercises U3 LTSSM state and hibernation mode is also checked. The transition sequence is U0->U3->U0 Please refer section 8.2 and 8.3 of USB3 Subsystem for 7600 (Document) and for detailed programming sequence.Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) Setup The Device TRBs and bypass the control transfer.4) Endpoints are configured and resources are allocated accordingly.5) Initialize the device registers. Predetermined device address is programmed in core.6) CPU waits for the connect-done event.7) Device enters into U0 LTSSM State.8) Store MPHY attributes into the System memory9) U3 Entry (LTSSM Transition U0 > U3)10) Wait for hibernate entry event11) Store the non-sticky registers into the System memory12) Host initated U3 exit 13) Assert reset to controller (Vcc_reset_n) (LTSSM Transition U3 > SS.Disabled > U3)14) Restore the non-sticky registers from system memory15) Assert reset to MPHY, restore the MPHY registers.16) Enter into Recovery LTSSM state and wait till U0 entry 17) CPU passes data to the VIP through VRI function call.18) CPU triggers the VIP to start the bulk transfer through VRI19) Endpoint start transfer command fetches the data TRB. 20) CPU waits to complete the bulk transfer event.21) CPU uses the VRI function call to implement the scoreboard mechanism22) Based on packet comparison, test case Pass/Fail.5.1.8 USB30_U1_U2_HRESUME1) DUT is Configured in SS Device Mode2) Verifying the transitions from U0 to U1 to U2 to U0 States due to host Resume3) Bulk Data Transfer in the U0 State before and after the transition.5.1.9 USB30_U1_U2_DRESUME1) DUT is Configured in SS Device Mode2) Verifying the transitions from U0 to U1 to U2 to U0 States due to Device Resume3) Bulk Data Transfer in the U0 State before and after the transition.5.1.10 USB20_HS_L2SUSPEND_REMTWKUP1) DUT is Configured in USB2.0 HS Dev Mode2) Verifying the L2 Suspend Remote Wakeup scenario.3) Bulk Data Transfer before suspend and after the remote wakeup.5.1.11 USB20_HS_L2SUSPEND_RESET1) DUT is Configured in USB2.0 HS Dev Mode2) Verifying the L2 Suspend Reset Wakeup scenario.3) Bulk Data Transfer before suspend and after the Reset wkup5.1.12 USB20_HS_L2SUSPEND_RESUME1) DUT is Configured in USB2.0 HS Dev Mode2) Verifying the L2 Suspend Resume Wakeup scenario.3) Bulk Data Transfer before suspend and after the Resume wkup5.1.13 USB20_HS_L1SUSPEND_REMTWKUP1) DUT is Configured in HS Dev Mode2) Verifying the L1 Suspend Remote Wakeup scenario.3) Bulk Data Transfer before suspend and after the remote wakeup5.1.14 USB20_HS_L1SUSPEND_RESET1) DUT is configured in HS Dev Mode2) Verifying the L1 Suspend Reset Wakeup scenario.3) Bulk Data Transfer before suspend and after the Reset wkup.5.1.15 USB20_HS_L1SUSPEND_RESUME1) DUT is configured in HS Dev Mode2) Verifying the L1 Suspend Resume Wakeup scenario.3) Bulk Data Transfer before suspend and after the Resume wkup5.1.16 USB20_HS_L2SUSPEND_REMTWKUP_HIB1) DUT is Configured in HS Dev Mode2) Verifying the L2 Suspend Remote Wakeup scenario.3) Bulk Data Transfer before suspend and after the remote wakeup5.1.17 USB20_HS_L2SUSPEND_RESET_HIB1) DUT is Configured in HS Dev Mode2) Verifying the L2 Suspend Reset Wakeup scenario.3) Bulk Data Transfer before suspend and after the Reset wkup.5.1.18 USB20_HS_L2SUSPEND_RESUME_HIB1) DUT is Configured in HS Dev Mode2) Verifying the L2 Suspend Resume Wakeup scenario.3) Bulk Data Transfer before suspend and after the Resume wkup.6 Final Maturity Scenarios/tests6.1 USB3 Warm Reset TestWarm reset is the inband reset mechanism which can be initiated from host (Refer USB3 specification 3.6.2)Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) RRAP commands are exchanged in the RxDetect LTSSM state4) Setup The Device TRBs and bypass the control transfer.5) Endpoints are configured and resources are allocated accordingly.6) Initialize the device registers. Predetermined device address is programmed in core.7) CPU waits for the connect-done event.8) Device enters into U0 LTSSM State.9) CPU triggers Host VIP model to issue warm reset10) Host Issues warm reset11) Device MPHY detects the line-reset12) Device controller resets the local MPHY and enters into RxDetect Reset LTSSM state.13) Host and device exchange the RRAP sequence14) LTSSM transition from RxDetect > Polling > U015) CPU passes data to the VIP through VRI function call.16) CPU triggers the VIP to start the bulk transfer through VRI17) Endpoint start transfer command fetches the data TRB. 18) CPU waits to complete the bulk transfer event.19) CPU uses the VRI function call to implement the scoreboard mechanism20) Based on packet comparison, test case Pass/Fail.

6.2 USB3 DSP Disconnect Test caseDSP Disconnect test (Refer 5.6.2 of USB3 specification for detailed explanation)Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) RRAP commands are exchanged in the RxDetect LTSSM state4) Setup The Device TRBs and bypass the control transfer.5) Endpoints are configured and resources are allocated accordingly.6) Initialize the device registers. Predetermined device address is programmed in core.7) CPU waits for the connect-done event.8) Device enters into U0 LTSSM State.9) CPU triggers Host VIP model to issue DSP Disconnect10) Host Issues line-reset11) Device MPHY detects the line-reset12) Device controller resets the local MPHY and enters into RxDetect Reset LTSSM state.13) Host and device exchange the RRAP sequence for DSP Disconnect14) Device controller resets the local MPHY and ready to reconnect.15) Host and device exchange the RRAP sequence16) LTSSM transition from RxDetect > Polling > U017) CPU passes data to the VIP through VRI function call.18) CPU triggers the VIP to start the bulk transfer through VRI19) Endpoint start transfer command fetches the data TRB. 20) CPU waits to complete the bulk transfer event.21) CPU uses the VRI function call to implement the scoreboard mechanism22) Based on packet comparison, test case Pass/Fail.

6.3 USB3 USP Disconnect TestcaseUSP Disconnect test (Refer 5.6.1 of USB3 specification for detailed explanation)Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) RRAP commands are exchanged in the RxDetect LTSSM state4) Setup The Device TRBs and bypass the control transfer.5) Endpoints are configured and resources are allocated accordingly.6) Initialize the device registers. Predetermined device address is programmed in core.7) CPU waits for the connect-done event.8) Device enters into U0 LTSSM State.9) Device MPHY Issues line-reset10) Host MPHY detects the line-reset11) Device controller resets the local MPHY and enters into RxDetect Reset LTSSM state.12) Device is ready to reconnect.13) Host and device exchange the RRAP sequence14) LTSSM transition from RxDetect > Polling > U015) CPU passes data to the VIP through VRI function call.16) CPU triggers the VIP to start the bulk transfer through VRI17) Endpoint start transfer command fetches the data TRB. 18) CPU waits to complete the bulk transfer event.19) CPU uses the VRI function call to implement the scoreboard mechanism20) Based on packet comparison, test case Pass/Fail.

6.4 USB3 Hot Reset Test-TBD-

6.5 USB3 U0_to_Recovery_to_U0 TestRecovery is LTSSM state, if entered, retraining on the port required.Test steps:1) Disable Scrambling and set scaledown mode to reduce link-training time for simulation2) CPU enables the USB3 feature through programming 3) RRAP commands are exchanged in the RxDetect LTSSM state4) Setup The Device TRBs and bypass the control transfer.5) Endpoints are configured and resources are allocated accordingly.6) Initialize the device registers. Predetermined device address is programmed in core.7) CPU waits for the connect-done event.8) Entry into U0 LTSSM State9) Link request to enter into Recovery LTSSM state (LTSSM U0 > Recovery)10) Retrain and entry into U0 LTSSM state (LTSSM Recovery > U0)11) CPU passes data to the VIP through VRI function call.12) CPU triggers the VIP to start the bulk transfer through VRI13) Endpoint start transfer command fetches the data TRB. 14) CPU waits to complete the bulk transfer event.15) CPU uses the VRI function call to implement the scoreboard mechanism16) Based on packet comparison, test case Pass/Fail7 Error Scenerios/Negative Test7.1 Data Packet Error1) CRC 32 error2) Sequence number error3) Data packet length error4) Actual data payload error7.2 Header Packet Error1) CRC 5 error2) CRC 16 error3) Header packet framing symbol error4) Header packet sequence number error5) Data packet start framing symbol error6) Data packet end framing symbol error7) Data packet abort framing symbol error 7.3 Link Command Packet Error1) CRC5 error2) Link command framing3) Symbol error4) Different link command error5) Link command sequence number error7.4 Training Sequence Error1) Corruption of training sequence symbols2) Corruption of K code

7.5 Physical layer error1) Disparity error2) 8b10b Error8 Software Sequence Details8.1.1.1 Test Steps:1) Perform the Bulk Transfer as mentioned in 2.4.6.1 or 2.4.6.2 or 2.4.7.1 respectively for FS, HS & SS mode2) Enable the Phy Suspend Enable bits (SUSPENDUSB20, ENBLSLPM) in the GUSB2PHYCFG register and GUSB3PIPECTL (SUSPENDENABLE) bit3) Write 0 into the USBCMD.Run_Stop bit.4) Write into the Denali to Put the controller into the Desired low power state (L1/L2/U1/U2/U3) by writing into PORTSC.PLS bits and PORTSC.LWS bit 1 3.5) Check the Entry into the desired state by checking the register bits DSTS.Link_State6) Check the Entry into the desired state by checking the register bits PORTSC.PLS7) If Hibernation is enable, follow the hibernation entry steps as mentioned in the Synopsys DesignWare core DataBook 12.2.3.28) Exit the hibernation state as per the Synopsys DesignWare core DataBook 12.2.3.4 or 12.2.2.3 depending upon the suspend exit event (Resume/ Remotewkup/ Reset) For Reset : Initiate USB_RESET from VRI before step 6 For Resume : Initiate Resume from VRI before step 6 For Remote Wkup : Initiate the Remote Wkup event from the DUT after step 6, by writing RECOVERY into the DCTL.LNKSTATE_CHNG_REQ register9) Check the Entry into the U0 state (DSTS.LINK_STATE)10) Perform the bulk transfer as mentioned in step 111) If Hibernation is enable, follow the hibernation entry steps as mentioned in the Synopsys DesignWare core DataBook 12.2.2.112) Exit the hibernation state as per the Synopsys DesignWare core DataBook 12.2.2.2 or 12.2.2.3 depending upon the suspend exit event (Resume/ Remotewkup/ Reset) For Reset : Set the PORTSC.PORT_RESET bit after step 7 For Resume : Set the PORTSC.PLS bit to U0 state and PORTSC.LWS bit 1, after step 7 For Remote Wkup : Initiate the Remote Wkup event from the VRI before step 713) Check the Entry into the U0 state (PORTSC.PLS)14) Perform the bulk transfer as mentioned in step 1

8.1.1.2 Device Mode Sequence1) Allocate the memory for the the different data structures2) Program the Scaledown register bits in GCTL to 2'b113) Write '1' to the GCTL.disscramble4) Write 0x8 to the GUSB2PHYCFG_0_USBTRDTIM (Synopsys Fix)5) Write 1 to the GCTL.PRTCAPDIR bit, to program the controller in device mode.6) Program the Device Speed in the DCFG Register.

8.1.1.3 Device Mode InitializationWrite the Data to be transmitted to the DUT_DATA_ADDR Space (for the Bulk IN transactions)Setup the Device TRB in the TR_ADDR Space for the BULKIN Transfer, as per Section 8.1.1 DWC Specs.Setup the Device TRB in the TR_ADDR Space for the BULKOUT Transfer, as per Section 8.1.1 DWC Specs. Device Tx Desc and CMD Registers Programming seq :Program the GTXFIFOSZ Register.Program the GEVNTADR Register with the Event_Ring Addr Pointer.Program the GEVNTSZ Register with the Event Ring Size.Program the DCFG.NUMP bit for the Interruptor Number for non-ep specific interrupt.Program the DCFG.DEVADDR for the Device Address.Program the DCTL.RunStop Register bit, to issue the Run Command.Set the DEVTEN.CONNECTDONEEVTEN bit, to enable the Connect Event Done Interrupt.8.1.1.4 EP_CONFIG - Start Configuration & SET EP CONFIGURATIONProgram the Configuration Parameters (Param 0, 1 & 2) for the EP, as per Section 7.3.2.5.1 DWC Specs.Program the DEPCMD Configuration Parameters to Start the New Configuration.Wait for the DEPCMD.CMDACT (Command Active) bit to go LOW.Program the DEPCMDPAR_0/1/2 Registers for the Configuration parameters selected for the EP0 (OUT).Program the DEPCMD Configuration Parameters to SET_EP_CONFIGURATION.Wait for the DEPCMD.CMDACT (Command Active) bit to go LOW.Repeat the steps 4, 5,6 for EP0 (IN) Repeat the steps 4, 5,6 for EP1 (BULK OUT) Repeat the steps 4, 5,6 for EP1 (BULK IN)

8.1.1.5 SET EP TRANSFER RESOURCE CONFIGURATION Repeat the Steps mentioned in the point e(6, 7, 8, 9) with DEPCMDPAR_0/1/2 as 0/0/1 for the DEPCMD as EP_TRANSFER_RESOUCE_CONFIGWait for the DEV CONNECT Interrupt (Connect Event Interrupt).Set the DEV_ADDR in the DCFG Register. Program the BULK_IN_TRANSFER a. Issue START TRANSFER COMMAND for the EP1-BULK_IN Physical EP, (similiar to steps e(4, 5, 6) with DEPCMD as START_TRANSFERDEPCMDPAR_2/1/0 = 0/TRB_ADDR_HI/TRB_ADDR_LO Issue the Start BULK_IN Transfer for EP1 from the Denali Host using VRI.Wait for the Transfer Complete Interrupt (Bulk_IN). Read the Data Received at Denali via VRI. Check and compare the Data Received at Denali and transmitted by DUT. 8.1.1.6 Program the BULK_OUT TRANSFER Issue START TRANSFER COMMAND for the EP1-BULK_OUT Physical EP, (similiar to steps e(4, 5, 6) with DEPCMD as START_TRANSFERDEPCMDPAR_2/1/0 = 0/TRB_ADDR_HI/TRB_ADDR_LO Issue the Start BULK_OUT Transfer for EP1 from the Denali Host using VRI.Wait for the Transfer Complete Interrupt. Check & Compare the data received.

9 Low Power Scenario/Tests (MVSIM/QUESTANLP)10 GLS Scenarios/tests

4

3

1

2

VIP

VAL

MEM

IP

AXI

4

MEM

1

AXI

2

IP

VIP

3

VAL