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A-UG-IPUTOPIA3MS-1.00
UTOPIA3MS
UTOPIA Level 3 MasterMegaCore Function
101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com
User GuideNovember 2001
ii Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide Copyright
Copyright © 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific devicedesignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise,the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names arethe property of their respective holders. Altera Corporation acknowledges the trademarks of other organizations for theirrespective products or services mentioned in this document, including the following: Verilog is a registered trademark of CadenceDesign Systems, Incorporated. Java is a trademark of Sun Microsystems Inc. Microsoft is a registered trademark and Windows isa trademark of Microsoft Corporation. ModelSim is a registered trademark of Model Technology Inc. Altera products areprotected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights.Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’sstandard warranty, but reserves the right to make changes to any products and services at any time withoutnotice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera Corporation. Alteracustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services. All rights reserved
About this User Guide
User Guide
This user guide provides comprehensive information about the Altera® UTOPIA Level 3 Master MegaCore® function (UTOPIA3MS).
Table 1 shows the user guide revision history.
� Go to the following sources for more information:
� Refer to the UTOPIA3MS readme file for late-breaking information that is not available in this user guide.
How to Find Information
� The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box, or click the right mouse button for a pull-down menu.
� Bookmarks serve as an additional table of contents.� Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.� Numerous links, shown in green text, allow you to jump to related
information.
Table 1. User Guide Revision History
Date Description
November 2001 Initial release.
Altera Corporation iii
About this User Guide UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
How to Contact Altera
For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources shown in Table 2.
Note:(1) You can also contact your local Altera sales office or sales representative.
Table 2. How to Contact Altera
Information Type Access USA & Canada All Other Locations
Altera Literature Services
Electronic mail [email protected] (1) [email protected] (1)
Non-technical customer service
Telephone hotline (800) SOS-EPLD (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time)
Fax (408) 544-7606 (408) 544-7606
Technical support Telephone hotline (800) 800-EPLD(7:00 a.m. to 5:00 p.m. Pacific Time)
(408) 544-7000 (1)(7:30 a.m. to 5:30 p.m. Pacific Time)
Fax (408) 544-6401 (408) 544-6401 (1)
On-line http://www.altera.com/mysupport http://www.altera.com/mysupport
FTP site ftp.altera.com ftp.altera.com
General product information
Telephone (408) 544-7104 (408) 544-7104 (1)
World-wide web site http://www.altera.com http://www.altera.com
iv Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide About this User Guide
Typographic Conventions
The UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide uses the typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue Meaning
Bold Type with Initial Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file.
Bold italic type Book titles are shown in bold italic type with initial capital letters. Example: 1999 Device Data Book.
Italic Type with Initial Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75 (High-Speed Board Design).
Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of Quartus II and MAX+PLUS II Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device with the BitBlaster™ Download Cable.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
� Bullets are used in a list of items when the sequence of the items is not important.
� The checkmark indicates a procedure that consists of one step only.
� The hand points to information that requires special attention.
� The angled arrow indicates you should press the Enter key.
� The feet direct you to more information on a particular topic.
Altera Corporation v
About this User Guide UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Abbreviations and Acronyms
AHDL Altera hardware description languageATM asynchronous transfer modeCPU central processing unitEDA electronic design automationEOP end of packetERR errorESB embedded system blockFIFO first-in first-outGbps gigabits per secondHDL hardware description languageI/O input/outputIP intellectual propertyLE logic elementLSB least significant bitLSByte least significant byteMbps megabits per secondMPHY multi-PHYMSB most significant bitMSByte most significant byteOC-12 optical carrier level 12OC-48 optical carrier level 48OSI open system interconnectionPC personal computerPHY OSI physical layerPLD programmable logic deviceRX receiveSOC start of cellSOP start of packetSPHY single-PHYTX transmitUTOPIA universal test & operations physical interface for ATMVHDL VHSIC hardware description languageVHSIC very high speed integrated circuit
vi Altera Corporation
Contents
About this User GuideHow to Find Information .............................................................................................................. iiiHow to Contact Altera .................................................................................................................. ivTypographic Conventions ..............................................................................................................vAbbreviations and Acronyms ...................................................................................................... vi
About this CoreGeneral Description .........................................................................................................................9Features .............................................................................................................................................9
Getting StartedDesign Walkthrough .....................................................................................................................11Obtaining & Installing the UTOPIA3MS ....................................................................................12
Downloading the MegaCore Function ...............................................................................12Installing the MegaCore Files ...............................................................................................12
Generating a Custom UTOPIA3MS ............................................................................................13Implementing the System .............................................................................................................14Simulating Your Design ................................................................................................................14
Using the Verilog HDL Demo Testbench ...........................................................................14Using the Visual IP Software ................................................................................................15
Synthesis, Compilation & Place & Route ...................................................................................15Using Third-Party EDA Tools for Synthesis ......................................................................15Using the Quartus II Development Tool for Compilation & Place-and-Route ............15
Licensing for Configuration .........................................................................................................16Performing Post-Routing Simulation ..........................................................................................16
SpecificationsPerformance ....................................................................................................................................18Interfaces & Protocols ....................................................................................................................19
UTOPIA Level 3 Interface .....................................................................................................19Atlantic Interface ....................................................................................................................19
Functional Description ..................................................................................................................20Data Flow (DIR) .....................................................................................................................20
TXUTOPIA3MS ..............................................................................................................20RXUTOPIA3MS ..............................................................................................................21UTOPIA Level 3 Block ..................................................................................................23FIFO Buffer .....................................................................................................................23
Bus Parity (PRTY) ..................................................................................................................23
Altera Corporation vii
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide Contents
Interface Bus Width ...............................................................................................................24UTOPIA Data Width (UDAT) ......................................................................................24Atlantic Data Width (ADAT) .......................................................................................24FIFO Buffer (FIFO) .........................................................................................................24
Cell Length (CLEN) ...............................................................................................................25PHY Configuration ................................................................................................................28
Multi-PHY (MPHY) .......................................................................................................28Number of Ports (NPORTS) .........................................................................................28Multi-PHY Address Translation (ATRANS) .............................................................28Direct Status Indication Mode (DSTAT) .....................................................................28
I/O Signals ......................................................................................................................................29Typical Configurations ..................................................................................................................32AC Timing .......................................................................................................................................36
viii Altera Corporation
About this Core
User Guide
About this Core
1
General Description
The UTOPIA Level 3 Master MegaCore® function (UTOPIA3MS) is designed for use in asynchronous transfer mode (ATM) devices that transfer data to and from physical layer (PHY) devices using the UTOPIA Level 3 interface, as defined by the ATM Forum.
The UTOPIA level 3 interface specifies an operating frequency of up to 104 MHz, and a data path width of 8, 16, or 32 bits resulting in data transfer rates of up to 832 Mbps, 1.6 Gbps, or 3.2 Gbps, respectively. Typical applications for the UTOPIA3MS include: OC-48, quad OC-12, or 16 × OC-3 line rates.
The UTOPIA3MS is compliant with all applicable standards, including:
� ATM Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November 1999.
� Altera® Corporation, AtlanticTM Interface Specification.
Features � Configurable for receive or transmit directions� Supports single-PHY (SPHY) and multi-PHY(MPHY) operation� Configurable for up to 31 devices in MPHY mode� Optional configuration of port/address map� Configurable UTOPIA data width of 8, 16, or 32 bits� Configurable Atlantic slave interface data width of 8, 16, 32, or 64 bits� Configurable cell transfer length� Optional parity error detection� Optional direct status indication
Altera Corporation 9
Notes:
Getting Started
User Guide
Getting Started
22
Getting Started
This section describes how to obtain a variant from the UTOPIA Level 3 Master MegaCore® function (UTOPIA3MS). It explains how to install the UTOPIA3MS on your PC, and walks you through the process of implementing the variant in a design.
You can test-drive a UTOPIA3MS using the Altera® OpenCore® feature—within the Quartus® II software—to instantiate it, to perform place-and-route, to perform static timing analysis, and to simulate it using a third-party simulator, within your custom logic. You only need licenses when you are ready to generate programming files.
Design Walkthrough
This design walkthrough involves the following steps:
1. Obtaining and installing the UTOPIA3MS MegaCore function.
2. Generating a custom UTOPIA3MS for your system using the Altera MegaWizard® Plug-In.
3. Implementing the rest of your system using AHDL, VHDL, or Verilog HDL.
4. Simulating the UTOPIA3MS within your design.
5. Synthesis, compilation, and place-and-route.
6. Licensing the UTOPIA3MS to configure the device.
7. Performing post-routing simulation.
The instructions assume that:
� You are using a PC � You are familiar with the Quartus II software.� The Quartus II software (the newest version) is installed in the default
location.� You are using the OpenCore feature to test-drive a UTOPIA3MS, or
you have licensed it.
Altera Corporation 11
Getting Started UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Obtaining & Installing the UTOPIA3MS
To start using the UTOPIA3MS, you need to obtain the MegaCore package, which includes the following:
� Data sheet� User guide� Atlantic interface functional specification� MegaWizard Plug-In
– Encrypted gate-level netlist– Place-and-route constraints (where necessary)– Secure RTL simulation model
� Demo testbench� Access to problem reporting system
Downloading the MegaCore Function
If you have Internet access, you can download the UTOPIA Level 3 MegaCore function from the Altera web site. Follow the instructions below to obtain the core via the Internet. If you do not have Internet access, you can obtain the core from your local Altera representative.
1. Point your web browser at http://www.altera.com/IPmegastore.
2. In the IP MegaSearch keyword field type UTOPIA.
3. Click the link for the UTOPIA Level 3 Master MegaCore function.
4. On the product page, click the Free Test-Drive icon.
5. Follow the on-line instructions to download the function and save it to your hard disk.
Installing the MegaCore Files
Use the MegaWizard Plug-In to generate the files and install them on your PC. The following instructions describe this process.
For UNIX systems, you must have Java runtime environment version 1.3 before you can use the MegaWizard Plug-In. You can download this file from the Java web site at http://www.java.sun.com.
For Windows, follow the instructions below:
1. Click Run (Start menu).
12 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingGetting Started
2
Getting Started
2. Type <path name>\<filename>.exe, where <path name> is the location of the downloaded UTOPIA3MS and <filename> is the filename of the UTOPIA3MS. Click OK.
3. The MegaCore Installer dialog box appears. Follow the MegaWizard Plug-In instructions to finish the installation.
Generating a Custom UTOPIA3MS
This section describes the design flow using the UTOPIA Level 3 Master MegaCore function and the Quartus II development system. A MegaWizard Plug-In is provided with the UTOPIA3MS. The MegaWizard Plug-In Manager—used within the Quartus II software—allows you to create or modify design files to meet the needs of your application. You can then instantiate the UTOPIA3MS in your design file.
To create a custom UTOPIA3MS using the MegaWizard Plug-In, follow these steps:
1. Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In Manager command (Tools menu) in the Quartus II software. The MegaWizard Plug-In Manager dialog box is displayed.
� Refer to Quartus II Help for detailed instructions on how to use the MegaWizard Plug-In Manager.
2. Specify that you want to create a new custom variant and click Next.
3. On the second page of the MegaWizard Plug-In, open the Communications folder, and select the UTOPIA3MS from the UTOPIA folder.
4. Choose the type of output files (language), specify the folder and name for the files the MegaWizard Plug-In creates, and click Next.
5. Select the optional parameters and choices that you require.
� If your chosen variant (configuration) is not included as part of the downloaded package, the MegaWizard Plug-In generates the necessary text to request this variant. Forward this text to [email protected] for processing.
6. The final screen lists the design files created by the MegaWizard Plug-In, and indicates the location of the simulation models for the selected variant. Click Finish.
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Getting Started UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Implementing the System
Once you have created/obtained your custom UTOPIA3MS, you are ready to implement it. You can use the files generated by the MegaWizard Plug-In, and use the Quartus II software or other EDA tools to create your design. Table 1 lists the generated files.
Note: (1) AHDL output file creation is not supported in the UTOPIA3MS v1.0.0 MegaWizard Plug-In. If AHDL output
files are required, please file a request through http://www.altera.com/mysupport.
Simulating Your Design
Altera provides three models to be used for functional verification of the UTOPIA3MS within your design. A Verilog HDL demo testbench, including scripts to run it, is also provided. This demo testbench used with the ModelSim-Altera simulation tool demonstrates how to instantiate a model in a design.
To find the simulation models for your selected variant, refer to the last page of the MegaWizard Plug-In Manager. These models and the demo testbench are located on your hard drive, the paths are:
� sim_lib/<variant>/modelsim_verilog/� sim_lib/<variant>/modelsim_vhdl/� sim_lib/<variant>/visual_ip/ � sim_lib/<variant>/test/
� <variant> is a unique code (aotXXXX_#_utopia3ms) assigned to the specific configuration requested through the MegaWizard Plug-In.
Using the Verilog HDL Demo Testbench
The demo testbench includes some simple stimulus to control the user interfaces of the UTOPIA3MS. Each UTOPIA3MS variant includes scripts to compile and run the demo testbench using a variety of simulators and models.
Table 1. MegaWizard Plug-In Files
Description Verilog HDL VHDL
Design File Wrapper .v .vhd
Sample Instantiation _inst.v _inst.vhd
Black Box Module _bb.v –
Symbol files for the Quartus II software used to instantiate the UTOPIA3MS into a schematic design
.bsf .bsf
An encrypted HDL netlist file .e.vqm.v .e.vqm.v
14 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingGetting Started
2
Getting Started
Using the Visual IP Software
The Visual IP software facilitates the use of Visual IP simulation models with third-party simulation tools. To view a simulation model, you must have the Visual IP software installed on your system. To download the software, or for instructions on how to use the software, refer to the Altera web site at http://www.altera.com, and search for Visual IP. For examples of how to use the provided Visual IP model, refer to the sample scripts included with the demo testbench.
Synthesis, Compilation & Place & Route
After you have verified that your design is functionally correct, you are ready to perform synthesis and place-and-route. Synthesis can be performed by the Quartus II development tool, or by a third-party synthesis tool. The Quartus II software works seamlessly with tools from many EDA vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic.
Using Third-Party EDA Tools for Synthesis
To synthesize your design in a third-party EDA tool, follow these steps:
1. Create your custom design instantiating a UTOPIA3MS.
2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the UTOPIA3MS instantiation as a black box by either setting attributes or ignoring the instantiation.
3. After compilation, generate a netlist file in your third-party EDA tool.
Using the Quartus II Development Tool for Compilation & Place-and-Route
To use the Quartus II software to compile and place-and-route your design, follow these steps:
1. Select Compile mode (Processing menu).
2. Specify the compiler settings in the Compiler Settings dialog box (Processing menu) or use the Compiler Settings wizard.
3. Specify the input settings for the project. Choose EDA Tool Settings (Project menu). Select Custom EDIF in the Design entry/synthesis tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list.
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Getting Started UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
4. Add your third-party EDA tool-generated netlist file to your project.
5. Add any .tdf, .vhd, or .v files not synthesized in the third-party tool.
6. Add the pre-synthesized and encrypted .e.vqm.v file from your working directory, created by the MegaWizard Plug-In Manager.
7. Constrain your design as required.
8. Compile your design. The Quartus II compiler synthesizes and performs place-and-route on your design.
� Refer to Quartus II Help for further instructions on performing compilation.
Licensing for Configuration
After you have compiled and analyzed your design, you are ready to configure your targeted Altera PLD. If you are evaluating the UTOPIA3MS with the OpenCore feature, you must license the function before you can generate programming files. To obtain licenses contact your local Altera sales representative.
� All current UTOPIA3MS variants use a single license, with ordering code: PLSM-UTOPIA3MS.
Performing Post-Routing Simulation
After you have licensed the UTOPIA3MS, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-routing simulation of your design.
1. Open your existing Quartus II project.
2. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu).
3. Compile your design with the Quartus II software, refer to the “Using the Quartus II Development Tool for Compilation & Place-and-Route”section. The Quartus II software generates output and programing files.
4. You can now import your Quartus II software-generated output files (.edo, .vho, .vo, or .sdo) into your third-party EDA tool for post-route, device-level, and system-level simulation.
16 Altera Corporation
Specifications
User Guide
Specifications
3
Customized variants of the UTOPIA Level 3 Master MegaCore function (UTOPIA3MS) can be generated/requested using the MegaWizard® Plug-In within the Quartus® II software.
Table 1 shows the optional features available to generate all variants.
Notes:(1) FIFO buffer required, otherwise Atlantic data width must be equal to UTOPIA data
width.(2) Only applicable for multi-PHY configuration.(3) Only available for multi-PHY configuration with up to 4 ports.
� For detailed instructions on generating a custom UTOPIA3MS, refer to the “Generating a Custom UTOPIA3MS” section in the “Getting Started” chapter.
Table 1. Optional Features
Options Parameters Choices
Data flow DIR RX / TX
Bus parity PRTY Yes / No
Include FIFO buffer FIFO Yes / No
UTOPIA data width UDAT 8 / 16 / 32
Atlantic data width (1) ADAT 8 / 16 / 32 / 64
Cell length CLEN 52
53 (n/a for UTOPIA data width of 16 or 32)
54 (n/a for UTOPIA data width of 8 or 32)
56 (n/a for UTOPIA data width of 8 or 16)
Multi-PHY MPHY Yes / No
Number of ports (2) NPORTS 2 - 31 (only valid when MPHY = Yes)
Multi-PHY address translation (2)
ATRANS Direct (No translation) Custom (Port to address mapping)
Direct status mode (3) DSTAT Yes / No
Altera Corporation 17
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Performance Tables 2 to 4 show the estimated resource utilization and performance for these sample configurations. The utilization and performance information was generated with the Quartus II version 1.1 software, for an APEX 20K400E-1 device
Table 2 lists the estimated resources and speed of a one port RXUTOPIA3MS and TXUTOPIA3MS.
Table 3 lists the estimated resources and speed of a four port RXUTOPIA3MS and TXUTOPIA3MS.
Table 4 lists the estimated resources and speed of an RXUTOPIA3MS and a TXUTOPIA3MS without FIFO buffers.
Table 2. One Port Configuration Utilization Performance
Direction Parameters LE ESB fMAX (MHz)
RXUTOPIA3MS PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=No
318 3 144
TXUTOPIA3MS PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=No
340 3 138
Table 3. Four Port Configuration Utilization Performance
Direction Parameters LE ESB fMAX (MHz)
RXUTOPIA3MS PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No
1,215 12 106
TXUTOPIA3MS PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No
1,329 12 116
Table 4. Four Port No FIFO Buffer Configuration Utilization Performance
Direction Parameters LE ESB fMAX (MHz)
RXUTOPIA3MS PRTY=No, FIFO=No, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No
364 – 125
TXUTOPIA3MS PRTY=No, FIFO=No, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No
241 – 116
18 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
Interfaces & Protocols
Two interfaces, described below, support the UTOPIA3MS.
UTOPIA Level 3 Interface
The UTOPIA level 3 interface is an external protocol defined by the ATM Forum. Depending on the variant chosen (see Table 1), the UTOPIA3MS uses this interface to support: a data width of 8, 16, or 32 bits, SPHY or MPHY operation, bus parity, 52, 53, 54, or 56 octet cells, and direct status or polling mode.
If MPHY = No, the utxaddr[4:0]/urxaddr[4:0] address lines are not present. If DSTAT = No, the utxclav[3:1]/urxclav[3:1] ports are not present. If PRTY = No, the utxprty/urxprty ports are not present.
� For further information on this interface, refer to the ATM Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November 1999, available at http://www.atmforum.com.
Atlantic Interface
The AtlanticTM interface is a full-duplex synchronous bus protocol. The UTOPIA3MS supports data widths of 8, 16, 32, and 64 bits on the Atlantic interface. If PRTY = No, the arxpar/atxpar ports are not present.
If the chosen variant of the UTOPIA3MS is configured to include a multi-cell first in first out (FIFO) buffer for crossing the clock domain, the Atlantic interface operates as a slave, otherwise it operates as a master.
� For further information on this interface, refer to the Atlantic Interface Functional Specification, available at http://www.altera.com.
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Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Functional Description
This section describes the various optional features available to generate a UTOPIA3MS, and their respective functions. Some of these options are inter-dependent, and are therefore grouped and described accordingly.
Data Flow (DIR)
The UTOPIA3MS functions either as a transmitter (TXUTOPIA3MS) where data flows from the ATM device to the PHY device, or as a receiver (RXUTOPIA3MS) where data flows from the PHY device to the ATM device. Both the TXUTOPIA3MS and RXUTOPIA3MS have control signals for handshaking.
� In order for the UTOPIA3MS to act as a full-duplex, bidirectional transceiver, you need to instantiate two variants: a TXUTOPIA3MS and a RXUTOPIA3MS.
TXUTOPIA3MS
The TXUTOPIA3MS polls the PHY layer device to determine whether it is ready to receive data transfers. Polling is achieved when the TXUTOPIA3MS outputs the port address on the utxaddr bus. If the port can accept one or more complete ATM cells, the PHY device accepts the data transfer by driving the utxclav signal high, in accordance with the UTOPIA level 3 interface specification. Thus the TXUTOPIA3MS accepts cells from the Atlantic interface and sends them to the PHY layer device via the UTOPIA Level 3 interface. Figure 1 shows the TXUTOPIA3MS block diagram.
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UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
Figure 1. TXUTOPIA3MS Block Diagram
Note:(1) N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
RXUTOPIA3MS
The RXUTOPIA3MS polls the PHY layer device to determine whether it is ready to transfer data. Polling is achieved when the RXUTOPIA3MS outputs the port address on the urxaddr bus. If the port is ready to send one or more complete ATM cells, the PHY device completes the data transfer by driving its urxclav signal high, in accordance with the UTOPIA level 3 interface specification. Thus the RXUTOPIA3MS accepts cells from the PHY layer device via the UTOPIA Level 3 interface, and sends them to the Atlantic interface. Figure 2 shows the RXUTOPIA3MS block diagram.
FIFO
Port 0
UTOPIA
Block
utxaddr[4/3/2/1/0:0]
utxdata[31/15/7:0]utxprtyutxsoc
utxenb_n
utxclav[3/0:0]
utxclk
prty_err
FIFO
Port N* (1)
UTOPIALevel 3Interface
Global Signal
utxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
FIFO Port N* Clock Domain
Level 3
arxdat_0[63/31/15/7:0]
arxclk_0
arxpar_0
arxsop_0
arxerr_0
arxreset_n_0
arxena_0
arxdav_0AtlanticInterface
soc_0
soc_err_0Global Signalsoflw_err_0
arxdat_N*[63/31/15/7:0]
arxclk_N*
arxpar_N*
arxsop_N*
arxerr_N*
arxena_N*
arxdav_N*
arxreset_n_N*
AtlanticInterface
soc_N*
soc_err_N*Global Signalsoflw_err_N*
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Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 2. RXUTOPIA3MS Block Diagram
Note:(1) N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1.
� For further details on the transmitter or receiver functions, including timing information, refer to the ATM Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November 1999.
Both variants, TXUTOPIA3MS and RXUTOPIA3MS, are further divided into sub-blocks: the UTOPIA block and the FIFO buffer, as illustrated in Figures 1 and 2.
FIFO
Port 0
UTOPIA
Block
urxaddr[4/3/2/1/0:0]
urxdata[31/15/7:0]urxprtyurxsoc
urxenb_n
urxclav[3/0:0]
urxclk
prty_err
FIFO
Port N* (1)
UTOPIALevel 3Interface
Global Signal
urxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
FIFO Port N* Clock Domain
Level 3
atxdat_0[63/31/15/7:0]
atxclk_0
atxpar_0
atxsop_0
atxerr_0
atxreset_n_0
atxena_0
atxdav_0
soc_0soc_err_0Global Signals
AtlanticInterface
uflw_err_0
atxdat_N*[63/31/15/7:0]
atxclk_N*
atxpar_N*atxsop_N*
atxerr_N*
atxena_N*atxdav_N*
atxreset_n_N*
AtlanticInterface
soc_N*soc_err_N*Global Signalsuflw_err_N*
atxval_0
atxeop_0
atxval_N*
atxeop_N*
22 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
UTOPIA Level 3 Block
The UTOPIA block is the Input/Output (I/O) port for the UTOPIA level 3 interface. This block’s primary function is address polling and port selection. The following is a summary list of functions.
� Round-robin address polling� Back-to-back cell transfer� Cell-based handshaking� UTOPIA data bus parity checking
– Parity error indication
FIFO Buffer
The FIFO buffer is used for clock decoupling between the internal clock and the UTOPIA clock. The following is a summary list of functions.
� Data width conversion� Cell-based handshaking� Start of packet (SOP) error detection
– SOP indication– Spurious or missing SOP error indication
� End of packet (EOP) generation� Error (ERR) signal generation� Overflow indication� Underflow indication
For both UTOPIA and FIFO buffer sub-blocks, functionality is largely dependent on the chosen variant, see Table 1.
Bus Parity (PRTY)
The UTOPIA level 3 interface specifies that odd parity be passed.
In the transmit direction, where data flows from the Atlantic interface to the UTOPIA level 3 interface, the user must insert the parity (arxpar) lines for the correct parity to be placed on the utxprty line. The data bus (arxdat) and parity (arxpar) are monitored for errors. When an error is detected, the prty_err signal is asserted for one clock cycle.
In the receive direction, where data flows from the UTOPIA level 3 interface to the Atlantic interface, the data bus (urxdata) and parity (urxprty) lines are monitored for errors. When a parity error is detected, the prty_err signal is asserted for one clock cycle. The error signal (atxerr) on the Atlantic bus is asserted upon detecting the parity error until the end of the current cell.
Altera Corporation 23
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Interface Bus Width
UTOPIA Data Width (UDAT)
This feature sets the UTOPIA data bus width. In accordance with UTOPIA level 3 interface handshaking, the UTOPIA3MS supports the three following options:
� 8-bit UTOPIA data bus� 16-bit UTOPIA data bus� 32-bit UTOPIA data bus
� The UTOPIA data bus width can differ from the Atlantic data bus width.
Atlantic Data Width (ADAT)
This feature sets the Atlantic data bus width. Four choices are available: 8, 16, 32, or 64 bits.
� If the Atlantic data width chosen is not equal to the UTOPIA data bus width, the user MUST also choose the “Include FIFO buffer” option.
FIFO Buffer (FIFO)
The user has the option to include, or not include a FIFO buffer. If the user chooses the “Include FIFO buffer” option, one FIFO buffer is included for each port. The FIFO buffer is large enough to store at least four full cells.
If the FIFO is not included, the Atlantic interface signals are on the same clock domain as the UTOPIA clock.
24 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
Three global signals: soc_N*, soc_err_N*, and oflw_err_N* or uflw_err_N* are also included, and intended as additional optional logic to be used as required by the user. The soc_N* signal indicates a cell has been written to the FIFO buffer from either the UTOPIA level 3 interface via the RXUTOPIA3MS, or the Atlantic interface via the TXUTOPIA3MS. The soc_err_N* signal is asserted to indicate a start of cell (soc) error condition. A soc error indicates a start of packet (SOP) is incorrectly positioned. The oflw_err_N* indicates that a cell transfer has been initiated with the arxdav (TXUTOPIA3MS) deasserted thus indicating that the FIFO buffer cannot accept a full cell. This overflow-type condition causes the cell to be discarded. The uflw_err_N* indicates an underflow condition exists in the FIFO buffer. The uflw_err_N* signal is asserted when a read from the FIFO buffer is attempted and no data is available.
In the TXUTOPIA3MS, the soc_N*, soc_err_N*, and oflw_err_N* signals are synchronous to the arxclk_N*. The soc_N* signal is asserted when the arxsop_N* signal is sampled asserted on the Atlantic interface. The soc_err_N* signal is asserted when an error is detected on the arxsop_N* signal on the Atlantic interface.
In the RXUTOPIA3MS, the soc_N*, and soc_err_N* signals are synchronous to the urxclk. The uflw_err_N* is synchronous to the arxclk. The soc_N* signal is asserted two clock cycles after the urxsoc signal is sampled asserted. The soc_err_N* signal is asserted one clock cycle after an error is detected on the utxsoc signal.
Cell Length (CLEN)
The UTOPIA level 3 interface specifies a standard cell structure of 52 octets for all UTOPIA data widths. The following cell structures are also supported:
� 53 octets for the 8-bit UTOPIA data bus� 54 octets for the 16-bit UTOPIA data bus� 56 octets for the 32-bit UTOPIA data bus
The UTOPIA3MS converts cells formatted for the Atlantic into a cell structure used by the UTOPIA level 3 interface. Figures 3 to 7 show the cell structures used to transport data across the Atlantic interface.
Altera Corporation 25
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 3. 8-Bit Atlantic Interface, 52-and 53-Octet Cell Structures
Figure 4. 16-Bit Atlantic Interface, 52 and 54 Octet Cell Structures
H1
H2
H3
H4
P1
P2
P48
1 0
0
0
0
0
0
0
0
0
0
0
0 1
SOP EOP
H1
H2
H3
H4
P1
P2
P48
1 0
0
0
0
0
0
0
0
0
0
0
0 1
SOP EOP
HEC
0 0
52 octets 53 octets
7 0 7 0DAT DAT
H2
H4
P2
P48
1 0
0
0
0
0
0 1
SOP EOP
H1
H3
P1
P47
52 octets
H2
H4
P2
P48
1 0
0
0
0
0
0 1
SOP EOP
H1
H3
P1
P47
54 octets
HEC UDF
0 0
15 0 15 0DATDAT
26 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
Figure 5. 32-Bit Atlantic Interface, 52 and 56 Octet Cell Structures
Figure 6. 64-Bit Atlantic Interface, 56 Octet Cell Structure
Figure 7. 64-Bit Atlantic Interface, 52 Octet Cell Structure
Note: (1) In the case of a 52-octet cell, DAT [31:0] is discarded
H4
P4
P48
1 0
0 0
0 1
SOP EOP
H3
P3
P47
H2
P2
P46
H1
P1
P45
52 octets
H4
P4
P48
1 0
0 0
0 1
SOP EOP
H3
P3
P47
H2
P2
P46
H1
P1
P45
56 octets
HEC UDF UDF UDF
0 0
31 0 31 0DAT DAT
P8
P48
1 0
0 0
0 1
SOP EOP
P7
P47
P6
P46
P5
P45
H4
P4
P44
H3
P3
P43
H2
P2
P42
H1
P1
P41
56 octets with HEC
HEC UDF UDF UDF
63 0DAT
P8
P48
1 0
0 0
0 1
SOP EOP
P7
P47
P6
P46
P5
P45
H4
P4
P44
H3
P3
P43
H2
P2
P42
H1
P1
P41
56 octet without HEC
X X X X63 0
(1) (1) (1) (1)
DAT
Altera Corporation 27
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
PHY Configuration
The UTOPIA3MS can be configured for one of two modes of operation: SPHY or MPHY.
The SPHY configuration is a single data path, point-to-point connection between the ATM device and PHY device. Only one Atlantic interface port is included.
Multi-PHY (MPHY)
The MPHY configuration is a multi data path, point-to-point connection between the ATM device and PHY device. A dedicated Atlantic interface is included for each port.
Number of Ports (NPORTS)
If the chosen UTOPIA3MS variant includes the MPHY option, the user can select the number of ports, up to 31.
Multi-PHY Address Translation (ATRANS)
This feature offers two options for translation: Direct or Custom.
� Direct implies no translation. Ports are assigned in a sequential order, starting at zero.
� Custom implies port to address mapping. The user specifies an address for each port via the MegaWizard Plug-In.
Direct Status Indication Mode (DSTAT)
The UTOPIA3MS can be configured to operate in direct, or polling status mode.
For polling status mode, in the TXUTOPIA3MS, a single UTOPIA Clav (utxclav[0]) signal is polled to determine whether the PHY device can accept at least one entire cell; in the RXUTOPIA3MS, a single UTOPIA Clav (urxclav[0]) signal is polled to determine whether the PHY device can transmit at least one entire cell. This applies for any number of ports, from 2 to 31.
28 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
For direct status indication mode, in the TXUTOPIA3MS, four UTOPIA Clav (utxclav[3:0]) signals, one for each port, are polled to determine whether the PHY device can accept at least one entire cell; in the RXUTOPIA3MS, four UTOPIA Clav (urxclav[3:0]) signals, one for each port, are polled to determine whether the PHY device can accept at least one entire cell. The DSTAT mode is only possible when the chosen variant is an MPHY device with up to four ports.
I/O Signals Tables 5 to 9 list the I/O signals used in the UTOPIA3MS The active low signals are indicated by _n.
Table 5. UTOPIA Level 3 Transmit Interface
Signal Direction Description Configuration Requirement
utxclk Input Transfer/Interface clock None
utxreset_n Input Active low synchronous reset None
utxenb_n ATM to PHY Active low signal. Enables port selection in MPHY mode
None
utxaddr[n:0] ATM to PHY Address for MPHY device being selected MPHY = Yes
utxclav[0] PHY to ATM Cell buffer may accept at least one entire cell None
utxclav[3:1] PHY to ATM Cell buffer may accept at least one entire cell NPORTS <=4, DSTAT
utxdata
[31/15/7:0]
ATM to PHY Data bus UDAT = 32, 16, 8
utxprty ATM to PHY Odd parity calculated across data bus PRTY = Yes
utxsoc ATM to PHY Start of cell None
Table 6. UTOPIA Level 3 Receive Interface (Part 1 of 2)
Signal Direction Description Configuration Requirement
urxclk Input Transfer/Interface clock None
urxreset_n Input Active low synchronous reset None
urxenb_n ATM to PHY Enables port selection in MPHY mode None
urxaddr[4:0] ATM to PHY Address for MPHY device being selected MPHY = Yes
urxclav[0] PHY to ATM At least one entire cell is available in the FIFO buffer
None
urxclav[3:1] PHY to ATM At least one entire cell is available in the FIFO buffer
NPORTS <=4, DSTAT
urxdata
[31/15/7:0]
PHY to ATM Data bus UDAT = 32, 16, 8
urxprty PHY to ATM Odd parity calculated across data bus PRTY = Yes
Altera Corporation 29
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
urxsoc PHY to ATM Start of cell None
Table 7. Atlantic Receive Interface
Signal Direction Description Configuration Requirement
arxclk Input Clock FIFO = Yes
arxreset_n Input Active low synchronous reset FIFO = Yes
arxena Master to Slave Enables port selection in MPHY mode None
arxdat
[63/31/15/7:0]
Input Data bus ADAT = 64, 32, 16, 8
arxval Slave to Master Data valid FIFO = No
arxdav Slave to Master Cell buffer may accept at least one entire cell None
arxpar Input Odd parity calculated across data bus PRTY = Yes
arxsop Input Start of packet None
arxerr Input Data error None
Table 8. Atlantic Transmit Interface
Signal Direction Description Configuration Requirement
atxclk Input Clock FIFO = Yes
atxreset_n Input Active low synchronous reset FIFO = Yes
atxena Master to Slave Enables port selection in MPHY mode None
atxdav Slave to Master Cell buffer may accept at least one entire cell None
atxdat
[63/31/15/7:0]
Output Data bus ADAT = 64, 32, 16, 8
atxval Slave to Master Data valid FIFO = Yes
atxpar Output Odd parity calculated across data bus PRTY = Yes
atxsop Output Start of packet None
atxeop Output End of packet None
atxerr Output Data error. Current cell contains a soc or prty error and should be discarded.
None
Table 6. UTOPIA Level 3 Receive Interface (Part 2 of 2)
Signal Direction Description Configuration Requirement
30 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
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3
Table 9. Global Signals
Signal Direction Description Configuration Requirement
prty_err Output Parity error in current cell PRTY = Yes
soc[n-1:0] Output Start of cell has been written to the FIFO. FIFO = Yes
soc_err[n-1:0] Output Start of cell error. FIFO = Yes
oflw_err[n-1:0] Output FIFO overflow. Current cell is discarded. FIFO=Yes, DIR=TX
uflw_err[n-1:0] Output FIFO underflow FIFO=Yes, DIR=RX
Altera Corporation 31
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Typical Configurations
This section shows some common example configurations, illustrated in Figures 8 to 12.
Figure 8 shows an RXUTOPIA3MS and a TXUTOPIA3MS configured for one port, and for full-duplex operation.
Figure 8. One Port Configuration.
FIFO
Port 0
UTOPIA
Blockurxdata[31:0]
urxsoc
urxenb_n
urxclav[0:0]
urxclk
UTOPIALevel 3Interface
urxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
Level 3
RXUTOPIA3MS
FIFO
Port 0UTOPIA
Blockutxdata[31:0]
utxsoc
utxenb_n
utxclav[0:0]
utxclk
UTOPIALevel 3Interface
utxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
Level 3
TXUTOPIA3MS
atxdat_0[31:0]
atxclk_0
atxsop_0
atxerr_0
atxreset_n_0
atxena_0
atxdav_0
soc_0soc_err_0Global Signals
AtlanticInterface
uflw_err_0
arxdat_0[31:0]
arxclk_0
arxsop_0
arxerr_0
arxreset_n_0
arxena_0
arxdav_0AtlanticInterface
soc_0
soc_err_0Global Signalsoflw_err_0
atxval_0
atxeop_0
32 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
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3
Figure 8 shows an RXUTOPIA3MS configured for four ports.
Figure 9. RXTUOPIA3MS Four Port Configuration
FIFO
Port 0
UTOPIA
Block
urxaddr[1:0]
urxdata[31:0]urxsoc
urxenb_n
urxclav[0:0]
urxclk
FIFO
Port 1
UTOPIALevel 3Interface
urxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
FIFO Port 1 Clock Domain
Level 3
FIFO
Port 2
FIFO Port 2 Clock Domain
FIFO
Port 3
FIFO Port 3 Clock Domain
atxdat_0[31:0]
atxclk_0
atxeop_0atxerr_0
atxreset_n_0atxena_0atxdav_0
soc_0soc_err_0Global Signals
AtlanticInterface
uflw_err_0
atxdat_1[31:0]
atxclk_1
atxeop_1atxerr_1
atxreset_n_1atxena_1atxdav_1
soc_1soc_err_1Global Signals
AtlanticInterface
uflw_err_1
atxdat_2[31:0]
atxclk_2
atxeop_2atxerr_2
atxreset_n_2atxena_2atxdav_2
soc_2soc_err_2Global Signals
AtlanticInterface
uflw_err_2
atxdat_3[31:0]
atxclk_3
atxeop_3atxerr_3
atxreset_n_3atxena_3atxdav_3
soc_3soc_err_3Global Signals
AtlanticInterface
uflw_err_3
atxval_0atxsop_0
atxval_1atxsop_1
atxval_2atxsop_2
atxval_3atxsop_3
Altera Corporation 33
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 10 shows a TXUTOPIA3MS configured for four ports.
Figure 10. TXUTOPIA3MS Four Port Configuration
FIFO
Port 0
UTOPIA
Blockutxaddr[1:0]
utxdata[31:0]utxsoc
utxenb_n
utxclav[3/0:0]
utxclk
FIFO
Port 1
UTOPIALevel 3Interface
utxreset_n
UTOPIA Clock DomainFIFO Port 0 Clock Domain
FIFO Port 1 Clock Domain
Level 3
FIFO
Port 2
FIFO Port 2 Clock Domain
FIFO
Port 3
FIFO Port 3 Clock Domain
arxdat_0[31:0]
arxclk_0
arxsop_0
arxerr_0
arxreset_n_0
arxena_0
arxdav_0
soc_0soc_err_0oflw_err_0
arxdat_1[31:0]
arxclk_1
arxsop_1
arxerr_1
arxreset_n_1
arxena_1
arxdav_1AtlanticInterface
soc_1soc_err_1Global Signalsoflw_err_1
Global Signals
AtlanticInterface
arxdat_2[31:0]
arxclk_2
arxsop_2
arxerr_2
arxreset_n_2
arxena_2
arxdav_2
soc_2soc_err_2oflw_err_2
Global Signals
AtlanticInterface
arxdat_3[31:0]
arxclk_3
arxsop_3
arxerr_3
arxreset_n_3
arxena_3
arxdav_3
soc_3soc_err_3oflw_err_3
Global Signals
AtlanticInterface
34 Altera Corporation
UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide GettingSpecifications
Specifications
3
Figure 11 shows an RXUTOPIA3MS configured for four ports, without FIFO buffers.
Figure 11. RXUTOPIA3MS No FIFO Buffer Configuration.
Note:(1) The Atlantic interface signals are intended to be on the same clock domain as the UTOPIA clock.
urxaddr[1:0]
urxdata[31:0]urxsoc
urxenb_n
urxclav[0:0]
uclk
UTOPIALevel 3Interface
ureset_nUTOPIA
Block
Level 3
atxdat_0[31:0]
atxclk_0
atxeop_0atxerr_0
atxreset_n_0atxena_0atxdav_0Atlantic
Interface
atxdat_1[31:0]
atxclk_1
atxeop_1atxerr_1
atxreset_n_1atxena_1atxdav_1Atlantic
Interface
atxdat_2[31:0]
atxclk_2
atxeop_2atxerr_2
atxreset_n_2atxena_2atxdav_2Atlantic
Interface
atxdat_3[31:0]
atxclk_3
atxeop_3atxerr_3
atxreset_n_3atxena_3atxdav_3Atlantic
Interface
atxsop_0
atxsop_1
atxsop_2
atxsop_3
urxaddr[1:0]
urxdata[31:0]urxsoc
urxenb_n
urxclav[0:0]
uclk
UTOPIALevel 3Interface
ureset_nUTOPIA
Block
Level 3
atxdat_0[31:0]
atxclk_0
atxeop_0atxerr_0
atxreset_n_0atxena_0atxdav_0Atlantic
Interface
atxdat_1[31:0]
atxclk_1
atxeop_1atxerr_1
atxreset_n_1atxena_1atxdav_1Atlantic
Interface
atxdat_2[31:0]
atxclk_2
atxeop_2atxerr_2
atxreset_n_2atxena_2atxdav_2Atlantic
Interface
atxdat_3[31:0]
atxclk_3
atxeop_3atxerr_3
atxreset_n_3atxena_3atxdav_3Atlantic
Interface
atxsop_0
atxsop_1
atxsop_2
atxsop_3
Altera Corporation 35
Specifications UTOPIA Level 3 Master MegaCore Function (UTOPIA3MS) User Guide
Figure 12 shows a TXUTOPIA3MS configured for four ports, without FIFO buffers.
Figure 12. TXUTOPIA3MS No FIFO Buffer Configuration.
Note:(1) The Atlantic interface signals are intended to be on the same clock domain as the UTOPIA clock.
AC Timing For timing information on the UTOPIA level 3 interface, refer to the ATM Forum, UTOPIA 3 Physical Layer Interface Specification, af-phy-0136.000, November 1999, available at http://www.atmforum.com.
utxaddr[1:0]
utxdata[31:0]utxsoc
utxenb_n
utxclav[0:0]
uclk
UTOPIALevel 3Interface
ureset_nUTOPIA
Block
Level 3
arxdat_0[31:0]
arxclk_0
arxsop_0
arxerr_0
arxreset_n_0
arxena_0
arxdav_0AtlanticInterface
arxdat_1[31:0]
arxclk_1
arxsop_1
arxerr_1
arxreset_n_1
arxena_1
arxdav_1AtlanticInterface
arxdat_2[31:0]
arxclk_2
arxsop_2
arxerr_2
arxreset_n_2
arxena_2
arxdav_2AtlanticInterface
arxdat_3[31:0]
arxclk_3
arxsop_3
arxerr_3
arxreset_n_3
arxena_3
arxdav_3AtlanticInterface
36 Altera Corporation