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SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRIDVolume 1, Number 1, December 2014

SOP TRANSACTIONS ON POWER TRANSMISSION AND SMART GRID

Modeling of Discrete Systems Using StateCharts and Using VHDL Language inElectronic CircuitsT. C. Manjunath1*, Latha Parthiban21 HKBK College of Engineering, S.No. 22/1, Nagawara, Arabic College Post, Bangalore-452 Department of Computer Science, Pondicherry University, Lawspet, Pondicherry-605 008

*Corresponding author: [email protected]

Abstract:Design is a complex process which can be thought of as a top down refinement of a specifica-tion. The main aim of this algorithm is to propose a Verilog Hardware Description Language(VHDL) code generator for real-time systems. Its importance lies in giving graphical interfaceto the designer. Here, a discrete event model for a digital circuit using VHDL is designed andimplemented. This paper presents the design of state charts for 4 types of systems, viz., avoice-mailing system, a washing machine, a microwave oven and a fax system. Once the statechart is drawn, a software is designed which will automatically generate the correspondingVHDL code for it.

Keywords:

1. INTRODUCTION

VHDL [1] is a language for describing digital electronic systems. A VHDL is designed in this paperto fill a number of needs in the design process. Firstly, it allows description of the structure of a design,i.e. how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, itallows the specification of the function of designs using familiar programming language forms. Thirdly,as a result, it allows a design to be simulated before being manufactured, so that designers can quicklycompare alternatives and test for correctness without the delay and expense of hardware prototyping.

A digital electronic system is designed as a module with inputs and / or outputs. The electrical valueson the outputs are some function of the values on the inputs. Figure 1 shows an example of this view of adigital system as a structural description. The module F has two inputs, A and B, and an output Y. UsingVHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports. Oneway of describing the function of a module is to describe how it is composed of sub-modules. Each ofthe sub-modules is an instance of some entity, and the ports of the instances are connected using signals.Figure 1 also shows how the entity F might be composed of instances of entities G, H and I. This kind ofdescription is called a structural description. Note that each of the entities G, H and I might also have astructural description [2].

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Modeling of Discrete Systems Using State Charts and Using VHDL Language in Electronic Circuits

Figure 1. A digital electronic designed system

2. DESCRIBING BEHAVIOR

In many cases, it is not appropriate to describe a module structurally. One such case is a module whichis at the bottom of the hierarchy of some other structural description. For example, for designing a systemusing Integrated Circuit (IC) packages bought from an IC shop, there is no need to describe the internalstructure of an IC. In such cases, a description of the function performed by the module is required,without reference to its actual internal structure. Such a description is called a functional or behavioraldescription. To illustrate this, suppose that the function of the entity F in Figure 1 is the exclusive-orfunction. Then a behavioral description of F could be the Boolean function [3]:

Y = A.B + A.B (1)

More complex behaviors cannot be described purely as a function of inputs. In systems with feedback,the outputs are also a function of time. VHDL solves this problem by allowing description of behavior inthe form of an executable program.

3. DISCRETE EVENT TIME MODELING

Once the structure and behavior of a module have been specified, it is possible to simulate the moduleby executing its behavioral description. This is done by simulating the passage of time in discrete steps.At some simulation time, a module input may be stimulated by changing the value on an input port. Themodule reacts by running the code of its behavioral description and scheduling new values to be placedon the signals connected to its output ports at some later simulated time. This is called scheduling atransaction on that signal. If the new value is different from the previous value on the signal, an eventoccurs, and other modules with input ports connected to the signal may be activated [4].

The simulation starts with an initialization phase, and then proceeds by repeating a two-stage simulationcycle. In the initialization phase, all signals are given initial values, the simulation time is set to zero,

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and each modules behavior program is executed. This usually results in transactions being scheduled onoutput signals for some later time. In the first stage of a simulation cycle, the simulated time is advancedto the earliest time at which a transaction has been scheduled. All transactions scheduled for that time areexecuted, and this may cause events to occur on some signals. In the second stage, all modules whichreact to events occurring in the first stage have their behavior program executed. These programs willusually schedule further transactions on their output signals. When all of the behavior programs havefinished executing, the simulation cycle repeats. If there are no more scheduled transactions, the wholesimulation is completed [5, 6].

The purpose of the simulation is to gather information about the changes in system state over time.This can be done by running the simulation under the control of a simulation monitor. The monitor allowssignals and other state information to be viewed or stored in a trace file for later analysis. It may alsoallow interactive stepping of the simulation process, much like an interactive program debugger. We startthe description of an entity by specifying its external interface, which includes a description of its ports.So, the counter is defined as:entity count2 isgeneric (prop delay: Time := 10 ns);port (clock: in bit;q1, q0: out bit);end count2;This specifies that the entity count2 has one input and two outputs, all of which are bit values, that is,

they can take on the values 0 or 1. It also defines a generic constant called prop delay which can beused to control the operation of the entity (in this case its propagation delay). If no value is explicitlygiven for this value when the entity is used in a design, the default value of 10 ns will be used. Animplementation of the entity is described in an architecture body. There may be more than one architecturebody corresponding to a single entity specification, each of which describes a different view of the entity.

The behavioral description of the counter is written as:architecture behavior of count2 isbegincount up: process (clock)variable coun value : natural := 0;beginif clock = 1 thencount value:= (count value + 1) mod 4;q0


Figure 2. Designed counter system

Figure 3. A Designed voice mail controller system

suspended until another change occurs on clock. The two-bit counter is also designed alternatively as acombination of 2 flops and an inverter, as shown in Figure 3. This can be written in VHDL as:architecture structure of count2 iscomponent t flipflopport (ck : in bit; q : out bit);end component;component inverterport (a : in bit; y : out bit);end component;

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signal 00, ff1, inv ff0 : bit;beginbit 0: t flipflop port map (ck => dock, q => ff0);inv: inverter port map (a => ff0, y => inv ff0);bit 1 : t flipflop port map (ck => inv ff0, q => ff1);q0


Figure 4. Implementation scheme algorithm

The statechart given below describes the behavior of the voice-mail controller system. In the Figure3, states are represented by boxes with names. Transitions between states are represented by labeledarrows. The states are either basic states like FSM states (e.g. address, repeat) or structured statescontaining sub-statecharts, the latter being classified as either an AND (concurrent) state or an OR state;e.g. voice-mail is an OR-state and send is a basic state.

The designed AND-OR tree representation for the voice-mail is shown above:

5. IMPLEMENTATION SCHEME

A statechart implementation as given in [7] consists in implementing all terms for all state charttransitions, in a way that is similar to the conventional FSM implementation. An Implementation scheme,simplified algorithm and flow chart for the proposed technique are as follows [9]:Basic Proposed Program Algorithm:

1. Start

2. Input the no of OR and AND states.

3. Generate Schematic

4. Implement the VHDL code.

5. Compile the structure.

6. If compilation error then detect the error.

7. Display the VHDL code.

8. Stop

A semi-automatic washing machine is designed as a concurrent state chart. This example has hierarchy(OR) and concurrency (AND) both, but we concentrate only on the concurrency aspect here. The semi-automatic washing machine has two tubs, one that washes the clothes and the other that dries them. Nowthe process of washing and drying can take place simultaneously. Thus there exists Concurrency (AND)

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Figure 5. Flow-chart of the proposed algorithm

Figure 6. Design of state chart for a washing machine

property. To maintain concurrency in the VHDL Code we can have designed separate architecturesfor each sub-state. Thus the coding will be implemented using an entity, followed by the number ofarchitectures equal to the number of concurrent states.

A microwave oven is designed as a Hierarchical State Chart. The simplified State Chart would beas under. In the oven, food can either be heated OR cooled; both cannot take place simultaneously.Thus hierarchy (OR) property exists. To maintain hierarchy, we have used processor components whileimplementing the VHDL Code [10].

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Figure 7. Design of state chart for a microwave oven

6. FORMULATION OF AN GENERALIZED ALGORITHM FOR TRANSLA-TION OF STATE CHARTS TO VHDL

1. Start

2. Input the State-name, which can be declared as Entity.

3. Enter the set of Inputs, Outputs useful for interfacing with environment.

4. Define a Package containing all the signals useful for communication between the Statechart & itscomponents, basically the global signals.

5. Define hierarchical states as components (OR-states).

6. The component (OR-states) will have a separate Entity,

7. Architecture, etc for their sub states (AND-states) and more components for basic OR-states.

8. The concurrent states (AND-states) have their behaviors in separate architecture.

9. The main entity is mapped to the components (OR-state) of sub states.

10. Stop.

7. CODE TESTING

The Program code was tested for its accuracy & correctness using a Statechart for a Car Audio &Light System, which is as shown below. The reason this typical example was used was that it involvesall possible aspects of Statecharts [11]. Once parsing has completed and the internal object model isconstructed, VHDL generation begins. The challenges associated with VHDL generation can be brokeninto two general categories: converting Statechart syntax and semantics into functionally equivalentVHDL, and creating VHDL code that will synthesize properly into hardware with functional and timingequivalence with the rest of the system. The two types of problems are somewhat independent. Forexample, you can have a solid methodology for converting Statechart syntax and execution order intoVHDL, but after synthesis the hardware may not match as expected, or may induce timing incompatibilitywith other components in the system. Therefore, the two problems were discussed separately.

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8. CONCLUSIONS

A discrete event model for a digital circuit using VHDL is designed and implemented. The design ofstate charts for 4 types of systems, viz., a voice-mailing system, a washing machine, a microwave ovenand a fax system is herewith considered. A software is designed which will automatically generate thecorresponding VHDL code for it after designing the statechart.

References

[1] R. Amann and U. G. Baitinger, Optimal state chains and state codes in finite state machines,Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 8, no. 2,pp. 153149, 1989.

[2] S. Devadas, H.-K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, Mustang: State assignmentof finite state machines targeting multilevel logic implementations, Computer-Aided Design ofIntegrated Circuits and Systems, IEEE Transactions on, vol. 7, no. 12, pp. 12901299, 1988.

[3] P. J. Ashenden, The Designers Guide to VHDL, 2nd Edition. Morgan Kaufmann.[4] D. Drusinsky-Yoresh, A state assignment procedure for single-block implementation of state charts,

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 10, no. 12,pp. 15691576, 1991.

[5] P. Ashenden and P. Wilsey, Abstraction of concurrency and Communication in VHDL, TranslogicUSA Corp. EASE 5.1, Tutorial for VHDL users, 2002.

[6] K. Agsteiner, D. Monjau, and S. Schulze, Object-Oriented High Level of system components forgeneration of VHDL code, pp. 436441, 1995.

[7] D. Harel, Statecharts: A visual formalism for complex systems, Science of computer programming,vol. 8, no. 3, pp. 231274, 1987.

[8] J. J. Hooman, S. Ramesh, and W.-P. de Roever, A compositional axiomatization of Statecharts,Theoretical Computer Science, vol. 101, no. 2, pp. 289335, 1992.

[9] S. Ramesh, Efficient Translation of Statecharts to Hardware circuits, in VLSI Design, 1999.Proceedings. Twelfth International Conference On, pp. 384389, IEEE, 1999.

[10] Evita Tutorial for VHDL.[11] Xilinx Tutorial for Statemachine encoding.

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INTRODUCTIONDESCRIBING BEHAVIORDISCRETE EVENT TIME MODELINGSTATECHART MODELING IMPLEMENTATION SCHEME FORMULATION OF AN GENERALIZED ALGORITHM FOR TRANSLATION OF STATE CHARTS TO VHDL CODE TESTINGCONCLUSIONS References

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