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ZORAN Corporation, 1390 Kifer Road, Sunnyvale, CA 94086-5305Phone (408) 523-6500 Fax (408) 523-6501

ZORAN Proprietary

1

Data Sheet

ZR36966ELCG-D

DVD SoC

Preliminary version

Version 0.926 Dec 2005

ZORAN Proprietary


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Vaddis 966-D


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Vaddis 966-D

Data sheet

Copyright 2005 Zoran Corporation.

The contents of this document are proprietary and confidential information of Zoran Corporation.

The material in this document is for information only. Zoran Corporation assumes no responsibility for errors or omissions and

reserves the right to change, without notice, product specifications, operating characteristics, packaging, etc. Zoran Corporation

assumes no liability for damage resulting from the use of information contained in this document.

Dolby Digital, AC-3 and Pro Logic are registered trademarks of Dolby Laboratories. DTS and DTS Digital Surround

are registered trademarks of Digital Theater Systems, Inc. Macrovision is a registered trademark of Macrovision Corporation.

HDCD is a registered trademark of Pacific Microsonics. Meridian Lossless Packing and MLP are registered trademarks of

Meridian Audio Limited. Windows Media Audio and WMA are registered trademarks of Microsoft Corporation.

PictureCD is a registered trademark of Kodak. Acrobat Exchange and Acrobat Reader are registered trademarks of Adobe

Systems Incorporated. All other trademarks referenced in this document are owned by their respective companies.

Zoran cannot ship Vaddis units which incorporate Macrovision technology to any customer until that customer has been

approved by Macrovision. To obtain approval for shipment of Vaddis samples, a Macrovision Proprietary Material License

Agreement is required. Contact Macrovision Corporation to facilitate this agreement.

Table of Contents


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1 Introduction 4

2 Functional Overview 4

2.1 Feature List ........................................................................................................................................................................ 62.1.1 Disc loader control and bitstream processing ........................................................................................................... 6

2.1.2 Decoding.................................................................................................................................................................... 6

2.1.3 Post Processing.......................................................................................................................................................... 7

2.1.4 Interfaces ................................................................................................................................................................... 7

3 Unit Description 83.1 External interface............................................................................................................................................................... 8

3.2 CPU - Central Processing Unit .......................................................................................................................................... 9

3.3 PDU - Picture Decoding Unit .......................................................................................................................................... 10

3.4 VPU - Video Processing Unit .......................................................................................................................................... 10

3.5 ADP - Audio Data Processor ........................................................................................................................................... 10

3.6 Inter-Unit Interfaces......................................................................................................................................................... 10

4 Pin Description 114.1 Pin List............................................................................................................................................................................. 11

5 DC and AC Characteristics 305.1 Absolute Maximum Ratings ............................................................................................................................................ 30

5.2 Operating Range .............................................................................................................................................................. 30

5.3 DC Characteristics ........................................................................................................................................................... 30

5.4 Digital Interface Timing Specifications ........................................................................................................................... 31

5.4.1 Digital Video Interface Timing ................................................................................................................................ 33

5.4.2 AV Interface Timing................................................................................................................................................. 34

5.4.3 Audio Interface Timing ............................................................................................................................................ 35

5.4.4 SDRAM Interface Timing (Update with TRAS -7) ................................................................................................... 36

5.4.5 PNVM (NOR Type Flash, EPROM, OTP ROM and Masked ROM) Interface Timing ............................................ 38

5.4.6 SSC Interface Timing ............................................................................................................................................... 40

5.4.7 GPIO Interface Timing ............................................................................................................................................ 40

5.5 Analog Interface Specifications....................................................................................................................................... 41

6 Package information 41

Figures and Tables


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Table 1 Pin functions allocation 12

Table 56. DC characteristics 30

Table 57. Max loading capacitance 32

Table 58. Digital video interface timing 33

Table 59. AV (parallel port) timing 34

Table 60. Audio port timing 35

Table 62. SDRAM interface timing for PCLK of 135 MHz 36

Table 63. NOR type Flash, EPROM, OTP ROM and Masked ROM interface timing 38

Table 64. SSC serial interface timing 40

Table 65. GPIO interface timing 40


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1 IntroductionThe Vaddis 966-D is Zorans ninth-generation of IC product for entry-level consumer DVD players. This highly-integrated device

includes the full front-end disc controller including the RF amplifier stage, back-end decoder functions including MPEG-4, DivX

memory cards and integrated audio DACs.

2 Functional Overview

Audio

Front Panel

Concentrator

IR-RC

SPI/I2C/GPIO

4-16 Mbits

NOR

Flash

27 MHz

RESET

16/64 Mbits

SDRAM

Servo

TV

Monitor

5.1 ch

Speakers

2ch

Headphones

S/PDIF

Disc loader

TRAY

SPINDLE

SLED

OPU

ADP

AFE

MCU

PLL

CPU

VPU

Servo

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Vaddis 966-D Data Sheet 2. Functional Overview Page 5

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ProprietaryandConfidentialInforma

tion

This document describes the technical specification of the Vaddis 966-D disc loader controller, flashmemory card, and decoder device.

Supported Media: DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, CD-DA, CD-ROM, CD-ROM

(XA) CD-R and CD-RW discs.

Memory Cards: Secure Digital (SD), Memory Stick (MS and MS Pro), Compact Flash (CF Mem and IDE),PCMCIA, XD, SDIO, MultiMedia Card (MMC) and Smart Media (SM).

HDD: The Vaddis 966-D can interface to a Hard Disc, IDE mode.

Video and Audio formats: DVD-Video, CD-DA, VCD (Video-CD), SVCD (Super Video-CD), various

formats of MPEG 4 (including DivX), JPEG and compressed audio (MP3, AAC, WMA).

FE Front End integration

The Vaddis 966-D integrates all of the common drive front-end components. It receives data from the discloader optical pick-up unit OPU, limit switches and other sensors and control the disc loader focus and

tracking coils, sled, spindle and tray motors through a servo amplifier external device(s). The Vaddis 966-D

implements all the signal processing, multi-pass ECC, EDC, track buffer management and servo functions

that result in an (error corrected) bitstream.


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2.1 Feature List

2.1.1 Disc loader control and bitstream processing

Single or differential analog RF input from the OPU

10 analog inputs for servo errors calculations and RF signals envelope monitoring

6 PWM actuators drive or control outputs which can be used e.g. for the tracking and focuscoils, for sled and spindle motors, programmed tray motion or external (analog) parameter

setting.

Processing of spindle and sled position read-back devices

All servo loop closure, closed loop control, jumps, disc identification and error handling. Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive

threshold calculations, Viterbi bit decision, defect detection, frame sync detection and

EFM/P conversion.

CD sub-code extraction and processing.

CD ECC for all CD types. CD EDC for Mode 1 discs

DVD ECC and EDC.

Track buffer and re-try management

2.1.2 Decoding

Single chip solution for playback of DVD-Video Video-CD, Super Video-CD, CD-DA, andMP3, WMA, MPEG 4, DivX or JPEG from flash cards, DVD-ROM, DVD-R, DVD-RW,

DVD+R, DVD+RW, CD-ROM, CD-R or CD-R/W discs.

Decoding and display of JPEG, MPEG-4, DivX, MPEG 1 and MPEG 2 still imagesequences.

Decoding of WMA, Dolby AC-3.

Decoding of MPEG 1 or MPEG 2 layer II mono, stereo, or multi-channel audio. Decoding ofMPEG 1 or MPEG 2 Layer 3 (MP3) mono and stereo audio (including low sampling rate).

PCM and LPCM audio playback from DVD-Video, Video-CD and CD-DA.

Decoding and playback of sub-picture (including Highlight), and closed captions (line 21)

data from DVD-Video discs. Decoding and playback of DivX sub-titles Interlaced and progressive digital and analog video output.

PAL playback of NTSC discs and NTSC playback of PAL discs.

Special modes support like pause, slow motion, fast forward, goto time and reverse.


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2.1.3 Post Processing

Audio down mixing, sample rate conversion, Dolby's Prologic II, Base Management and 3Denhancement.

Karaoke mixing of decoded audio and two channels of input audio.

De-jittering filtering of S/PDIF inputs using a high speed PLL and DTO.

On-chip OSD engine with 256 color (24-bit YUV) palette, up to 8 levels of transparency;and capability of blinking regions and vertical and horizontal scrolling.

On-screen and off-screen OSD memory regions for animation support.

1/4 pixel and 1/4 line pan&scan. Supported

Horizontal and vertical up- and down-scaling with polyphase two-tap vertical and horizontal

interpolation.

Letterbox and Pan-scan display aspect ratio conversion (16:9 to 4:3).

Frame rate conversion (e.g., 3/2 pull down) and format conversion (16:9, 4:3, 1:1).

EIA-608 compatible modulation of line 21 (NTSC) or line 22 (PAL) closed captions dataover the video output.

2.1.4 Interfaces

8-bit YUV 4:2:2 digital SD interlaced or progressive video output with optional embeddedsyncs.

Composite, Y/C, YUV or RGB SD interlaced analog video output or SD componentprogressive analog video output (using five 14 bits on-chip V.DACs)

Internally generated SD video sync signals and internally generated audio port clock signals.

6/18/20/24-bit I2S or EIAJ serial audio outputs. 16 bit I2S EIAJ serial audio input

2 to 8 channels audio output

2 channels audio input

S/PDIF output for compressed audio (including DTS) or reconstructed audio (according toIEC 60958 and IEC 61937).

Two S/PDIF inputs for compressed or PCM audio (according to IEC 60958 and IEC 61937).

Single 128 Mbits, single 64-Mbit, single 16-Mbits and dual 16 Mbits SDRAMs (16 bits data)

including power-down.

Direct interface (through servo amplifiers) to several types of disc loaders.

Direct interface to the following types of serial and parallel flash memory cards: SecureDigital (SD), Memory Stick (MS and MS Pro), Compact Flash (CF Mem and IDE),

PCMCIA, XD, SDIO, MultiMedia (MM) and Smart Media (SM).

3 line serial general purpose slave interface (SSC)

2 UART interfaces for CPU SW debug


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3 Unit Description

3.1 External interfaceThe main external interfaces of the Vaddis 966-D are shown in the next figure.

Figure 1. Vaddis 966-D main external i nterfaces

Audio

ADC DAC

TRAY

SPINDLE

SLED

OPU

Loader

ADP

AFE

DSP

MCU

PLL

CPU

VPU

SERVO

I96

S/PDIF

27 MHz

RESET

Digital Video

TV

Monitor

SDRAM

SRAM

(for debug)

NOR

FlashUARTs

Front Panel

Concentrator

Servo amp

SPI/I2C/IR-RC/GPIO

S/PDIF

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tion

3.2 CPU - Central Processing Unit

The CPU is the central processing unit of the Vaddis 966-D. It is based on a 16 bits Intel 186 instruction set

compatible licensed CPU core. The CPU executes from a NOR type Flash memory with 16 bit data bus.

Alternately, a compatible EPROM, PROM, OTPROM or masked ROM can be connected.

The CPU core has attached to it 2 KWords instruction/data cache to the flash, 1KWords data/instruction

cache to the SDRAM, 6KWords instruction ROM (most of it is dedicated to the DSP) shared with the DSP,

4KWords "scratch pad" data/instruction RAM and peripheral units mentioned below.

The core has internal real-time clock unit, two UART units, GPIO control unit and interrupt handler.

Most of the data transferred over the CPU_Bus are called CPU parameters. The CPU SW always writes and

reads 16 bits (or multiple of 16 bits transferred consecutively to/from the same CPU_Bus address) for each

parameter. CPU parameters written or read from the same address may or may not have the same name. In

the CPU parameters description in the following sections, only "active" bits are mentioned. All "non-active"

bits should be written with B0 or return B0 when read. It would be prudent for the CPU SW to ignore the

values read for of non-active bits. Non-active addresses should not be written to or read from at all.

CPU SW is responsible for user interface and player control, internal units set-up and control, navigation and

high level front end functions.

The CPU interfaces with the following external entities using GPIO functions: IR remote control receiver;

Audio ADCs and DACs; Serial flash memory; Other player chips and debug aids.


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3.3 PDU - Picture Decoding Unit

The PDU unit is mainly responsible for the decoding of MPEG video streams and reconstructing the coded

frames. It is made of two main parts: A dedicated programmable processor (DVP) and a dedicated HW

called PRU (picture reconstruction unit).

3.4 VPU - Video Processing Unit

The VPU is responsible for all video output processing and timing. It outputs 8 bit (U, Y V, Y interleaved)

digital interlaced or progressive SD video with separate syncs and optionally embedded syncs It can alsooutput interlaced composite, S- or component SD analog video, or progressive components SD analog video.

The VPU units have three operating modes: SD Interlaced when the digital and analog outputs are interlaced,

SD Progressive when the digital output is progressive. In this mode, the analog output can be either SD

interlaced or progressive. A two fields Deinterlacer can be used (as needed) for the decoded image. The third

mode is SD progressive digital output with a mixture of interlaced and progressive SD analog output.

3.5 ADP - Audio Data Processor

The ADP is the audio processing unit of the Vaddis 966-D.

All the ADP peripheral units are connected to the ADP core through the AP_Bus (audio peripherals bus).

The interrupt handler is also connected directly to the interrupt port of the ADP core.

3.6 Inter-Unit Interfaces

The main inter-unit interfaces are described below.

The CPU is connected to all BE units and all FE units (apart from the AFE, DRC and SERVO), using the

C_Bus. The number of data lines used is 16. The C_Bus signals are described in Section 336HError! Reference

source not found..

The MCU is connected to the following units: STP, ECC, EDC, DSP, CPU, VPU, ADP, DVP and PDU. For

testing and debug, the AFE is also connected to the MCU.

The PLL is generating several processing clocks signals, audio port master clock, and the reset signal,n_reset, that is used by all units.


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Vaddis 966-D Data Sheet 4. Pin Description Page 11

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tion

4 Pin Description

4.1 Pin List

The table below lists the pins, their functions, the direction or nature of each function (according to the legend

below). Following is the table legend:

I - standard input-only. O - standard active driver, with a 3-state option. I/O - bi-directional I/O pin, with a 3-

state option. AI - Analog input signal. AO - Analog output signal. AI/O - Analog connection. ID - input, not

sampled by PCLK. S - Power supply or ground.

Pins that are designated AI, S or ID should not be left not connected or floating.

Pins designame with 2 (PINNAME_2) marks the 2nd(or 3rd) appearance of this function.

GPIOs designated by a preceding I (IGPIO) means they can be use as interrupts to the CPU.


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Phone (408) 523-6500 Fax (408) 523-6501

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Table 1 Pin functions allocation

Pkg Pin Functions Dir

.

Description

Left wall

1 MEMDA[2] I/O PNVM/SRAM bi-directional data bus

FCUDA[2] I/O Flash card interface unit input/output signal FCUIF[4]


GPIO[0] I/O General purpose input/output, monitored/controlled bythe CPU if RS8BIT or RS8BIT16 is active






















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Description


11 GNDC S Digital core ground (of 1.8V and 3.3V supplies)



13 MEMDA[15] O PNVM/SRAM address bus outputs

MEMAD[9] O PNVM/SRAM address bus if RS8BIT is active

MEMAD_1 O PNVM/SRAM address bus if RS8BIT16 is active


14 VDDC S 1.8 V Digital core power supply

15 VDDP S 3.3 V Digital periphery power supply

16 MEMAD[16] O PNVM/SRAM address bus outputs

FCUAD[16] O Flash card interface unit output signal FCUIF[43]


GPIO[6]_2 I/O General purpose input/output, monitored/controlled bythe CPU if RS8BIT is active

17 MEMCS[1]# O PNVM/SRAM chip select (active low) output

MEMLSB O PNVM/SRAM l.s. byte select output

GPIO[5] I/O General purpose input/output, monitored/controlled bythe CPU

MEMCS[0]# O If BOOTSEL2 == B1 swap with MEMCS[1]#

FCUIF[29] O Flash card interface unit output signal




FGPIO[5] I/O General purpose input/output, monitored/controlled bythe V8 SW if RS8BIT is active


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.

Description

IGPIO[7]_2 I/O General purpose input/output, monitored/controlled bythe CPU. Can be used as an interrupt for the CPU

User only as output (see comment below: 340HRetentionlimitation on Pin 38) if RS8BIT is active



RS_PLLUBYP I PLLu (Level sampled during RESET. In normaloperation the pin must be low during RESET






FCUAD[12] I/O Flash card interface unit output signal FCUIF[39]












FCUAD[8] I/O Flash card interface unit output signal FCUIF[18]

RS_DECCFG I Dec Config indication input. Level sampled duringRESET



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.

Description

26 MEMWR# O PNVM/SRAM write enable (active low) output

FCUIF[0] O Flash card interface unit output signal




GPIO[6] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW if RS8BIT and RS8BIT16 arenot active




RS8BIT16 I Reset Selection 8bit mode in 16bit flash.

Level sampled during RESET

MEMWR# O PNVM/SRAM write enable (low) if RS8BIT is active



RS_SYSIND[1] I General purpose system configuration indication input.Level sampled during RESET




RS_ADDRSWAP I General purpose system configuration indication input.Level sampled during RESET





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.

Description


RS8BIT I Reset Selection 8bit only flash is used.

Level sampled during RESET

FCUAD[4] I/O Flash card interface unit input/output signal FCUIF[14]


RS_SYSIND[0] I General purpose system configuration indication input.Level sampled during RESET





RS_BOOTSEL2 I CPU SW boot (and execute) source selection. Levelssampled during RESET. If BOOTSEL2 is B1 CS#0and CS#1 are swapped.



RS_BOOTSEL1 I CPU SW boot (and execute) source selection. Levelssampled during RESET.



FGPIO[6] I/O General purpose input/output, monitored/controlled bythe V8 SW if RS8BIT and RS8BIT16 are both notactive. Use as output only.

IGPIO[7] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW. Can be used as an interrupt forthe CPU INT3. if RS8BIT and RS8BIT16 are bothnot active. Use as output only.

Use only as output (see comment below: 341HRetentionlimitation on Pin 38)


39 VDD S 3.3 V power supply

40 N/A I/O N/A

GPO[68] O General purpose output, controlled by the CPU


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Description

41 N/A I/O N/A


42 GND S Ground of 3.3 V supply

43 RAMADD[4] O SDRAM address bus output










Bottom wall









60 RAMCS[0]# O SDRAM chip select (active low)

RAMBA[1] O SDRAM bank select output

61 RAMBA[0] O SDRAM bank select output

62 RAMCS[1]# O SDRAM chip select (active low)


63 RAMRAS# O SDRAM row select (active low) output


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Description

64 RAMCAS# O SDRAM column select (active low) output



67 RAMWE# O SDRAM write enable (active low) output

68 RAMDQM O SDRAM data masking (active high) output

69 GNDPCLK S Digital ground of filtered 3.3 V supply for PCLK

70 PCLK O SDRAM clock output (same as internal processing

clock)

71 VDDPCLK S 3.3 V filtered digital power supply for PCLK

72 RAMDAT[8] I/O SDRAM bi-directional data bus





















93 VDDP S 3.3 V Digital periphery power supply (208 pin only)


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Description

94 RAMDQM2 O SDRAM data masking (active high) output

RAMCKE O Clock enable signal to the SDRAM (for power down)

GPO[66] O General purpose output, monitored/controlled by theCPU


96 GPIO[10] I/O General purpose input/output, monitored/controlled by

the CPU

SDI_PSC I Serial Data input for the DDX Core (supplymeasurement)

RAMCKE_2 O Second appearance ofRAMCKE

97 GPAIO I/O General purpose input/output, to/from the ADP SW

IGPIO[11] I/O General purpose input/output, monitored/controlled bythe CPU. Can be used as an interrupt for the CPU INT0.

98 APWM[7]_P O Audio PWM #7 Positive

GPIO[12] I/O General purpose input/output, monitored/controlled by

the CPU

VID[0] O Digital Video Out

99 APWM[7]_N O Audio PWM #7 Negative







APWM[6]_N O Audio PWM #6 Negative





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.

Description




GPIO[17] I/O General purpose input/output, monitored/controlled bythe CPU.


104 AIN[1] I Serial input of digital stereo audio

SPDIFIN[1] I S/PDIF receiver input for digital coded or reconstructedaudio data

IGPIO[18] I/O General purpose input/output, monitored/controlled bythe CPU. Can be used as an interrupt for the CPU INT1.

Right wall



PWMCO[5] O PWM4 output signal





CLK1 O CLK1

APWM[6]_P O Audio PWM #6 Positive




VSYNC# O Digital Video Output - vertical sync output signal




AOUT[3] O Serial output of digital stereo audio


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.

Description

HSYNC# O Digital Video Output - horizontal sync output signal




FGPIO[7] I/O General purpose input/output, monitored/controlled by

the V8 SW

IGPIO[23] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW. Can be used as an interrupt forthe CPU INT2.


APWM[2]_N O Audio PWM #2 Negative



VCLKx2 I/O Digital video clock input/output. 27 MHz (for SDinterlaced) or 54 MHz (for SD progressive)

MEMCS[1]# O If BOOTSEL2 == 0 and selected by IOCOnfig

MEMCS[0]# O If BOOTSEL2 == 1 and selected by IOCOnfig

COSYNC O Composite sync output. Active only when componentanalog output is selected

GPIO[24] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW








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Description







the CPU or DSP SW

117 GNDC-A2 S Digital core ground (of 1.8V and 3.3V supplies)

118 AMCLK I/O Audio Master Clock input/output. 128, 192, 256 or 384times the sampling frequency (programmable)


119 VDDP-A2 S 3.3 V filtered digital power supply for AMCLK

120 ALRCLK O Digital audio left/right select output for the audio port.Square wave, at the sampling frequency.Programmable polarity


121 ABCLK O Digital audio bit-clock output. Data onAOUT andAINis output or latched, respectively, with the rising orfalling (programmable) edge of this clock


122 SPDIFOUT O S/PDIF transmitter output for digital coded orreconstructed audio data



123 SPDIFIN[3] I S/PDIF receiver input for digital coded or reconstructedaudio data

AIN[2] I Serial input of digital stereo audio


124 GPIO[34] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW


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Description


RAMCKE_3 O Clock enable signal to the SDRAM (for power down)

DVDDAT[7] I DVD DSP interface input



VID[0]_2 O Digital Video Out




127 IGPIO[37] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW. Can be used as an interrupt forthe CPU INT4.

FGPIO[4] I/O General purpose input/output, monitored/controlled by

the V8 SW



CPUNMI_2 I CPU non-maskable interrupt input




129 GPIO[39] I/O General purpose input/output, monitored/controlled by

the CPU or DSP SW



130 GPIO[40] I/O General purpose input/output, monitored/controlled bythe CPU



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.

Description


FGPIO[0] I/O General purpose input/output, monitored/controlled bythe V8 SW

SSCRXD I SSC data input.


CPUNMI I CPU non-maskable interrupt input



SSCCLK O SSC clock output.




VID[6]_2O Digital Video Out

SSCTXD O Serial Interface output

134 IGPIO[44] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW. Can be used as an interrupt forthe CPU INT5.



136 DUPTD0 O Main debug UART data output


the CPU or DSP SWPWMCO[5]_3 O PWM5 output signal (for SCART control)

137 DUPRD0 I Main debug UART data input


138 DUPTD1 O Second debug UART data output


139 DUPRD1 I Main debug UART data input


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Description




142 RESET# ID Reset input (active low)

143 GNDA S Ground plane of internal PLL circuit

144 VDDA S 1.8 V Power supply for internal PLL circuit

145 XO AO Output to a crystal that is connected to XI. If a crystal isnot used at XI, XO must be left not connected

146 XI ID 27.000MHz clock generator or crystal input for the PLL

147 DAC5 AO CVBS/C/Y - Analog video output - can be selected tobe CVBS, C or Y.

148 GNDDACD S Ground for the video DACs 3.3 V analog power supply

149 DAC4 AO CVBS/G/Y - Analog video output that can be selectedto be CVBS, G or Y.

150 VDDDAC S 3.3 V Analog power supply for the video DACs

151 DAC3 AO CVBS/C/Y - Analog video output that can be selectedto be CVBS, C or Y.

152 DAC2 AO Y/R/V/C - Analog video output that can be selected tobe Y, or R/V or C.

153 VDDDAC S 3.3 V Analog power supply for the video DACs

154 DAC1 AO C/B/U - Analog video output that can be selected to beC or B or U.

155 RSET AI/O

Resistive load for gain adjustment of the DACs

156 GNDDABS2 S Common Ground for the video and SERVO DACs

Top wall

157 RFINP AI RF positive input signal (differential input) // RF inputsignal (single ended)

158 RFINN AI RF negative input signal (differential input) // RFreference input signal

159 VDDAFE S Analog AFE 3.3 V supply


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.

Description

160 ADCIN[A] AI ADC input signal (e.g. from OPU)

161 ADCIN[B] AI ADC input signal (e.g. from OPU)

162 VDDAFE S Analog AFE 3.3 V supply

163 ADCIN[C] AI ADC input signal (e.g. from OPU)

164 ADCIN[D] AI ADC input signals (e.g. from OPU)

165 ADCIN[J ] AI ADC input signals (e.g. from OPU)

166 ADCIN[E] AI ADC input signals (e.g. from OPU)

167 ADCIN[K] AI ADC input signals (e.g. from OPU)

168 ADCIN[F] AI ADC input signals (e.g. from OPU)

169 GNDAFE S Analog ADC (AFE) ground of 3.3 V supply

170 ADCIN[G] AI ADC input signals (e.g. from OPU)

171 ADCIN[H] AI ADC input signals (e.g. from OPU)

172 GND1AFE S Analog ADC (AFE) ground of 3.3 V supply

173 OPUREF AO VC - OPU reference voltage output

174 VREF AI/

O

Capacitive load for internal band-gap voltage

generation

175 RESLOAD AI/O

Resistive load for internal reference voltage generation

176 GNDAFER AI AFE analog reference voltage ground

177 VDDSAFE S Analog AFE 3.3 V supply shield

178 CDMD AI CD LASER monitor diode input

179 DVDMD AI DVD LASER monitor diode input

180 CDLD AO CD LASER diode drive output

181 DVDLD AO DVD LASER diode drive output

182 PWMCO[0] O PWM output signal focus PWM



RFDAT[0] I RF channel sample data input for RF by-pass

183 VDDPWMS S 3.3 V SERVO PWM power supply


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Description

184 PWMCO[1] O PWM output signal track PWM


DVDSTRB I AV bit strobe input. Programmble polarity

RFDAT[1] I RF channel sample data input for RF by-pass

185 GNDPWMS S SERVO PWMs ground of 3.3V supply

186 PWMCO[2] O PWM output signal spindle PWM


DVDVALID I AV data valid input for FE by-pass. Programmablepolarity

187 PWMCO[3] O PWM output signal sled PWM


DVDSOS I AV start of sector indication input for FE by-pass.Programmable polarity

188 PWMCO[4] O PWM output signal


DVDERR I AV error indication input for FE by-pass. Programmablepolarity

RFDAT[4] I RF channel sample data inputs for RF by-pass

189 IGPIO[54] I/O General purpose input/output, monitored/controlled bythe CPU. Can be used as an interrupt for the CPU INT6.

DVDREQ O AV data request output for FE by-pass. Programmable

polarity

RFDAT[5] I RF channel sample data inputs for RF by-pass



192 IGPIO[55] I/O General purpose input/output, monitored/controlled bythe CPU. Can be used as an interrupt for the CPU INT7.


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Description

FCUIRQ I Card interrupt input

RFCLK O RF channel sampling clock output for RF by-pass


FCURST O Card reset output


FCUWAIT# I Card wait (not ready) signal input FCUIF[30]


FCUCS[3]# O Flash card interface unit output signal


FCUCS[2]# O Flash card interface unit output signal


FCUSCLK O Flash card interface unit output signal - FCUIF[34]


FCUIOWR# O Flash card interface unit output signal - FCUIF[33]


200MEMCS[2]# O PNVM/SRAM chip select (active low) output


MEMMSB O PNVM/SRAM m.s. byte select output

FCUAD[20] O Flash card interface unit input/output signal FCUIF[50]


MEMAD[-1] O PNVM/SRAM address bus outputs lower address bit(byte select) in case of 8bit flash


202 MEMCS[0]# O PNVM/SRAM chip select (active low) output

FCUCS[0]# O Flash card interface unit output signal FCUIF[38]

MEMCS[1]# O If BOOTSEL2 == 1


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Description

203 MEMRD# O PNVM/SRAM read enable (active low) output

FCUOE O Flash card interface unit output signal




GPIO[8] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW only if RS8BIT is active

MEMDA[1] I/O PNVM/SRAM bi-directional data bus (if 160 pinpackage)



MEMDA[2] I/O PNVM/SRAM bi-directional data bus (if 160 pinpackage)



GPIO[9] I/O General purpose input/output, monitored/controlled bythe CPU or DSP SW only if RS8BIT is active

CLK1_2 O CLK1_2 only if RS8BIT is active

MEMDA[3] I/O PNVM/SRAM bi-directional data



Comments:

Retention limitation on Pin 38 it is forbidden to use this pin as input. Both functions on this pin FGPIO[6]andIGPIO[7]can be used as outputs without limitation.


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5 DC and AC Characteristics

This section does not include specs of the RF amplifier, servo amplifier and loader interface signals which

appear in the separate FE T-specs document.

5.1 Absolute Maximum Ratings

Storage Temperature -65C to +150C

VDDP, VDDP-IP,VDDP-A2, VDDDAC, VDDDACS -0.5V to + 4.6V

VDDAFERF, VDDAFES, VDDPWMS supply voltage to ground

VDDC, VDDA supply voltage to ground -0.5V to + 3.6V

DC voltage applied to digital outputs for high impedance output state -0.5V to +5.5V(all digital output pins apart from SDRAM, VID[7-0], VCLKx2 andS/PDIFOUT

pins)

DC voltage applied to digital outputs for high impedance output state -0.5V to +3.6V

(SDRAM, VID[7-0], VCLKx2 andS/PDIFOUTpins),

or analog output

DC voltage applied to digital inputs -0.5V to 5.5V

(all digital input pins apart from SDRAM, VID[7-0], VCLKx2 andS/PDIFOUT

and pins)

DC voltage applied to digital inputs -0.5V to 3.6 V

(SDRAM, VID[7-0], VCLKx2 andS/PDIFOUTand pins), or analog inputs)

DC output current, into output (apart from DACs) 20mA/output (total 200 mA)

DC input current -10mA to +3.0mA

NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device

failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended

periods may affect device reliability.

5.2 Operating Range

Temperature 0C < TA < +70C

VDDP, VDDP-IP, VDDP-A2, VDDDAC, VDDDACS 3.15V< VPP < 3.45V

VDDAFERF, VDDAFES, VDDPWMS Supply Voltage (3.3V supply)

VDDC, VDDA Supply Voltage (1.8V supply) 1.7 V< VCC < 1.9 V

5.3 DC Characteristics

Table 2. DC characteristi cs

Symbol Parameter Min Max Units Test Conditions

VIL Digital input low voltage -0.5 0.8 V

VIH Digital input high voltage 2 5.5 V


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Table 2. DC characteristi cs

Symbol Parameter Min Max Units Test Conditions

(for all input pins, apartfrom the SDRAM, VID[7-0],VCLKx2 and S/PDIFOUT)

VIH Digital input high voltage(for the SDRAM, VID[7-0],VCLKx2 and S/PDIFOUTpins)

2 3.6 V

VOL Digital output low Voltage - 0.4 V IOL = 2 mA

VOH Digital output high voltage

(for driven pins)

2.4 - V IOH = 0.4 mA

VOHP Digital output high voltage(for externally pulled up to5V pins)

3.5 - V 1 KOhm pull-up resistor, 50nSec after pin release

ICC18 Power Supply Current,1.8V supply

- 270 mA f =135 MHz

VCC = 1.9V

VPP = 3.45V

ICC33 Power Supply Current,3.3V supply

- 360 mA f =135 MHz

VPP = 3.45V

VCC = 1.9V

ILI Input Leakage Current -- 10 uA

ILIP Input Leakage Current(internally pulled pins)

25 180 uA Min value indicates the minstrength of the pull

CIN Input Capacitance - 10 pF

CIO I/O and OutputCapacitance

- 10 pF Garentee by design

5.4 Digital Interface Timing Specifications

The timing characteristics in this section are given from the external devices stand point.

When the timing depend on the process clock (PCLK), the min or max column is specified for 135 MHz. In

these cases, the Comment column indicate the dependency where P is one PCLK cycle.


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Device

Under Test OUTPUTINPUT

2.0V

0.8V

1.4V1.4V

0.8V

2.0V

2.4V

0.4V

During AC testing, inputs are driven at 0.4V and 2.4V levels. Unless

otherwise specified, switching times are measured between the 1.4V,

0.8V or 2.0V levels at the input/output.

Figure 2. AC testing input and output

During AC testing, unless otherwise specified, outputs are loaded as

described in this figure. Cmax is given in the following table.

Test PointFrom Output

Under Test

Cmax

Figure 3. Normal AC test load

Table 3. Max loading capacitance

Pins Cmax Comment

ABCLK ,ALRCLK 80 pF

VCLKx2 30 pF

SDRAM 15 pF

All other interfaces 50 pF

Note that the I/O HW of the Vaddis 966-Dlimit all digital outputs, apart from the SDRAM interface and (for

I76-H) the digital video port, to 40 MHz.


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5.4.1 Digital Video Interface Timing

Table 4. Digital video interface timing

Description Min [ns] Max [ns] Comment

tVCP VCLKx2 period 37 For 27 MHz

tVCH VCLKx2 high time 15 For 27 MHz

tVCL VCLKx2 low time 15 For 27 MHz

tVCP VCLKx2 period 18.5 For 54 MHz

tVCH VCLKx2 high time 5 For 54 MHz

tVCL

VCLKx2 low time 5 For 54 MHz

tVCR VCLKx2 rise time 4 For 27 or 54 MHz

tVCF VCLKx2 fall time 4 For 27 or 54 MHz

VCLKx2

tVCP

tVCH tVCL

tVCR

tVCF

Figure 4. VCLKx2 Timing


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VCLKx2

VID[7:0]

VSYNC

HSYNC

tVOD

tVOD

Figure 5. Digital video interface timing

5.4.2 AV Interface Timing

Table 5. AV (parallel port) tim ing


tDSTRB Time between two consecutiveDVDSTRB edges

40 4P

tDH, tDL DVDSTRB signal high and low 12 1.5P

tDOD DVDREQ output delay afterDVDSTRB 15 When synchronized

tDIS Input set-up time before DVDSTRB 9

tDIH Output hold time afterDVDSTRB 3


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Clock Timing

PCLK

tT

tT

tPCH

tPCL

Figure 6. AV Bitstream interface timing

5.4.3 Audio Interface Timing

Table 6. Audio port timing


tAUD0 AMCLK period 20

tAUD1 AMCLK high width 45% 55% Percentage of duty cycle ofAMCLK

tAUD2 AMCLK low width 45% 55% Percentage of duty cycle ofAMCLK

tAUD3 ABCLK period 80

tAUD4 ABCLK high width 45% 55% Percentage of duty cycle ofABCLK

tAUD5 ABCLK low width 45% 55% Percentage of duty cycle ofABCLK

tAUD6 AOUT andALRCLK delay time fromABCLK

25 Measured from selected samplingedge ofABCLK.

tAUD7 AIN set-up time beforeABCLK 15 Measured from selected sampling


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Table 6. Audio port timing


edge ofABCLK.

tAUD8 AIN hold time afterABCLK 15 Measured from selected samplingedge ofABCLK.

tAUD7

ALRCLK

AOUT

AIN

tAUD8

ABCLK

AMCLK

tAUD6

tAUD5tAUD4

tAUD3

tAUD0

tAUD1 tAUD2

Figure 7. Audio port tim ing

5.4.4 SDRAM Interface Timing (Update with TRAS -7)

Table 7. SDRAM interface timing fo r PCLK of 135 MHz


tOD Output delay 1 5

tIH Input hold 1.5

tIS Input set-up 1.4

tTR transition time 1

tPCH PCLK high 3.9

tPCL PCLK low 3.9


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tT

tT

tPCH tPCL

Figure 8. SDRAM clock timing


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PCLK

RAMADD

RAMRAS#

RAMCAS#

RAMWE#

RAMCS#

RAMDQM

RAMDAT

Write Data Read Data

tOD(min) tOD(min)

tOD(max) tOD(max)

tOD(max)tIH

tIS

Figure 9. SDRAM interface tim ing

5.4.5 PNVM (NOR Type Flash, EPROM, OTP ROM and Masked ROM) Interface Timing

Table 8. NOR type Flash, EPROM, OTP ROM and Masked ROM interface timing


tDIS MEMDA set-up time before MEMADchange (when XMIConfig[5]=B0), orMEMCS# de-activation (when

XMIConfig[5]=B1)

25

tDIH MEMDA hold time afterMEMAD change(when XMIConfig[5]=B0), orMEMCS#de-activation (when XMIConfig[5]=B1)

0


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MEMAD [20:0]

MEMCS#

MEMWR#

tDIH

MEMRD#

MEMDA [15:0]

Data Sampled

tDIS

Figure 10. PNVM read cyc le (when XMConfig[5] equal B1)

MEMAD [20:0]

MEMCS#

MEMRD#

MEMWR#

MEMDA [15:0] First Middle Last

tDIS

Data Sampled

tDIH

Figure 11. PNVM read cycle (when XMIConfig[5] equal B0)


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5.4.6 SSC Interface Timing

Table 9. SSC serial interface timing


tDIS SSCRXD input set-up time beforeSSCCLK sampling edge

3*P

tDIH SSCRXD input hold time afterSSCCLKsampling edge

3*P

tDOD SSCTXD output delay time afterSSCCLK non-sampling edge

0 8*P

tCLP SSCCLK period 20*PtCLD First SSCCLK edge afterSSCInterface-

Busy change from B0 to B1.8*P Guarantee by Design

5.4.7 GPIO Interface Timing

Table 10. GPIO interface timing


tCOD GPIO output signals delay afterGPIODirorGPIOData CPU parameters write

0 40

tRIS GPIO input signals set-up time beforeGPIOData CPU parameters read

0 30


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5.5 Analog Interface Specifications

6 Package informationGreen package


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