Variation AwareVariation Aware Application Scheduling Application Scheduling

in Multi-core in Multi-core SystemsSystems

Lavanya Subramanian, Aman KumarLavanya Subramanian, Aman Kumar

Carnegie Mellon UniversityCarnegie Mellon University

{lsubrama, amank}@andrew.cmu.edu{lsubrama, amank}@andrew.cmu.edu

Document MapDocument Map

• MotivationMotivation• Leakage PowerLeakage Power and and FrequencyFrequency Variations in Variations in

CMPCMP

• ProblemProblem• Application scheduling exploiting frequency Application scheduling exploiting frequency

variation and leakage per core in CMPsvariation and leakage per core in CMPs

• Related WorkRelated Work

• Proposed SchemeProposed Scheme• Unified Power Performance ApproachUnified Power Performance Approach

• MilestonesMilestones22

MotivationMotivation

• Variations in chip multi processors are a major concern. There are two components to this:• The die-to-die component.• The within-die component. At the

transistor/device level, these are variations in• Leff

• Vth

• These variations in Leff and Vth translate into frequency and leakage current variations at the micro-architecture level.

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Motivation Motivation (contd…)(contd…)

Why a UNIFIED Power/Performance approach??

For cores that can operate at a specific maximum frequency, there is a wide variation in the leakage profiles.

Analogously, for cores that have a certain leakage power, there is a wide spread in the maximum frequency characteristics. [3]

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ProblemProblem

• The perspective of a chip multi processor being a homogenous set of cores is hence not a practical one.

• A CMP has to be relooked as:• a collection of heterogeneous cores• each core operating at different

frequency• each core with a different power profile

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Related WorkRelated Work

• Work being done at UIUC, talks about a set of scheduling algorithms taking either power or performance in account but not both together.[1]

• The basic power efficiency inclined algorithm (VarP) tries to map applications onto the least leaky cores.

• The enhanced version of this (VarP+AppP) tries to map the highest dynamic power consuming applications onto the least leaky cores.

• Similarly, the performance centric algorithms (VarF) map applications onto the fastest cores.

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Proposed SchemeProposed Scheme

1.1. Rank the Rank the corescores in the order of the maximum in the order of the maximum frequencies.frequencies.

2.2. Obtain the static leakage power number for each Obtain the static leakage power number for each core (profiled statically at a nominal temperature)core (profiled statically at a nominal temperature)

3.3. Rank the Rank the applicationsapplications in the order of dynamic power in the order of dynamic power (obtained by static profiling on a core)(obtained by static profiling on a core)

4.4. For each application, starting from the highest For each application, starting from the highest dynamic power one, map the application onto the dynamic power one, map the application onto the core with the highest frequency, with the least core with the highest frequency, with the least leakage. This could be achieved by sorting the cores leakage. This could be achieved by sorting the cores in frequency and leakage bins/levels.in frequency and leakage bins/levels.

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MilestonesMilestones

• Milestone 1.1:• Building variability information into the CMP

simulator.• Static profiling of applications.

• Milestone 2:• Building a scheduler into the CMP simulator.

• Milestone 3:• Implementing and analyzing the proposed

scheme against the baseline algorithms.

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ReferencesReferences

[1] R. Teodorescu and J. Torrellas. Variation-aware [1] R. Teodorescu and J. Torrellas. Variation-aware application scheduling and power management for chip application scheduling and power management for chip multiprocessors. In multiprocessors. In ISCA’08: Proceedings of the 35th ISCA’08: Proceedings of the 35th annual InternationalSymposium on Computer annual InternationalSymposium on Computer ArchitectureArchitecture, 2008, 2008

[2] Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB [2] Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB in microprocessors. in microprocessors. IEEE Transactions on VLSI SystemsIEEE Transactions on VLSI Systems, , 13(10), Oct 200613(10), Oct 2006

[3] S. Borkar et. al., “Parameter variations and impact on [3] S. Borkar et. al., “Parameter variations and impact on circuits and micro-architecture,” Proc. DAC 2003, pp. 338-circuits and micro-architecture,” Proc. DAC 2003, pp. 338-342342

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Questions !!Questions !!

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