vedic multiplier6

ANALYSIS, COMPARISON AND APPLICATION OF VEDIC MULTIPLIERS

Figure 5.8 16-bit Modified Booth Multiplier Design

From the above Fig.5.8 it is clear that there is no carry propagation for the last Partial

product elements so , in the 16x16 bits Modified booth Multiplier there is no carry

propagation from one RCA to another RCA.

5.6 ATTRIBUTES OF MODIFIED BOOTH MULTIPLIER

1. Modified Booth Multiplier is based on the Modified Booth Algorithm.

2. Bit pair recoding technique is used to reduce the number of Partial Products.

3. At most for N-bit Modified Booth Multiplier N/2+1 partial products are generated

based on the triplets of the multiplier bits (i.e. bit pair recoding).

4. The number of RCA s for the design of the multiplier depends on the number of

partial products.

Department of ECE, SITAMS Page 1

32 BIT RCA

27 BIT RCA

25 BIT RCA

23 BIT RCA

21 BIT RCA

19 BIT RCA

17 BIT RCA

16 BIT RCA(FINAL

ADDER)R[31:16]....................................R[15].............................................................................R[0]


5. For Reduction of partial products a total of 8 RCA s are used and for final addition

of the sum vectors one RCA is used.

CHAPTER -6

COMPARISON OF MULTIPLIERS

This chapter deals with the design and performance comparison of the Vedic

Multipliers with the array and the Modified booth Multiplier.

6.1 DESIGN COMPARISON

Firstly all the Multipliers are compared based on their algorithm used, partial product

generation and partial product reduction.

6.1.1 Array Multiplier



I. Algorithm: An array Multiplier uses shift and add algorithm to get the

multiplication result of two numbers.

II. Partial product generation: N partial products are generated for an N x N Array

Multiplier using the AND gates.

III. Partial product reduction: Partial product reduction is done by summing up the

partial products using (N-1) number of (N-1) bit RCA array of adders and producing

sum and carry vectors.

IV. Final addition: The sum and carry vectors are reduced to final result using a ripple

carry adder (or any fast adder).

6.1.2 Modified Booth Multiplier

I. Algorithm: Booth Multiplier is based on the Modified Booth’s Algorithm.

II. Partial product generation: (N/2+1) partial products are generated for an N x N-bit

unsigned Multiplier by scanning three bits of the Multipliers. These three bits are: the

two bits from present pair; and a third bit from the higher order bit of an adjacent

lower order pair. After examining each triplet of bits, the triplets are converted by

booth logic into a set of five controls.

III Partial product reduction: Partial product reduction is done by summing up the

partial products using an (N/2+1) number of array of adders where the number of

adders in a given nth row is given by (2N-2(n-1)) (where n=1, 2, ... N/2+1) which

produces sum and carry vectors.

IV. Final addition: The sum and carry vectors are reduced to final result using an N-

bit Ripple Carry Adder (or any fast adder).

6.1.3 Vedic Multipliers

1. Based on Urdhva Tiryakbhyam Sutra

I. Algorithm: Uses Vedic multiplication sutra named Urdhva Tiryakbhyam Sutra.



II. Partial product generation: The partial products are generated by four N/2xN/2

Multipliers for an N x N Multiplier.

III. Partial product reduction: Two N-bit ripple carry adders are used for an N x N bit

multiplication producing sum and carry vectors.

IV. Final addition: The sum and carry vectors are reduced to final result using a ripple

carry adder (or any fast adder).

2. Based on Nikhilam Sutra

I. Algorithm: Uses Vedic multiplication Sutra named Nikhilam Sutra.

II. Partial product generation: (only for large number multiplication) N inverters

along with two N-bit RCA are used to generate the partial products.

III. Partial product reduction: One N bit RCA and an N/2 x N/2 bit Multiplier are

used to reduce the partial products which gives the final result and no need for the

final addition.

6.2 PERFORMANCE COMPARISON

Array, modified Booth and Vedic Multipliers are compared based on their

performance using the parameters Latency, Throughput, Area, Design complexity and

power.

Latency expresses the propagation delay of the combinational Multiplier

where as Throughput gives the speed of the combinational Multiplier. Area and power

parameters depends on the number of components used, while the design complexity

shows the types of the components used and the arrangement of the components

which determines the layout of the design.

6.2.1 Array Multiplier



I. Latency: The propagation delay of the array Multiplier depends on the signals

delay that propagates through the array of adders that form the multiplication array.

II. Throughput: As Latency of the design is more the Throughput of it is less.

III. Area: The array Multiplier uses more number of gates because for an NxN bit

multiplication there are N partial products to sum.

IV Power: As much area is occupied due to more number of components the power

dissipation is high in array Multiplier.

VI. Design complexity: Array Multiplier is regular in structure so layout for this

Multiplier can be developed easily but due to the arrangement of the adders in the

Multiplier it occupies more silicon area.

6.2.2 Modified Booth Multiplier

I. Latency: The propagation delay of the modified booth Multiplier is less when

compared to the Array Multiplier because the number of partial products of N x N-bit

multiplication is reduced to N/2+1 partial products which reduces the number of array

of adders in the design.

II. Throughput: As the propagation delay is reduced the speed of the Multiplier

design is increased when compared to Array Multiplier.

III. Area: As the number of partial products is reduced numbers of gates are also

reduced this effects the area to be reduced than an array Multiplier.

IV. Power: The power dissipation is less when compared to Array Multiplier as area

occupied by Modified booth Multiplier is less. However because of usage of large

number of adder cells the power consumption is more (but lesser when compared to

Array Multiplier.

V. Design complexity : The design complexity of booth Multiplier depends on

arrangement of the adders used for the partial product reduction .Using a structure

like Wallace tree makes the layout of the design difficult but using array of adder

Reduces the design complexity.



6.2.3 Vedic Multipliers.

1. Vedic Multiplier based on Urdhva Tiryakbhyam Sutra

I. Latency: Propagation delay of Vedic Multiplier is less when compared to Booth

Multiplier because for an N x N Multiplier only four N-bit partial products are

generated.

II. Throughput: As the propagation delay of the design is lesser than Modified

Booth Multiplier the speed of the Vedic Multiplier is greater than Modified Booth

Multiplier.

III. Area: As the number of partial products is reduced, numbers of gates are also

reduced this effects the area to be reduced than a Modified Booth Multiplier.

IV. Power: The power dissipation is lesser when compared to Modified Booth

Multiplier as area occupied by Vedic Multiplier is less.

V. Design complexity: As the Multiplier is structurally hierarchal the design

complexity gets reduced so, layout is easier to form.

2. Vedic Multiplier based on Nikhilam Sutra

Vedic Multiplier based on Nikhilam Sutra is an special case suitable only for large

case multiplication. All the parameters defined by assuming only large number

multiplication.

I. Latency: The propagation delay of the Multiplier is reduced further than Urdhva

Sutra based Multiplier as only two partial products are involved.

II. Throughput: As the propagation delay of the design is lesser than Urdhva Sutra

based Multiplier the speed of the Vedic Multiplier based on Nikhilam Sutra is greater

than Urdhva Sutra based Multiplier.

III. Area: As the numbers of partial products are reduced to two, numbers of gates

are also reduced this effects the area to be reduced than an Modified Booth Multiplier.



IV. Power: The power dissipation is lesser when compared to Urdhva Tiryakbhyam

Sutra based Multiplier as area occupied by Vedic Multiplier based on Nikhilam Sutra

is less.

V. Design complexity: As the Multiplier is structurally hierarchal the design

complexity gets reduced so, layout is easier to form.

CHAPTER - 7

APPLICATIONS OF VEDIC MULTIPLIER

This chapter presents two applications of Vedic Multiplier using Urdhva

Tiryakbhyam Sutra. The first application is a design of an IEEE 32 bit floating point

Multiplier and second application is a16 bit Squarer.

The first section presents an introduction to IEEE 32 bit floating point format, basic

Algorithm to multiply these number and design of the floating point Multiplier.

The second section presents a Squarer design which is a slight modification of the

Vedic Multiplier based on Urdhva Tiryakbhyam sutra.



7.1 IEEE 32 BIT FLOATING POINT NUMBER AND MULTIPLICATION

ALGORITHM

7.1.1 IEEE 32-bit Floating Point Format

In scientific notation, a floating point number A is represented in the following

format:

A = SarEa Eq. (7.1)

Where, Sa is called the Significant or Mantissa Ea is the Exponent

r is the radix or base of the number system which is binary (i.e. r = 2) for

digital systems

For representation in the above format, the real number (in decimal or binary

format) must be normalized i.e. there should be just one digit/bit to the left of decimal

point.eg: 456.7887 x 103 would be normalized to 4.567887 x 105. So here, mantissa

has value 4.5677887 while radix is 10 and exponent value is 5.

Similarly, in digital systems where radix is 2, the above number is represented

in binary in normalized form. The IEEE Standard 754 single precision (32-bit)

floating-point format [12], which is widely implemented in digital systems, uses 32

bits for floating point number representation. Out of the 32 bits, the MSB-bit is used

for indicating sign, next 8-bits for indicating integer exponent (biased by 127) and the

rest 23-bits for Mantissa. Also, there is an additional implicit MSB bit for mantissa

with value ‘1’.

MSB bit used for representing sign takes value of ‘1’ for negative numbers

and value ‘0’ to indicate positive number.

The value of 8-bit exponent ranges between 0 and 255. The exponent is

expressed in an excess 127 code (bias) so that its effective (true) value is determined

by subtracting 127 from the stored value. Thus, the range of effective values of the

exponent is -127 to 128, corresponding to stored values of 0 to 255, respectively. A

stored exponent value of 0 (Emin) serves as a flag indicating that the value of the



number is 0 (if the mantissa is 0) and for de-normalized numbers (if the mantissa is

nonzero). A stored exponent value of 255 (Emax) serves as a flag indicating that the

value of the number is infinity (if the mantissa is 0) and for ‘‘not a number’’ (if the

mantissa is nonzero)[11].

The mantissa is actually a 24-bit number (the binary point is to the right of the

most significant bit). The leading bit of the mantissa is always a ONE (except for de-

normalized numbers). As a result, when numbers are stored, the leading bit is omitted,

giving an extra bit of precision and effectively makes size of mantissa as 23

(including the sign bit used in MSB). So, a number 25.25 whose binary equivalent is

11001.01 when normalized becomes 1.100101 x 2+4 can be represented as in 32 bit

IEEE floating point format as

Sign Bit omitted MSB of mantissa (implicit)

0 1000_00111 100 1010 0000 0000 0000 0000

Exponent Mantissa (with implicit MSB 1)

(4 + 127 bias = 131)

7.1.1.1 Exceptional Cases

Using this encoding scheme, the largest number that can be represented is :

± (2-2-23)x2128 =±6.8x1038.Likewise, the smallest number that can be represented is :

±( 1.0)x2 -127 =±5.9x10-39.The IEEE standard reduces this range slightly to free bit

patterns that are assigned special meanings. In particular, the largest and smallest

numbers allowed in the standard are =±3.4x1038 and ± 1.2 x10-38 [11],[12],[13].

The freed bit patterns allow three, special classes of numbers: (1) ±0 is defined

as all of the mantissa and exponent bits being zero. (2) ± ∞is defined as all of the

mantissa bits being zero, and all of the exponent bits being one. (3) A group of very

small de-normalized numbers (subnormal) between± 1.2 x10-38and. ±1.4 x10-45 these



are lower precision numbers obtained by removing the requirement that the leading

digit in the mantissa be a one. Besides these three special classes, there are bit

patterns that are not assigned a meaning, commonly referred to as NaNs (Not a

Number).

The IEEE standards specifies following special values: ±0 ,de-normalized

numbers, ±∞ and NaN (Not a Number). These special values are encoded with

exponents of emin-1 or emax+1.The following table7.1 lists the special values

Table 7.1 special Values of IEEE 754 standards

Exponent Mantissa representsemin-1 M=0 ±0emin-1 M≠0 0.M x 2emin

emin ≤ e ≥ emax -- 1.M x 2e

emax+1 M=0 ±∞emax+1 M≠0 NaN

Note: emin and emax for IEEE 32 bit floating point representation is -126 and 127

7.2.2. Basic Multiplication Algorithm

Multiplication of two floating-point numbers is done in following steps:

Non-signed multiplication of mantissas: it must take account of the integer

part ,implicit in normalization.

The number of bits of the result is twice the size of the operands (48 bits) .

Normalization of the result: the exponent can be modified accordingly.


Documents

vedic multiplier6