Embed Size (px)
Citation preview
Verification Code Longevity: Learn Verification Code Longevity: Learn Expert Techniques Expert Techniques
WebinarWebinar
Created byMike MintzTrusster, [email protected]
www.aldec.comwww.aldec.com
2
Agenda
• Introduction
• What is bit rot?
• Adaptable versus Reusable code
• Minimizing your assumptions to Maximize Adaptability
• Canonical Monitors and Checkers
• Aldec RTL Simulators & Design Rule Checking
• Question and Answer Session
www.aldec.comwww.aldec.com
3
What is bit rot ?
• Funny term for code that does not continue to work
• All code rots !
• The environment changes : DUT, simulator, protocol, methodology, etc.
• It’s all a probability game
www.aldec.comwww.aldec.com
4
Adaptable versus Reusable code
• Focus your thinking on the “core” parts
• It’s all a probability game
• Reusable code is a myth
• Adaptable code means you have to do work to some existing codebase
www.aldec.comwww.aldec.com
5
Maximize Adaptability
• Changes are easy – or just plain impossible
• Separate interface from Implementation
• Keep the abstraction level constant
• Make simple utility objects!
www.aldec.comwww.aldec.com
Standard Components
Teal Truss
www.aldec.comwww.aldec.com
7
The “standard parts”
• A way to wiggle wires, perform randomization, and make threads
• Orthogonal parameter passing
• A memory read/writer system
• A logger
www.aldec.comwww.aldec.com
8
Canonical MonitorMonitor class Derived for printing
namespace usb { struct printer: public usb::monitor { virtual void receive_completed_ (const data& d) {
printf (“Packet Type is %d\n”, d.type); for (int i(0); i < d.payload.size; ++i) { printf (“Packet [%d]:0x%x\n”, i,
d.payload[i]); } } };}
Derived for channelnamespace usb { typedef truss::channel<data> channel;
struct usb_monitor_agent : public usb_monitor { virtual void receive_completed_ (const data& d) { channel_->put (d); } usb::channel* channel_;};
namespace usb {
struct data {
int type;
std::vector<int> payload;
};
struct interface {
teal::reg d_plus, d_minus;
};
struct monitor : truss::thread {
interface i_;
void start_ ();
virtual void receive_completed_(const data&) =0;
};
}
www.aldec.comwww.aldec.com
9
Canonical Checker
• Should be simple
• Goals are the “real” meat
• What does done() mean ?
class checker {public: truss::checker (const std::string& n) : truss::checker (n) {} virtual void start_ () { do { data e = get_expected_(); data a = get_actual_(); if (e != a) { log_ << teal_error << “Expected != actual” << teal::endm; } note_actual_check_(); note_expected_check_(); } while (! done_()); }}protected: virtual data get_expected_ () = 0; virtual data get_actual_ () = 0; virtual bool done_ () = 0;};
www.aldec.comwww.aldec.com
10
Sumary
• All code “rots”
• It always take some effort to adapt
• Box your assumptions!!!
• Use a small set of useful components
• Monitors/Checkers have a standard form
• It’s all a probability game--- but you can rig the odds
www.aldec.comwww.aldec.com
11
Aldec RTL Simulators• Common-Kernel Simulators
• Languages: VHDL, Verilog® , SystemVerilog, SystemC & EDIF 200
• HDL Design Tools: Design Creation, Code2Graphics™, Block and State Diagram, Waveform editor, stimulus generation, Language and legacy design support. (Active-HDL)
• Debugging: Advanced Waveform Viewer, Memory Viewer, Xtrace, Advanced Dataflow, Profiler, HDL/SystemC code level Debugging & Post-Simulation Debugging.
• Code Coverage: Code/Line, Statement, Branch, Expression, Condition and Toggle coverage.
• Advanced Verification: ESL, TLM, OVM and VMM
• Assertion-Based Verification: Assertion waveform viewer, coverage, breakpoint editor. SystemVerilog IEEE 1800 Assertions/Coverage, PSL & OVA.
• Co-Simulation: MATLAB® and Simulink® Interfaces
• ALINT Design Rule Checking: also available as stand-alone application with custom rule creation support
• Simulation Regression Manager (SFM)
• Riviera-PRO (Linux 32/64, Windows XP/Vista/2003/2000) Active-HDL (Windows ONLY.)
Active-HDLActive-HDL
Riviera-PRORiviera-PRO
www.aldec.comwww.aldec.com
12
Q&A and Contact Info
ALDECALDECWebsite:
http://www.aldec.comTel. USA: +1-702-990-4400Tel. Canada: +1-613-867-8600Fax USA/Can: +1-702-990-4414E-mail: [email protected]. Europe: +33-6-80-32-60-56Fax Europe: +33-1-46-34-85-91E-mail Europe: sales-
ALDECALDECWebsite:
http://www.aldec.comTel. USA: +1-702-990-4400Tel. Canada: +1-613-867-8600Fax USA/Can: +1-702-990-4414E-mail: [email protected]. Europe: +33-6-80-32-60-56Fax Europe: +33-1-46-34-85-91E-mail Europe: sales-
[email protected]• To attend additional ALDEC events, go to To attend additional ALDEC events, go to www.aldec.com/events/www.aldec.com/events/. .
• To download free HDL Simulator evaluation, go to To download free HDL Simulator evaluation, go to www.aldec.com/downloads/www.aldec.com/downloads/. .
• To see some chapters from the books, go to To see some chapters from the books, go to www.trusster.com/books/www.trusster.com/books/. .
• To download TealnTruss, go to To download TealnTruss, go to www.trusster.com/downloads/www.trusster.com/downloads/. .
Trusster CorporationTrusster Corporation
Website: http://www.trusster.com/
E-mail: [email protected]
Trusster CorporationTrusster Corporation
Website: http://www.trusster.com/
E-mail: [email protected]
