Verification of Scheduling in High-level Synthesis Presented by Chris Reade Authors

Verification of Schedulingin

High-level Synthesis

Presented by

Chris Reade

Authors

C. Karfa, C. Mandal, D. Sarkar, S. R. PentakotaIndian Institute of Technology, Kharagpur, India

&

C. Reade

Kingston Business School, Kingston University, England

ISQED 06 IIT Kharagpur & Kingston Uni 2

Overview

• Formal method for checking equivalence betweentwo descriptions of the target system,(before and after scheduling).

• Based on equivalence checking of FSMDs (finite state machines with data paths).

• (Roughly)Find cutpoints in one FSMD to break loops, Visualize computations as concatenation of paths from cutpoints to cutpointsIdentify equivalent finite path segments in the other FSMD; Repeat with the FSMDs interchanged.


Application

• Algorithm works for

Basic block based scheduling.

Path-based scheduling where path segments are merged by the scheduler. Most of the existing algorithms failed in this case.

Can handle many arithmetic transformations.

Supports simple code motions.


FSMD vs. FSM (Why FSMD ?)

• The general equivalence problem of FSMDs (EPFSMD) is undecidable and not even partially decidable.

• Final targeted hardware only has finite datapath.So the restricted problem could be reduced to equivalence problem of FSM models (EPFSM). EPFSM is decidable.

• BUT… this gives a state explosion– An n-bit datapath results in a number of states of the order 2kn .

Thus, FSM modelling faces state explosion.– Also, scheduling algorithms may never use the finiteness of the

targeted hardware - so neither should their analysis.

• Hence look for approximation with FSMDs…


- Path from qm to qn

A finite transition sequence.

All intermediate qj are distinct,

qn may be equal to qm.

R - Condition of execution of Logical expression over variables.

If R is satisfied at the beginning of , then is executed.

r - Data transformation over r = S, O where

S is transformation of variables

O is the output listalong the path .


A Computation of an FSMD:

A finite walk from the reset state back to itself without intermediate occurrences of the reset state.

• Computation can be represented as concatenation of paths.• Two computations c1 and c2 are equivalent if

Rc1 = Rc2 & rc1 = rc2.

A sample computation is shown in Fig. 2.

Computations of an FSMD


Normalization• Checking

Rc1 = Rc2 & rc1 = rc2

could involve the whole of integer arithmetic which is an undecidable problem (validity problem of first order logic).

• In this work, we use a syntactic approximation -normal forms for expressions

• R and r may be calculated by forward or backward substitution method.

• So normal forms for R and r as well.


Correctness Problem

Finite Path Cover :

A set P = { p0, p1, p2, … pk } of FSMD M is said to be a path cover of M iff any computation of M can be viewed as a concatenation of paths from P.

Equivalence of two FSMDs :

For any computation c0 of M0, there exists an equivalent computation c1 in M1 and vice-versa.

In other words, there exists a finite path cover of M0, such that each path has a corresponding equivalent in M1 (with consistency for corresponding endpoints),

and vice-versa.


For machines M0 and M1 keep track of: • pairs of corresponding states (found so far)• matched pairs of paths (found so far) • unmatched paths to be processed

Step 1: Identify initial cutpoints in M0 to break loops:Reset state + states with more than one output transition

Step 2: (Main loop)Process an unmatched path from M0 (succeed when none left).

Use findEquivalent (, q) on M1 where q corresponds to start of may find direct corresponding path in M1, ormay require path to be extended

(creating new cutpoints and new paths to match), or may fail with no possible extension (exit with failure)

Step 3 : Identify initial cutpoints in M1.Step 4 : Repeat the same procedure as described in step 2

with roles of M0 and M1 interchanged.Step 5 : If succeed for both step 2 and 4 then

M0 and M1 are computationally equivalent, otherwise report a failure.

Verification Algorithm


Algorithm Complexity• The complexity of the algorithm is determined by step 2.

• For n control states in M0 or M1 we have O(n) cutpoints.

• Time complexity of function findEquivalent (, q) is O(kn2). – Proportional to number of paths from q examined.

with k parallel edges between two states

– Lower bound is (1) when equivalent path found directly

• Path extensions may be required. Maximum length after extensions is O(n), so starting from a cutpoint, up to O(kn-1), if k 1 or O(n2), if k = 1 paths of M0 may need to be examined.

• Thus, total number of pairs of the form (, q) that need to be examined is O(n2kn-1), if k 1 or O(n4), if k = 1.

Lower bound is (n) as all the nodes of M0 need to be examined at least once and each cutpoint of M0 paired with one cutpoint in M1.

• Overall complexity of step 2 is O(n4kn) if k1 or O(n6) if k=1 and (n).


Name

#state #path in cover

#path extended

CPU time

In ms

M0 M1 M0 M1

DIFFEQ 4 12 3 3 0 2.442

EWF 4 35 1 1 0 1.820

GCD 7 4 11 7 3 3.976

DCT 3 29 1 1 0 1.754

TLC 7 8 13 14 2 4.196

MODN 6 7 8 12 2 4.324

PERFECT 9 6 7 5 2 4.028

• Execution time sensitive on number of paths explored, not on number of states in FSMD.

Experimental Results• Implemented in ‘C’.• Results are shown for several High-level Synthesis benchmarks.


Summary

• Equivalence checking of FSMDs introduced as a formal verification method for scheduling..

• Algorithm is strong enough to accommodatepath based scheduling algorithm where consecutive path segments of input behavior are merged by the scheduler.

• Most of the existing verification algorithms can fail in this case. Algorithm can also handle simple code motions.

• Normal form is considered for the representation of condition of execution and data transformation to handle the arithmetic transformation.

• Implementation has been completed. Experimental results are for several high-level synthesis benchmarks. Efficiency reflects in the execution time for these examples.


An Example


NO PATH FOUND

Extend this path


Finite State machine with Data path (FSMD) :

An ordered tuple < Q, q0, I, V, O, f, h > where• Q = { q0, q1, q2, …, qn } is the finite set of control states.• q0 Q is the reset state.• I is the set of primary input signals.• V is the set of storage variables.• O is the set of output signals.• f : Q x S → Q, is the state transition function.• h : Q x S → U, is the update function of the output and storage

variables. S and U is defined below.1. U = { x e | x O V and e E } represents a set of

storage or output assignments, where E represents a set of arithmetic expressions over the set I V.

2. S is a set of arithmetic relations between two expressions from the set E.

Verification Problem Formulation

Documents

Verification of Scheduling in High-level Synthesis Presented by Chris Reade Authors