1 //----------------------------------------------------- 2 // Design Name : mux_using_if 3 // File Name : mux_using_if.v 4 // Function : 2:1 Mux using If 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module mux_using_if( 8 din_0 , // Mux first input 9 din_1 , // Mux Second input 10 sel , // Select input 11 mux_out // Mux output 12 ); 13 //-----------Input Ports--------------- 14 input din_0, din_1, sel ; 15 //-----------Output Ports--------------- 16 output mux_out; 17 //------------Internal Variables-------- 18 reg mux_out; 19 //-------------Code Starts Here--------- 20 always @ (sel or din_0 or din_1) 21 begin : MUX 22 if (sel == 1'b0) begin 23 mux_out = din_0; 24 end else begin 25 mux_out = din_1 ; 26 end 27 end 28 29 endmodule //End Of Module mux

Mux : Using case Statement

1 //----------------------------------------------------- 2 // Design Name : mux_using_case 3 // File Name : mux_using_case.v 4 // Function : 2:1 Mux using Case 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module mux_using_case( 8 din_0 , // Mux first input 9 din_1 , // Mux Second input 10 sel , // Select input 11 mux_out // Mux output 12 ); 13 //-----------Input Ports--------------- 14 input din_0, din_1, sel ; 15 //-----------Output Ports--------------- 16 output mux_out; 17 //------------Internal Variables-------- 18 reg mux_out; 19 //-------------Code Starts Here--------- 20 always @ (sel or din_0 or din_1) 21 begin : MUX 22 case(sel ) 23 1'b0 : mux_out = din_0; 24 1'b1 : mux_out = din_1; 25 endcase 26 end 27 28 endmodule //End Of Module mux

AdderFull Adder rtl

modulefull_adder(in_x,in_y,carry_in,sum_out,carry_out);inputin_x;inputin_y;inputcarry_in;outputsum_out;outputcarry_out;

wirew_sum1;wirew_carry1;wirew_carry2;

assigncarry_out=w_carry1|w_carry2;

// Instantiate two half-adders to make the circuit. Click here for half-adder rtl

half_adder u1_half_adder(.in_x(in_x),.in_y(in_y),.out_sum(w_sum1),.out_carry(w_carry1));half_adder u2_half_adder(.in_x(w_sum1),.in_y(carry_in),.out_sum(sum_out),.out_carry(w_carry2));endmoduleResultsin_x = 0, in_y = 0, carry_in = 0, out_sum_fa = 0, out_carry_fa = 0in_x = 0, in_y = 0, carry_in = 1, out_sum_fa = 1, out_carry_fa = 0in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1in_x = 0, in_y = 1, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1in_x = 1, in_y = 1, carry_in = 1, out_sum_fa = 1, out_carry_fa = 1in_x = 1, in_y = 0, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1in_x = 1, in_y = 0, carry_in = 0, out_sum_fa = 1, out_carry_fa = 0in_x = 0, in_y = 1, carry_in = 1, out_sum_fa = 0, out_carry_fa = 1

// Half Addermodulehalf_adder (in_x, in_y, out_sum, out_carry);input in_x;input in_y;outputout_sum;outputout_carry;assignout_sum= in_x^in_y;assignout_carry = in_x&in_y;endmoduleResults:in_x = 0, in_y = 0, out_sum = 0, out_carry = 0in_x = 0, in_y = 1, out_sum = 1, out_carry = 0in_x = 1, in_y = 1, out_sum = 0, out_carry = 1in_x = 1, in_y = 0, out_sum = 1, out_carry = 0in_x = 1, in_y = 1, out_sum = 0, out_carry = 1in_x = 0, in_y = 1, out_sum = 1, out_carry = 0