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8/8/2019 VERILOG Encoder,Mux
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A2 VERILOGPage 1
ECEn 224 © 2003-2008BYU
Dataflow Verilog
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Motivation
• Structural design can be cumbersome
– Lots of typing• 32-bit busses & logic
• Structural designs are static– At least in Verilog (not so for VHDL)
– Little or no parameterization possible
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A Dataflow MUX – Version 1
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b);
endmodule
Much simpler, less typing, familiar C-like syntax.
Synthesizer turns it into optimized gate-level design.
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A Dataflow MUX – Version 2
module mux21(q, sel, a, b);
input sel, a, b;output q;
assign q = sel ? b : a;
endmodule
Even simpler, uses C-like ternary ( ?: ) construct
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Dataflow OperatorsOperator
TypeOperatorSymbol
OperationPerformed
# ofOperands Comments
Arithmetic *, /, +, - As expected 2
* and / take
LOTS of
hardware
% Modulo 2
Logical ! Logic NOT 1 As in C
&& Logic AND 2 As in C|| Logic OR 2 As in C
Bitwise ~ Bitwise NOT 1 As in C
& Bitwise AND 2 As in C
| Bitwise OR 2 As in C
^ Bitwise XOR 2 As in C
~^ Bitwise XNOR 2Relational <, >, <=, >= As expected 2 As in C
Equality ==, != As expected 2 As in C
Reduction & Red. AND 1 Multi-bit input
~& Red. NAND 1 Multi-bit input
| Red. OR 1 Multi-bit input
~| Red. NOR 1 Multi-bit input
^ Red. XOR 1 Multi-bit input~^ Red. XNOR 1 Multi-bit input
Shift << Left shift 2 Fill with 0's
>> Right shift 2 Fill with 0's
Concat { } Concatenate Any number
Replicate { { } } Replicate Any number
Cond ?: As expected 3 As in C
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Bitwise vs. Logic Operators
• Similar to C
assign q = ((a<4’b1101) && ((c&4’b0011)!=0)) ? 1’b0:1’b1;
Use &&, ||, ! for 1-bit quantities (results of comparisions)
Use &, |, ~ for bit-by-bit logical operations
Pseudo-code (not real Verilog):if (a<4’b1101 && (c&4’b0011) != 0) then
q <= ‘0’;elseq <= ‘1’;
<a
“1101”
c
“0011”
q
1
14
4
4
4
4
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Reduction Operators
wire[3:0] x;
wire z;
assign z = &x; // Same as z = x[3] & x[2] & x[1] & x[0]
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Concatenation and Replication Operators
wire[3:0] x, y;
wire[7:0] z, q, w, t;
wire[31:0] m, n;
assign x = 4’b1100;
assign y = 4’b0101;
assign z = {x, x}; // z is 8’b11001100assign q = {x, y}; // q is 8’b11000101
assign w = {4’b1101, y}; // w is 8’b11010101
assign t = {2{x}}; // same as {x, x}
assign m = {{4{x}}, {2{q}}};// m is 32’b11001100110011001100010111000101
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Operator Precedence
• Similar to CHigher precedence
Unary -, unary +, !, ~*, /, %
+, -
<<, >>
<, <=, >, >=
==, !=
&, ~&
^, ~^
|, ~|
&&||
?:
Lower precedence
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A Note on Matching Widths
• This a valid 2:1 MUX statement:
• But the following is not:
Why?
wire a, b, sel, q;
assign q = (~sel & a) | (sel & b);
wire[3:0] a, b, q;
wire sel;
assign q = (~sel & a) | (sel & b);
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More On Matching Wire Widths
• This is an acceptable substitute:
• It turns the sel and ~sel values into 4-bitversions for AND-ing and OR-ing
• A more elegant version:
wire[3:0] a, b, q;wire sel;
assign q = ({4{~sel}}&a)|({4{sel}}&b);
wire[3:0] a, b, q;
wire sel;
assign q = sel ? b: a;
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Design Example: A 2:4 Decoder
module decode24(q, a);
output[3:0] q;
input[1:0] a;
assign q = (4’b0001) << a;
endmodule
Can you see how to make a 3:8 or 4:16 decoder in the same fashion?
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Multi-bit Designand
Parameterization
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A Dataflow MUX – Multi-Bit
module mux21(q, sel, a, b);
input sel;
input[15:0] a, b;
output[15:0] q;
assign q = sel ? b : a;
endmodule
Key Ideas:The predicate must evaluate to true or false (1 or 0)The parts getting assigned must be all same widths.
0
1
a
b
s
q16
16
16
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A Dataflow MUX – Parameterized Width module mux21n(q, sel, a, b);
parameter WID = 16;
input sel;
input[ WID-1:0] a, b;
output[ WID-1:0] q;
assign q = sel ? b : a;
endmodule
• By default, this is now a 16-bit wide MUX.• When instantiating, the default value of 16 can be overridden:
mux21n M1(q, sel, a, b); // Instance a 16-bit version mux21n #(4) M0(q, sel, a, b); // Instance a 4-bit version
Does this work for a 1-bit MUX?
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Using Parameterization
• Careful planning often allows you to write one
design which can be reused– Reuse is a common goal in design• Simplifies your work
• Eliminates errors • Saves time later
• Whenever possible, plan for reuse
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Parameterization Exercise
• Design a 4:1 MUX that works with any size
operands (arbitrary bit-width)• Either:
– Build arbitrary bit-width 2:1 MUX
– Structurally instance 3 of these to make a 4:1MUX
or
– Write an arbitrary bit-width 4:1 MUX usingthe ?: operator
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4:1 MUX – Method 1
module mux41n(q, sel, a, b, c, d);
parameter WID=16;
input[1:0] sel;
input[WID-1:0] a, b, c, d;output[WID-1:0] q;
wire[WID-1:0] tmp1, tmp2;
mux21n #(WID) M0(tmp1, sel[0], a, b);
mux21n #(WID) M1(tmp2, sel[0], c, d);
mux21n #(WID) M2(q, sel[1], tmp1, tmp2);
endmodule
If the mux21n cells are parameterizable for bit-width this works…If not, it doesn’t work…
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4:1 MUX – Method 2
Cascaded ?: operators form an if-then-else structure
Note how sel can be compared to bit patterns (2’b00) or to numbers (1)
module mux41(q, sel, a, b, c, d);
parameter WID=16;
input[1:0] sel;
input[WID-1:0] a, b, c, d;
output[WID-1:0] q;
assign q = (sel==2'b00) ? a:
(sel==1) ? b:
(sel==2’b10) ? c:d;
endmodule
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Behavioral Verilog
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Used for Sequential Circuits and
Combinational Circuits module dff(clk, d, q);
input clk, d;
output reg q;
always @(posedge clk)
q <= d;
endmodule
You can use this as a DFF for your design.
Figure out how to parameterize it for arbitrary input/output widths
Remainder of behavioral design not covered in this class…
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Conclusion
• With what you know…
– You can do reasonable designs– Must structurally instance all storage elements(flip flops)
• Behavioral Design– A number of nuances with respect to timingsemantics
– Not recommended beyond simple FF’s for thisclass• You will learn full range of behavioral design in
later courses