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DIVYA SHAH25/02/09

VERILOG HARDARE DESCRIPTION

LANGUAGE

LECTUER-3

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Structural Modeling

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The module is implemented by connecting set ofprimitives defined by the language (called built-inprimitives) or by the user (called user defined

primitives)

Verilog has a set of twenty six built-in primitivesclassified into 3 different categories

Logic Gates

and or xor nand nor xnor

Buffers

buf bufif0 bufif1 not notif0

notif1 pulldown pullup Transistor

nmos pmos cmos rnmos

rpmos rcmos tran tranif0

tranif1 rtran rtranif0 rtranif1

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GATE LEVEL MODELING

VERILOG SUPPORTS BASIC LOGIC GATES OR PREDEFINEDPRIMITIVES

THEY ARE INSTANTIATED LIKE MODULES EXCEPT THAT THEY AREPREDEFINED IN VERILOG AND NO NEED FOR A MODULEDEFINATION.

Verilog has two classes of basic gates

and/or

Have one scalar output and multiple scalar inputs.

The first terminal in the port list is output and rest are inputterminals.

buf/not Have one scalar input and one or more scalar outputs.

Last terminal in the port list is connected to the input andothers are connected to the output.

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Eg:

wire out,in1,in2;

//basic gate instantiationsand a1(out,in1,in2);

nand na1(out,in1,in2);

or or1(out,in1,in2);

//more than two inputs

Nand na1_3ip(out,in1,in2,in3);

//gate instantiation without instance nameand(out,in1,in2);

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Array of instances:

when there are repetitive instances requied and

they are differ from each other only by the vectorto which they are connected ,then they can besimplify in this way

Eg:

wire[7:0]out,in1,in2;nand n_gate[7:0](out,in1,in2);

//this is same as following 8 statements

nand n0(out[0],in1[0],in2[0]);

nand n1(out[1],in1[1],in2[1]);

nand n2(out[2],in1[2],in2[2]);

and so on

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Example : 4_to_1 Multiplexer

i0

i1

i2

i3

sel1

sel0

out1 out0

y0

y1

y2

y3

out

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Example: 4-to-1 multiplexer Verilog structural model.

module mux4_to_1(out, i0,i1,i2,i3,sel0,sel1);

output out; //output port

input i0,i1,i2,i3; //input ports

input sel0,sel1; //control lines (input ports)

wire out0, out1; //internal wire declarations

wire y1,y2,y3,y4;not (out0,sel0);

not(out1,sel1);

and(y0,i0,out0,out1);

and(y1,i1,out0,sel1);

and(y2,i2,sel0,out1);and(y3,i3,sel0,sel1);

or(out,y1,y2,y3,y4);

endmodule

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Gate Delays

In real circuits, logic gates have delaysassociated with them.

Gate delays allow the user to specify delays

through logic circuits

Pin-to-Pin delays can also be specified in

verilog.

Three types of delays from input to output of a

primitive gate is defined in VerilogRise Delay

Fall Delay

Turn-off Delay

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Example Types of Delay specification

and #(5) a1(out,inp1,inp2);//Delay of 5 for all transactions

and #(4,6) a2(out,inp1,inp2);//rise=4,fall=6

bufif0 #(3,4,5) b1 (out, in, control);//rise=3,fall=4,turnoff=5

Example module test

//Write the verilog code for it:

# 5

# 4

a

b

c

d

out

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module test (out, a,b,c);

output out;

input a,b,c;

wire d;

// Instantiate primitive gates to build the circuit

and #(5) a1(d,a,b);

or #(4) a2 (out, c,d);

endmodule

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User defined primitives User defined primitives describes a piece of logic with a truth

table.

UDPs can be either combinational or sequential.

UDPs can have only one output and none of its inputs andoutputs can be a vectors.

Syntax

primitive primitive_name(port ids);

output port_id_names;

input port_id_names;

table

inputs : output

endtable

endprimitives

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Example: //combinational UDPs(mux_2_to 1)

primitive mux2to1(y,sel,in1,in2);

output y;

input sel,in1,in2;

table

// sel in1 in2 : y

0 0 ? : 0;0 1 ? : 1; // ? Can be 0,1 or x

1 ? 0 : 0;

1 ? 1 : 1;

x 0 0 : 0; // x unknown

x 1 1 : 1;

endtable

endprimitive

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YOUR WORK

WRITE A CODE OF 3:8 DECODER

USING GATE LEVEL MODELING

WRITE A CODE OF 16:1 MUX USING 4:1MUX

WRITE A CODE OF 4 INPUT PRIORITY

ENCODER USING GATE LEVEL

MODELING