VERTICALDEFLECTION CIRCUITS FOR TV & MONITOR

TECHNICAL NOTE

VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR

AN373/0694

By Alessandro MESSI

SUMMARY Page1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 OSCILLATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 RAMP GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 BLANKING GENERATOR AND CRT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 POWER AMPLIFIER STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 THERMAL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 FLYBACK BEHAVIOUR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 CURRENT - VOLTAGE CHARACTERISTICS OF THE RECIRCULATING DIODES . . 11

9 CALCULATION PROCEDURE OF THE FLYBACK DURATION . . . . . . . . . . . . . . . . . . 12

10 APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

11 SUPPLY VOLTAGE CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

12 CALCULATION OF MIDPOINT AND GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

13 MONITOR APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

14 POWER DISSIPATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

15 BLANKING PULSE DURATION ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16 LINEARITY ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 FACILITIES AND IMPROVEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18 GENERAL APPLICATION AND LAYOUT HINTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

19 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1/23

AN

373-

01.E

PS

Figure 1 : Block Diagram of a General Deflection Stage

1 - INTRODUCTION

In a general way we can define vertical stagescircuits able to deliver a current ramp suitable todrive the vertical deflection yoke.

In Figure 1 is represented the more general possi-ble block diagram of a device performing the verti-cal deflection.

Such a device will be called ”complete verticalstage” because it can be simply driven by a syn-chronization pulse and it comprises all the circuitrynecessary to perform the vertical deflection that is :oscillator, voltage ramp generator,blanking gene-

tor, output power and flyback generator.

At the right side of the dotted line in Figure 1 isrepresented the circuitry characterizing a ”verticaloutput stage”. This kind of device comprises only

the power stages and it has to be driven by avoltage sawtooth generated by a previous circuit(for example a horizontal and vertical synchroniza-tion stage.In the first class there are the following devices :TDA1170D, TDA1170N, TDA1170S, TDA1175,TDA1670A, TDA1675, TDA1770A, TDA1872A,TDA8176.In thesecondclass thereare : TDA2170,TDA2270,TDA8170, TDA8172, TDA8173, TDA8175,TDA8178, TDA8179.

There is also a thrid class of vertical stages com-praising the voltage ramp generator but without theoscillator; these circuits must be driven by an al-ready synchronized pulse. In this third class thereare : TDA1771 and TDA8174.


2/23

AN

373-

02.E

PS

Figure 2 : First Kind of Oscillator Stage

2 - OSCILLATOR

There are two different kinds of oscillator stagesused in SGS-THOMSON complete vertical deflec-tions, one is used in TDA1170D, TDA1170N,TDA1170S, TDA1175 and TDA8176, the other inTDA1670A,TDA1675,TDA1170Aand TDA1872A.

The principle of the first kind of oscillator is repre-sented in Figure 2.

The followingexplanationswill be the more generalpossible; we shall inform the reader when we referto a particular device.

When the switches T1 and T2 are opened the COcapacitor charges exponentially through RO to thevalue V+

(MAX) determined by the integrated resis-tors R1, R2, R3 and R4. At this point the switchesare closed, short-circuiting R3 and R4, so the volt-age at thenon-inverting input becomesV+

(MIN). Thecapacitor CO discharges to this value through the

integrated resistor R5.The free running frequency can be easily calcu-lated resulting in :

TO = RO ⋅ CO ⋅ logVR − V (MIN)

+

VR − V (MAX)+

(1) fO = 1TO

+ R5 ⋅ CO ⋅ logV (MAX)

+

V (MIN)+

with RO = 360 kΩ and CO = 100 nF, it results in43.7Hz.The oscillator synchronization is obtainedreducingthe superior threshold V+

(MAX) short-circuiting theR4 resistor when a vertical synchronization pulseoccurs.The second kind of oscillator is represented inFigure 3.

AN

373-

03.E

PS

Figure 3 : Second Kind of Oscillator Stage


3/23

When the switch T is in position 2, a constantcurrent ICO = V - / RO flows through CO charging itwith a voltage ramp. When the voltage VO reachesVO(MAX), T passes in position 1, so a constantcurrent ICO = ( VB - V - ) / RO discharges the capaci-tor causing the inversion of the voltage ramp slopeat the output VO ( t ). The discharges stops whenVO reaches the value VO(MIN) and the cycle takesplace again.It ispossible tocalculate the free runningfrequencyfO with the following formula :

TO =( VO(MAX) − VO(MIN) ) ⋅ RO ⋅ CO

V−

(2)

+( VO(MAX) − VO(MIN) ) ⋅ RO ⋅ CO

VB − V−

with VO(MAX) - VO(MIN) = 3.9V, VB = 6.5V, V-

= 0.445V,RO = 7.5kΩ and CO = 330nF it resultsin : fO = 43.8Hz.The oscillator synchronization isstill obtained in theabove mentioned way.In order to guarantee a minimum pull-in range of14Hz the threshold value has been chosen inVP = 4.3V.The spread of the free running frequency in thiskind of oscillator is very low because it mainlydepends from the thresholdvalues VO(MAX), VO(MIN)and V - that are determined by resistor rates thatcan be done very precise.

3 - RAMP GENERATOR

The ramp generator is conceptually represented inFigure 4.The Voltage ramp is obtained charging the groupR1, C1 and C2 with a constant current IX.It iseasy to calculate the voltage VRAMP Thatresultsin :

VRAMP (t) = (V(MIN) − R1 ⋅ IX) e− 1R1 ⋅ C + R1 ⋅ IX (3)

where V(MIN) is the voltage in A when the chargestarts and C is the series of C1 and C2.The resistorR1 is necessaryto givea ”C correction”to the voltage ramp. The ramp amplitude is deter-mined by IX = VREG / P1 ,so the potentiometer P1 is

necessary to perform the height control.The voltage ramp is then transferred on a lowimpedence in B through a buffer stage.The P2 potentiometer connected between D and Bperforms the ramp linearity control or ”S correction”that is necessary to have a correct reproductionofthe images on the TV set.The voltage ramp in B grows up until the switch T1is closed by a clock pulse coming from the oscilla-tor; in this way the capacitors discharge fastly toV(MIN) that is dependent upon the saturation volt-age of the transistor that realizes the switch.At this point the exponential charge takes placeagain.

4 - BLANKING GENERATOR AND CRT PRO-TECTION

This circuit senses the presence of the clock pulsecoming from the oscillator stage and the flybackpulse on the yoke. If both of them are present ablanking pulse is generatedable to blank the CRTduring the retrace period. The duration of this pulseis the same of the one coming from the oscillator.If for any reason the vertical deflection would fail,for instance for a short circuit or an open circuit ofthe yoke, the absence of the flyback pulse puts thecircuit in such a condition that a continuousverticalblanking is generated in order to protect the CRTagainst eventual damages.This circuit is available only in the following de-vices :TDA1670A, TDA1675, TDA1770A andTDA1872A.The stages we will consider starting from this pointare common both to complete vertical stages andvertical output stages.

5 - POWER AMPLIFIER STAGE

This stage can be divided into two distinct parts :the amplifier circuit and the output power.The amplifier is realized with a differential circuit; aschematic diagram is represented in Figure 5.The open-loop gain of the circuit is variable from60dB to 90dB for the different integrated circuits.The compensation capacitor C determines thedominant pole of the amplifier. In order to obtain adominant pole in the range of 400Hz, the capacitormust be of about 10pF.


4/23

AN

373-

04.E

PS

Figure 4 : Ramp Generator

AN

373-

05.E

PS

Figure 5 : Amplifier Stage

As an example in Figure 6 is represented the boolediagram of the amplifier open loop gain forTDA8172.

AN

373-

07.E

PS

Figure 7 : Power Stage

2 3 4 5 6 7

GA

IN(d

B)

FREQUENCY, f (Hz)1 10 10 10 10 10 10 10

100

80

60

40

20

0

90

45

0

- 45

- 90

- 135

PH

AS

E(D

egre

es)

PHASE

GAIN

AN

373-

06.E

PS

Figure 6 : Amplifier Open Loop Gain and Phase

The output power stage is designed in order todeliver to the yoke a vertical deflectioncurrent from1 to 2Apeak,dependingupon the differentdevices,and able to support flyback voltages up to 60V. Atypical output stage is depicted in Figure 7.


5/23

AN

373-

08.E

PS

Figure 8 : Output Power and Flyback Stages

The upperpower transistor Q1 conductsduring thefirst part of the scanning period when the verticaldeflection current is flowing from the supply voltageinto the yoke; when the current becomesnegative,that is it comes out of the yoke, it flows through thelower power transistor Q2.The circuit connectedbetween the two output transistors is necessary toavoid distortion of the current at the crossing ofzero, when Q1 is turned off and Q2 is turned on.When the flyback begins, Q2 is switched-off by Q3in order to make it able to support the high voltageof the flyback pulse.The circuit behaviourduring flyback is explained inchapter 7.

6 - THERMAL PROTECTION

The thermalprotectionis available in all the devicesexcept the TDA1170 family and the TDA8176.This circuit is usefull to avoid damages at theintegrated circuit due to a too high junction tem-perature caused by an incorrect working condition.It is possible to sense the silicon temperature be-cause the transistor VBE varies of - 2 mV/ oC, so a

temperature variation can be reconducted to avoltage variation.If the temperature increases and it is reaching150oC, the integrated circuit output is shut down byputting off the current sources of the power stage.

7 - FLYBACK BEHAVIOUR

In order to obtain sufficiently short flyback times, avoltage greather than the scanning voltage mustbe applied to the deflection yoke.

By using a flyback generator, the yoke is onlysupplied with a voltage close to double the supplyduring flyback.

Thus, the power dissipated is reduced to approxi-mately one third and the flyback time is halfed.

The flyback circuit is shown in Figure 8 togetherwith the power stage.

Figure 9 shows the circuit behaviuor, to show op-eration clearly. The graphs are not drawn to scale.Certain approximations are made in the analysis inorder to eliminate electrical parameters that do notsignificantly influence circuit operations.


6/23

AN

373-

09.E

PS

Figure 9 : Current in the Yoke and Voltage Drop on The Yoke during Vertical Deflection

a) Scan period (t 6 - t7) : Figure 10During scanning Q3, Q4 and Q5 are off and thiscauses Q6 to saturate.A current from the voltage supply to ground flowsthrough DB, CB and Q6 charging the CB capacitorup to :

VCB = VS - VDB - VQ6SAT (4)

At the end of this period the scan current hasreached its peak value (IP) and it is flowing from theyoke to the device. At the same time VA hasreached its minimum value.In Figures 11 and 12 are depicted the voltage drop A

N37

3-10

.EP

S

Figure 10 : Circuit involved during Scan Period

AN

373-

12.E

PS

Figure 12 : Voltage Drop on the Yoke and Cur-rent Flowing through the YokeV = 10V/div. - I = 1A/div.t = 5ms/div.

AN

373-

11.E

PS

Figure 11 : Voltage Drop on the Yoke and Cur-rent Flowing through DB

V = 10V/div. - I = 0.5A/div.t = 2ms/div.

on the yoke and the currents flowing through DBand the yoke.


7/23

AN

373-

13.E

PS

Figure 13 : Circuit involved duringFlyback Starting

b) Flyback starting (t 0 - t1) : Figure 13Q8, that was conducting the - IP current, is turnedoff by the buffer stage.The yoke, charged to IP, now forces this current toflow partially through the Boucherot cell (I1) andpartially through D1, CB and Q6 (I2).In Figures 14, 15 and 16 are represented thecurrents flowing through the yoke, the Boucherotcell and D1.

AN

373-

14.E

PS

Figure 14 : Voltage Drop on the Yoke and Cur-rent Flowing through the BoucherotCell - V = 10V/div.I = 1A/div. - t = 1µs/div.

AN

373-

15.E

PS

Figure 15 : Voltage Drop on the Yoke and Cur-rent Flowing through D1

V = 10V/div. - I = 1A/div.t = 1µs/div.

c) Flyback starting (t 1 - t2)When the voltage drop at pin A rises over VS, Q3turns on and this causes Q4 and Q5 to saturate.Consequently Q6 turns off.During this period the voltage at pin D is forced to :

VD = VS - VQ4SAT (5)

Therefore the voltage at pin B becomes :

VB = VCB + VD (6)

The yoke current flows in the Boucherot cell addedto another current peak flowing from VS via Q4 andCB (Figures 14 and 15).


8/23

AN

373-

17.E

PS

Figure 17 : Circuit involved during the NegativeCurrent Rise

AN

373-

16.E

PS

Figure 16 : Voltage Drop on the Yoke and Cur-rent Flowing through the YokeV = 10V/div. - I = 100mA/div.t = 1µs/div.

d) Negative current rise (t 2 - t3) : Figure 17

During this period, the voltage applied at pin A is :

VA = VB + VD1,VA = VCB + VD + VD1,VA = VS - VDB - VQ6SAT + VS + VD2 + VD1,VA = 2 . VS + VD1 + VD2 - VDB - VQ6SAT

(7)

It is possible to calculate the current solving thefollowing equation :

VA = LYdidt

+ 1CD

∫ i ⋅ dt + R ⋅ i (8)

where R = RF + RY

Because the voltage at pin A is approximativelyconstant (error less than 2%) we can simplify the(8) in the following equation :

d2 i

dt2+ R

LY

didt

+ 1LY CD

i = 0 (9)

it results in :

i(t) =IP

e2β∆T1 − 1e(−α +β) t

(10)

-IP

1 − e−2β∆T1e(−α − β) t

where :

α =R

2 LYβ = √R2

4 ⋅ LY2 − 1

LY CD∆T1 = t3 - t2

Because of ∆T1 is two orders of magnitude lowerthan the scan time, we can apply an exponentialsum to obtain the following equation :

i(t) =α cosh (2β∆T1) + β sinh (2β∆T1) − α

cosh (2β∆T1) − 1t − IP (11)

Simplifying :

i(t) = IP

α + 1∆T1

t − IP (12)

The slope of the current is therefore :

didt

=

R2 LY

+ 1∆T1

IP (A/s) (13)

The current flows from the yoke to VS through D1,CB and D2, and it is depicted in Figure 18.

AN

373-

18.E

PS

Figure 18 : Voltage Drop on the Yoke and Cur-rent Flowing through the YokeV = 10V/div. - I = 250mA/div.t = 100µs/div.


9/23

e) Positive current rise (t 3 - t4) : Figure 19

AN

373-

20.E

PS

Figure 20 : Voltage Drop on the Yoke and Cur-rent Flowing through CB

V = 10V/div. - I = 0.5mA/div.t = 100µs/div.

AN

373-

19.E

PS

Figure 19 : Circuit involved during the PositiveCurrent Rise

When the current becomes zero, D1 turns off andQ2 saturates ; so the pin A voltage becames :

VA = VB - VQ2SATVA = 2 . VS - VDB - VQ6SAT - VQ4SAT - VQ2SAT

(14)

The current flows from +VS into the yoke throughQ4, CB and Q2 and rises from zero to IP as it canbe seen in Figure 18.By using the previous procedure explained in sec-tion d), we can obtain the slope of the current :

didt

=

R2 LY

+ 1∆T2

IP (A/s)

where ∆T2 = t4 − t3

f) Flyback decay (t 4 - t5)When the yoke current reaches its maximum peak,Q2 desaturates and conducts the maximum peakcurrent flowing from VS via Q4 and CB into LY; thecurrent flowing through CB is depicted in Figure20. A

N37

3-21

.EP

S

Figure 21 : Voltage Drop on the Yoke and Cur-rent Flowing through the BoucherotCell - V = 10V/div.I = 100mA/div. - t = 100µs/div.


10/23

An eventualantiringing parallel resistor modify thelinear decay slope in an exponential one, as it canbe seen in Figure 22.This continues until the buffer stage turns Q2 on.The effect of the Boucherot cell during this periodeis negligible (see Figure 21).

AN

373-

24.E

PS

Figure 24 : I-V Characteristics of the Diode D2

V = 500mV/div. - I = 200mA/div.

AN

373-

23.E

PS

Figure 23 : I-V Characteristics of the Diode D1

V = 500mV/div. - I = 200mA/div.

AN

373-

22.E

PS

Figure 22 : Effect of Resistor in Parallel con-nected to the YokeV = 10V/div.

g) VA pedestal (t 5 - t6)When VA reaches the value VS of the supply volt-age, the flyback generator stops its function.Q3 is turned off and turns off Q4 that open theconnection between pin D and VS.Therefore VB drops to VS - VDB while :VA = VS − VDB − VQ2CE on

At this point the normal scan takes place.

8 - CURRENT-VOLTAGE CHARACTERISTICSOF THE RECIRCULATING DIODESThe following Figures 23 and 24 reproduce the I-Vcharacteristics of the integrated recirculating di-odes D1 and D2 (see Figure 8)

These characteristics are useful in order to calcu-late the maximum voltage reached at pin Awith theformula (7) explained in chapter 7.


11/23

9 - CALCULATION PROCEDURE OF THE FLY-BACK DURATIONThe flyback duration can be calculated using thefollowing procedure (referring to Figure 25).

AN

373-

25.E

PS

Figure 25 : Circuit involved in the Calculation ofFlyback Duration

AN

373-

26.E

PS

Figure 26 : Simplified Circuit for the Calculationof Flyback Duration

During the flyback period the voltage applied atpin A is about 2 VS, as previously explained inchapter 7. The voltage drop across CD is approxi-matively a constant voltage little less than VS /2.The voltage on the feedbackresistor RF is :VRF ( t ) = RF IY ( t )

so in the period which we are considering it isnegligible respect to VS/2.The effect of the Boucherot cell during this periodis not sensible as it can be seen in Figure 21; whileRD acts principally during the flyback decay time(Figure 9 : t4 - t5) reducingits slopeand the resultingoscillations but doesn’t influence the total flybacktime as shown in Figure 22. So their influences arealso negligible.Now the effective voltage drop across the yoke canbe approximated to :

2 ⋅ VS −VS

2= 3

2VS

Figure 25 can be simplified as shown in Figure 26.

The voltage charges the coil with a linear currentthat can be calculated in the following way :

i(t) = 1LY

∫ V ⋅ dt = 1LY

∫ 32

VS ⋅ dt

(16)

i(t) = 1LY

32

VS ⋅ t + K

K is calculated imposing that the current at thebeginning of the flyback is -IP.

i(0) = - IP K = - IP

i(t) =32

VS

LYt − IP

(17)

At the end of the flyback period the current will be+IP, so we can write :

IP = 32

VS

LYtF − IP

The duration of the flyback period is then :

tF = 43

IP LY

VS= 2

3IY LY

VS(18)

10 - APPLICATION INFORMATION

The vertical deflection stages productedby SGS-THOMSON are able to cover the complete rangeof applications that the market need for color tele-vision and high/very high resolution monitors.Television and monitor applications are not verydifferent but in monitor field, in addition to thelinearity and interlacing problems, we have to payattention to the flyback time that must be very shortfor very high resolution models.In television applications the most important re-quirement is to choose the lowest supply voltagepossible in order to minimize the power dissipationin the integrated circuit, reducing the dimension ofthe heatsink, and the power dissipation from thevoltage supplier.These results can be reached very easily withSGS-THOMSON deflection stages because of thehigh efficiency of the flyback generatorcircuit used.In high resolution monitors one of the main prob-lems is to reach the very short flyback time re-quested; the flyback generator, together with thehigh current and power dissipation capabilities,solve all the problems in a simple way.In Figures 27, 28 and 29 are depicted three typicalapplication circuits for the different kinds of inte-grated circuits available.


12/23

AN

37-2

8.E

PS

Figure 28 : Application Circuit for TDA1670A

AN

37-2

7.E

PS

Figure 27 : Application Circuit for TDA1170

In the following chapters we shall do the calculation for television and monitor in order to choose the rightvoltage supply and external network for the yoke used and the current requirements.


13/23

AN

37-2

9.E

PS

Figure 29 : Application Circuit for TDA8170

11 - SUPPLY VOLTAGE CALCULATION

For television applications we shall calculate theminimum supply voltage necessary to have verticalscanning knowing the yoke characteristicsand the

current required for the given application.

Figure 30 shows the terms used in this section,while the circuit part involved in the following cal-culations is depicted in Figure 31.

AN

373-

30.E

PS

Figure 30 : Parameters used in the Calculation of the Supply Voltage


14/23

AN

373-

33.E

PS

Figure 33 : Saturation Characteristic of theLower Power Transistor

AN

373-

32.E

PS

Figure 32 : Saturation Characteristic of theUpper Power Transistor

AN

373-

31.E

PS

Figure 31 : Circuit involved in the Calculation ofthe Supply Voltage

VS = supply voltageVY = nominal voltage required to produce the

scanning current including the feedbackresistance and the 20% increasing fortemperature variations in the yokecurrent

VY = (1.2 RY + RF) IY (19)

VSAT1 = nominal output saturationvoltage due tothe upper power transistor Q1(see Figure 32);

VSAT2 = nominal output saturationvoltage due tothe lower power transistor Q2(see Figure 33)

VOM = nominal quiescent voltage (midpoint) onthe output power transistors

VC = voltage peak due to the charge of CDcapacitor

VC = IY ⋅ tS8 ⋅ CD

(20)

VL = vol tage dro p due to the yokeinductance LY

VL = LY ⋅ IYtS

(21)

VD = nominal voltage drop on DB diode inseries with the supply

T = vertical scan periodtF = flyback time

tF = 23

IY ⋅ LY

VS


15/23

tS = scanning time

tS = T - tF

IY = peak-to-peak deflection currentRY = nominal yoke resistanceLY = nominal yoke inductanceRF = feedbak resistor

Referring to Figure 30 it is easy to see that theminimum supply voltage is given by

VS = VOM + VTOP (22)

where :

VOM =VY

2+ VSAT2 + VC + VL (23)

and :

VTOP =VY

2+ VD + VSAT1 − VL − VC (24)

So we obtain :

VS = VY + VD + VSAT1 + VSAT2 (25)

The (25) gives the minimum voltage supply if wedo not consider the tolerances of the integratedcircuit and of the external components, but thecalculation, even if it was not realistic, it was usefulin order to understand the procedure.

Now we shall do the same thing considering all thepossible spreads; we can in this way obtainthe realminimum supply voltage.

We shall follow the statistical composition ofspreads because it is never possible that all of themare present at the same time with the same sign.

We must consider the following spreads : ∆VY due to the variation of yoke and feedback

resistance and yoke current, supposing a10% of regulation range in scanningcurrent and a precision of 7% for resistors ;

∆VY = (1.2 RY + RF) 1.07 (1.1 IY) - VY (26)

∆VC due to the toleranceof CD and yoke currentregulation ;

∆VC =1.1 IY tS8 CD(min)

− VC (27)

∆VL due to the toleranceof LY (± 10%)and yokecurrent regulation;

∆VL =1.1 IY 1.1 LY

tS− VL (28)

∆VSAT1 = VSAT1(MAX) - VSAT1∆VSAT2 = VSAT2(MAX) - VSAT2

For each parameter, it is necessary to calculate thefactor p, expressing the percentual influence ofevery parameter variation on the nominal supplyvoltage, with the following formulas :for VOM :

ρ =∆VVOM

for VTOP :

ρ =∆V

VTOP

We have then to calculate the square mean root ofthe spreads expressed as :

√ Σ ρ2

So if we call :

VOM1 = VOM

1 + √ Σ ρ2

and :

VTOP1 = VTOP

1 + √ Σ ρ2

We can write :

VS = VOM1 + VTOP1 (29)

An example of calculation will better explain theprocedure. We shall consider a 26”, 110o,neck 29.1mm tube whose characteristics are :IY = 1.2 App,RY = 9.6Ω ± 7%,LY = 24.6mH ± 10%.

We shall use a coupling capacitance CD of 1500µFwith + 50% and - 10% tolerance and a feedbackresistance RF of 1.2Ω.


16/23

a) Nominal minimum supply voltage :

VY = (1.2 RY + RF) IY = 15.264V

VC =IY ⋅ tS8 ⋅ CD

= 2V

VL =LY ⋅ IY

tS= 1.476V

VSAT1 = 1.25V VSAT2 = 0.68V

VD = 1V

VOM = 11.788V VTOP = 6.406V

We obtain : VS = 18.2V

b) Statistical minimum supply voltage :

∆VC = 2.702V

ρ VYM =VY⁄2VOM

ρ2 VYM = 1.313 . 10-3

ρ VYT =VY⁄2

VTOPρ2 VYT = 4.447 . 10-3

∆VC = 0.445V ρ2 VCM = 1.421 . 10-3

ρ2 VCT = 4.813 . 10-3

∆VL = 0.31V ρ2 VLM = 6.914 . 10-4

ρ2 VLT = 2.341 . 10-3

∆VSAT1 = 0.45V ρ2 VSAT1T = 4.935 . 10-3

∆VSAT2 = 0.27V ρ2 VSAT2T = 5.246 . 10-4

VOM1 = VOM ( 1 + √Σ ρ2 ) = 13.268V

VTOP1 = VTOP ( 1 + √Σ ρ2 ) = 7.930V

VS = VOM1 + VTOP1 = 21.2V

This is a real value for the minimum supply voltageneeded by the above mentioned application.In this case we obtain a flyback duration of about :

tF = 23

IY ⋅ LY

VS≈ 900µs

12 - CALCULATION OF MIDPOINT AND GAIN

For the calculation of the output midpoint voltage,it is necessary to consider the different feedbacknetwork for the applications of the various inte-grated circuits.We shall first consider the TDA1170 family, the

AN

373-

34.E

PS

Figure 34 : Circuit utilized for the calculation ofMidpoint and Gain for TDA1170,TDA1175, TDA8176, TDA2170,TDA2270, TDA8170, TDA8172,TDA8173 and TDA8175

TDA1175, TDA2170, TDA2270, TDA8170,TDA8172, TDA8173, TDA8175 and TDA8176.The equivalent circuit of the output stage is repre-sented in Figure 34.

For DC considerations we shall consider the twocapacitors as open circuits. Because of the veryhigh gain of the amplifier we can suppose :V − = VR.

We can so write :

I1 + I2 = I3 (30)

where :

I1 =Vi − VR

R1I2 =

VO − VR

RA + RBI3 =

VR

RF + RS

Substituting into the (30) we obtain :

VO = VR

1 +RA + RB

RF + RS

− ( Vi − VR )(RA + RB

R1(31)


17/23

AN

373-

35.E

PS

Figure 35 : Circuit utilized for the calculation ofMidpoint and Gain for TDA1670A,TDA1675, TDA1770A, TDA1771,TDA1872A and TDA8174

Let ’s consider now TDA1670A, TDA1675,TDA1770A, TDA1771, TDA1872A and TDA8174.The equivalent output circuit is depicted in Fig-ure 35.

We can write :

I1 = I2 (32)

I2 + I3 = I4 (33)

where :

I1 =Vi − VR

R1I2 =

VR − VX

R2I3 =

VO − VX

RAI4 =

VX

RB + RS

wth the (32) and (33) we can calculate the DC

output voltage. It results in :

VO = VR

1 +RA + R2

R1+

RA ( R1 + R2 )R1 ( RB + RS )

(34)

- Vi

RA + R2

R1+ RA ⋅ R2

R1 ( RB + RS )

Referring to Figures 34 and 35, it is possible tocalculate the transconductancegain of the poweramplifier. For this calculation we shall do the follow-ing approximations :- the capacitors are practically short circuits;- the gain A of the amplifier is very high (A → ∞).For the circuit represented in Figure 34 we obtain :

IY =RF

R1 ⋅ RSVi (36)

while for the application in Figure 35 the kokecurrent results in :

IY =R2 + RA // RB // RC

R1 ⋅ RSVi (37)

Using the (31), (34), (35) and (36) it is possible tocalculate the external feedback network for everydifferent yoke known the scanning current and themidpoint ouput voltage.We can now consider the open loop gain of thewhole system amplifier plus external feedbacknet-work. This calculation isuseful in order to verify thatno oscillations can occur at any frequency.We shall consider some typical applications; theresults are reported in Figures 36, 37 and 38.It is easy to verify that in all cases, when the gainreaches 0dB, the phase margin is about 60o, so thestability of the system is assured.


18/23

AN

373-

38.E

PS

Figure 38 : Open Loop Gain and Phase for the Application Circuit in Figure 29A

N37

3-37

.EP

S

Figure 37 : Open Loop Gain and Phase for the Application Circuit in Figure 28

AN

373-

36.E

PS

Figure 36 : Open Loop Gain and Phase for the Application Circuit in Figure 27


19/23

13 - MONITOR APPLICATIONS

In monitor applications the flyback time neededcould be very smaller than the onewe get using theminimum supply voltage calculation.It is possible to reduce the flyback time in twodifferent ways :a) increasing the supply voltage, when the

nominal value calculated is lower than theintegrated circuit limit ;

b) choosing a yoke with lower values ininductance and resistance and by supplyingthe circuit with the voltage needed for gettingthe right flyback time.

In both cases we have to calculate the biasing andthe gain conditions using the nominal voltage andthen we fix the supply voltage for the flyback timerequested with the formula (18) :

VS =23

IY ⋅ LY

tF

The calculation procedure for monitors is so thesame as the one we have explained in the previouschapters for television applications.

14 - POWER DISSIPATION

We shall now examine the power dissipation of theintegrated circuit and the dimensions of theheatsink.To calculate the powerdissipatedwe must considerthe maximum scanning current required to drivethe yoke IY(MAX) and the maximum supply voltageVS(MAX) because we have to dimension theheatsink for the worst case.The current absorbed from the power supply isdepicted in Figure 39.

AN

373-

39.E

PS

Figure 39 : Current absorbed from the PowerSupply during Scanning

The equation of the curve :

i(t) =IY2

−IYT

t for 0 < t ≤ T/2

i(t) = 0 for T/2 < t ≤ T(37)

To the previous one we have to sum the DC currentnecessary to supply the other parts of the circuit(quiescent current).The power absorbed by the deflection circuit isthen :

PA = ∫0

T/2

VS(MAX) ⋅ i(t) ⋅ dt + VS(MAX) ⋅ IDC

= VS(MAX) ∫0

T/2

IY(MAX)

2−

IY(MAX)

Tt

dt + VS(MAX) ⋅ IDC

The solution is :

PA = VS(MAX)

IY(MAX)

3+ IDC

(38)

The power dissipated outside the integrated circuitis formed by the three following fundamental com-ponents : the scanning power dissipated in theyoke for which the minimum resistance of yokeRY(MIN) and the maximum scanning current IY(MAX)must be considered, the power dissipated in thefeedback resistance RF and that one dissipated inthe diode for recovery of flyback.The power dissipated outside the integrated circuitis then :

PY = ∫0

T( RY(MIN) + RF ) i2(t) ⋅ dt + ∫ V

0

T/2

VD i(t) ⋅ dt

= ( RY(MIN) + RF ) ∫0

T

IY(MAX)

2−

IY(MAX)

Tt

2dt

+ VD ∫0

T/2

IY(MAX)

2−

IY(MAX)

Tt

dt

The solution is :

PY =I Y(MAX)2 ( RY(MIN) + RF )

12+

IY(MAX) ⋅ VD

8(39)

The Power dissipated inside the integated circuitis :

PD = PA - PY (40)


20/23

The thermal resistance of the heatsink to be usedwith the integrated circuit depends upon the maxi-mum junction temperature TJ(MAX), the maximumambient temperature Tamb and the thermal resis-tance between junction and tab Rth (j -TAB) that isdifferent for the various packages used. The ther-mal resistance of the heatsink is expressed by thefollowing formula :

Rth (j − a) = TJ(MAX) −Tamb(MAX)PD(MAX)

− Rth ( j − TAB ) (41)

As an example we can calculate the dissipatedpower and the thermal resistance of the heatsinkfor the 26”, 110o, neck 29.1mm tube for which wecalculated the minimum supply voltage in chap-ter 11.We shall consider the integratedcircuit TDA1670Aand we can suppose a maximum supply voltage of25V.The power absorbed from the supply is :

PA = 25

1.28

+ 0.04

= 4.75W

The powerdissipated outside the integrated circuitis :

PY =1.22 (9.6 ⋅ 0.93 + 1.2)

12+ 1.21

8= 1.37W

therefore the power dissipated by the integratedcircuit is :

PD = 4.75 - 1.37 = 3.38W

The thermal resistance of the heatsink,consideringthe RTH J-TAB for the multiwatt package of 3oC/W, amaximum junction temperature of 120oC and amaximum ambient temperature of 60oC is :

Rth (j−a) = 120 − 603.38

− 3 = 15°C/W

For the same application with TDA1170S we havea thermal resistance for the heatsink of about8oC/W.

15 - BLANKING PULSE DURATION ADJUST-MENT

For the devices that have the blanking generator itis possible to adjust the blanking pulse duration.We shall consider as an example the TDA1670A;the circuit arrangement is depicted in Figure 40.

By adjusting R3 the blanking pulse duration will beadapted to the flyback time used and the picturetube protection will be ready to work properly.When necessary, it is possible to use a trimmersystem to adjust it very carefully.

16 - LINEARITY ADJUSTMENT

The complete vertical stageshave the possibility tocontrol the linearity of the vertical deflection ramp.There are two different methods to obtain theabove mentioned performance.

a) For the first method we shall refer toFigure 41The linearity regulation is obtainedby meansof RA,RB and RT2.

AN

373-

40.E

PS

Figure 40 : Circuit Arrangement for BlankingPulse Duration Adjustment

AN

373-

41.E

PS

Figure 41 : Circuitry for Ramp Linearity Regula-tion

In order to choose the right values of this compo-nents we suggest to follow the following proce-dure :1 - Set the amplitude regulation potentiometer

RT1 for the nominal raster size ;2 - Disconnect the RA resistance ;3 - Adjust the linearity control potentiometer RT2

in order to obtain the top and the bottom of theraster with the same amplitude ;

4 - In this condiotion the center of the raster mustbe narrower then the top and the bottom. Ifwith RA disconnected the center is larger thanthe top and the bottom it is necessary to acton the feedbacknetwork. Referring to Figures27, 28 and 29 it is necessary to increase thecapacitors C11, C8 or C6 ;


21/23

5 - After increasing the capacitors it is necessaryto repeat the linearity adjustment (R12potentiometer) in order to get the top and thebottom with the same amplitude again ;

6 - Connect the RA resistor and repeat thelinearity adjustment (point 3 regulation) ;

7 - Check the top and the bottom amplitudecomparing it with the center. If the centeramplitude is still narrower it is necessary toreduce RA. If the center amplitude becomeslarger it is necessary to increase RA.

Note : Every time the linearity conditions arechanged (for adjusting or setting) before checkingthe linearity status, the point 3 adjustment must berepeated.

b) For the second method we shall refer toFigure 28In this case the linearity regulation is obtainedacting directly on the feedback network, that issubstituting the R8 resistance with a potentiometer.This solution is cheaper than the first one, becauseit is possible to save the resistors RA, RB (seeFigure 41), the potentiometerRT2 and to use onlya capacitor instead of the series C1 and C2.On the other hand a disadvantage is due to the factthat the resistanceR8 influencesnot only the linear-ity of the ramp but also the gain of the amplifier, asit can be seen in the equation (36). So to performa linearity adjustment it is necessary to act at thesame time on the potentiometer in the feedbackloop and on the potentiometer RT1 (see Figure 41)in order to correct the vertical amplitude variations.On the contrary, in the method a) the linearitycontrol network doesn’t influence any other pa-rameters. this is the reason why the a) method isgenerally adopted by all television set producers.

17 - FACILITIES AND IMPROVEMENTS

In this section we shall briefly examine some facili-ties which may be useful to improve operations ofthe television set.

a) Blanking generator and CRT protection forTDA1170 familyAt pin 3 a pulse is available which has the sameduration and phase as the flyback and amplitudeequal to the supplyvoltage.If the retrace duration is not sufficient for carrying

AN

373-

42.E

PS

Figure 42 : Blanking Generator and CRT Protec-tion for TDA1170

out correct vertical blanking, for instance in thepresence of text and teletext signals the circuit ofFigure 42 can be used.

The true blanking generator is formed by Q1,R3 andC2and the blankingduration is dependentupon thevalues of R3 and C2. The other components areused for picture tube protection in the event of lossof vertical deflection current. If for any reason thereis no flyback, the transistor Q1 is permanentlyinhibited and provides continuous switch off whicheliminates the white line at the center of the screen.Thermal stability and stability with the supply volt-age is good in relation to the simplicity of theapplication.

b) Vertical deflection current compensation tomaintain picture size with beam current vari-ationsChanges in the supply voltage or the brightnessand contrast controls will bring out changes of thebeam current, thus causing EHT and picture sizevariations.The rate of change of the picture size is mainlydependentupon the EHT internal resistance.In order to avoid variations of the vertical picturesize it is necessary to track the scanning current tothe beam current. Because the tracking ratio :

∆ IYOKE

∆ IBEAM⋅ 100 (42)

varies from one chassis design to another, threesuggested tracking circuits are shown in Figures43, 44 and 45.


22/23

AN

373-

45.E

PS

Figure 45 : Circuit for Vertical Scanning CurrentVariation according with the SupplyVoltage

AN

373-

44.E

PS

Figure 44 : Circuit for Vertical Scanning CurrentVariation according with the SupplyVoltage

AN

373-

43.E

PS

Figure 43 : Circuit for Vertical Scanning CurrentVariation according with the BeamCurrent

The circuit in Figure 43 adopts the straight forwardtechnique of linking the vertical scanning currentdirectly to the beam current .Its drawback lies in thefact thata long wireconnection is requiredbetweenthe EHT transformer and the vertical circuit, andthe layout of this connection could be critical forflashover.

The circuit of Figure 44, which links the verticalscanning current directly to the supply voltage, isthe simplest one. Its drawback could be incorrecttracking ratio and ripple on the supply voltage.Toovercome the drawbacks of the preceding circuit itis usefull to filter out the supply voltage ripple andadjust the tracking ratio by transferring the supplyvoltage to a lower level by means of a Zener diodeas shown in Figure 45. Tracking ratio is adjustedby choosing a suitable Zener voltage value.

18 - GENERAL APPLICATION AND LAYOUTHINTS

In order to avoid possible oscillations induced bythe layout it is very important to do a good choiceof the Boucherot cell position and ground placing.The Boucherot cell must be placed the most pos-sible closed to the vertical deflection output of theintegrated circuit, while the ground of the sensingresistor in series connected with the yoke must bethe same as the one of the integrated circuit anddifferent from the one of other power stages.Particular care must be taken in the layout designin order to protect the integrated circuit againstflashover of the CRT. For instance the ground ofthe filter capacitor connected to the power supplymust be near the integrated circuit ground.

19 - REFERENCES

1) Television Deflection Systems - A. Boekhorst,J. Stolk - Philips Technical library.

2) TV Vertical Deflection System TDA1170S -SGS-THOMSON Application Notes.

3) TDA1670A Technical Note - SGS-THOMSONTechnical Note.

4) TV and Monitor Vertical Deflection usingTDA1670A - O. Cossutta,F. Gatti SGS-THOMSON Application Notes.

5) TDA1670A Flyback Stage Behaviour -A. Messi, G. Nardini - SGS-THOMSONApplication Notes.


23/23

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibilityfor the consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the PhilipsI2C Patent. Rights to use these components in a I 2C system, is granted provided that the system conforms to

the I2C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - MoroccoThe Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. O

RD

ER

CO

DE

:

Documents

VERTICALDEFLECTION CIRCUITS FOR TV & MONITOR