Vhdl and Verilog

7/31/2019 Vhdl and Verilog

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Aneesh R Broadcast and communication group

Centre for development of advanced computingThiruvananthapuram


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Main topics:Circuit design based on VHDLVHDL basics

Advanced VHDL language structuresCircuit examples


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VHDLVHDLis an acronym of VHSIC Hardware DescriptionLanguageVHSICis an acronym of Very High Speed IntegratedCircuits

A Formal Language for Specifying the Behavior andStructure of a Digital CircuitAllows Top-Down Design


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Gajskis YGajskis Y--chartchart

Each axis represents type of description Behavioral

Defines out uts as function of in uts

BehaviorStructural

Processors, memories

Registers, FUs, MUXs

Gates, flip-flops

Transistors

Sequential programs

Register transfers

Logic equations/FSM

Transfer functions

Cell Layout

Algorithms but no implementation Structural

Implements behavior by connectingcomponents with known behavior

Physical

Gives size/locations of componentsand wires on chip/board

Design process is illustrated by travelroute

Physical

ModulesChips

Boards


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Test Vector

Generator

ExecutableSpecification

Results,Errors=

A Series of Refined

Models

TestVectors

Final Chip

Model


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VHDL requirements for SimulationCreation of test benches =>

File I/ODetection of errors function & timin

Multiple simultaneous modelsCombination of low & high level models

(for efficiency)


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VHDL requirements for HW DescriptionBehavioral models =>

Combinatorial & Sequential LogicRTL models

Structural modelsTiming models


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Requirements for VHDL Synthesis ToolsPre- & post synthesis behavior should be identicalSynthesis should be efficient =>

Logic SynthesisFSM SynthesisArea & Timing Optimization


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Shorter development times for electronic designSimpler maintenanceTraditional way: schematic design


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VHDL originated in the early 1980sThe American Department of Defense initiated thedevelopment of VHDL in the early 1980s

because the US military needed a standardized method of describing electronic systems

VHDL was standardized in 1987 by the IEEEIt is now accepted as one of the most importantstandard languages for

specifyingverifyingdesigning of electronics


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IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used byindustry worldwideVHDL enables hardware modeling from the gate levelto the system level

t e ma or too manu acturers now support t eVHDL standardVHDL is now a standardized language, with theadvantage that it is easy to move VHDL codebetween different commercial platforms (tools)

=> VHDL code is interchangeable among the differenttools


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VHDL is an acronym of VHSIC Hardware DescriptionLanguage

VHSIC is an acronym of Very High Speed IntegratedCircuitsAll the major tool manufacturers now support the

VHDL is now a standardized language, with theadvantage that it it easy to move VHDL codebetween different commercial platforms (tools)

=> VHDL code is interchangeable among the differenttools


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It was the American Department of Defense whichinitiated the development of VHDL in the early 1980sbecause the US military needed a standardized methodof describing electronic systemsVHDL was standardized in 1987 by the IEEE

- -ANSI Standard in 1988Added Support for RTL Design

VITAL: VHDL Initiative Towards ASIC Library

Revised version in 1993IEEE Std-1076-1993


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1995:

numeric_std/bit: IEEE-1076.3VITAL: IEEE-1076.41999: IEEE-1076.1 (VHDL-AMS )

IEEE-1076-2000IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)

Added mixed-signal support to VHDL in 2001 ->VHDL-AMS

IEEE Std-1076.1-2001

2002: IEEE-1076-2002


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Good VHDL tools, and VHDL simulators in particular, have also

been developed for PCs

Prices have fallen dramatically, enabling smaller companies to

,

There are also PC synthesis tools, primarily for FPGAs and

EPLDs


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High-tech companiesTexas Instruments, Intel use VHDLmost European companies use VHDL

Universities

VHDL groups to support new users


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IEEE is the Institute of Electrical and Electronics

EngineersThe reference manual is called IEEE VHDL LanguageReference Manual Draft Standard version 1076/B

It was ratified in December 1987 as IEEE 1076-1987

Important:

the VHDL is standardized for system specificationbut not for design


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The design of VHDL components can be technology-independentor more-or-less technology independent for a technical family

The com onents can be stored in a librar for reuse in several

different designs

VHDL models of commercial IC standard components can now

be bought, which is a great advantage when it comes toverifying entire circuit boards


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VHDL has not yet been standardized for analog electronics

Standardization is in progress on VHDL with an analog extension(AHDL) to allow analog systems to be described as well

and will have a number of additions for describing analog

functions


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There are several other language extensions built to either aid in RTL construction

or assist in modeling:

ParaCore - http://www.dilloneng.com/paracore.shtmlRubyHDL -http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml

MyHDL -http://jandecaluwe.com/Tools/MyHDL/Overview.shtml

JHDL - http://www.jhdl.org/

Lava - http://www.xilinx.com/labs/lava/HDLmaker - http://www.polybus.com/hdlmaker/users_guide/

SystemC

AHDL http://www.altera.com

It is good for Altera-made chips only, which limits its usefulness

But i t is easy to pick up and use successfully

The main purpose of a language -- programming, hdl, or otherwise -- is to ease theexpression of design


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Verifying Logic

Phil Moorby from Gateway Design Automation in 1984 to 1987

Absorbed by Cadence

Cadence 's ownership of Verilog => others support VHDLVerilog-XL simulator from GDA in 1986

Synopsis Synthesis Tool in 1988

In 1990 became o en lan ua e

OVI: Open Verilog International

IEEE Standard in 1995

IEEE Std-1364-1995

Last revision in 2001

IEEE Std-1364-2001

Ongoing work for adding

Mixed-signal constructs: Verilog-AMS

System-level constructs: SystemVerilog


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VHDLVHDL VerilogVerilog

All abstraction levelsAll abstraction levels All abstraction levelsAll abstraction levels

Complex grammarComplex grammar Easy languageEasy language

Describe a system (everything)Describe a system (everything) Describe a digital systemDescribe a digital systemLots of data typesLots of data types Few data typesFew data types

UserUser--defined package & librarydefined package & library No userNo user--defined packagesdefined packages

u es gn parame er za onu es gn parame er za on mp e parame er za onmp e parame er za on

Easier to handle large designsEasier to handle large designs

VVery consistent language.ery consistent language. Code written andCode written andsimulated in one simulator will behavesimulated in one simulator will behaveexactly the same in another simulator.exactly the same in another simulator. E.g.E.g.

strong typing rules.strong typing rules.

LL ess consistent language.ess consistent language. If you don'tIf you don'tfollow some adhoc methodology for codingfollow some adhoc methodology for codingstyles, you will not get it right.styles, you will not get it right.

IItt executes differently on different platformsexecutes differently on different platformsunlessunless you follow some adhoc coding rules.you follow some adhoc coding rules.


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It does seem that Verilog is easier for designing at thegate-level, but that people who do higher level simulations express apreference for VHDLVHDL places constraints on evaluation order that limit theoptimizations that can be performed

Verilog allows the simulator greater freedom

For example, multiple levels of zero-delay gates can be collapsed into asingle super-gate evaluation in VerilogVHDL requires preserving the original number of delta cycles of delayin propagating through those levels

VHDLVHDL VerilogVerilogIn Europe the VHDL is the most popularIn Europe the VHDL is the most popularlanguagelanguage

Based on Pascal languageBased on Pascal language Based on C languageBased on C language

Most FPGA design in VHDLMost FPGA design in VHDL MostMost ASIC design in VerilogASIC design in Verilog


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VHDL:process (siga, sigb)

begin...end;

er o :always @ (siga or sigb)begin.

end


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VHDL:c


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VHDL:a


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VHDL:

signal clk : std_logic := 0;processbegin

clk


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Not well suited for complex, high level modelingNo user defined type definitionNo concept of libraries, packages, configurationsNo generate statement - cant build parameterizedstructural models

No complex types above a two-dimensional array


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VHDL:Configuration, generate, generic and package statements allhel mana e lar e desi n structures

Verilog:There are no statements in Verilog that help manage largedesigns


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VHDL:

Verilog:does not allow concurrent task calls


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VHDL:The generate statement replicates a number of instances of the same design-unit or some subpar o a es gn, an connec s appropr a e y

Verilog:There is no equivalent to the generate statement

in Verilog.


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SystemVerilogExtending Verilog to higher levels of abstraction forarchitectural and algorithm design and advanced verification

VHDL 200x

Enhance/update VHDL for to improve performance, modelingcapability, ease of use, simulation control, and the type system

e.g.: Data types and abstractions:variant records

interfaces


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Vhdl and Verilog