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VHDL code for a 74LS194 Universal Shift Register Hi everyone! I've got an assignment about writing the VHDL code for a 74LS194 shift register, but I'm not allowed to use the functional description. So far I've made this, but I'm not sure if it's ok (I've simulated it, but since I'm new to VHDL I'm not sure if it's working as it should). Thanks a lot for your help, here's the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity IC74LS194 is Port ( clear, S0, S1, clk, SL, SR, A, B, C, D : in STD_LOGIC; Qa, Qb, Qc, Qd : out STD_LOGIC); end IC74LS194; architecture Schematic of IC74LS194 is signal Qas, Qbs, Qcs, Qds : STD_LOGIC; signal LogicA, LogicB, LogicC, LogicD : STD_LOGIC; begin LogicA <= (SR and not(S1) and S0) or (S0 and S1 and A) or (not(S0) and S1 and Qbs) or (S0 and not(S1) and Qas); LogicB <= (S0 and not(S1) and Qas) or (S0 and S1 and or (not(S0) and S1 and Qcs) or (not(S0) and not(S1) and Qbs); LogicC <= (S0 and not(S1) and Qbs) or (S0 and S1 and C) or (not(S0) and S1 and Qds) or (not(S0) and not(S1) and Qcs); LogicD <= (S0 and not(S1) and Qcs) or (S0 and S1 and D) or (not(S0) and S1 and SL) or (not(S0) and not(S1) and Qds); FFA: process (clear, clk, Qas) begin if clear ='0' then Qas <= '0'; elsif rising_edge (clk) then Qas <= LogicA; else Qas <= Qas; end if; end process; FFB: process (clear, clk, Qbs) begin if clear ='0' then Qbs <= '0'; elsif rising_edge (clk) then Qbs <= LogicB;

VHDL Code for a 74LS194 Universal Shift Register

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VHDL code for a 74LS194 Universal Shift RegisterHi everyone!I've got an assignment about writing the VHDL code for a 74LS194 shift register, but I'm not allowed to use the functional description. So far I've made this, but I'm not sure if it's ok (I've simulated it, but since I'm new to VHDL I'm not sure if it's working as it should).Thanks a lot for your help, here's the code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity IC74LS194 isPort ( clear, S0, S1, clk, SL, SR, A, B, C, D : in STD_LOGIC;Qa, Qb, Qc, Qd : out STD_LOGIC);end IC74LS194;

architecture Schematic of IC74LS194 issignal Qas, Qbs, Qcs, Qds : STD_LOGIC;signal LogicA, LogicB, LogicC, LogicD : STD_LOGIC;begin

LogicA


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