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VHDLVHDL
Rabee ShatnawiRabee Shatnawi
&&
Rami HaddadRami Haddad
What is this presentation What is this presentation about?!about?!
This presentation will introduce the key concepts in
VHDL and theimportant syntax required for
most VHDL designs,
Why to use VHDL?Why to use VHDL?
In most cases, the decision to use In most cases, the decision to use VHDL over other languages such VHDL over other languages such asasVerilog or SystemC, will have less Verilog or SystemC, will have less to do with designer choice, and to do with designer choice, and more to do with software more to do with software availability and company availability and company decisions…. Or the professor's decisions…. Or the professor's choicechoice ;-);-)
•Verilog has come from a ‘bottom-up’ tradition and has been heavily used by the IC industry for cell-based design,
• whereas the VHDL language has been developed much more from a ‘topdown’ perspective.
Of course, these are generalizations and largely out of date in a modern context
Entity: model interface
•The entity defines how a design element described in VHDL connects to other VHDL models …
•and also defines the name of the model.
• It allows the definition of any parameters that are to be passed into the model using hierarchy.
Entity definition
entity test is …. end entity test;
• or:
entity test is …end test;
Ports
• How to connect Entities together?How to connect Entities together?
-The method of connecting entities together is using PORTS.
- PORTS are defined in the entity using the following method:
port (...list of port declarations... );
•The port declaration defines the type of connection and direction where appropriate.
port ( in1, in2 : in bit; out1 : out bit );
Entity Port ModesEntity Port Modes
• in: in: – signal values are read-only signal values are read-only
• out: out: – signal values are write-onlysignal values are write-only
• buffer: buffer: – comparable to out comparable to out – signal values may be read, as wellsignal values may be read, as well
• inout:inout:– bidirectional port bidirectional port
Generics
If the model has a parameter, then it is defined using generics.
generic ( gain : integer := 4; time_delay : time = 10 ns );
Constants
• It is also possible to include model specific constants in the entity using the standard declaration of constants method
constant : rpullup : real := 1000.0;
a complete examples, meet our first Entity……. test entity test is port ( in1, in2 : in bit; out1 : out bit ); generic ( gain : integer := 4; time_delay : time := 10 ns ); constant : rpullup : real := 1000.0; end entity test;
Architecture: model behavior• Implementation of the designImplementation of the design
• Always connected with a specific Always connected with a specific entityentity– one entity can have several architectures one entity can have several architectures – entity ports are available as signals entity ports are available as signals
within the architecture within the architecture
• Contains concurrent statements Contains concurrent statements
Basic definition of an architecture
•While the entity describes the interface and parameter aspects of the model ……….
• the architecture defines the behavior.
•There are several types of VHDL architecture and ….
• VHDL allows different architectures to be defined for the same entity.
architecture behaviour of test is ..architecture declarations begin ...architecture contents end behaviour;
any local signals or variables
can be declared here
SignalsSignals
• Signals are the primary objects describing the Signals are the primary objects describing the hardware system and are equivalent to hardware system and are equivalent to “wires”.“wires”.
• They represent communication channels They represent communication channels among concurrent statements of system among concurrent statements of system application.application.
• Signals can be declared in:Signals can be declared in:– Package declarationPackage declaration– ArchitectureArchitecture– Block:Block:– Subprograms: Subprograms:
Hierarchical design
•Functions
•Packages
•Components
•Procedures
Functions
•A simple way of encapsulating behavior in a model that can be reused in multiple architectures.
•Can be defined locally to an architecture or more commonly in a package
•The simple form of a function is to define a header with the input and output variables as shown below:
function name (input declarations) return output_type is
... variable declarationsbegin... function bodyend
function mult (a,b : integer) return integer is
beginreturn a * b;end;
Package : Function containers
package name is...package header contentsend package;package body name is... package body contentsend package body;
The header: is the place where the types
and functions aredeclared
package body: where the declarations
themselvestake place
Component
library ieee; use ieee.std_logic_1164.all; -- here is the entity entity halfadd is port (a, b : in std_logic; sum, c : out std_logic); end halfadd; architecture comp of halfadd is begin -- a concurrent statement implementing the and
gate c <= a and b; -- a concurrent statement implementing the xor
gate sum <= a xor b; end comp;
library ieee; use ieee.std_logic_1164.all; entity fulladd is port (ina, inb, inc : in std_logic; sumout, outc : out std_logic); end fulladd; architecture top of fulladd is component halfadd port (a, b : in std_logic; sum, c : out std_logic); end component; signal s1, s2, s3 : std_logic; begin -- a structural instantiation of two half adders h1: halfadd port map( a => ina, b => inb, sum => s1, c => s3); h2: halfadd port map( a => s1, b => inc, sum => sumout, c => s2); outc <= s2 or s3; end top;
VHDLVHDL
• Case insensitiveCase insensitive• Comments: '--' until end of line Comments: '--' until end of line
Statements are terminated by ';'Statements are terminated by ';'(may span multiple lines) (may span multiple lines)
• List delimiter: ',' List delimiter: ',' • Signal assignment: '<=‘Signal assignment: '<=‘• User defined names:User defined names:
– letters, numbers, underscores letters, numbers, underscores – start with a letter start with a letter
VHDL …. IdentifierVHDL …. Identifier• (Normal) Identifier Letters, numerals, (Normal) Identifier Letters, numerals,
underscores underscores
• Case insensitive Case insensitive
• No two consecutive underscores No two consecutive underscores
• Must begin with a letter Must begin with a letter
• Not a VHDL keyword Not a VHDL keyword mySignal_23 -- normal identifierrdy, RDY, Rdy -- identical identifiersvector_&_vector -- X : special characterlast of Zout -- X : white spacesidle__state -- X : consecutive underscores24th_signal -- X : begins with a numeralopen, register -- X : VHDL keywords
VHDL Structural ElementsVHDL Structural Elements
• Entity : Interface Architecture : Entity : Interface Architecture : • Implementation, behavior, function Implementation, behavior, function • Configuration : Model chaining, structure, Configuration : Model chaining, structure,
hierarchy hierarchy • Process : Concurrency, event controlled Process : Concurrency, event controlled • Package : Modular design, standard Package : Modular design, standard
solution, solution, • data types, constants data types, constants • Library : Compilation, object code Library : Compilation, object code
Hierarchical Model LayoutHierarchical Model Layout
• VHDL allows for a hierarchical model layout, which VHDL allows for a hierarchical model layout, which means that a module can be assembled out of means that a module can be assembled out of several submodules. The connections between several submodules. The connections between these submodules are defined within the these submodules are defined within the architecture of a top module. As you can see, a architecture of a top module. As you can see, a fulladder can be built with the help of two fulladder can be built with the help of two halfadders (module1, module2) and an OR gate halfadders (module1, module2) and an OR gate (module3).(module3).
entity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;architecture STRUCT of FULLADDER is signal W_SUM, W_CARRY1, W_CARRY2 : bit; component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component; component ORGATE port (A, B : in bit; RES : out bit); end component;begin
begin MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 ); MODULE2: HALFADDER port map ( W_SUM, CARRY_IN, SUM, W_CARRY2 ); MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY ); end STRUCT;
Component :exampleComponent :exampleENTITY half_adder IS PORT ( A, B : IN STD_LOGIC; sum, carry : OUT STD_LOGIC ); END half_adder; ARCHITECTURE structural OF half_adder IS COMPONENT xor2 PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT;COMPONENT and2
PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END COMPONENT;BEGIN ex1 : xor2 PORT MAP ( a => a, b => b, c => sum ); or1 : and2 PORT MAP ( a => a, b => b, c => carry ); END structural;
ENTITY and2 IS PORT ( a, b : IN STD_LOGIC; output : OUT STD_LOGIC ); END and2; ARCHITECTURE gate OF and2 IS BEGIN output <= ( a AND b ) AFTER 5ns; END gate
begin
MODULE1: HALFADDER port map ( A => A, SUM => W_SUM, B => B, CARRY => W_CARRY1 ); . . .end STRUCT;
ProcessProcess•The process in VHDL is the mechanism by which
sequential statements can be executed in the correct sequence, and with more than one process, concurrently.– Contains sequentially executed statements Contains sequentially executed statements – Exist within an architecture,Exist within an architecture,– only Several processes run concurrently only Several processes run concurrently – Execution is controlled either via sensitivity list (contains Execution is controlled either via sensitivity list (contains
trigger signals), or wait-statements trigger signals), or wait-statements
ProcessProcessJustToShow: processBegin
Some statement 1;Some statement 2;Some statement 3;Some statement 4;wait<condition>;
end process JustToShow;
JustToShow: processBegin
Some statement 1;Some statement 2;Some statement 3;Some statement 4;Some statement 5;
end process JustToShow;
• Wait for type expression• Wait until condition• Wait on sensitivity list• Complex waitComplex wait
Wait until CLK=‘1’
Wait on Enable
Wait unit date after 10ns
Wait for 10ns
ProcessProcessJustToShow: process ( ) Begin
Some statement 1;Some statement 2;Some statement 3;Some statement 4;end process JustToShow;
• VHDL provides a VHDL provides a construct called construct called sensenitivity list sensenitivity list of a process of a process
• The list specified The list specified next to the next to the process keyword.process keyword.
• The same as wait The same as wait on sensitivity_list on sensitivity_list at the end of a at the end of a processprocess
JustToShow: process Begin
Some statement 1;Some statement 2;Some statement 3;Some statement 4;wait on
end process JustToShow;SomeSig
ProcessProcess
JustToShow: process (signa1,signal2,signal3) JustToShow: process (signa1,signal2,signal3)
BeginBegin
Some statement 1;Some statement 1;
Some statement 2;Some statement 2;
Some statement 3;Some statement 3;
Some statement 4;Some statement 4;
Some statement 5;Some statement 5;
end process JustToShow;end process JustToShow;
Signal2 has changedSignal3 has changed
Example:Example:
JustToShow: process (signal1,signal2,signal3) JustToShow: process (signal1,signal2,signal3) BeginBegin
Some statement 1;Some statement 1;signal3<=signal1+5;signal3<=signal1+5;Some statement 3;Some statement 3;Some statement 4;Some statement 4;Some statement 5;Some statement 5;
end process JustToShowend process JustToShow
Signa1= 0 Signal3=5 6
Example:Example:
process(C,D)process(C,D)beginbegin
A<=2;A<=2;B<=A+C;B<=A+C;A<=D+1;A<=D+1;E<=A*2;E<=A*2;
end process;end process;
A=1B=1C=1D=1E=1
A<=2B<=A+C;A<=D+1
E<=A*2;
32
2
VariablesVariables
• Variables are available within processesVariables are available within processes– Named within process declarations Named within process declarations – Known only in this process Known only in this process
• Immediate assignment Immediate assignment • An assignment to a variable is made with := symbol.An assignment to a variable is made with := symbol.• The assignment take instance effect and each variable can The assignment take instance effect and each variable can
be assigned new values as many times as needed.be assigned new values as many times as needed.• A variable declaration look similar to a signal declaration A variable declaration look similar to a signal declaration
and starts with variable keywordand starts with variable keyword• Keep the last value Keep the last value • Possible assignments Possible assignments
– Signal to variable Signal to variable – Variable to signal Variable to signal – Types have to match Types have to match
Variables vs. SignalsVariables vs. Signals
• SignalsSignals– In a process, only the last signal assignment is In a process, only the last signal assignment is
carried outcarried out– Assigned when the process execution is Assigned when the process execution is
suspendedsuspended– ““<=<=“ to indicate signal assignment“ to indicate signal assignment
• VariablesVariables– Assigned immediatelyAssigned immediately– The last value is keptThe last value is kept– ““:=:=“ to indicate variable assignment“ to indicate variable assignment
Variables vs. Signals Variables vs. Signals (contd.)(contd.)
signalsignal A, B, C, X, Y : A, B, C, X, Y : integerinteger;;beginbegin processprocess (A, B, C) (A, B, C) variable variable M, N : M, N : integerinteger;; beginbegin M M :=:= A; A; N N :=:= B; B; X <= M + N; X <= M + N; M M :=:= C; C; Y <= M + N; Y <= M + N;
endend processprocess;;
signalsignal A, B, C, Y, Z : A, B, C, Y, Z : integerinteger;;signal signal M, N : M, N : integerinteger;;beginbegin processprocess (A, B, C, M, N) (A, B, C, M, N) beginbegin M M <=<= A; A; N N <=<= B; B; X <= M + N; X <= M + N; M M <=<= C; C; Y <= M + N; Y <= M + N;
end processend process;;
+A
BX
+C
BY
+C
BX
+C
BY
VariablesVariables
process(C,D)process(C,D)Variable Av,Bv,Ev :integer :=0;Variable Av,Bv,Ev :integer :=0;beginbegin
A<=2;A<=2;Bv<=Av+C;Bv<=Av+C;Av<=D+1;Av<=D+1;Ev <= Av*2;Ev <= Av*2;A <=Av;A <=Av;B <=Bv;B <=Bv;E <=Ev;E <=Ev;
end processend process
The world is not sequentialThe world is not sequential
• Its convention to specify Its convention to specify things in a sequential way, things in a sequential way, this is not the simplest this is not the simplest way to describe reality.way to describe reality.
• Processes are concurrent Processes are concurrent statements statements
• Several processes run Several processes run parallel linked by signals parallel linked by signals in the sensitivity list in the sensitivity list
• sequential execution of sequential execution of statements statements
• Link to processes of other Link to processes of other entity/architecture pairs entity/architecture pairs via entity interface via entity interface
Architecture SomeArch of SomeEnt isArchitecture SomeArch of SomeEnt is
BeginBegin
P1:process(A,B,E)P1:process(A,B,E)
BeginBegin
Somestatment;Somestatment;
Somestatment;Somestatment;
Somestatment;Somestatment;
D<=Someexpression;;D<=Someexpression;;
End process P1;End process P1;P2:process(A,C)Begin
Somestatment;Somestatment;Somestatment;
End process P1;P3:process(B,D)Begin
Somestatment;Somestatment;Somestatment;
End process P1;end Architecture SomeArch ;
IF Statement: IF Statement: entity IF_STATEMENT isentity IF_STATEMENT is port (A, B, C, X : in bit_vector (3 downto 0); port (A, B, C, X : in bit_vector (3 downto 0); Z : out bit_vector (3 downto 0); Z : out bit_vector (3 downto 0); end IF_STATEMENT; end IF_STATEMENT;
architecture EXAMPLE1 of IF_STATEMEarchitecture EXAMPLE1 of IF_STATEMENT isNT isbeginbegin process (A, B, C, X) process (A, B, C, X) begin begin Z <= A; Z <= A; if if (X = "1111") (X = "1111") then then Z <= B; Z <= B; elsif elsif (X > "1000") (X > "1000") then then Z <= C; Z <= C; end if; end if; end process; end process;end EXAMPLE1;end EXAMPLE1;
architecture EXAMPLE2 of IF_STATEMEarchitecture EXAMPLE2 of IF_STATEMENT isNT isbeginbegin process (A, B, C, X) process (A, B, C, X) begin begin
if if (X = "1111") (X = "1111") then then Z <= B; Z <= B; elsif elsif (X > "1000") (X > "1000") then then Z <= C; Z <= C; else else Z <= a; Z <= a; end if; end if; end process; end process;end EXAMPLE2;end EXAMPLE2;
entity RANGE_1 isentity RANGE_1 isport (A, B, C, X : in integer range 0 toport (A, B, C, X : in integer range 0 to 15; 15; Z : out integer range 0 to Z : out integer range 0 to 15;15;end RANGE_1;end RANGE_1; architecture EXAMPLE of RANGE_1 isarchitecture EXAMPLE of RANGE_1 isbeginbegin process (A, B, C, X) process (A, B, C, X) begin begin case X is case X is when 0 => when 0 => Z <= A; Z <= A; when 7 | 9 => when 7 | 9 => Z <= B; Z <= B; when 1 to 5 => when 1 to 5 => Z <= C; Z <= C; when others => when others => Z <= 0; Z <= 0; end case; end case; end process; end process;end EXAMPLE;end EXAMPLE;
entity RANGE_2 isentity RANGE_2 isport (A, B, C, X : in bit_vector(3 downto port (A, B, C, X : in bit_vector(3 downto 0);0); Z : out bit_vector(3 downto Z : out bit_vector(3 downto 0);0);end RANGE_2;end RANGE_2; architecture EXAMPLE of RANGE_2 isarchitecture EXAMPLE of RANGE_2 isbeginbegin process (A, B, C, X) process (A, B, C, X) begin begin case X is case X is when "0000" => when "0000" => Z <= A; Z <= A; when "0111" | "1001" => when "0111" | "1001" => Z <= B; Z <= B; when "0001" to "0101" => -- when "0001" to "0101" => -- wrongwrong Z <= C; Z <= C; when others => when others => Z <= 0; Z <= 0; end case; end case; end process; end process;end EXAMPLE;end EXAMPLE;
Case statementCase statement
For loopFor loop• entity FOR_LOOP isentity FOR_LOOP is
port (A : in integer range 0 to 3; port (A : in integer range 0 to 3; Z : out bit_vector (3 downto 0)); Z : out bit_vector (3 downto 0)); end FOR_LOOP; end FOR_LOOP; architecture EXAMPLE of FOR_LOOP isarchitecture EXAMPLE of FOR_LOOP isbegin begin process (A) process (A) begin begin Z <= "0000"; Z <= "0000"; for for I I in in 0 to 3 0 to 3 loop loop if (A = I) then if (A = I) then Z(I) <= `1`; Z(I) <= `1`; end if; end if; end loop; end loop; end process; end process;end EXAMPLE;end EXAMPLE;
entity CONV_INT isentity CONV_INT is port (VECTOR: in bit_vector(7 downto 0); port (VECTOR: in bit_vector(7 downto 0); RESULT: out integer); RESULT: out integer); end CONV_INT; end CONV_INT;
architecture A of CONV_INT architecture A of CONV_INT isisbeginbegin process(VECTOR) process(VECTOR) variable TMP: integer; variable TMP: integer;
begin begin TMP := 0; TMP := 0;
for I in 7 downto 0 loop for I in 7 downto 0 loop if (VECTOR(I)='1') if (VECTOR(I)='1') thenthen TMP := TMP + 2**I; TMP := TMP + 2**I; end if; end if; end loop; end loop;
RESULT <= TMP; RESULT <= TMP; end process; end process;end A;end A;
architecture B of CONV_INT architecture B of CONV_INT isisbeginbegin process(VECTOR) process(VECTOR) variable TMP: integer; variable TMP: integer;
begin begin TMP := 0; TMP := 0;
for I in VECTOR'range for I in VECTOR'range looploop if (VECTOR(I)='1') then if (VECTOR(I)='1') then TMP := TMP + 2**I; TMP := TMP + 2**I; end if; end if; end loop; end loop;
RESULT <= TMP; RESULT <= TMP; end process; end process;end B;end B;
architecture C of architecture C of CONV_INT isCONV_INT isbeginbegin process(VECTOR) process(VECTOR) variable TMP: integer; variable TMP: integer; variable I : integer; variable I : integer; begin begin TMP := 0; TMP := 0; I := VECTOR'high; I := VECTOR'high; while (I >= while (I >= VECTOR'low) loopVECTOR'low) loop if (VECTOR(I)='1') if (VECTOR(I)='1') thenthen TMP := TMP + TMP := TMP + 2**I;2**I; end if; end if; I := I - 1; I := I - 1; end loop; end loop; RESULT <= TMP; RESULT <= TMP; end process; end process;end C;end C;
Exit & Next
• The exit command allows a FOR loop to be exited completely. This can be useful when a condition is reached and the remainder of the loop is no longer required. The syntax for the exit command is shown below:
for i in 0 to 7 loopif ( i = 4 ) thenexit;endif;endloop;
• The next command allows a FOR loop iteration to be exited, this is slightly different to the exit command in that the current iteration is exited, but the overall loop continues onto the next iteration. This can be useful when a condition is reached and the remainder of the iteration is no longer required. An example for the next command is shown below:
for i in 0 to 7 loopif ( i = 4 ) thennext;endif;endloop;
Conditional Signal Conditional Signal AssignmentAssignment
• entity CONDITIONAL_ASSIGNMENT isentity CONDITIONAL_ASSIGNMENT is port (A, B, C, X : in bit_vector (3 downto 0); port (A, B, C, X : in bit_vector (3 downto 0); Z_CONC : out bit_vector (3 downto 0); Z_CONC : out bit_vector (3 downto 0); Z_SEQ : out bit_vector (3 downto 0)); Z_SEQ : out bit_vector (3 downto 0));end CONDITIONAL_ASSIGNMENT;end CONDITIONAL_ASSIGNMENT;architecture EXAMPLE of CONDITIONAL_ASSIGNMENT isarchitecture EXAMPLE of CONDITIONAL_ASSIGNMENT isbeginbegin -- Concurrent version of conditional signal assignment -- Concurrent version of conditional signal assignment Z_CONC <= B when X = "1111" else Z_CONC <= B when X = "1111" else C when X > "1000" else C when X > "1000" else A; A; -- Equivalent sequential statements -- Equivalent sequential statements process (A, B, C, X) process (A, B, C, X) begin begin if if (X = "1111") (X = "1111") then then Z_SEQ <= B; Z_SEQ <= B; elsif elsif (X > "1000") (X > "1000") then then Z_SEQ <= C; Z_SEQ <= C; else else Z_SEQ <= A; Z_SEQ <= A; end if; end if; end process; end process;end EXAMPLE;end EXAMPLE;
• TARGET <= VALUE;TARGET <= VALUE_1 when CONDITION_1 else VALUE_2 when CONDITION_2 else . . . VALUE_n;
Selected Signal AssignmentSelected Signal Assignment• entity SELECTED_ASSIGNMENT isentity SELECTED_ASSIGNMENT is
port (A, B, C, X : in integer range 0 to 15; port (A, B, C, X : in integer range 0 to 15; Z_CONC : out integer range 0 to 15; Z_CONC : out integer range 0 to 15; Z_SEQ : out integer range 0 to 15); Z_SEQ : out integer range 0 to 15);end SELECTED_ASSIGNMENT;end SELECTED_ASSIGNMENT; architecture EXAMPLE of SELECTED_ASSIGNMENT is architecture EXAMPLE of SELECTED_ASSIGNMENT isbeginbegin
-- Concurrent version of selected signal assignment-- Concurrent version of selected signal assignment with X select with X select Z_CONC <= A when 0, Z_CONC <= A when 0, B when 7 | 9, B when 7 | 9, C when 1 to 5, C when 1 to 5, 0 when others; 0 when others;
-- Equivalent sequential statements -- Equivalent sequential statements process (A, B, C, X)process (A, B, C, X) begin begin case X is case X is when 0 => Z_SEQ <= A; when 0 => Z_SEQ <= A; when 7 | 9 => Z_SEQ <= B; when 7 | 9 => Z_SEQ <= B; when 1 to 5 => Z_SEQ <= C; when 1 to 5 => Z_SEQ <= C; when others => Z_SEQ <= 0; when others => Z_SEQ <= 0; end process; end process;end EXAMPLE;end EXAMPLE;
with EXPRESSION select TARGET <= VALUE_1 when CHOICE_1, VALUE_2 when CHOICE_2 | CHOICE_3, VALUE_3 when CHOICE_4 to CHOICE_5, · · · VALUE_n when others;
Miscellanies Miscellanies operatorsoperators
**** absabs notnot
Multiplying Multiplying operatorsoperators
* /* / Mod Mod remrem
Signed operatorSigned operator ++ --
Adding operator Adding operator ++ -- &&
Shift operatorShift operator sllsll srlsrl slasla srasra
rolrol rorror
Relational Relational operationoperation
== /=/= << <=<=
>> >=>=
Logical operatorLogical operator andand oror nandnand
nornor xorxor xnorxnor
OperatorsOperators
SubprogramsSubprograms
• FunctionsFunctions– function name can be an operator function name can be an operator – arbitrary number of input parameters arbitrary number of input parameters – exactly one return value exactly one return value – no WAIT statement allowed no WAIT statement allowed – function call <=> VHDL expression function call <=> VHDL expression
• ProceduresProcedures– arbitrary number of parameters of any possible direction arbitrary number of parameters of any possible direction
(input/output/inout) (input/output/inout) – RETURN statement optional (no return value!) RETURN statement optional (no return value!) – procedure call <=> VHDL statement procedure call <=> VHDL statement
• Subprograms can be overloaded Subprograms can be overloaded • Parameters can be constants, signals, variables or Parameters can be constants, signals, variables or
files files
functionfunction architecture EXAMPLE of FUNCTIONS isarchitecture EXAMPLE of FUNCTIONS is
function COUNT_ZEROS (A : bit_vector) function COUNT_ZEROS (A : bit_vector) return integer is return integer is variable ZEROS : integer; variable ZEROS : integer; begin begin ZEROS := 0; ZEROS := 0; for I in A'range loop for I in A'range loop if A(I) = '0' then if A(I) = '0' then ZEROS := ZEROS +1; ZEROS := ZEROS +1; end if; end if; end loop; end loop; return ZEROS; return ZEROS; end COUNT_ZEROS; end COUNT_ZEROS;
signal WORD: bit_vector(15 downto 0); signal WORD: bit_vector(15 downto 0); signal WORD_0: integer; signal WORD_0: integer; signal IS_0: boolean; signal IS_0: boolean;
beginbegin WORD_0 <= COUNT_ZEROS(WORD); WORD_0 <= COUNT_ZEROS(WORD); process process begin begin IS_0 <= true; IS_0 <= true; if COUNT_ZEROS("01101001") > 0 then if COUNT_ZEROS("01101001") > 0 then IS_0 <= false; IS_0 <= false; end if; end if; wait; wait; end process; end process;end EXAMPLE;end EXAMPLE;
procedureprocedure• architecture EXAMPLE of PROCEDURES isarchitecture EXAMPLE of PROCEDURES is
procedure COUNT_ZEROS procedure COUNT_ZEROS (A: in bit_vector;signal Q: out integer) is (A: in bit_vector;signal Q: out integer) is variable ZEROS : integer; variable ZEROS : integer; begin begin ZEROS := 0; ZEROS := 0; for I in A'range loop for I in A'range loop if A(I) = '0' then if A(I) = '0' then ZEROS := ZEROS +1; ZEROS := ZEROS +1; end if; end if; end loop; end loop; Q <= ZEROS; Q <= ZEROS;
end COUNT_ZEROS;end COUNT_ZEROS;
signal COUNT: integer; signal COUNT: integer; signal IS_0: boolean; signal IS_0: boolean;beginbegin process process begin begin IS_0 <= true; IS_0 <= true; COUNT_ZEROS("01101001", COUNT); COUNT_ZEROS("01101001", COUNT); wait for 0 ns; wait for 0 ns; if COUNT > 0 then if COUNT > 0 then IS_0 <= false; IS_0 <= false; end if; end if; wait; wait; end process; end process;end EXAMPLE;end EXAMPLE;
Data TypesData Types
• Each object in VHDL has to be of some type, Each object in VHDL has to be of some type, which defines possible values and which defines possible values and operations that can be performed on this operations that can be performed on this object (and other object of the same type) .object (and other object of the same type) .
• VHDL is strongly typed language which VHDL is strongly typed language which causes that two types defined in exactly causes that two types defined in exactly the same way but differing only by names the same way but differing only by names will be considered differently. will be considered differently.
• If a translation from one type to another is If a translation from one type to another is required, then type convention must be required, then type convention must be applied even if the two types are similar.applied even if the two types are similar.
A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage.
type distance is range 0 to 1E5unitsum;mm = 1000 um;In_a=25400 um;end units;Variable Dis1,dis2 :Distance;Dis1:=28mm;
An integer type is a scalar whose set of values include integer numbers in specific range.
type byte_int is range 0 to 255;type voltage_level is range 0 to 5;
A floating point type is a discrete approximation to the set of real numbers in a specified range.
type signal_level is range –10.00 to +10.00;
An enumeration type is a type whose values are defined by listing (enumerating) them explicitly.
type logic_level is (unknown, low, undriven, high);
Data TypesData Types
Data TypesData Types
Is an indexed collection of elements all of the same type. Arrays may be one-dimensional (with one index) or multidimensional (with a number of indices).• type VAR is array (0 to 7) of integer; constant SETTING: VAR := (2,4,6,8,10,12,14,16); • type VECTOR2 is array (natural range <>, natural range <>) of std_logic; variable ARRAY3x2: VECTOR2 (1 to 3, 1 to 2)) := ((‘1’,’0’), (‘0’,’-‘), (1, ‘Z’));
A record type allows declaring composite objects whose elements can be from different types.
Type RegName is (AX,BX,DX);Type Operation is record
Mnemonic:string (1 to 10);OpCode:Bit_Vector(3 downto 0);Op1,op2,Reg:RegName;
End record;Variable Instr3:= Operation;Instr3. Mnemonic:= “Mul AX, BX”;Inst3.Op1:=Ax;
SubtypeSubtype
• A type with a constraints. A value A type with a constraints. A value belong to a subtype of a given type if belong to a subtype of a given type if it belongs to the type and satisfied it belongs to the type and satisfied the constraints.the constraints.– Subtype Digits is Integer range 0 to 9;Subtype Digits is Integer range 0 to 9;
• Integer is a predefined type and the Integer is a predefined type and the subtype digits will constraints the subtype digits will constraints the type to ten values only.type to ten values only.
Standard Data TypesStandard Data Types
• Every type has a Every type has a number of possible number of possible values values
• Standard types are Standard types are defined by the defined by the language language
• User can define his User can define his own types own types
package STANDARD is type BOOLEAN is (FALSE,TRUE); type BIT is (`0`,`1`); type CHARACTER is (-- ascii set); type INTEGER is range -- implementation_defined type REAL is range -- implementation_defined -- BIT_VECTOR, STRING, TIMEend STANDARD;
AliasAlias
• Signal Signal InstructionInstruction :Bit_vector( :Bit_vector(1515 downto downto 00););– Alias Alias OpCodeOpCode : Bit_vector( : Bit_vector(33 downto downto 00) is ) is
InstructionInstruction((1515 downto downto 1212););– Alias Alias SourceSource : Bit_vector( : Bit_vector(11 downto downto 00) is ) is
InstructionInstruction((1111 downto downto 1010););– Alias Alias designdesign : Bit_vector( : Bit_vector(11 downto downto 00) is ) is
InstructionInstruction((99 downto downto 88););– Alias Alias ImmdataImmdata : Bit_vector( : Bit_vector(77 downto downto 00) is ) is
InstructionInstruction((77 downto downto 00););
AggregateAggregate• A basic operation that combines one or more values A basic operation that combines one or more values
into a composite value of a record or array type;into a composite value of a record or array type;– Variable data_1 :Bit_vecot(0 to 3) := (‘0’,’1’,’0’,’1’);Variable data_1 :Bit_vecot(0 to 3) := (‘0’,’1’,’0’,’1’);– Variable data_1 :Bit_vecot(0 to 3) := (1=>‘1’,0=>’0’, Variable data_1 :Bit_vecot(0 to 3) := (1=>‘1’,0=>’0’,
3=>’1’,2=>’0’);3=>’1’,2=>’0’);– Signal data_Bus :std_logic_vector (15 downto 0)Signal data_Bus :std_logic_vector (15 downto 0)
data_Bus<=(15 downto 8 => ‘0’, 7 downto 0 =>’1’);data_Bus<=(15 downto 8 => ‘0’, 7 downto 0 =>’1’);– Signal data_Bus :std_logic_vector (15 downto 0)Signal data_Bus :std_logic_vector (15 downto 0)
data_Bus<=(14downto 8 => ‘0’, others=>’1’);data_Bus<=(14downto 8 => ‘0’, others=>’1’);– Signal data_Bus :std_logic_vector (15 downto 0)Signal data_Bus :std_logic_vector (15 downto 0)
data_Bus<=(others=>’z’’);data_Bus<=(others=>’z’’);– Type Status_record is record Type Status_record is record
Code:Integer;Code:Integer; Name:string(1 to 4);Name:string(1 to 4);
End record;End record; Variable Status_var: Status_record :=(code=>57, Variable Status_var: Status_record :=(code=>57,
name=>”MOVE”); name=>”MOVE”);
ConcatenationConcatenation
• architecture EXAMPLE_1 of CONCATENATION isarchitecture EXAMPLE_1 of CONCATENATION is signal BYTE : bit_vector (7 downto 0); signal BYTE : bit_vector (7 downto 0); signal A_BUS, B_BUS : bit_vector (3 downto 0); signal A_BUS, B_BUS : bit_vector (3 downto 0);beginbegin BYTE <= A_BUS BYTE <= A_BUS && B_BUS; B_BUS;end EXAMPLE;end EXAMPLE;
• Variable Bytedat : bit_vector(7 downto 0);Variable Bytedat : bit_vector(7 downto 0);
Alias Modulus: bit_vector(6 downto 0) is bytedat(6 downto 0);Alias Modulus: bit_vector(6 downto 0) is bytedat(6 downto 0);
…………
Bytedate:=‘1’ & modulas;Bytedate:=‘1’ & modulas;
AttributeAttribute
• Attributes are a feature of VHDL that allow you to extract additional Attributes are a feature of VHDL that allow you to extract additional information about an object (such as a signal, variable or type) that information about an object (such as a signal, variable or type) that may not be directly related to the value that the object carries.may not be directly related to the value that the object carries. – Type table is array (1 to 8) of Bit;Type table is array (1 to 8) of Bit;
Variable array_1: table:=‘00001111’;Variable array_1: table:=‘00001111’;Arrat_1’left, the leftmost value of table array is equal to 1;Arrat_1’left, the leftmost value of table array is equal to 1;
– architecturearchitecture example example ofof enums enums isis typetype state_type state_type isis (Init, Hold, Strobe, Read, Idle); (Init, Hold, Strobe, Read, Idle); signalsignal L, R: state_type; L, R: state_type;beginbegin L <= state_typeL <= state_type’left’left; -- L has the value of Init; -- L has the value of Init R <= state_typeR <= state_type’right’right; -- R has the value of Idle; -- R has the value of Idleendend example; example;
– (clock(clock'EVENT'EVENT andand clock='1') clock='1') – typetype state_type state_type isis (Init, Hold, Strobe, Read, Idle); (Init, Hold, Strobe, Read, Idle); variablevariable P: integer := state_type P: integer := state_type’pos’pos(Read); -- P has the value of 3(Read); -- P has the value of 3– typetype state_type state_type isis (Init, Hold, Strobe, Read, Idle); (Init, Hold, Strobe, Read, Idle); variablevariable V: state_type := state_type V: state_type := state_type’val’val(2); -- V has the value of Strobe(2); -- V has the value of Strobe
ReferenceReference
• http://www.seas.upenn.edu/~ese201/vhttp://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html#_Toc526061356hdl/vhdl_primer.html#_Toc526061356
• http://www.vhdl-online.de/~vhdl/tutoriahttp://www.vhdl-online.de/~vhdl/tutoriall//
• http://tams-http://tams-www.informatik.unihamburgwww.informatik.unihamburg .de / .de /vhdlvhdl/doc/cookbook/VHDL Cookbook ./doc/cookbook/VHDL Cookbook .pdfpdf
