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Stim u lu s DeviceU n d e rMoni torn d Test biFigure 1: a) Testbench configuration with separate Stimulus and Monitor sections, b) Testbenchconfiguration with a single Stimulus and Monitor section.

Using a descriptive coding styleBefore one designs a VHDL module,one should consider a descriptive coding stylethat will be easy to reuse in future designs. Theeasiest way to describe your code is to usecomment statements or remarks. Thesecomments will describe the operations of thecode for others to understand. This may beadequate for simple modules, but for complexmodules, other methods may be more desirable.Using prefixes, suffixes, underscores andcapital lettersIn w riting code, your engineering teammay want to decide on a coding style whicheveryone will follow. Prefixes and suffixes canbe very helpful in telling the reader exactly whatan identifier is. Underscores or capital letterscan be used to sepa rate words in a signal name.Look at the examp le below:Address-Enable-Out-Sig-Low

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and adding new modules to test the additionalnew features.Avoiding Hard-Coded values intestbenches

In writing code, hard-coding of timingvalues should be avoided. These statementseasily lose their meaning over time, often evento the di gta l designer who wrote the statementsas memories fade. Also, force statements, aseries of linear staements of the form X occursat time Y or in VHDL, X

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Using different designers to develop thehardware and the testbenchOne important concept to consider ishaving separate designers for the device undertest and the testbench. Th e designers shouldwork independently, each basing hisfunctionality on the original specification, notthe others interpretation. When the testbenchand the DUT are connected together, andpotential errors are uncovered, the designers canexamine their interpretations of the specificationand correct and eliminate the errors. Thistechnique reduces the chances of hum an error inthe fina l product.Taking advantage of behavioral non-synthesizable) codeSince a testbench does not need to besynthesized, the de signer may take advantage ofthe non-synthesizable language constructs thatexists in VHDL. Thu s unsynthesizable waitstatements and loop statements, amon g otherscan be used to implement the stimulus accordingto what the specification requires and can makethe task of monitoring resu lts much easier.Using an input file can addtremendous flexibility as well. Th is allows thesame program to read in variables that maychange the overall operation of the testbench.For example, the stimulus of a testbench of anIntel 8255A 2, rogrammable pe ripheral interface,could contain a da ta file for the inpu t, and a datafile that would contain the mode word thatwould be written to the device. The monitorcould us a data file for the expected o utputs.Testing the fabricated design using thesoftware testbench.One advantage of a software testbenchis that it c an be used at various levels of testing.For example, an ASIC design can be testedbefore synthesis, to verify the functionality of theASIC can be tested; after synthesis, to verrfyfunctionality and timing; prior to release tofabrication, to verify the total operation of thesystem; an d after fabrication, to verify the ASICdesign. After the ASIC has been fabricated, thistesting c n occur straight from the HDL byconnecting a hardware modeler to theworkstation network, or by a separate tester that

c n use the HDL or translate the HDL to aspecial language required by th e tester.Using vendor technology dependentlibrariesMuch can be said in favor and againstvendor libraries. Thu s this paper will reviewsame advantages and disadvantages.AdvantagesEfficient /Sp ecia lized ComponentsThe vendor libraries allow the designerto take advantage of highly specialized orefficient components in their designs. Somevendors allow complex multipliers, analog-to-digital converters and even microprocessors tobe added to the design. These components allowenhancement of the design to g reater levels.Architecture-Specific Constructs s WithProgrammable Logic Device s PLDs)Every PLD company has a W e r e n tarchitecture for its devices. Th us if ones codecan be designed for architecture of the PLDbeing used, one can get higher density of gatesand greater throughput on the PLD. Forexample, Xilinx 4000 series FPGAs useConfigurable Logic Blocks that m ake it easy toimplement certain DSP functions such as d igitalfilters [11DisadvantagesUnavailable Simulation Models and Non-Digital SimulationsOne of the main problems with usingthese components in the design is that they aredifficult to test with a testbench. For example, ifa digital designer uses the vendorsmicroprocessor, how would the microprocessorin the system be tested. Or if an analog-to-digital converter is used, how does one test themixed signal chip. Most HDLs do not allow foranalog inputs. A second problem with thelibraries is they are vendor dependent. Thu s ifproblems occur and the vendor quits supportingthe libraries or goes out of business, it will bedifficult to get the design fabricated. A thirdproblem is that most of the libraries aretechnology dependent. Th us if your designneeds to use the latest and greatest libraries,

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these devices may not exist in the newesttechnology.Non-Portability across vendors and even acrosssame ven dors technology

Many of the ASIC and PLD companieshave proprietary library designs that are notcompatible with any other companies libraries.Also, old library designs becoming ob solete overtime. This makes designs with the old librariesobsolete as well. One of the main goals of HDLsis to reduce design time through reuse andflexibility, and these vendor technologydependent libraries hender the flexibility of theHDL code, and can reduce the ability of acompany to reuse old HDL code.The future of hardware descriptionlanguagesThere are several ways that HDLs aregoing. Two of the most popular are system levelHDLs and Analog AHDLs) or Mixed signalHDLs. The system level HDL allows a designerto write a high-level code similar to acomponent specification. The synthesizer willthen convert the code into a gate-level designused in ASICs or PLDs. This may eliminate theneed for the lower level HDLs used today.Analog HDLs will allow analogdesigner the opportunity to design usingreusable code similar to VHDL[2]. Currently alarge push has been made to enter analog fieldprogram mable arrays into the market. AHDLswill be necessary to the success of these newdevices. Likewise with the development ofAHDLs, a new set of HDLs will be developedthat will combine the analog and digital HDLsinto a single language.ConclusionIn conclusion, this has been anoverview of VHDL and VHDL testbenches. It

has discussed topics about writing VHDLtestbenches. Using a descriptive coding style,mimicking the hardware, and parameterizingthe hardware have been discussed as ways ofmaking VHDL code more flexible and easier touse by others. Also how using reuse libraries toreduce design time for the designers of futureprojects has been discussed. The advantages anddisadvantages of using vendor dependentlibraries have been reviewed. And a final lookinto the future of Hardware DescriptionLangu ages was discussed.AcknowledgmentsI would like to acknowledge the help ofmy wife Shobana for helping me by reviewingthis paper. Also, I would like to thank Mr.David Clark, a Senior Engineer and VHDLexpert at Hughes Missile Systems Company, forhis comments and suggestions.BibliographyDan Biederman graduated fromTennessee Technological University with hisB.S.E.E. in 1993. In 19 95, he completed hisM.S .E.E.. His thesis was titled A NeuralNetwork-Based Digital Multiplier. He hasworked at Hughes Missile Systems Companysince 1996 as part of an ASIC-level and board-level digital design team. He has writtenseveral VHDL testbenches for both the ASIC-level and board-level designs.References1. Newgard, Bruce. Signal Processing withXilinx FPGAs. Xilinx, San Jose. July1996.Rhodes, David L A Design Language for

Analog Circuits. IEEE Spectrum. pages 43- 48 October 1996.

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