Vi Xu Ly the He Moi

Ti liu tham kho cho mn Vi x l

Cc h vi x l th h mi

MC LC LI NI U.................................................................................................................1 CHNG1. H VI IU KHIN 8051........................................................................4 1.1. GII THIU CU TRC PHN CNG H MCS-51 (89C51):......................4 1.1.1. Gii thiu h MCS -51 ..................................................................................4 1.1.2. KHO ST S CHN 89C51, CHC NNG TNG CHN ...........5 1.1.2.1 S chn 89C51...................................................................................5 1.1.2.2. Chc nng cc chn ca 89C51..............................................................6 1.1.3. CU TRC BN TRONG VI IU KHIN..............................................8 1.1.3.1. T chc b nh.......................................................................................8 1.1.3.2. Cc thanh ghi c chc nng c bit:...................................................11 1.1.3.3. B nh ngoi (External memory):........................................................14 1.1.4. HOT NG TIMER CA 89C51...........................................................16 1.1.4.1. Gii thiu..............................................................................................16 1.1.4.2. Thanh ghi iu khin Timer TCON: ....................................................17 1.1.4.3. Thanh ghi mode timer (TMOD):..........................................................18 1.1.4.4. Cc mode v c trn .............................................................................18 1.1.4.5. Cc ngun xung clock (CLOCK SOURCES):.....................................20 1.1.4.6. S bt u, dng v iu khin cc timer: ...........................................21 1.1.4.7. S khi ng v truy xut cc thanh ghi timer: ...................................22 1.1.5. CNG NI TIP ........................................................................................22 1.1.5.1. Gii thiu:.............................................................................................22 1.1.5.2. Thanh ghi port ni tip: ........................................................................23 1.1.5.3. Cc ch hot ng ..........................................................................24 1.1.6. T CHC NGT CA MCS51 ................................................................26 1.1.6.1. u tin ngt: .........................................................................................27 1.1.6.2. Hi vng tun t:..................................................................................27 1.1.7. TM TT TP LNH CA 89C51 ..........................................................28 1.1.7.1. Cc ch nh v a ch (addressing mode): ....................................28 1.1.7.2. Tm tt tp lnh ca h MCS 51:......................................................28 1.2 VI IU KHIN AT89C55................................................................................31 1.2.1 c trng .................................................................................................31 1.2.2. Phn m t ...................................................................................................32 1.3 VI IU KHIN AT89C54/58...........................................................................48 1.3.1 M t.............................................................................................................48 1.3.2.T chc b nh.............................................................................................49 1.4 VI IU KHIN AT89C2051...........................................................................55 1.4.1 c trng ca AT89C2051 ........................................................................55 1.4.2 M t.............................................................................................................55 CHNG 2. H VI IU KHIN AVR AT90S8535................................................57 2.1 Cc c tnh .........................................................................................................57 2.2. Phn m t ......................................................................................................59 CHNG 3. CNG NGH CHIP PSoC .....................................................................77 3.1 Chp PSoC CY8C29x66 .................................................................................77 3.1.1 Chc nng................................................................................................77 3.1.2 S lc chc nng ca PSoC ..................................................................79 3.2. Ngn ng lp trnh cho PSoC.........................................................................84 3.3 Gii thiu nhng nt c bn v IDE...............................................................85B mn Cng ngh iu khin t ng

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TI LIU THAM KHO .............................................................................................98 MC LC .......................................................................................................................1

B mn Cng ngh iu khin t ng

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LI NI U Trong s pht trin ca t nc, T ng ho ng vai tr rt quan trng trong s pht trin . Cc h thng t ng ho c ng dng trong mi lnh vc ca i sng x hi cng nh trong cc dy truyn sn xut. xy dng ln cc h thng t ng ho phi cn rt nhiu kin thc nh: Phn tch h thng, thit k nh gi h thng, kin thc v phn cng, kin thc v phn mm. V vy i hi cc k s t ng ho phi c mt nn kin thc vng vng. Ti liu ny cung cp cc kin thc b xung cho mn vi x l. Ni dung ca ti liu gm 3 chng: Chng 1: Cung cp kin thc c bn cho vi iu khin h 8051 nh: AT89C2051, AT89C51/52, AT89C55WD, SST89C54/58. Chng 2: M t nhng kin thc chung nht v h vi iu khin AVR: AT90S8535 v AT89LS8535. Chng 3: Cung cp mt vi iu khin PSoC. Vi iu khin ny ang c s dng nhiu trong cng nghip. Ti liu ny c son trong mt thi gian ngn nn cn rt nhiu li. Tc gi rt mong c s gp ca cc c gi. Mi thc mc xin lin h vi tc gi ti B mn iu khin t ng - Khoa CNTT - i hc Thi Nguyn.


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CHNG1. H VI IU KHIN 8051 1.1. GII THIU CU TRC PHN CNG H MCS-51 (89C51): 1.1.1. Gii thiu h MCS -51 * MCS-51 l h IC (integrated circuit) v iu khin (Microcontroller) do hng Intel sn xut. Cc IC tiu biu cho h MSC-51 l: 8051, 8031, 89C51, 892051, 8751,... Vic x l trn Byte v cc ton s hc cu trc d liu c thc hin bng nhiu ch truy xut d liu nhanh trn RAM ni. Tp lnh cung cp mt bng tin dng ca nhng lnh s hc 8 Bit gm c lnh cng, tr, nhn v lnh chia. N cung cp nhng h tr m rng trn Chip dng cho nhng bin mt Bit nh l kiu d liu ring bit cho php qun l v kim tr a Bit trc tip trong iu khin. * 89C51 l mt vi iu khin 8 Bit, ch to theo cng ngh CMOS cht lng cao, vi 4 KB EEPROM (Flash Programmable and erasable read only memory). Thit b ny c ch to bng cch s dng b nh khng bc hi mt cao ca ATMEL v tng thch vi chun cng nghip MCS 51 v tp lnh v cc chn ra. ATMEL AT89C51 l mt vi iu khin mnh (c cng sut ln) m n cung cp mt s linh ng cao v gii php v gi c i vi nhiu ng dng v iu khin. Cc c im ca 89C51 c tm tt nh sau: * 4 KB b nh c th lp trnh li nhanh. * Tn s hot ng t: 0Hz n 24 MHz. * 2 b Timer/counter 16 Bit * 128 Byte RAM ni * 4 Port xut/ nhp I/O 8 bt * Giao tip ni tip * 64 KB vng nh m ngoi * 64 KB vng nh d liu ngoi * X l Boolean (hot ng trn bit n) * 210 v tr nh c th nh v bit.


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Hnh 1.1. S khi MSC-51

1.1.2. KHO ST S CHN 89C51, CHC NNG TNG CHN 1.1.2.1 S chn 89C51


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Hnh 1.2. S chn IC 89C51

1.1.2.2. Chc nng cc chn ca 89C51 89C51 c tt c 40 chn c chc nng nh cc ng xut nhp. Trong c 24 chn c tc dng kp (c ngha 1 chn c 2 chc nng), mi ng c th hot ng nh ng xut nhp hoc nh ng iu khin hoc l thnh phn ca cc bus d liu v bus a ch. a. Cc Port: Port 0: l port c 2 chc nng cc chn 32 39 ca 89C51. Trong cc thit k c nh khng dng h nh m rng n c chc nng nh cc ng I/O. i vi cc thit k c ln c b nh m rng, n c kt hp gia bus a ch v bus d liu. Port 1: l port I/O trn cc chn 1 8. Cc chn c k hiu P1.0, P1.2,... c th dng cho giao tip vi cc thit b ngoi nu cn. Port 1 khng c chc nng khc, v vy chng ch c dng cho giao tip vi cc thit b bn ngoi. Port 2: l 1 port c tc dng kp trn cc chn 21 28 c dng nh cc ng xut nhp hoc l byte cao ca bus a ch i vi cc thit b dng b nh m rng. Port 3: Port 3 l port c tc dng kp trn cc chn 10-17. Cc chn ca port ny c nhiu chc nng, cc cng dng chuyn i c lin h vi cc c tnh c bit ca 89C51 nh bng sau:

Bit

Tn

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Cc h vi x l th h mi

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

RXT TXD INT0\ INT1\ T0 T1 WR\ RD\

Ng vo d liu ni tip Ng xut d liu ni tip Ng vo ngt 0 Ng vo ngt 1 Ng vo ca TIMER/ COUNTER 0 Ng vo ca TIMER/ COUNTER 1 Tn hiu ghi d liu ln b nh ngoi Tn hiu c b nh d liu ngoi

b. Cc ng tn hiu iu khin: * Ng tn hiu PSEN (Program store enable): * PSEN l tn hiu ng ra chn 29 c tc dng cho php c b nh chng trnh m rng thng c ni n chn 0E\ (output enable) ca EPROM cho php c cc byte m lnh. * PSEN mc thp trong thi gian Microcontroller 89C51 ly lnh. Cc m lnh ca chng trnh c c t EPROM qua bus d liu v c cht vo thanh ghi lnh bn trong 89C51 gii m lnh. Khi 89C51 thi hnh chng trnh trong ROM ni PSEN s mc logic 1. * Ng tn hiu iu khin ALE (Address Latch Enable): Khi 89C51 truy xut b nh bn ngoi, port 0 c chc nng l bus a ch v bus d liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30 dng lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni chng vi IC cht. Tn hiu ra chn ALE l mt xung trong khong thi gian port 0 ng vai tr l a ch thp nn cht a ch hon ton t ng. * Ng tn hiu EA\ (External Acces): Tn hiu vo /EA chn 31 thng c mc ln ngun. Nu mc 1, 89C51 thi hnh chng trnh t ROM ni trong khong a ch thp 8 Kbyte. Nu mc 0, 89C51 s thi hnh chng trnh t b nh m rng. Chn /EA c ly lm chn cp ngun 21V khi lp trnh cho EPROM trong 89C51. * Ng tn hiu RST (Reset): Ng vo RST chn 9 l ng vo Reser ca 89C51. Khi ng vo tn hiu ny a ln cao t nht l 2 chu k my, cc thanh ghi bn trong c np nhng gi tr thch hp khi ng h thng. Khi cp in mch t ng Restet.B mn Cng ngh iu khin t ng

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* Cc ng vo b giao ng X1, X2: B dao ng c tch hp bene trong 89C51, khi s dng 89C51 ngi thit k ch cn kt ni thm thch anh v cc t nh hnh v trong s . Tn s thch anh thng s dng cho 89C51 l 12 Mhz. * Chn 40 (Vcc) c ni ln ngun 5V. 1.1.3. CU TRC BN TRONG VI IU KHIN 1.1.3.1. T chc b nh FFFF FFFF CODE Memory FF ON CHIP Memory c chn qua PSEN 00 0000 B nh trn chip 0000 External MomeryHnh 1.3. S b nh

DATA Memory c chn qua RD&WR


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Ti liu tham kho cho mn Vi x l 7F Hnh 1.4. Bn b nh Data trn Chip nh sau: FF F0 F7 F6 RAM a dng

Cc h vi x l th h mi

F5

F4

F3 E3

F2 E2

F1

F0

B

E0 E7 E6 E5 E4 D0 D7 D6 D5 D4 B8 -

E1 E0 ACC

RAM a mc ch30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 0F 08 07 00 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00

D3 D2 D1 D0 PSW

BC BB BA B9 B8 IP B3 B2 B1 B0 P.3

B0 B7 B6 B5 B4 A8 AF

AC AB AA A9 A8 IE A3 A2 A1 A0 P2 99 91 98 90 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0

A0 A7 A6 A5 A4 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 88

Khng c a ch ha bit 9F 9E 9D 9C 9B 9A 97 96 95 94 93 92

Bank 3 Bank 2 Bank 1 Bank thanh ghi 0 (Mc nh cho R0 R7) RAM

Khng c a ch ha bit Khng c a ch ha bit Khng c a ch ha bit Khng c a ch ha bit Khng c a ch ha bit 8F 8E 8D 8C 8B 8A Khng c a ch ha bit Khng c a ch ha bit Khng c a ch ha bit Khng c a ch ha bit 87 86 85 84 83 82

89

88

81

80

CC THANH GHI CHC NNG C BIT

- B nh trong 89C51 bao gm ROM v RAM. RAM trong 89C51 bao gm nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank thanh ghi v cc thanh ghi chc nng c bit. - 89C51 c b nh theo cu trc Harvard: c nhng vng b nh ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn trong 89C51 nhng 89C51 vn c th kt ni vi 64K byte b nh chng trnh v 64K byte d liu. Cc c tnh cn ch l: Cc thanh ghi v cc port xut nhp c nh v (xc nh) trong b nh v c th truy xut trc tip ging nh ca c s a ch b nh khc. Ngn xp bn trong Ram ni nh hn so vi Ram ngoi.


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RAM bn trong 89C51 c phn chia nh sau: Cc bank thanh ghi c a ch t 00H n 1FH. RAM a ch ha tng bit c a ch t 20H n 2FH. RAM a dng t 30H n 7FH. Cc thanh ghi chc nng c bit t 80H n FFH. a. RAM a dng: Mc d trn hnh v cho thy 80 byte a dng chim cc a ch t 30H n 7FH, 32 byte di t 00H n 1FH cng c th dng vi mc ch tng t (mc d cc a ch ny c mc ch khc). - Mi a ch trong vng RAM a dng u c th truy xut t do dng kiu a ch trc tip hoc gin tip. b. RAM c th truy xut tng bit: - 89C51 cha 210 bit c a ch ha, trong c 128 bit c cha cc byte c cha cc a ch t 20F n 2FH v cc bit cn li cha trong nhm thanh ghi c chc nng c bit. - tng truy xut tng bit bng phn mm l cc c tnh mnh ca microcontroller x l chung. Cc bit c th c t, xa, AND, OR, ..., vi 1 lnh n. a s cc microcontroller x l i hi mt chui lnh c sa ghi t c mc ch tng t. Ngoi ra cc port cng c th truy xut c tng bit. + 128 bit truy xut tng bit ny cng c th truy xut nh cc byte hoc nh cc bit ph thuc vo lnh c dng. c. Cc bank thanh ghi: - 32 byte thp ca b nh ni c dnh cho cc bank thanh ghi. B lnh 89C51 h tr 8 thanh ghi c tn l R0 n R7 v theo mc nh sau khi reset h thng, cc thanh ghi ny c cc a ch t 00H n 07H. - Cc lnh dng cc thanh ghi R0 n R7 s ngn hn v nhanh hn so vi cc lnh c chc nng tng ng dng kiu a ch trc tip. Cc d liu c dng thng xuyn nn dng mt trong cc thanh ghi ny. - Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c truy xut bi cc thanh ghi R0 n R7 chuyn i vic truy xut cc bank thanh ghi ta phi thay i cc bit chn bank trong thanh ghi trng thi.


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1.1.3.2. Cc thanh ghi c chc nng c bit: - Cc thanh ghi ni ca 89C51 c truy xut ngm nh bi b lnh. - Cc thanh ghi trong 89C51 c nh dng nh mt phn ca RAM trn chip v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0 n R7, 89C51 c 21 thanh ghi c chc nng c bit (SFR: Special Function Register) vng trn ca RAM ni t a ch 80H n FFH. * Ch : Tt c 128 a ch t 80H n FFH khng c nh ngha, ch c 21 thanh ghi c chc nng c bit c nh ngha sn cc a ch. - Ngoi tr thanh ghi A c th c truy xut ngm nh ni, a s cc thanh ghi c chc nng c bit SFR c th a ch ha tng bit hoc byte. Thanh ghi trng thi chng trnh (PSW: Prorgam Status Word): a ch D0HBIT SYMBOL ADDRESS DESCRIPTION

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3

CY AC F0 RS1 RS0

D7H D6H D5H D4H D3H

PSW.2 PSW.1 PSW.0

OV P

D2H D1H D0H

C nh C nh ph C 0 Bit 1 chn bank thanh ghi Bit 0 chn bank thanh ghi 00 = Bank 0; address 00h 07H 01 = Bank 1; address 08H 0FH 10 = Bank 2; address 10H 17H 11 = Bank 3; address 18H 1FH C trn D tr C parity chn

Chc nng tng bit trng thi chng trnh: + C Carry CY: C nh c tc dng kp. Thng thng n c dng cho cc lnh ton hc: C = 1 nu php ton cng c s trn hoc php tr c mn v ngc li C = 0 nu php ton cng khng trn v php tr khng c mn. + C Carry ph AC: Khi cng nhng gi tr BCD (Binary Code Decimal), c nh ph AC c set nu kt qu 4 bit thp nm trong phm vi iu khin 0AH 0FH. Ngc li AC = 0. + C 0 (Flag 0): C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng.


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+ Nhng bit chn bank thanh ghi truy xut: RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset h thng v c thay dodi bi phn mm khi cn thit. Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l Bank 0, Bank 1, Bank 2, Bank 3. RS1 0 0 1 1 RS0 0 1 0 1 BANK 0 1 2 3

+ C trn OV: C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc. Khi cc s c du c cng hoc tr vi nhau, phn mm c th kim tra bit ny xc nh xem kt qu c nm trong tm xc nh khng. Khi cc s khng c du c cng bit OV c b qua. Cc kt qu ln hn +127 hoc nh hn 128 th bit OV = 1. + Bit Party (P): Bit t ng c set hay Clear mi chu k my lp Parity chn vi thanh ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn. V d A cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to thnh s chn. Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu. +Thanh ghi B: Thanh ghi B a ch F0H c dng cng vi thanh ghi A cho cc php ton nhn chia. Lnh MUL AB ly A chia B, kt qu nguyn t vo A, s d t vo B. Thanh ghi B c th c dng nh mt thanh ghi m trung gian a mc ch. N l nhng bit nh v thng qua nhng a ch t F0H F7H. + Con tr Ngn xp SP (Stack Pointer): Con tr ngn xp l mt thanh ghi 8 bit a ch 81H. N cha a ch ca byte d liu hin hnh trn nh ngn xp. Cc lnh trn ngn xp bao gm cc lnh ct d liu vo ngn xp (PUSH) v ly d liu ra khi ngn xp (POP). Lnh ct d liu vo ngn xp s lm tng SP trc khi ghi d liu v lnh ly ra khi ngn xp s lm gim SP. Ngn xp ca 8031/8051 c gi trong RAM ni v gii hn cc a ch c th truy xut bng a ch gin tip, chng l 128 byte u ca 89C51. - khi ng SP vi ngn xp bt u ti a ch 60H, cc lnh sau y c dng: MOV SP, # 5F.


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- Vi lnh trn th ngn xp ca 89C51 ch c 32 byte v a ch cao nht ca RAM trn chip l 7FH. S d gi tr 5FH c np vo SP v SP tng ln 60H trc khi ct byte d liu. - Khi Reset 89C51, SP s mang gi tr mc nh l 07H v d liu u tin s c ct vo nh ngn xp c a ch 08H. Nu phn mm ng dng khng khi ng SP mt gi tr mi th bank thanh ghi 1 c th c 2 v 3 s khng dng c v vng RAM ny c dng lm ngn xp. Ngn xp c truy xut trc tip bng cc lnh PUSH v POP lu tr tm thi v ly li d liu, hoc truy xut ngm bng lnh gi chng trnh con (ACALL, LCALL) v cc lnh tr v (RET, RETI) lu tr gi tr ca b m chng trnh khi bt u thc hin chng trnh con v ly li khi kt thc chng trnh con. + Con tr d liu DPTR (Data Pointer): Con tr d liu (DPTR) c dng truy xut b nh ngoi l mt thanh ghi 16 bit a ch 82H (DPL: byte thp) v 83H (DPH: byte cao). Ba lnh sau s ghi 55H vo RAM ngoi a ch 1000H: MOV A, # 55H MOV DPTR, # 1000H MOV @ DPTR, A Lnh u tin dng np 55H vo thanh ghi A. Lnh th hai dng np a ch ca nh cn lu gi tr 55H vo con tr d liu DPTR. Lnh th ba s di chuyn ni dung thanh ghi A (l 55H) vo nh RAM bn ngoi c a ch cha trong DPTR (l 1000H). + Cc thanh ghi Port (Port Register): Cc Port ca 89C51 bao gm Port 0 a ch 80H. Port 1 a ch 90H, Port 2 a ch A0H v Port 3 a ch B0H. Tt c cc Port ny u c th truy xut tng bit nn rt thun tin trong kh nng giao tip. + Cc thanh ghi Timer (Timer Register): 89C51 c cha hai b nh thi/ b m 16 bit c dng cho vic nh thi c m s kin. Timer 0 a ch 8AH (TL0: byte thp) v 8CH (TH0: byte cao). Timer 1 a chri 8BH (TL1: byte thp) v 8DH (TH1: byte cao). Vic khi ng timer c SET bi Timer Mode (TMOD) a ch 89H v thanh ghi iu khin Timer (TCON) a ch 88H. Ch c TCON c a ch ha tng bit. + Cc thanh ghi Port ni tip (Serial Port Register): 89C51 cha mt Port ni tip cho vic trao i thng tin vi cc thit b ni tip nh my tnh, modem hoc giao tip ni tip vi cc IC khc. Mt thanh ghi m d liu ni tip (SBUF) a ch 99H s d c hai d liu truyn v d liu nhp. Khi truyn d liu ghi ln SBUF, khiB mn Cng ngh iu khin t ng

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nhn d liu th c SBUF. Cc mode vn khc nhau c lp trnh qua thanh ghi iu khin Port ni tip (SCON) c a ch ha tng bit a ch 98H. + Cc thanh ghi ngt (Interrupt Register): 89C51 c cu trc 5 ngun ngt, 2 mc u tin. Cc ngt b cm sau khi b reset h thng v s c cho php bng vic ghi thanh ghi cho php ngt (IE) a ch A8H. C hai c a ch ha tng bit. + Thanh ghi iu khin ngun PCON (Power Control Register): Thanh ghi PCON khng c bit nh v. N a ch 87H cha nhiu bit iu khin. Thanh ghi PCON c tm tt nh sau: Bit 7 (SMOD): Bit c tc Baud mode 1, 2, 3 Port ni tip khi set. Bit 6, 5, 4: Khng c a ch. Bit 3 (GF1): Bit c a nng 1. Bit 2 (GF0): Bit c a nng 2. Bit 1 (PD): Set khi ng mode Power Down v thot reset. Bit 0 (IDL): Set khi ng mode Idle v thot khi ngt mch hoc reset. Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC h MSC 51 nhng ch c thi hnh trong s bin dch ca CMOS. 1.1.3.3. B nh ngoi (External memory): 89C51 c kh nng m rng b nh ln n 64K byte b nh chng trnh v 64K byte b nh d liu ngoi. Do c th dng thm RAM v ROM nu cn. B nh d liu ngoi l mt b nh RAM c c hoc ghi khi c cho php ca tn hiu RD\ v WR. Hai tn hiu ny nm chn P3.7 (RD) v P3.6 (WR). 4. Hot ng Reset: **89C51 c 2 cch thc hin reset: reset bng tay hoc reset t ng. Reset t ng:

Hnh 1.6. Reset t ng:


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Cc h vi x l th h mi

- Mch Autoreset thng c dng xc nh trng thi u tin ca mch ngay khi va cp ngun mch lun lun hot ng ng nh yu cu thit k. Khi cha cp ngun in p trn t bng 0V, nn khi va cp in t np t 0V -> Vcc, do khi cp in th in p a vo chn Reset l Vcc, nn mch t ng h thng. Reset bng tay:

Hnh 1.7. Reset bng tay

- Thng trong h thng rt cn ng tc Reset khi mch ang hot ng, do ch c mch Reset khi va bt my l cha . Vic thit k mch Reset bng tay rt n gin ch vic thm vo mch Reset t ng mt SW v in tr nh hnh. Nguyn l mch ging nh mch Reset t ng. - Trang thi ca tt c cc thanh ghi trong 89C51 sau khi reset h thng: Thanh ghi Ni dung m chng trnh PC 0000H Thanh ghi tch ly A 00H Thanh ghi B 00H Thanh ghi thi PSW 00H SP 07H DPRT 0000H Port 0 n port 3 FFH IP XXX0 0000 B IE 0X0X 0000 B Cc thanh ghi nh thi 00H SCON SBUF 00H PCON (HMOS) 0XXX XXXXH PCON (SMOS) 0XXX 0000 B - Thanh ghi quan trng nht l thanh ghi b m chng trnh PC c reset ti a ch 0000H. Khi ng vo RST xung mc thp, chng trnh lun bt u ti a


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Cc h vi x l th h mi

ch 0000H ca b nh chng trnh. Ni dung ca RAM trn chip khng b thay i bi tc ng ca ng vo reset. 1.1.4. HOT NG TIMER CA 89C51 1.1.4.1. Gii thiu - B nh thi ca Timer l mt chui cc Rlip Flop c chia lm 2, n nhn tn hiu vo l mt ngun xung clock, xung clock c a vo Flip Flop th nht l xung clock ca Flip Flop th hai m n cng chia tn s clock ny cho 2 v c tip tc. - V mi tng k tip chia cho 2, nn Timer n tng phi chia tn s clock ng vo cho 2n. Ng ra ca tng cui cng l clock ca Flip Flop trn Timer hoc c m n kim tra bi phn mm hoc sinh ra ngt. Gi tr nh phn trong cc FF ca b Timer c th c ngh nh m xung clock hoc cc s kin quan trng. V d: Timer 16 bit c th m n t FFFFH sang 0000H. - Hot ng ca Timer n gin 3 bit c minh ha nh sau:

Hnh 1.8. Biu thi gian

- Cc Timer c ng dng thc t cho cc hot ng nh hng, 89C51 c 2 b Timer 16 bit, mi Timer c 4 mode hot ng. Cc Timer dng m gi, m cc s kin cn thit v s sinh ra tc ca tc Baud cho Port ni tip. - Mi s nh thi l mt Timer 16 bit, do tng cui cng l tng th 16 s chia tn s clock vo cho 216 = 65536.


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- Trong cc ng dng nh thi, 1 Timer c lp trnh trn mt khong thi gian u n v c set c trn Timer. C c dng ng b chng trnh thc hin mt hot ng nh vic a ti 1 tng cc ng vo hoc gi d liu m ng ra. Cc ng dng khc c s dng vic ghi gi u ca Timer o thi gian tri qua hai trng thi (v d o rng xung). Vic m mt s kin c dng xc nh s ln xut hin ca s kin , tc thi gian tri qua gia cc s kin. - Cc Timer ca 89C51 c truy xut bi vic dng 6 thanh ghi chc nng c bit nh sau:TIMER SFR MC CH A CH

TCON TMOD TL0 TL1 TH0 TH1

Control Mode Timer 0 low byte Timer 1 low byte Timer 0 high byte Timer 1 high - byte

88H 89H 8AH 8BH 8CH 8DH

1.1.4.2. Thanh ghi iu khin Timer TCON: Thanh ghi iu khin bao gm cc bit trng thi v cc bit iu khin bi Timer 0 v Timer 1. Thanh ghi TCON c bit nh v. Hot ng ca tng bit c tm tt nh sau: Bit Symbol Bit Address Description C trn Timer 1 c set bi phn cng s trn, c xa bi phn mm hoc bi phn cng khi cc vect x l n th tc phc v ngt ISR. Bit iu khin chy Timer 1 c set hoc xa bi phn mm chy hoc ngng chy Timer. C trn Timer 0 (hot ng tng t TF1) Bit iu khin chy Timer 0 (ging TR1) C kiu ngt 1 ngoi. Khi cnh xung xut hin trn INT1 th IE1 c xa bi phn mm hoc phn cng khi CPU nh hng n th tc phc v ngt ngoi. C kiu ngt 1 ngoi c set hoc xa bng phn mm bi cnh kch hot bi s ngt ngoi. C cnh ngt 0 ngoi C kiu ngt 0 ngoi.

TCON.7

TF1

8FH

TCON.6 TCON.5 TCON.4 TCON.3

TR1 TF0 TR0 IE1

8EH 8DH 8CH 8BH

TCON.2 TCON.1 TCON

IT1 IE0 IT0

8AH 89H 88H


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1.1.4.3. Thanh ghi mode timer (TMOD): Thanh ghi TMOD gm hai nhm 4 bit l: 4 bit thp t mode hot ng cho Timer 0 v 4 bit cao t mode hot ng cho Timer 1.8 bit ca thanh ghi TMOD c tm tt nh sau: Bit 7 6 5 4 3 2 1 0 Name GATE C/T M1 M0 GATE C/T M1 M0 Timer 1 1 1 1 0 0 0 0 Description Khi GATE = 1, Timer ch lm vic khi INT1 = 1 Bit cho m s kin hay ghi gi C/T = 1: m s kin C/T = 0: Ghi gi u n Bit chn mode ca Timer 1 Bit chn mode ca Timer 1 Bit cng ca Timer 0 Bit chn Counter/ Timer ca Timer 0 Bit chn mode ca Timer 0 Bit chn mode ca Timer 0

** Vi hai bit M0 v M1 ca TMOD chn mode cho Timer 0 hoc Timer 1. Bit 0 0 1 Name 0 1 0 Timer 0 1 2 Description

Mode Timer 13 bit (mode 8048) Mode Timer 16 bit Mode t ng np 8 bit Mode Timer tch ra: Timer 0: TL0 l Timer 8 bit c iu khin bi cc 1 1 3 bit ca Timer 0. TH0 tng t nhng c iu khin bi cc bit ca mode Timer 1. Timer 1: c ngng li. TMOD khng c bit nh v, n thng c LOAD mt ln bi phn mm u chng trnh khi ng mode Timer. Sau s nh gi c th dng li v c khi ng li nh th bi s truy xut cc thanh ghi chc nng c bit ca Timer. 1.1.4.4. Cc mode v c trn - 89C51 c 2 Timer v Timer 0 v Timer 1. Ta dng k hiu TLx v Thx ch 2 thanh ghi byte thp v byte cao ca Timer 0 hoc Timer 1. Mode Timer 13 bit (MODE 0):

Hnh 1.10. S mode 0 B mn Cng ngh iu khin t ng

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- Mode 0 l mode Timer 13 bit, trong byte cao ca Timer (THx) c t thp v 5 bit trng s thp nht ca byte thp Timer (TLx) t cao hp thnh Timer 13 bit. 3 bit cao ca TLx khng dng. Mode Timer 16 bit (MODE 1):

Hnh 1.11. S mode 1

- Mode 1 l mode Timer 16 bit, tng t nh mode 0 ngoi tr Timer ny hot ng nh mt Timer y 16 bit, xung clock c dng vi s kt hp cc thanh ghi cao v thp (TLx, THx). Khi xung clock c nhn vo, b m Timer tng ln 0000H, 0001H, 0002H, ...., v mt s trn s xut hin khi c s chuyn trn b m Timer t FFFH sang 0000H v s set c trn Timer, sau Timer m tip. - C trn l bit TFx trong thanh ghi TCON m n s c c hoc ghi bi phn mm. - Bit c trng s ln nht (MSB) ca gi tr trong thanh ghi Timer l bit 7 ca THx v bit c trng s thp nht (LSB) v bit 0 ca TLx. - Cc thanh ghi Time. Mode t ng np 8 bit (MODE 2): c bo trn TL x (8 bit) TF x

Timer Clock

np li (RELOAD) TH x (8 bit)Hnh 1.12. S Mode2

- Mode 2 l mode t ng np 8 bit, byte thp TLx ca Timer hot ng nh mt Timer 8 bit trong khi byte cao THx ca Timer gi gi tr Reload. Khi b m trn t FFH sang 00H, khng ch c trn c set m gi tr trong THx cng c np vo TLx: B m c tip tc t gi tr ny ln n s chuyn trng thi t FFH sang


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00H k tip v c th tip tc. Mode ny th ph hp bi v cc s trn xut hin c th m mi lc ngh thanh ghi TMOD v THx c khi ng. Mode Timer tch ra (MODE 3): Timer Clock TL1 (8 bit) Timer Clock TL1 (8 bit) Timer Clock TH0 (8 bit)Hnh 1.13. S Mode 3

TH1 (8 bit) C bo trn TF0 C bo trn TF1

- Mode 3 l mode Timer tch ra v l s khc bit cho mi Timer. - Timer 0 mode 3 c chia l 2 timer 8 bit. TL0 v TH0 hot ng nh nhng Timer ring l vi s trn s set cc bit TL0 v TF1 tng ng. - Timer 1 b dng li mode 3, nhng c th c khi ng bi vic ngt n vo mt trong cc mode khc. Ch c nhc im l c trn TF1 ca Timer 1 khng b nh hng bi cc s trn ca Timer 1 bi v TF1 c ni vi TH0. - Khi timer 0 ch 3, timer 1 vn c th s dng bi port ni tip nh to tc baud (v n khng cn c ni vi TF1). 1.1.4.5. Cc ngun xung clock (CLOCK SOURCES): - C hai ngun xung clock c th m gi l s nh gi bn trong v s m s kin bn ngoi. Bit C/T trong TMOD cho php chn 1 trong 2 khi Timer c khi ng.

Hnh 1.14. Ngun cp xung nhp


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S m cc s kin (Event Counting): - Nu bit C/T = 1 th b Timer c ghi gi t ngun bn ngoi trong nhiu ng dng, ngun bn ngoi ny cung cp 1 s nh gi vi 1 xung trn s xy ra ca s kin. S nh gi l s m s kin. Con s s kin c xc nh trong phn mm bi vic c cc thanh ghi Timer. TLx/THx, bi v gi tr 16 bit trong cc thanh ny tng ln cho mi s kin. - Ngun xung clock bn ngoi a vo chn P3.4 l ng nhp ca xung clock bi Timer 0 (T0) v P3.5 l ng nhp ca xung clock bi Timer 1 (T1). - Trong cc ng dng m cc thanh ghi Timer c tng trong p ng ca s chuyn trng thi t 1 sang 0 ng nhp Tx. 1.1.4.6. S bt u, dng v iu khin cc timer: - Bit TRx trong thanh ghi c bit nh v TCON c iu khin bi phn mm bt u hoc kt thc cc Timer. bt u cc Timer ta set bit TRx v kt thc Timer ta Clear TRx. V d Timer 0 c bt u bi lnh SETB TR0 v c kt thc bi lnh CLR TR0 (bit Gate = 0). Bit TRx b xa sau s reset h thng, do cc Timer b cm bng s mc nh. Thm phng php na iu khin cc Timer l dng bit GATE trong thanh ghi TMOD v ng nhp bn ngoi INTx. iu ny c dng o cc rng xung.

Hnh 1.15. Thi gian hot ng ca mode 1


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1.1.4.7. S khi ng v truy xut cc thanh ghi timer: - Cc Timer c khi ng 1 ln u chng trnh t mode hot ng cho chng. Sau trong chng trnh cc Timer c bt u, c xa, cc thanh ghi Timer c c v cp nht theo yu cu ca tng ng dng c th. - TMOD l thanh ghi u tin c khi to, bi v t mode hot ng cho cc Timer. V d khi ng cho Timer 1 hot ng mode 1 (mode Timer 16 bit) v c ghi gi bng dao ng trn Chip ta dng lnh: MOV TMOD, # 00001000B. - Trong lnh ny M1 = 0, M0 = 1 vo mode 1 v C/T = 0, GATE = 0 cho php ghi gi bn trong ng thi xa cc bit mode ca Timer 0. Sau lnh trn Timer vn cha m gi, n ch bt u m gi khi set bit iu khin chy TR1 ca n. - Nu ta khng khi gn gi tr u cho cc thanh ghi TLx/THx th Timer s bt u m t 0000H ln v khi trn t FFFFH sang 0000H n s bt u trn TFx ri tip tc m t 0000H ln tip - Ta c th lp trnh ch sau mi ln trn ta s xa c TFx v quay vng lp khi gn cho TLx/THx Timer lun lun bt u m t gi tr khi gn ln theo ta mong mun. - c bit nhng s khi gn nh hn 256 s, ta s gi mode Timer t ng np 8 bit ca mode 2. Sau khi khi gn gi tr u vo THx, khi set bit TRx th Timer s bt u m gi tr khi gn v khi trn t FFH sang 00H trong TLx, c TFx t ng c set ng thi gi tr khi gn m ta khi gn cho Thx c np t ng vo TLx v Timer li c m t gi tr khi gn ny ln. Ni cch khc, sau mi trn ta khng cn khi gn li cho cc thanh ghi Timer m chng vn m c li t gi tr ban u. 1.1.5. CNG NI TIP 1.1.5.1. Gii thiu: + 89C51 c 1 port ni tip, c th hot ng theo nhiu ch . + Chc nng chnh ca port ni tip l: - Chuyn i t song song sang ni tip i vi d liu xut v ngc li i vi d liu nhp, truy cp phn cng vi port ni tip thng qua port 3: p3.0 (RXD) chn 10 v p3.1 (TXD) chn 11. - Port ni tip hot ng song cng v b m nhn cho php 1 k t c gi trong b m trong khi k t th hai c thu nhn.


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- Hai thanh ghi SFR (serial registry): SBUF v SCON, cho truy xut n cng ni tip bng phn mm. B m SBUF a ch 99H tht ra l 2 b m l SBUF ch cho ghi, v SBUF ch cho c. TXD CLK SBUF (ch ghi) RXD D thanh ghi dch CLK

Xung nhp (pht)

Xung nhp (thu) Bus ngoi 8051/8031

SBUF (ch c)

Hnh 1.16. S khi port ni tip

- Thanh ghi SCON a ch 98H c a ha theo tng bit: cha cc bit trng thi v cc bit iu khin. Cc bit trng thi c kim tra trong phn mm hoc c lp trnh to ngt. - Tn s hot ng ca port ni tip hay tc baud c th c nh (mch dao ng trong 89C51) hoc thay i c (timer 1 cung cp xung nhp, v phi c lp trnh tng ng (trong timer 2 ca 89C52/80C52 c th cung cp xung nhp). 1.1.5.2. Thanh ghi port ni tip: Ch hot ng ca port ni tip c t bng cc thanh ghi. Sau y l bng tm tt ca thanh ghi SCON: Bit SCON. 7 SCON. 6 SCON. 5 SCON. 4 SCON. 3 SCON. 2 SCON. 1 SCON. 0 K hiu SM0 SM1 SM2 REN TB8 RB8 TI RI a ch 9FH 9EH 9DH 9CH 9BH 9AH 99H 98H M ta Bit 0 ca ch port ni tip Bit 1 ca ch port ni tip Bit 2 ca ch port ni tip. Cho php truyn thng a X l trong ch 2 v 3; nu bit thu l 0 th RI khng b tc ng. Cho php b thu khi n c t ln 1 Bit th 9 trong qu trnh pht trong ch 2 v 3; c t v xa bng phn mm. Bit th 9 thu c. C ngt pht, t ln 1 khi kt thc pht k t; c xa bng phn mm. C ngt thu t ln 1 khi kt thc thu k t v c xa bng phn mm.


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Cc ch port ni tip: SM0 SM1 Ch M t Tc baud 0 0 0 Thanh ghi dch C nh (Fosc/12) 0 1 1 UART 8 bit Thay i (t bng timer 1) 1 0 2 UART 9 bit C nh (Fosc/12 hoc 64) 1 1 3 UART 9 bit Thay i (t bng timer 1) Trc khi s dng port ni tip ta phi khi to SCON ng ch ta mong mun nh c quy nh nh trn. 1.1.5.3. Cc ch hot ng Port ni tip c 4 ch hot ng. Trong c 3 ch truyn thng bt ng b. Vi 1 k t c pht hoc thu u c ng khung bng bit start v kt thc bng 1 bit stop. Ch cn li hot ng nh 1 thanh ghi dch n gin. a. Thanh ghi dch 8 bit (ch 0): Ch ny c chn khi SM0 = 0 v SM1 = 0. D liu vo ra chn RXD, cn TXD xut xung nhp dch. Bit u tin ca thu hoc pht l LSB. Tc c nh 1/12 ca dao ng trn chip. Vic pht i c khi ng bng bt c lnh no ghi d liu vo SBUF. D liu c dch ra ngoi trn ng RXD (P3.0) vi cc xung nhp c gi ra t chn TXD (P3.1). Mi bit pht i hp l trong 1 chu k my. Vic thu khi bit REN = 1 v RI = 0. Khi RI b xa, cc xung nhp c a ra ng TXD, bt u chu k my k tip, v d liu theo xung ra chn RXD. Ly xung nhp cho d liu vo port ni tip xy ra cnh dng ca TXD. b. UART 8 bit vi tc baud thay i c (ch 1): UART (universal Asynchronous receiver/transmitter: b pht thu bt ng b vn nng) vi chc nng thu/ pht ni tip. Vi mi k t d liu i trc l bit start mc thp v theo sau l bit stop mc cao. C hoc khng bit kim tra chn l parity. ch ny 10 bit c pht trn TXD hoc thu trn RXD. Vi hot ng thu, bit stop c a vo RB8 trong SCON. Trong 8051/8031 ch baud c t bng tc bo trn ca timer 1. To xung nhp v ng b cc thanh ghi dch trong ch 1, 2, 3 c thit lp bng b m 4 bit chia cho 16, ng ra l xung nhp tc baud, ng vo c chn bng phn mm. Truyn d liu c khi ng bng cch ghi vo SBUF. C ngt TI = 1 khi xut hin bit stop trn chn TXD.


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Thu d liu bng 1 chuyn trng thi t 1 xung 0 trn chn RXD. Lung bit n c ly mu gi 16 ln m. Gi s pht hin bit start hp l, th tip tc thu k t. Sau khi thu xong th: Bit th 9 (bit stop) c cht vo RB8 trong SCON. SBUF c np 8 bit d liu. C RI t ln 1. c. UART 9 bit vi tc baud c nh (ch 2): Khi SM1 = 1, SM0 = 0, lc ny 11 bit c pht hoc thu: 1 bit srat, 8 bit d liu, bit th 9 c th lp trnh c v 1 bit stop. Khi pht bit th 9 l bit a vo TB8 trong SCON. Khi thu bit th 9 s trong RB8. c baud l 1/32 hoc 1/64 tn s dao ng trn chip ty theo bit SMOD. d. UART 9 bit tc baud thay i c (ch 3): - Ch ny ging ch 2 ngoi tr tc baud c th thay i c bng timer1. - Tc baud ca port ni tip: Tc b nh hng bi 1 bit trong thanh ghi iu khin ngun cung cp (PCON) l SMOD = 1 th tc baud trong ch 1, 2, 3 s gp i. - Ch 0, 2 c tc c nh: Ch 0: bng tn s dao ng trn chip chia cho 12. Ch 2: bng tn s dao ng trn chip chia 32 hoc 64 ty vo SMOD. SMOD = 0: chia 64. SMOD = 1: chia 32. Sau khi reset th chia 64. - Ch 1 v 3: Tn s da vo thi gian trn ca timer1. - V PCON khng c a ch theo bit, nn t bit SMOD ln 1 th ta c th lm nh sau: MOV A, PCON; ly gi tr hin thi ca PCON SETB ACC.7; t ln 1 MOV PCON, A; np ngc li.B mn Cng ngh iu khin t ng

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Nhng ch khi s dng timer 1 lm xung nhp tc baud ch 1 v 3: Xt 8051, ta khi ng TMOD ch 8 bit t ng np li, c th lm nh sau: MOV TMOD, #0010xxxxB Vi: x l bit 0 hoc 1. Ta c th dng ch 16 bit. MOV TMOD, # 0001xxxxB. Tuy nhin tn thm phn mm v phi np li TH1, TL1 sau mi ln trn, vic ny phi thc hin trong chng trnh phc v ngt. Cng thc tng qut xc nh tc baud trong ch 1,3: Tc baud = tc trn timer1/32. * V vic lm trn s nn c sai s trong tc baud, ta s c tc baud chnh xc nu dng thch anh 11.059MHz. Ta hy so snh gia thch anh 12MHz v 11.059MHz Tc Tn s thch anh SMOD Gi tr np Th1 Baud 9600 12MHz 1 - 7 (F9H) 2400 12MHz 0 - 13 (F3H) 1200 12MHz 0 - 26 (E6H) 9600 11.059 0 - 3 (FDH) 2400 11.059 0 - 12 (F4H) 1200 11.059 0 - 24 (E8H) Tc baud tht 8923 2404 1202 9600 2400 1200

Sai s 7% 0.16% 0.16% 0 0 0

1.1.6. T CHC NGT CA MCS51 - C 5 ngun ngt MCS51: 2 ngt ngoi, ngt t timer v 1 ngt port ni tip. Tt c cc ngt theo mc nhin u b cm sau khi reset h thng v c cho php tng ci bng phn mm. - Khi c 2 hoc nhiu ngt ng thi, hoc mt ngt xy ra trong khi 1 ngt khc ang c phc v, th c 2 cch gii quyt: s tun t hi vng v s u tin. Vic hi vng tun t th c nh, cn u tin ngt th c th lp trnh. - Cho php v cm cc ngt: Thng qua thanh ghi IE (interrupt enable) a ch A8H


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Bit IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

K hiu EA ET2 ES ET1 EXT0 ET0 EX0

a ch bit AFH AEH ADH ACH ABH AAH A9H A8H

M t (1: cho php, 0: cm) Cho php/cm ton b Khng c nh ngha Ngt timer 2 (8052) Ngt port ni tip Ngt timer 1 Ngt ngoi 1 Ngt timer 0 Ngt ngoi 0

1.1.6.1. u tin ngt: Lp trnh thng qua thanh ghi chc nng c bit a ch bit IP (interrupt priority) a ch B8H. Bng tm tt thanh ghi IP Bit IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 K hiu PT2 PS PT1 PX1 PT0 PX0 a ch bit BDH BCH BBH BAH B9H B8H M t (1: mc cao hn, 0: mc thp hn) Khng nh ngha Khng nh ngha u tin ngt timer (8052) u tin ngt port ni tip u tin ngt timer 1 u tin ngt ngoi 1 u tin ngt timer 0 u tin ngt ngoi 0

1.1.6.2. Hi vng tun t: Nu 2 ngt cng u tin xy ra ng thi, th hi vng tun t s xc nh ci no s phc v trc theo th t nh sau: Ngt ngoi 0, timer 0, bn ngoi 1, timer 1, port ni tip v timer 2. Cc vect ngt: Ngt Reset h thng Bn ngoi 0 Timer 0 Bn ngoi 1 Timer 1 Port ni tip RST IE0 TF0 IE1 TF1 TI hoc RI C a ch vect 0000H 0003H 000BH 0013H 001BH 0023H


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1.1.7. TM TT TP LNH CA 89C51 Cc chng trnh c cu to t nhiu lnh, chng c xy dng logic, s ni tip ca cc lnh c ngh ra mt cch hiu qu v nhanh. Tp lnh h MSC 51 c s kim tra ca cc mode nh v v cc lnh ca chng c cc Opcode 8 bit. iu ny cung cp kh nng 28 = 256 lnh c thi hnh. Vi lnh c 1 hoc 2 byte bi d liu hoc a ch thm vo Opcode. Trong ton b cc lnh c 139 lnh 1 byte, 92 lnh 2 byte v 24 lnh 3 byte. 1.1.7.1. Cc ch nh v a ch (addressing mode): Cc mode nh v l mt b phn thng nht ca tp lnh. Chng cho php nh r ngun hoc ni gi ti ca d liu cc ng khc nhau ty thuc vo trng thi ca ngi lp trnh. 89c51 c 8 mode nh v c dng nh sau: Thanh ghi. Trc tip Gin tip. Tc thi. Tng i. Tuyt i. Di. nh v. 1.1.7.2. Tm tt tp lnh ca h MCS 51: a. Nhm lnh chuyn d liu: Lnh MOV A, Rn MOV A, @Ri MOV A, # data MOV Rn, A MOV Rn, #data MOV direct, Rn MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @ Ri, direct MOV @Ri, #data MOVX @ Ri, A MOVX @ dptr, A PUSH directB mn Cng ngh iu khin t ng

M t (A) (Rn) (A) ((Ri)) (A) #data (Rn) (A) (Rn) #data (direct) (Rn) (direct) ((Ri)) (direct) #data ((Ri)) (A) ((Ri)) (direct) ((Ri)) (data) ((Ri)) (A) ((dptr) (A) (SP) (SP) + 1 28Khoa CNTT - HTN


Cc h vi x l th h mi

POP direct XCH A, Rn XCH A, direct XCHA, @Ri XCHD A, @Ri b. Nhm lnh ton hc: Lnh ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri INC dptr DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV AB DA A c. Nhm lnh logic: Lnh ANL A, Rn ANL A, direct ANL A, @ Ri ANL A, #data

((SP)) (direct) (direct) ((SP)) (SP) (SP) 1 (direct) (Rn) (A) (direct) (A) ((Ri)) (A3 0) ((Ri3 0))

M t (A) (A) + (Rn) (A) (A) + (direct) (A) (A) + ((Ri)) (A) (A) + #data (A) (A) (Rn) (C) (A) (A) (direct) (C) (A) (A) ((Ri)) (C) (A) (A) - #data (C) (A) (A) + 1 (Rn) (Rn) + 1 (direct) (direct) +1 ((Ri)) ((Ri)) + 1 (dptr) (dptr) +1 (A) (A) 1 (Rn) (Rn) 1 (direct) (direct) - 1 ((Ri)) ((Ri)) 1 (B15 8), (A7 0) (A) x (B) (A15 8), (B7 0) (A) / (B) Content of A l BCD

M t (A) (A) AND (Rn) (A) (A) AND (direct) (A) (A) AND ((Ri)) (A) (A) AND #data


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ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL direct, A CLR A CPL A SWAP A d. Nhm lnh chuyn iu khin: Lnh LJMP addr 16 SJMP rel JMP @ A + dptr JZ rel

(direct) (direct) and (A) (direct) (direct) and #data (A) (A) OR (Rn) (A) (A) OR (direct) (A) (A) OR ((Ri)) (A) (A) OR #data (direct) (direct) OR (A) (direct) (direct) OR #data (A) (A) XOR (Rn) (A) (A) XOR (direct) (A) (A) XOR ((Ri)) (direct) (direct) XOR (A) (A) 0 (A) (-A) (A3 0) (A7 4)

JNZ rel

JC rel

JNC rel

JB bit, rel

JNB bit, rel

JBC bit, rel CJNE A, direct, relB mn Cng ngh iu khin t ng

M t (PC) addr15 0 (PC) (PC) + 2 (PC) (PC) + rel (PC) (A) + (dptr) (PC) (PC) + 2 IF (A) = 0 then (PC) (PC) + rel (PC) (PC) + 2 IF (A) 0 then (PC) (PC) + rel (PC) (PC) + 2 IF (C) = 0 then (PC) (PC) + rel (PC) (PC) + 2 IF (C) 0 then (PC) (PC) + rel (PC) (PC) + 3 IF (bit) = 0 then (PC) (PC) + rel (PC) (PC) + 3 IF (bit) 0 then (PC) (PC) + rel (PC) (PC) + 3 IF (bit) = 0 then (bit) 0 (PC) (PC) + rel (PC) (PC) + 3 30Khoa CNTT - HTN


Cc h vi x l th h mi

CJNE A, #data, rel

DJNZ Rn, rel

DJNZ direct, rel NOP e. Nhm lnh x l bit: Lnh CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, / bit ORL C, bit ORL C, / bit MOV C, bit MOV bit, C

IF (direct) < (A) then (C) 0 and (PC) (PC) + rel IF (direct) > (A) then (C) 1 and (PC) (PC) + rel (PC) (PC) + 3 IF #data > (A) then (C) 0 and (PC) (PC) + rel IF #data > (A) then (C) 1 and (PC) (PC) + rel (PC) (PC) + 2 (Rn) (Rn) 1 IF ((Ri)) 0 then (PC) (PC) + rel (PC) (PC) + 3 (direct) (direct) 1 IF (direct) 0 then (PC) (PC) + rel (PC) (PC) + 1

M t (C) 0 (bit) 0 (C) 1 (bit) 1 (C) (-C) (bit) (bit) (C) (C) AND (bit) (bit) (C) AND (bit) (C) (C) OR (bit) (bit) (C) OR (bit) (C) (bit) (bit) (C)

1.2 VI IU KHIN AT89C55 1.2.1 c trng Tng thch vi nhng sn phm MCS-51 B nh Flash 20K Bytes c th lp trnhB mn Cng ngh iu khin t ng

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Kh nng: 1000 chu trnh ghi /xa Phm vi in p hot ng : 4V n 5.5V Di tn s hot ng: 0 Hz - 33 MHz Ba mc kha b nh chng trnh RAM tch hp 256x8 bit. 32 ng iu khin vo/ra c th lp trnh c Ba b nh thi/b m 16 bit 8 ngun ngt Knh ni tip c th lp trnh Ch ngun thp Idle v ch ngun gim Phc hi ngt t ch ngun gim B nh thi bo v phn cng (Watchdog) 1.2.2. Phn m t AT89C55WD l mt vi iu khin 8bit CMOS c cng sut ngun tiu th thp, hiu sut cao vi 20K byte Flash ROM lp trnh c v 256 byte RAM. Thit b c sn xut s dng cng ngh b nh khng mt ni dung c tch hp cao ca Atmel v tng thch vi tp lnh v cc chn ra ca tiu chun cng nghip 80C51 v 80C52. Flash trn chip ny cho php b nh chng trnh c ngi dng chng trnh ha bng lp trnh b nh khng mt ni dung quy c. Bng vic kt hp mt CPU linh hot 8- bt vi Flash trn mt chip n th, Atmel AT89C55WD l mt my vi tnh mnh cung cp mt gii php c hiu qu v chi ph v rt linh hot i vi nhiu ng dng iu khin nhng. AT89C55WD c cc c trng chun sau y: 20 K byte Flash , 256 byte RAM, 32 ng nhp/xut, ba b nh thi/b m 16-bt, su vect, cu trc ngt hai mc, mt cng ni tip song cng hon ton (full-duplex serial), mch dao ng v to xung clock trn chp. Ngoi ra,AT89C55WD c thit k vi lgic tnh cho hot ng c tn s gim xung 0 v h tr hai ch tit kim nng lng c la chn bng phn mm. Ch ngh dng CPU trong khi vn cho php RAM, cc thit b nh thi/m, cng ni tip v h thng ngt tip tc hot ng. Ch ngun gim duy tr ni dung ca RAM nhng khng cho mch dao ng cung cp xung clock nhm v hiu ha cc hot ng khc ca chip cho n khi c reset cng tip theo


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S khi

Hnh 1.17. Cu trc bn trong AT89C55WD B mn Cng ngh iu khin t ng

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Hnh 1.18. S chn AT89C55WD

M t cc chn Port 1 Port 1 l mt port nhp/xut 8- bt hai chiu c cc in tr ko ln bn trong. Khi cc logic 1 c ghi ln cc chn ca port 1, cc chn ny c ko ln mc cao bi in tr ko ln bn trong v c th c s dng nh l cc ng vo. Khi lm nhim v port nhp, cc chn ca port 1 ang c ko xung mc thp do tc ng bn ngoi s cp dng cho cc in tr ko ln bn trong. Ngoi ra, P1. 0 v P1. 1 c th c nh cu hnh l u vo m ngoi (P1.0/ T2) ca b nh thi/m 2 v u vo trigger ( P1.1/T2EX) ca b nh thi/m 2, theo th t cho trong bng sau:

Port 1 cng nhn byte a ch thp trong thi gian lp trnh cho Flash v kim tra chng trnh. RST: Ng vo reset. Mc cao trn chn ny trong 2 chu k my trong khi b dao ng hot ng s reset AT89C55WD. Chn ny iu khin mc cao cho 98 chu k dao ng sau khi Watchdog ht gi. Bit DISRTO trong SFR AUXR (a ch 8 EH) c th c dng v hiu ha c tnh ny. Trong trng thi mc nh ca bit DISRTO, RESET HIGHT ngoi c tnh c cho php. XTAL1: Ng vo n mch khuch i o ca mch dao ng v ng vo n mch to xung clock bn trong chip.


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XTAL2: Ng ra t mch khuch i o ca mch dao ng . Nhng thanh ghi chc nng c bit Ch rng khng phi tt c a ch ang c s dng, v nhng a ch nhn ri c th khng c thc hin trn chp. Nhng truy nhp c ti cc a ch ny s ni chung tr li d liu ngu nhin,v nhng truy nhp ghi khng hiu qu.Phn mm ngi dng khng nn ghi mc logic 1 ti nhng vng ny, chng c th c dng cho nhng sn phm trong tng lai xut hin cc c tnh mi.Trong trng hp ,cc gi tr reset hay khng hot ng lun = 0

Thanh ghi nh thi 2: Cc bit iu khin v trng thi cho b nh thi 2c cha ng trong cc thanh ghi T2CON v T2MOD.Cp thanh ghi (RCAP2H, RCAP2L) l cc thanh ghi Thu nhn /Np li cho b nh thi 2 trong ch Thu nhn 16- bt hay ch Np li t ng 16- bt. Hnh minh ha:T2CON(thanh ghi iu khin b nh thi 2)


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Chc nng C trn ca b nh thi 2.C ny c set bng phn cng v c xa bng phn mm.TF2 khng th c set khi RCLK=1 hoc TCLK=1 EXF2 C ngoi ca b nh thi 2.C ny c set khi c s np li hoc thu nhn to ra bi chuyn trng thi m trn chn T2EX v EXEN2 =1.Khi ngt do b nh thi 2 c php , EXF2=1 s lm cho CPU tr ti trnh phc v ngt nh thi. EXF2 phi c xa bng phn mm. RCLK Clock thu.Khi c set,port s dng cc xung trn ca b nh thi 2 lm clock thu trong cc ch 1 v 3.RCLK=1 gy ra trn b nh thi 1 c s dng lm clock thu. TCLK Clock pht. Khi c set port ni tip s dng cc xung trn ca b nh thi 2lm clock pht trong cc ch 1v 3. TCLK=0 gy ra trn b nh thi 1 c s dng lm clock pht. EXEN2 C cho php ngoi ca b nh thi 2. Khi c set c ny cho php thu nhn hoc np li khi c s chuyn trng thi m trn chn T2EX nu b nh thi 2 hin khng c dng lm xung clock cho port ni tip. EXEN2=0 lm cho b nh thi 2 b qua cc s kin trn chn T2EX. TR2 Bit cho php hoc khng cho php b nh thi 2 hot ng .Bit ny iu khin START/STOP b nh thi 2. Logic 1 ca bit ny khi ng b nh thi. C/T2 Chn ch nh thi hay m cho b nh thi 2.C/T2=0 cho nh thi bn trong,C/T2=1cho m s kin bn ngoi. CP/RL2 C thu nhn/np li .Khi c ny c set ,vic thu nhn xy ra khi c chuyn trng thi m trn chn T2EX nu EXEN2=1.Khi c xa vic t np s li xy ra khi trn b nh nh thi 2 hoc c chuyn trng thi m trn chn T2EX khi EXEN2=1.Khi RCLK hoc TCLK=1,bit ny c b qua v b nh thi phi t np li khi trn Hnh minh ha:T2MOD (Thanh ghi iu khin ch b nh thi 2)

Biu tng TF2

Biu tng Chc nng Khng c cp, dnh cho tng lai T2OE DCEN Bit cho php u ra b nh thi 2 Khi thit lp,bit ny cho php b nh thi 2 c nh cu hnh nh mt b m Tin/Li

Cc thanh ghi ngt: Thanh ghi cho php ngt IE (Interrupt Enable) lm cho cc bit c th ngt ring r. Trong thanh ghi u tin ngt IP (Interrupt Priority) c 2 mc u tin c th thit lp cho mi trong 6 ngun ngt.B mn Cng ngh iu khin t ng

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Thanh ghi con tr d liu kp (Dual Data Pointer Registers ): to iu kin thun li cho truy nhp c b d liu trong v ngoi 2 dy thanh ghi con tr d liu c cung cp:DP0 vng a ch 82H-83H v DP1 84H-85H. Bit DPS=0 trong SFR AUXR1 chn DP0 v DPS=1 chn DP1. Ngi s dng cn phi lun lun khi tobit DPS ti gi tr thch hp trc khi truy cp thanh ghi con tr d liu tng ng. C tt ngun in (Power Off Flag ): C tt ngun in (POF) c nh v ti bit 4 (PCON.4) trong PCON SFR. POF c thit lp ti "1" trong thi gian ngun tng. N c th c thit lp v thit lp li di iu khin phn mm v khng b nh hng bi Reset. AUXR:Thanh ghi h tr(Auxilliary Register) AUXR a ch =8EH Gi tr khi to=XXX00XX0B

-

Dnh ring cho s m rng trong tng lai

DISALE Cho php/khng cho phpALE DISALE 0 1 Ch hot ng ALE c pht ra ti tn s =1/6 tn s ca mch dao ng ALE c hot ng trong 1 lnh MOVX hocMOVC

DISRTO Cho php/khng cho php Reset u ra DISRTO Ch hot ng 0 1 chn Reset c t ti mc cao sau u ra nh thi WDT Chn Reset ch l u vo

WDIDLE Cho php/khng cho php WDT trong ch IDLE WDIDLE Ch hot ng 0 1 WDT tip tc m trong ch IDLE WDT tm dng m trong ch IDLE


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AUXR1: Thanh ghi h tr 1 AUXR1 a ch =A2H Gi tr khi to =XXXXXXX0B

Dnh cho s m rng trong tng lai DPS La chn thanh ghi con tr d liu DPS 0 1 Chn cc thanh ghi DPTR : DP0L,DP0H Chn cc thanh ghi DPTR : DP1L,DP1H

T chc b nh Thit b MCS-51c khng gian b nh ring dnh cho chng trnh v d liu. Ti a 64 Kbytes ca b nh chng trnh v d liu ngoi c th c nh a ch. B nh chng trnh Nu chn EA c kt ni vi GND, tt c cc chng trnh nh sn c hng ti b nh ngoi.Trong AT89C55WD, nu EA c kt ni ti VCC, cachng trnh tm np t a ch 0000H n 4FFFH c hng ti b nh trong v tm np t a ch 5000H ti FFFFH hng ti b nh ngoi. B nh d liu AT89C55WD b sung 256 bytes RAM trn chip. 128 byte cao chim gi 1 khng gian a ch song song ti cc thanh ghi chc nng c bit . C ngha l 128 bytes cao c khng gian a ch ca SFR nhng khng gian vt l th tn ti ring so vi khng gian SFR. Khi 1 lnh truy cp ti 1 vng nh ngoi vt qu a ch 7FH, ch a ch ny c s dng trong 1 lnh ch r CPU truy cp ti 128 byte cao ca khng gian RAM hay SFR .Nhng lnh s dng a ch trc tip truy cp khng gian SFR.V d lnh nh a ch trc tip sau truy cp khng gian SFR tai vng nh 0A0H (which is P2). MOV 0A0H, #data Nhng lnh s dng a ch gin tip truy cp ti 128 byte cao ca RAM. V d ,lnh nh a ch gin tip sau,ti R0 cha 0A0H, truy cp ti byte d liu tai a ch 0A0H, ng hn P2 (ca a ch 0A0H).B mn Cng ngh iu khin t ng

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MOV @R0, #data Ch rng cc thao tc ngn xp l v d ca nh a ch gin tip ,v th 128 byte cao ca RAM d liu c th dng nh khng gian ngn xp. nh thi bo v phn cng (One-time Enabled with Reset-out) WDT c mong i nh 1 phng php phc hi ti v tr m CPU qun l cc upset phn mm. WDT gm c 1 b m 13 bit v WatchDog Timer Reset (WDTRST) SFR. The WDT c mc dnh v hiu ho t exiting reset. c WDT, 1 ngi dng phi ghi 01EH v 0E1H ng trnh t ti thanh ghi WDTRST (vng 0A6H ca SFR). Khi WDT c cho php, n s gia tng tr s mi chu trnh my trong khi my to dao ng ang chy.WDT time-out period ph thuc tn s clock ngoi. Khng c cch no v hiu ha WDT tr khi reset hon ton (reset phn cng hoc reset trn WDT ). Khi WDT trn b nh, n s iu khin mt xung ra RESET HIGH ti chn RST. S dngWDT cho php WDT ,ngi s dng phi ghi 01EH v 0E1H trong trnh t ti thanh ghi WDTRST (SFR vng 0A6H).Khi WDT c cho php ,ngi s dng cn phc v n bng cch ghi 01EH v 0E1H ti WDTRST trnh 1 WDT trn b nh.B m 13-bit trn khi n ti 8191(1FFFH),v khi s Reset thit b.Khi WDT c cho php n s gia tng mi chu k my trong khi b dao ng ang chy. iu c ngha l ngi s dng phi khi chy li WDT ti ti thiu mi 8191 chu k my. khi chy li WDT ngi s dng phi phi gi 01EH v 0E1H ti WDTRST. WDTRST l 1 thanh ghi ch c.B m WDT khng th c c hay ghi.Khi WDT trn b nh,n s to ra 1 xung RESET u ra chn RST.Thi hiu xung Reset l 98xTOSC,ti TOSC=1/FOSC s dng WDT tt nht ,nen phc v n trong nhng on m m s nh k thc hin trong khong thi gian cn ngn 1 Reset WDT WDT trong lc Ngun gim v Ngh Trong ch ngun gim ,mch dao ng ngng,c ngha l WDT cng ngng.Khi ngun gim ngi dung khng cn phc v WDT.C 2 cch thot khi ch ngun gim :bng Reset phn cng hoc theo 1 mc kch hot ngt ngoi m n lm cho c th i vo ch ngun gim.Khi thot ch ngun gim bng Reset phn cng,s phc v WDT cn din ra bnh thng ging nh khi Reset AT89C55WD.Thot ch Ngun gim bng ngt l 1 cch khc . Ngt c gi mc thp di mch dao ng n nh.Khi ngt c y ln mc cao ,ngt c phc v. ngn WDT t Reset thit b trong khi chn ngt dc gi mc thpB mn Cng ngh iu khin t ng

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,WDT khng c bt u n tn khi ngt c y len mc cao.N c a ra WDT c Reset trong qu trnh phc v ngt cho ngt c dng thot khi ch ngun gim. m bo WDT khng trn b nh trong trng thi thot ch ngun gim,tt nht l Reset WDT ngay trc khi vo ch ngun gim. Trc lkhi vo ch IDLE ,bit WDIDLE trong SFR AUXR dc s dng quyt nh WDT c tip tc m hay khng nu c th.WDT gi m trong IDLE(bit WDIDLE=0) ging nh trng thi mc nh. ngn AT89C55WD khi ng li WDT trong ch IDLE, ngi s dng phi lun ci t mt b nh thi nh k thot khi IDLE, phc v WDT, v vo li ch IDLE. Vi bit WDIDLE cho php, WDT s dng m trong ch IDLE v phc hi li m trn kt thc t IDLE. UART: UART trong AT89C55WD vn hnh cng cch vi UART trong AT89C51 v AT89C52. B nh thi 0 v B nh thi 1 B nh thi 0 v b nh thi 1 trong AT89C55WD hot ng ging nh b nh thi 0 v b nh thi 1 trong AT89C51 v AT89C52. B nh Thi 2 B nh thi 2 l mt b m/nh thi c th hot ng nh thi hoc m mt s kin. Kiu hot ng c chn bng bit C/T2 trong SFR T2CON. B nh thi 2 c 3 ch hot ng: Thu nhn, t np li, to ra tc baud, tc m bng 1/12 tn s ca mch dao ng. Cc ch hot ng ca b nh thi 2 RCLK+TCLK CP/RL2 TR2 Ch Np t ng 16-bit 0 0 1 Thu nhn 16-bit 0 1 1 To tc Baud 1 X 1 tt X X 0 Trong chc nng m, thanh ghi c tng mt tr s trong p ng chuyn 1 thnh 0 trong chn u vo bn ngoi hot ng ng ca n, T2. Trong chc nng ny u vo bn ngoi ly mu trong qu trnh S5P2 ca mi chu k my. Khi mu c a ln mc cao mt chu k v t mc thp trong chu ki tip theo th m c tng 1 gi tr. Gi tr m mi xut hin trong thanh ghi trong S3P1 ca chu k sau chu k m s chuyn tip c pht hin. T 2 chu k my(24 chu k mch dao ng ) c yu cu tha nhn chuyn tip 1 thnh 0, tc m ti a l 1/24 tnB mn Cng ngh iu khin t ng

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s mch dao ng. m bo 1 mc nht nh c ly mu ti thiu 1 ln trc khi thay i,mc nn c gi trong ti thiu 1 chu k my trn vn. Ch Thu nhn (Capture) Trong ch thu nhn, 2 ty chn c chn bi EXEN2 trong T2CON . Nu EXEN2=0,b nh thi 2 l 1 b m hay nh thi 16-bit thit lp bit TF2 trong T2CON khi trn b nh. Bit c th dc dng to ra 1 ngt. Nu EXEN2=1, b nh thi 2 thc thi cng hot ng ,nhng chuyn i 1 0 ti u vo ngoi T2EX cng gy ra gi tr hin ti TH2 v TL2 c thu nhn ln lt trong RCAP2H v RCAP2L.Ngoi ra ,s chuyn i ti T2EX cng l nguyn nhn khin bit EXF2 trong T2CON c thit lp.Bit EXF2 cng nh TF2 c th to ra 1 ngt. Hnh v minh ha:

Ch T np li (B m tin hoc li ) B nh thi 2 c th c lp trnh m tin hoc li khi nh cu hnh trong ch t np li 16-bit.Tnh nng ny c gi ti bng bit DCEN (Down Counter Enable) c nh v trong SFR T2MOD.Trong lc Reset, bit DCEN c set ti 0 v th b nh thi 2 s mc nh m tin. Khi DCEN c set , b nh thi 2 c th m tin hoc li , ph thuc gi tr ca chn T2EX.


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Hnh v minh ha: DCEN=0 Trn hnh v trn ta thy b nh thi 2 t ng m tin khi DCEN=0. Trong ch ny, 2 ty chn c chn bi bit EXEN2 trong T2CON.Nu EXEN2=0 b nh thi 2 m tng ti 0FFFFH v sau thit lp bit TF2 khi trn b nh .Trn b nh cng khin cc thanh ghi nh thi c np li vi 16-bit gi tr trong RCAP2H v RCAP2L.Cc gi tr tong RCAP2Hv RCAP2L trong b nh thi trong ch Thu nhn c nh sn bng phn mm . Nu EXEN2=1, ch np li 16-bit c th c khi chy bng s trn b nh hoc s chuyn 1 0 ti u vo ngoi T2EX . S chuyn i cng thit lp bit EXF2. C 2 bit TF2 v EXF2 u c th to ra 1 ngt nu c php. DCEN=1

S thit lp bit DCEN(DCEN=1) cho php b nh thi 2 m tin hoc li. Trong ch ny ,chn T2EX iu khin hng m .T2EX=1,b nh thi 2 m tin.B nh thi s trn ti 0FFFFH v thit lp bit TF2.S trn b nh cng khinB mn Cng ngh iu khin t ng

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16-bit gi tr trong RCAP2H v RCAP2L c np li ln lt vo trong cc thanh ghi nh thi TH2 v TL2. T2EX=0,b nh thi m li.B nh thi thiu b nh khi gi tr lu tr trong TH2 v TL2 bng gi tr lu tr trong RCAP2H v RCAP2L. Underflow thit lp bit TF2 v lm cho 0FFFFH c np li vo cc thanh ghi nh thi . Bit EXF2 toggles mi khi b nh thi 2 trn b nh hoc thiu b nh v c th c s dng nh bit th 17.Trong ch hot ng ny EXF2 khng lm c trn. My pht tc baud B nh thi 2 c la chn nh my pht tc baud bng vic thit lp TCLK , RCLK trong T2CON(bng 5.2) .Ch rng tc baud cho truyn v nhn c th khc nu b nh thi 2 c dung cho my nhn hoc my truyn v b nh thi 1 c dng cho chc nng khc.Vic thit lp RCLK , TCLK t b nh thi 2 vo ch my pht tc baud ca n, c ch ra trong hnh minh ha 13-1Ch my pht tc baud tng t nh ch t np li,trong 1 rollover trong TF2 lm cho cc thanh ghi b nh thi 2 c np li vi 16 bit gi tr trong cc thanh ghi RCAP2H v RCAP2L,chng c nh sn bng phn mm.Tc baud trong cc ch 1v 3 c xc nh bng tc trn b nh theo phng trnh sau: Tc baud cc ch 1v3 = tc trn b nh ca b nh thi 2/16. B nh thi c th c cu hnh hot ng nh thi hoc m.Trong hu ht cc ng dng ,n c cu hnh cho hot ng nh thi.Thng thng ,nh 1 thit b nh thi,n gia tng mi chu k my(ti 1/12 tn s mch dao ng).Tuy nhin nh 1 my pht tc baud ,n gia tng mi trng thi thi gian(ti tn s mch dao ng). Cng thc tnh tc baud : Ch 1v 3 Tc baud Tn s mch dao ng 32x[65536-(RCAP2H,RCAP2L)]


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Trong (RCAP2H , RCAP2L)l ni dung ca RCAP2H v RCAP2L c ly bng 1 s nguyn khng du 16bit.

Hnh 1.19: B nh thi 2 trong ch my pht tc baud B nh thi 2trong ch 1 my phat tc baud c minh ha bng hnh 1.19 .Hnh minh ha ny ch ng nu RCLK hocTCLK=1trong T2CON. Ch rng 1 rollover trong TH2 khong thit lp TF2 v s khng to ra ngt. Cng lu rng nu EXEN2 c thit lp ,1 chuyn i 1 0 trong T2EX s thit lp EXF2 nhng khng np li t (RCAP2H , RCAP2L) ti (TH2 ,THL) . Nh vy khi b nh thi 2 c s dng trong ch my pht tc baud , T2EX c th c dung nh mt ngt ngoi. Ch rng khi b nh thi 2 ang chy (TR2 = 1) nh mt b nh thi trong ch to tc baud , TH2 hoc TL2 khng c c t hoc ghi ti b nh thi 2 . Di nhng iu kin , b nh thi gia tng mi trng thi thi gian , v kt qu ca vic c hay ghi khng th chnh xc . Thanh ghi RCAP2 c th c nhng khng th ghi ,bi v vic ghi c th chng ln vic np li gy ra cc li np li , ghi . B nh thi phi c tt trc khi truy cp b nh thi 2 hoc cc thanh ghi RCAP2 Programmable Clock Out Mt xung clock chu k nhim v 50% c th c lp trnh i ra trn P1.0 , nh c ch ra trn hnh 14-1 . Chn ny thm vo tr thnh mt chn nhp /xut thng thng ,c hai chc nng xen k nhau . N c th c lp trnh ti u vo ca xung clock ngoi cho b m /nh thi 2 hoc ti u ra ca xung clock chu k nhim v 50% trong di t 61Hz n 4MHz cho tn s hot ng l 16MHz


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nh cu hnh b m /nh thi 2nh l my to xung clock ,bit C/T2 (T2CON.1) phi c xo v bit T2OE (T2MOD.1) phi c thit lp . Bit TR2 (T2CON.2) bt u v dng b nh thi . Tn s xung nhp ra ph thuc tn s mch dao ng v gi tr np li ca cc thanh ghi thu nhn ca b nh thi 2 (RCAP2H ,RCAP2L) c tnh theo phng trnh sau : Tn s xung nhp ra =Tn s mch dao ng/{4x[65536-(RCAP2H,RCAP2L)]} Trong ch xung nhp ra ,b nh thi 2 roll-overs s khng to ra ngt . Phng thc ca ch ny tng t khi b nh thi 2 c s dng nh mt my pht tc baud .C th ng thi s dng b nh thi 2 nh mt my pht tc baud v mt my pht xung clock . Tuy nhin ch rng cc tn s tc baud v xung clock ra khng th xc nh c lp t mt thit b khc , chng s dng c RCAP2H v RCAP2L . Hnh minh ho: B nh thi 2 trong ch xung nhp ra

Ngt AT89C55WD c tt c 6 vector : 2 ngt ngoi (INT0 ,INT1), 3 ngt nh thi (b nh thi 0,1 v 2) v 3 ngt cng ni tip . Nhng ngt ny c ch ra trong hnh minh ho 15-1 . Bng 15-1 . Thanh ghi cho php ngt(IE) EA ET2 ES ET1 EX1 ET0 EX0

Bit cho php =1 cho php ngtB mn Cng ngh iu khin t ng

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Bit cho php =0 v hiu ha ngt Mi ngun ngt c th c cho php hoc khng cho php ring l bng cch thit lp hoc xo mt bit trong thanh ghi. chc nng c bit IE . IE cng cha mt bit v hiu ho chung ,EA, n v hiu ho tt c cc ngt trc . Ch rng bng 5 ch ra rng bit v tr IE.6 c b sung . Phn mm ngi dng khng nn ghi 1 ti bit v tr , n c th c s dng trong cc sn phm AT89 tng lai . Ngt b nh thi 2 c to bi vng OR ca cc bit ca TF2 v EXF2 trong thanh ghi T2CON . Khng c no c xo bng phn cng khi s phc v thng l Biu tng V tr EA IE.7 Chc nng V hiu ha mi ngt. Nu EA= 0, khng c ngt no c tha nhn. Nu EA= 1, mi ngun ngt cho php hay v hiu ha bng cch thit lp hoc xa bit cho php ca n IE.6 D tr. ET2 IE.5 Bit cho php ngt b nh thi 2. ES IE.4 Bit cho php ngt port ni tip. ET1 IE.3 Bit cho php ngt b nh thi 1. EX1 IE.2 Bit cho php ngt ngoi . ET0 IE.1 Bit cho php ngt b nh thi 0 . EX0 IE.0 Bn ngoi gin on 0 mu c th. Phn mm ngi dng khng bao gi nn ghi 1S ti cc bit d tr , bi v chng c th s dng trong nhng sn phm AT89 tng lai. c vector ho . Trong thc t ,s phc v thng l c th phi xc nh TF2 hay EXF2 to ra ngt ,v bit phi c xa trong phn mm. Cc c TF0,TF1ca b nh thi 0 v b nh thi 1 c thit lp ti S5P2 ca chu k m cc b nh thi tn b nh. Cc gi tr ny c lm trn bng bng circuitry trong chu k tip theo.Tuy nhin,c TF2 ca b nh thi 2li c thit lp ti S2P2 v c lm trn trong cng chu k vi chu k b nh thi trn. 16. Cc c tnh ca mch dao ng XTAL1v XTAL2 ln lt l u vo v u ra ca 1 b khuch i o c cu hnh lm mch dao ng trn chip, c ch ra trong hnh minh ha 18-1 . Hoc 1 tinh th thch anh hoc mch cng hng gm c s dng. iu khin thit b ny t 1 ngun xung clock bn ngoi,XTAL2 c th ni ( khng kt ni )trong khi XTAL1 c iu khin.(nh hnh 18-2).Khng c yu cu no v chu k nhim v ca tn hiu xung clock bn ngoi ,v u vo ny n c mch to xung clock bn trong chip phi i qua 1 flip-flop chia-2,nhng cc chi tit k thut v thi gian mc cao v mc thp , in p cc tiu v cc i phi c xem xt .B mn Cng ngh iu khin t ng

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Ch Ngh Trong ch ngh ,CPU t chnh n vo trng thi ng trong khi tt c cc ngoi vi bn trong chip vn tch cc. Ch ny c iu khin bi phn mm . Ni dung ca RAM trn chip v ca tt c cc thanh ghi chc nng c bit vn khng i trong thi gian tn ti ch ny.Ch ngh c kt thc bi 1 ngt bt k no c php hoc bng Reset cng. Ta cn lu rng khi ch ngh c kt thc bi 1 reset cng ,chip vi iu khin s tip tc bnh thng vic thc thi chng trnh t ni chng trnh b tm dng ,trong vng 2 chu k my trc khi gi thut reset mmm nm quen iu khin. ch ngh ,phn cng trn chip cm truy xut RAM ni dung nhng cho php truy xut cc chn ca cc port. trnh kh nng c 1 thao tc ghi khng mong mun n 1 chn port khi ch ngh kt thc bng reset ,lnh tip theo lnh yu cu ch ngh khng nn l lnh ghi n chn port hoc n b nh ngoi. Ch ngun gim Trong ch ngun gim ,mch dao ng ngng hot ng v lnh yu cu ch ngun gim l lnh sau cng c thc thi.RAM trn chip v cc thanh ghi chc nng c bit vn duy tr gi tr ca chng cho n khi ch ngun gim kt thc . Ra khi ch ngun gim bng reset cng hoc bng 1 ngt c php.Reset xc nh li cc thanh ghi chc nng c bit nhng khng thay i RAM trn chip.Vic reset khng nn xy ra trc khi Vcc c khi phc li mc in p bnh thng v phi ko di trng thi tch cc ca chn reset lu cho php mch dao ng hot ng tr li v t trng thi n nh .

Bng trng thi ca cc chn ngoi trong ch ngun gim, ch ngh Ch Ngh Ngh Ngun gim Ngun gim B nh Chng trnh Bn trong Bn ngoi Bn trong Bn ngoi ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 D liu Th ni D liu Th ni PORT1 D liu D liu D liu D liu PORT2 D liu a ch D liu D liu PORT3 D liu D liu D liu D liu


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Cc h vi x l th h mi

1.3 VI IU KHIN AT89C54/58 1.3.1 M t SST89C54 v SST89C58 l thuc h FlashFlex51 vi mch iu khin 8-bit. SST89C54/58 cng tp lnh mnh v s dng cng kiu kin trc, thch hp vi tiu chun thit b vi iu khin 8xC5x . SST89C54/58 c 20/ 36 KB ca b nh chng trnh EEPROM trong chp tch hp. Phn chnh ca khi SupperFlash 0 chim 16/32 KB (ca) khng gian nh chng trnh bn trong v khi SupperFlash chim gi 4 KB ca SST89C54/58 trong khng gian nh chng trnh bn trong. 4Kbyte ca khi SuperFlash th hai c th c sp xp v tr cao hay thp 64 KByte; n c th cng c n di b m chng trnh v s dng d liu nh mt EEPROM c lp. Khi b nh Flash c th c lp trnh qua mt tiu chun 87C5x OTP EPROM ph hp vi mt b tip hp c bit v vi chng trnh cho nhng thit b SST89C54/58.

Hnh 1.20. S khi SST89C54/58

Hnh 1.21. S chn ra SST89C54/58


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Cc h vi x l th h mi

1.3.2.T chc b nh SST89C54/58 c vng a ch ring bit cho b nh chng trnh d liu. B nh chng trnh C hai khi b nh truy cp nhanh bn trong SST89C54/58. Khi b nh block 0 c 16/32 Kbyte v chim gi vng a ch 0000H n 3FFFH/7FFFH. Khi b nh truy cp nhanh th hai l Block 1 c 4 Kbyte v chim gi vng a ch F000H ti FFFFH. 16/32 K khi nh truy cp nhanh x8 c t chc nh 128/256 ging nh khu vc a ch t A15 n A17. Mi khu vc cha ng 2 hng vi a ch hng t A15 n A6. Mi hng c 64 byte vi a ch byte t A5 n A0

`

Hnh 1.22. T chc thnh cc Sector

Khi cho php thao tc m bn trong (EA#=1), 16/32 khi nh truy cp nhanh u tin lun hin my m chng trnh m lnh. Hnh 5 v hnh 6 cho thy s t chc b nh chng trnh cho SST89C54/58


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Cc h vi x l th h mi

Hnh 1.23. T chc chng trnh b nh SST89C54/58

Khi cho php thao tc m bn trong(EA#=1), khi b nh 4Kbyte th 2 truy cp nhanh cho m lnh, khi b nh th 2 lun lun c th tip cn nhng thanh ghi ca hm th: SFCM, SFCF, SFAL, SFAH, SFDT v SFST. Khi no bit 7 ca cu hnh hm th SupperFlash (SFCF[7]), SFR nh a ch B1H, trc ph ca khi 4Kbyte s hin r b m chng trnh. Sp xp b nh SST89C54/58 cho php sp xp mt cch c bit, ngi s dng c th sp xp b nh Flash vo bn trong cc rnh t, v th c th ngn chn Block 0 ca b nh Flash c chng trnh ho. T c th ngn chn Block 0 chim gi vng a ch chng trnh bn phi ca 8051 ti v tr cc vector ngt c tr, nhng vector ngt s khng sn c khi Block 0 ang c chng trnh ha. SST89C54/58 cung cp 4 tu chn ca s sp xp b nh. Khi no 4Kbyte mc thp c nh x, bt k s truy nhp chng trnh bn trong, a ch logic s b hn ch t 0000H n 0FFFH s c 4 gi tr ln nht ca a ch thnh bit 1, mt ln na s truy cp li c gi ti F000H FFFFH. Block 1 cng c th truy cp n F000H FFFFH. Hnh 7 v 8 biu din s sp xp li t chc b nh chng trnh ca SST89C54/58.


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Hnh 1.24. SST89C54/58 T chc li b nh chng trnh

Hnh 1.25. SST89C54/58 sp xp li chng trnh t chc b nh

B nh d liu SST89C54/58 c 256x8 bit ca b nh RAM v 64Kbyte d liu b nh ngoi

Hnh 1.26. T chc nh trong thanh ghi chc nng ca Flashflex51


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Cc h vi x l th h mi

Thanh ghi chc nng c bit c a SST89C54/58 Bng 3A: CPU related SFRs K hiu M t Ch dn a ch E0H a ch bit, k hiu hoc thay th chuyn hm Khi to Gi tr LSB 00H 00H 00H OV F1 P 07H 00H 00H EX 1 PX 1 GF 0 ET0 EX0 PT0 PD 40H

Bnh c quy B* ng k B F0H PSW* T tnh D0 trng H CY A chng C trnh SP Ngn xp 81H con tr DPL im d 82H liu thp 0 DPH im d 83H liu cao 0 IE* Cho php A8 ngt H EA IP* u tin B8H ngt PCON iu khin 87H ngun SM OD Bng 3B: Lp trnh b nh Flash SFRs K hiu SFST M t Ch dn a ch B6H

ACC*

ACC[7:0] B[7:0] F0 RS RS0 1

SP[7:0] DLP[7:0] DHP[7:0] ET 2 PT 2 ES 0 PS ET 1 PT 1 GF 1

PX0 xx000000 b IDL 0xxx0000 b

a ch bt, k hiu hoc thay th chuyn hm

Khi to gi tr LSB

Tnh SECD - Busy Flash_busy - xxx00000B trng Super Flash SFCF Cu B1H VIS IAPEN - MAP_EN 000000xxB hnh Super Flash SFCM Lnh B2H FIE FCM 00H Super Flash SFDT D B5H Thanh ghi d liu SuperFlassh 00H liu SuperB mn Cng ngh iu khin t ng

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Flash SFAL a B3H ch thp Super Flash SFAH a B4H ch cao Super FLash

SuperFlash sp t thanh ghi a ch thp t A7-A0(SFAL)

00H

SuperFlash sp t thanh ghi a ch cao t A15 A8 (SFAH)

00H

Thanh ghi trng thi SuperFlash (SFST) ( Thanh ghi ch c) V tr 0B6H K hiu SECD2 SECD1 SECD0 7 6 5 4 SECD2 SECD1 SECD0 3 Busy 2 1 Flash_busy 0 -

Chc nng Kim tra bit 1 Kim tra bit 2 Kim tra bit 3 Chuyn ti bng 8 cho tu chn kim tra kha BUSY Truyn lot chng trnh hon thnh kim sot vng bit 1: Thit b bn vi thao tc flash 0: Thit b sn sng cho thao truyn lot chng trnh tip theo Flash_busy Hon thnh thao tc kim tra Flash 1: Thit b bn vi thao tc flash 0: Thit b hon thnh cc lnh cui cng, bao gm c truyn lot chng trnh Thanh ghi lnh SuperFlash (SFCM) v tr 0B2H K hiu FIE 7 6 5 FCM5 4 FCM4 3 FCM3 2 FCM2 1 FCM1 0 FCM0

FIE FCM6

FCM[6:0]

Chc nng Flash cho php ngt 1: INT1# hon thnh thao tc gn tn hiu IAP INT1# khng cho php ngt ngoi 0: INT1# khng gn Flash thao tc lnh 000 0001B chp xo


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000 0110B truyn lot chng trnh 000 1011B xo rnh t 000 1100B Kim tra byte 000 1101B Xo khi 000 1110B Byte chng trnh tt c cc s kt hp khc khng c thc hin, v d tr cho s dng trong tng lai. Thanh ghi d liu SuperFlash (SFDT) v tr 0B5H 7 6 5 4 3 2 1 0

Thanh ghi d liu SuperFlash

Thanh ghi a ch SuperFlash (SFAL) v tr 0B3H 7 6 5 4 3 2 1 0

Thanh ghi a ch thp SuperFlash

Thanh ghi a ch SuperFlash( SFAH) V tr 0B4H 7 6 5 4 3 2 1 0

Thanh ghi a ch cao SuperFlash WDRE WDTS WDT SWDT X0H

Bng 3C: thit b bm gi SFRs WDTC iu C0H - - khin thit b bm gi WDTD Thit b 86H WDRL bm gi d liu/ np li

00H


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Cc h vi x l th h mi

1.4 VI IU KHIN AT89C2051 1.4.1 c trng ca AT89C2051 Tng thch vi sn phm h MCS_51. Chim 2k bytes ca b nh flass. H thng hot ng trong ngun in 2,7v n 6v. Thao tc trong min tnh tn s:0Hz ti 24MHz. C hai mc xo chng trnh. 128bytes RAM. c 15 ng xut nhp. c 2 b nh thi timer/counter chim 16bit. 6 ngun ngt. knh UART dng lp trnh tun t. LED thit b dn tn hiu ra trc tip. Trong b nh c cha thc so snh tn hiu tng t 1.4.2 M t AT89C2051 l mt h vi tnh 8bit_n chp CMOS c hiu xut cao.cng xut ngun tiu th thp v c 2 k bytes b nh ROM FLASH c th Xo/lp trnh c.chp ny sn xut da vo cng ngh b nh ko mt ni dung c tch hp cao ca ATMEL. AT89C2051 cng thch hp vi cc lnh v cc chn ra ca chun cng nghip MCS_51 flash trn chp cho php b nh chng trnh c lp trnh lp li trn h thng hoc bng b lp b nh khng mt ni dung qui c.bng cch kt hp cpu linh hot 8bit vi Flash trn mt chp mnh p ng cho ta nhng ng dng diu khin AT89C2051 thit k vi logic tnh cho hot ng c tn s gim xung 0 v h tr hai ch tit kim nng lng. N c cc ch nh ch ngh dng CPU


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Cc h vi x l th h mi

trong khi vn cho php RAM,cc b nh thi/m,port ni tip v h thng ngt tip tc hot ng. Ch ngun gim duy tr ni dung trong RAM khng cho mch dao ng cung cp xung clock nhm v hiu ho Cc hot ng khc ca chp cho n khi c reset phn cng tip theo. Cu hnh chn ra AT89C2051:


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Cc h vi x l th h mi

CHNG 2. H VI IU KHIN AVR AT90S8535 2.1 Cc c tnh AVR -Cu trc RISC(reduced instruction set computer:my tnh dng tp lnh rt gn) hiu nng cao- ngun in thp 118 lnh mnh m -a s thc hin theo ng h chu k n 32 x 8 thanh ghi lm vic ch a dng Ln ti 8 triu lnh mi giy thng lng 8 MHZ 8k bytes trong h thng c th chng trnh ho mt cch nhanh chng B giao din ni tip SPI trong h thng lp trnh Kh nng chu ng : 1,000 vit/xo b nhng chu trnh 512 Bytes EEPROM Kh nng chu ng : 100,000 vit/xo b nhng chu trnh 512 Bytes SRAM bn trong Son chng trnh kho cho cc phn mm an ton 8 knh, 10 bit ADC(Analog to digital conversion:chuyn i tn hiu tng t sang tn hiu s) C th chng trnh ho h thng UART B giao din ni tip SPI ch/khch Hai thit b tnh gi/my m 8 - bit cng vi my m v ch so snh ring bit Mt thit b tnh gi/my m 16 bit cng vi my m, ch so snh v s ginh c ring bit v i 8-, 9-,10- bit PWM Ngi kim sot thit b tnh gi c th lp trnh vi vic bt b dao ng chp My so snh tng t trn chp Mch xc lp li ngun in ng h thi gian thc(RTC) cng vi b dao ng v kiu my m ring bit Cc ngun ngt bn trong v bn ngoi Ba ch ng(tnh) : ch nhn ri, ch tit kim in, ch ngt in.


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Tiu th in 4 MHz, 3V, 20C -Hot ng : 6.4 mA -Ch nhn ri: 1.9 mA -Ch ngt in:

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