Vivado Design Suite Tcl

UG835 (v2015.4) 2015 11 18

2015.4

get_gtbanksget_gtbanksget_gtbanks : get_iobanks -filter {BANK_TYPE == BT_MGT}

open_netlist_designopen_netlist_designopen_netlist_design : link_design

read_vcdread_vcdread_vcd :

2015.4

config_webtalkiphys_opt_designpr_analyzerread_iphys_opt_tclregister_procedure_information

write_iphys_opt_tcl

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1

Vivado Tcl

Tcl (Tool Command Language) Vivado Tcl

SDC (Synopsys Design Constraints)

SDC Synopsis Synplify FPGA

Tcl

Tcl

Tcl

Vivado Tcl

: Tcl Vivado Design Suite Tcl Tcl

Vivado Design Suite

Vivado Design Suite

Tcl

Tcl Vivado

IDE Vivado Design Suite

: (UG892)

Tcl

Tcl Tcl

Vivado IDE Vivado Design Suite Tcl Tcl

Vivado IDE [Tcl Console] Tcl

Vivado Design Suite Tcl Tcl

Vivado IDE Tcl

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1 :

Vivado Design Suite Tcl Linux Windows

vivado -mode tcl

: Windows [] [] [Xilinx Design Tools] [Vivado yyyy.x] [Vivado yyyy.x Tcl Shell] (yyyy.x Vivado )

Tcl Tcl Vivado Design Suite : Tcl

(UG894) Vivado Tcl Vivado Design

Suite : (UG888)

Tcl

Tcl Vivado

Linux Windows

vivado -mode batch -source

Vivado Design Suite Tcl Tcl

Tcl

Vivado IDE

GUI Windows Linux Vivado IDE Vivado IDE Vivado

Design Suite : Vivado IDE (UG893)

Vivado IDE Vivado

Vivado

Windows OS [] [] [Xilinx Design Tools] [Vivado 2015.x] [Vivado

2015.x]

: Windows Vivado IDE

Linux OS

vivado -or- vivado -mode gui

Vivado

vivado -help

Vivado Vivado Design Suite Tcl Tcl start_gui Vivado IDE

Vivado IDE Vivado Tcl Vivado IDE stop_gui

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1 :

Tcl

Vivado vivado.logvivado.jou Tcl Tcl

: vivado_.backup.jou Vivado Tcl

Tcl

Tcl help Tcl

help : Tcl

help

File I/O

help -category category :

help -category object

Tcl

help pattern :

help get_*

get_ Tcl

help command :

help get_cells

get_cells

help -args command :

help -args get_cells

help -syntax command :

help -syntax get_cells

Tcl

Tcl

: Vivado init.tcl Vivado init.tcl

Vivado 2 Tcl

1. : installdir/Vivado/version/scripts/init.tcl

2. :

Windows 7 : %APPDATA%/Roaming/Xilinx/Vivado/init.tcl

Linux : $HOME/.Xilinx/Vivado/init.tcl

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1 :

:

installdir : Vivado Design Suite

init.tcl Vivado

init.tcl

Vivado

init.tcl

init.tcl

Vivado Design Suite init.tcl init.tcl

init.tcl Tcl Vivado Tcl init.tcl Tcl

source path_to_file/file_name.tcl

: Vivado Design Suite -init vivado -help

Tcl

Tcl 1 GUI Vivado

(IDE) Tcl [Tools] [Run Tcl Script]

Tcl

source file_name

Tcl Vivado IDE

IDE

OS

(kill)

Tcl help sourcesource

Tcl.pre Tcl.post

Tcl run run

(tcl.pre) (tcl.post) Tcl run Tcl

Tcl

Tcl Tcl

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1 :

: Tcl

(phys_opt_design )

: tcl.pre tcl.post run // run DIRECTORY Tcl

get_property DIRECTORY [current_project] get_property DIRECTORY [current_run]

Tcl Vivado Design Suite : Tcl

(UG894)

Tcl

Tcl OS Linux (/)

Vivado Design Suite Tcl

eval

Tcl Tcl

Tcl eval Tcl

help -category 1

help -category ipflow

set cat "ipflow"

:

set : Tcl

cat :

"ipflow" :

Tcl

eval help -category $cat

set cat "category ipflow" eval help $cat

("") ({})

set runblocksOptDesignOpts { -sweep -retarget -propconst -remap } eval opt_design $runblocksOptDesignOpts

Tcl help evaleval

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1 :

Tcl Tcl

( {} )

: [] Tcl () 4

Vivado

add_wave {bus[4]}

Tcl

add_wave bus(4)

Verilog : Verilog Verilog Verilog

(\)

Tcl

: Tcl

VHDL

my wire Vivado

add_wave {\my wire }

:

Verilog Tcl

w Vivado

Vivado

add_wave {\w }

w

add_wave w

VHDL : VHDL Tcl (\)

( \} )Tcl VHDL

Tcl \my sig\

add_wave \\my\ sig\\

: 2

Vivado Design Suite Tcl

command [optional_parameters] required_parameters

( _ ) - - -

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1 :

get_

set_

report_

get_cells -help

get_cells

Description:

Get a list of cells in the current design

Syntax:

get_cells [-hsc ] [-hierarchical] [-regexp] [-nocase] [-filter ]

[-of_objects ] [-match_style ] [-quiet] [-verbose]

[]

Returns:

list of cell objects

Usage:

Name Description

----------------------------

[-hsc] Hierarchy separator

Default: /

[-hierarchical] Search level-by-level in current instance

[-regexp] Patterns are full regular expressions

[-nocase] Perform case-insensitive matching (valid only when -regexp

specified)

[-filter] Filter list with expression

[-of_objects] Get cells of these pins, timing paths, nets, bels, sites

or drc violations

[-match_style] Style of pattern matching

Default: sdc

Values: ucf, sdc

[-quiet] Ignore command errors

[-verbose] Suspend message limits during command execution

[] Match cell names against patterns

Default: *

Categories:

SDC, XDC, Object

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1 :

Tcl Tcl Vivado

OS exec OS

Tcl

Tcl 0

1

Tcl Tcl catch catch // Tcl

Vivado Tcl TCL_OK TCL_ERROR Tcl

$ERRORINFO

$ERRORINFO Tcl

puts $ERRORINFO

Tcl (procs.tcl) (loads)

5

Line 1: Vivado % source procs.tcl

Line 2: Vivado% loads

Line 3: Found 180 driving FFs

Line 4: Processing pin a_reg_reg[1]/Q...

Line 5: ERROR: [HD-Tcl 53] Cannot specify -patterns with -of_objects.

Line 6: Vivado% puts $errorInfo

Line 7: ERROR: [HD-Tcl 53] Cannot specify -patterns with -of_objects. While executing

"get_ports -of objects $pin" (procedure "my_report" line 6) invoked from within procs.tcl

Tcl catch puts $errorInfo Tcl puts $errorInfo

6 puts $errorInfo7

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1 :

Tcl

Vivado Design Suite Tcl

Vivado

Vivado Design Suite

LUTI/O RAMDSP

I/O FPGA

1

DCMPLLMMCM UCF

TIMESPEC PERIOD

Tcl get_

get_

get_cells */inst_1

inst_1

get_cells -hierarchical inst_1

inst_1

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1 :

help get_cells

get_cells -help

get_property property_name object

lib_cell UniSim

get_property lib_cell [get_cell inst_1]

report_property

report_property [get_cells inst_1]

bel OLOGICE1.OUTFF string

class cell string

iob TRUE string

is_blackbox 0 bool

is_fixed 0 bool

is_partition 0 bool

is_primitive 1 bool

is_reconfigurable 0 bool

is_sequential 1 bool

lib_cell FD string

LOC OLOGIC_X1Y27 string

name error string

primitive_group FD_LD string

primitive_subgroup flop string

site OLOGIC_X1Y27 string

type FD & LD string

XSTLIB 1 bool

UCF HDL

Tcl set_property

set_property loc OLOGIC_X1Y27 [get_cell inst_1]

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1 :

get_*

FD

get_cells * -hierarchical -filter "lib_cell == FD"

=~

get_cells * -hierarchical -filter "lib_cell =~ FD*"

OR (||) AND (&&)

get_cells * -hierarchical -filter {lib_cell =~ FD* && loc != ""}

: " " { } Tcl loc

get_cells get_sites Tcl Tcl

foreach_in_collection Vivado Design Suite lsortlsearchforeach Tcl

get_* Tcl Tcl

get_* Vivado Tcl

Vivado Design Suite

tcl.collectionResultDisplayLimit get_cells get_sites Tcl (...) tcl.collectionResultDisplayLimit set_param

: Vivado Design Suite 2 tcl.collectionResultDisplayLimitin ni in ni in not-in in ni lsearchlsort

if {[lsearch -exact [get_cells *] $cellName] != -1} {...}

get_* Tcl

set allSites [get_sites]

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1 :

tcl.collectionResultDisplayLimit

%set allCells [get_cells -hierarchical]

DataIn_pad_0_i_IBUF[0]_inst DataIn_pad_0_i_IBUF[1]_inst \

DataIn_pad_0_i_IBUF[2]_inst DataIn_pad_0_i_IBUF[3]_inst \

DataIn_pad_0_i_IBUF[4]_inst ...

%llength $allCells

42244

%lindex $allCells end

wbArbEngine/s4/next_reg

get_cells -hierarchical $allCells 4

: join get_* Tcl (\n) (\t) (" ")

join [get_parts] " "

get_* -of

get_pins -of [get_cells inst_1]

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1 :

get_* -of Tcl

Vivado Design Suite Tcl

(UG912)

GUI

INFOWARNING

CRITICAL_WARNINGERROR

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1 :

INFO

INFO: [HD-LIB 1] Done reading timing library

Tcl Tcl

Tcl

Tcl Tcl

catch

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2

Tcl ()

Bitgen

Board ()

ChipScope

CreatePeripheral ()

DRC

Debug ()

FileIO ()

Floorplan ()

GUIControl (GUI )

Hardware ()

IPFlow (IP )

IPIntegrator (IP )

Memory ()

Netlist ()

Object ()

PinPlanning ( )

Power ()

Project ()

PropertyAndParameter ()

Report ()

SDC

Simulation ()

SysGen (System Generator)

Tcl

Timing ()

ToolLaunch ()

Tools ()

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2 : Tcl ()

Waveform ()

XDC

XPS

projutils ( )

simulation ()

synthesis ()

user-written ()

xilinxtclstore ( Tcl Store)

Bitgen

calc_config_time

Board ()

apply_board_connection

current_board

current_board_part

get_board_bus_nets

get_board_buses

get_board_component_interfaces

get_board_component_modes

get_board_component_pins

get_board_components

get_board_interface_ports

get_board_ip_preferences

get_board_jumpers

get_board_parameters

get_board_part_interfaces

get_board_part_pins

get_board_parts

get_boards

ChipScope

launch_chipscope_analyzer

launch_impact

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2 : Tcl ()

CreatePeripheral ()

add_peripheral_interface

create_peripheral

generate_peripheral

write_peripheral

DRC

add_drc_checks

create_drc_check

create_drc_ruledeck

create_drc_violation

delete_drc_check

delete_drc_ruledeck

get_drc_checks

get_drc_ruledecks

get_drc_violations

remove_drc_checks

report_drc

reset_drc

reset_drc_check

Debug ()

apply_hw_ila_trigger

connect_debug_port

create_debug_core

create_debug_port

delete_debug_core

delete_debug_port

disconnect_debug_port

get_debug_cores

get_debug_ports

implement_debug_core

report_debug_core

write_debug_probes

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2 : Tcl ()

FileIO ()

config_webtalk

encrypt

generate_mem_files

infer_diff_pairs

pr_analyzer

pr_verify

read_bd

read_checkpoint

read_csv

read_edif

read_ip

read_mem

read_saif

read_schematic

read_twx

read_verilog

read_vhdl

read_xdc

write_bd_layout

write_bitstream

write_bmm

write_bsdl

write_cfgmem

write_checkpoint

write_csv

write_debug_probes

write_edif

write_ibis

write_inferred_xdc

write_mem_info

write_schematic

write_sdf

write_verilog

write_vhdl

write_xdc

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2 : Tcl ()

Floorplan ()

add_cells_to_pblock

create_pblock

delete_pblocks

delete_rpm

get_pblocks

place_cell

place_pblocks

remove_cells_from_pblock

resize_pblock

swap_locs

unplace_cell

GUIControl (GUI )

endgroup

get_highlighted_objects

get_marked_objects

get_selected_objects

highlight_objects

mark_objects

redo

select_objects

show_objects

show_schematic

start_gui

startgroup

stop_gui

undo

unhighlight_objects

unmark_objects

unselect_objects

Hardware ()

add_hw_probe_enum

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2 : Tcl ()

boot_hw_device

close_hw

close_hw_target

commit_hw_mig

commit_hw_sio

commit_hw_sysmon

commit_hw_vio

connect_hw_server

create_hw_axi_txn

create_hw_bitstream

create_hw_cfgmem

create_hw_sio_link

create_hw_sio_linkgroup

create_hw_sio_scan

create_hw_sio_sweep

current_hw_cfgmem

current_hw_device

current_hw_ila

current_hw_ila_data

current_hw_server

current_hw_target

delete_hw_axi_txn

delete_hw_bitstream

delete_hw_cfgmem

detect_hw_sio_links

disconnect_hw_server

display_hw_ila_data

display_hw_sio_scan

get_cfgmem_parts

get_hw_axi_txns

get_hw_axis

get_hw_cfgmems

get_hw_devices

get_hw_ila_datas

get_hw_ilas

get_hw_migs

get_hw_probes

get_hw_servers

Vivado Design Suite Tcl http://japan.xilinx.com 22UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

get_hw_sio_commons

get_hw_sio_gtgroups

get_hw_sio_gts

get_hw_sio_iberts

get_hw_sio_linkgroups

get_hw_sio_links

get_hw_sio_plls

get_hw_sio_rxs

get_hw_sio_scans

get_hw_sio_sweeps

get_hw_sio_txs

get_hw_sysmon_reg

get_hw_sysmons

get_hw_targets

get_hw_vios

open_hw

open_hw_target

program_hw_cfgmem

program_hw_devices

read_hw_ila_data

read_hw_sio_scan

read_hw_sio_sweep

readback_hw_cfgmem

readback_hw_device

refresh_hw_axi

refresh_hw_device

refresh_hw_mig

refresh_hw_server

refresh_hw_sio

refresh_hw_sysmon

refresh_hw_target

refresh_hw_vio

remove_hw_probe_enum

remove_hw_sio_link

remove_hw_sio_linkgroup

remove_hw_sio_scan

remove_hw_sio_sweep

report_hw_axi_txn

Vivado Design Suite Tcl http://japan.xilinx.com 23UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

report_hw_mig

reset_hw_axi

reset_hw_ila

reset_hw_vio_activity

reset_hw_vio_outputs

run_hw_axi

run_hw_ila

run_hw_sio_scan

run_hw_sio_sweep

run_state_hw_jtag

runtest_hw_jtag

scan_dr_hw_jtag

scan_ir_hw_jtag

set_hw_sysmon_reg

stop_hw_sio_scan

stop_hw_sio_sweep

upload_hw_ila_data

verify_hw_devices

wait_on_hw_ila

wait_on_hw_sio_scan

wait_on_hw_sio_sweep

write_hw_ila_data

write_hw_sio_scan

write_hw_sio_sweep

Vivado Design Suite Tcl http://japan.xilinx.com 24UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

IPFlow (IP )

add_peripheral_interface

check_ip_cache

compile_c

convert_ips

copy_ip

create_ip

create_ip_run

create_peripheral

delete_ip_run

extract_files

generate_peripheral

generate_target

get_ip_upgrade_results

get_ipdefs

get_ips

import_ip

open_example_project

read_ip

report_ip_status

reset_target

synth_ip

update_ip_catalog

upgrade_ip

validate_ip

write_peripheral

IPIntegrator (IP )

apply_bd_automation

apply_board_connection

assign_bd_address

close_bd_design

compile_c

connect_bd_intf_net

connect_bd_net

Vivado Design Suite Tcl http://japan.xilinx.com 25UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

copy_bd_objs

create_bd_addr_seg

create_bd_cell

create_bd_design

create_bd_intf_net

create_bd_intf_pin

create_bd_intf_port

create_bd_net

create_bd_pin

create_bd_port

current_bd_design

current_bd_instance

delete_bd_objs

disconnect_bd_intf_net

disconnect_bd_net

exclude_bd_addr_seg

find_bd_objs

generate_target

get_bd_addr_segs

get_bd_addr_spaces

get_bd_cells

get_bd_designs

get_bd_intf_nets

get_bd_intf_pins

get_bd_intf_ports

get_bd_nets

get_bd_pins

get_bd_ports

get_example_designs

get_template_bd_designs

group_bd_cells

include_bd_addr_seg

instantiate_example_design

instantiate_template_bd_design

move_bd_cells

open_bd_design

read_bd

regenerate_bd_layout

Vivado Design Suite Tcl http://japan.xilinx.com 26UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

replace_bd_cell

save_bd_design

ungroup_bd_cells

upgrade_bd_cells

validate_bd_design

write_bd_tcl

Memory ()

implement_mig_cores

Netlist ()

connect_net

create_cell

create_net

create_pin

disconnect_net

get_net_delays

remove_cell

remove_net

remove_pin

rename_cell

rename_net

rename_pin

rename_port

rename_ref

resize_net_bus

resize_pin_bus

tie_unused_pins

Object ()

add_drc_checks

apply_board_connection

check_ip_cache

create_drc_check

Vivado Design Suite Tcl http://japan.xilinx.com 27UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

create_drc_ruledeck

current_board

current_board_part

delete_drc_check

delete_drc_ruledeck

delete_hw_bitstream

filter

find_routing_path

get_bel_pins

get_bels

get_board_bus_nets

get_board_buses

get_board_component_interfaces

get_board_component_modes

get_board_component_pins

get_board_components

get_board_interface_ports

get_board_ip_preferences

get_board_jumpers

get_board_parameters

get_board_part_interfaces

get_board_part_pins

get_board_parts

get_boards

get_cells

get_cfgmem_parts

get_clock_regions

get_clocks

get_debug_cores

get_debug_ports

get_designs

get_drc_checks

get_drc_ruledecks

get_drc_violations

get_files

get_filesets

get_generated_clocks

get_highlighted_objects

Vivado Design Suite Tcl http://japan.xilinx.com 28UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

get_hw_axi_txns

get_hw_axis

get_hw_cfgmems

get_hw_devices

get_hw_ila_datas

get_hw_ilas

get_hw_migs

get_hw_probes

get_hw_servers

get_hw_sio_commons

get_hw_sio_gtgroups

get_hw_sio_gts

get_hw_sio_iberts

get_hw_sio_linkgroups

get_hw_sio_links

get_hw_sio_plls

get_hw_sio_rxs

get_hw_sio_scans

get_hw_sio_sweeps

get_hw_sio_txs

get_hw_sysmons

get_hw_targets

get_hw_vios

get_interfaces

get_io_standards

get_iobanks

get_ip_upgrade_results

get_ipdefs

get_ips

get_lib_cells

get_lib_pins

get_libs

get_macros

get_marked_objects

get_net_delays

get_nets

get_nodes

get_package_pins

Vivado Design Suite Tcl http://japan.xilinx.com 29UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

get_parts

get_path_groups

get_pblocks

get_pins

get_pips

get_pkgpin_bytegroups

get_pkgpin_nibbles

get_ports

get_projects

get_property

get_runs

get_selected_objects

get_site_pins

get_site_pips

get_sites

get_slrs

get_speed_models

get_tiles

get_timing_arcs

get_timing_paths

get_wires

list_property

list_property_value

remove_drc_checks

report_property

reset_drc_check

reset_property

run_state_hw_jtag

runtest_hw_jtag

scan_dr_hw_jtag

scan_ir_hw_jtag

set_property

Vivado Design Suite Tcl http://japan.xilinx.com 30UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

PinPlanning ( )

create_interface

create_port

delete_interface

make_diff_pair_ports

place_ports

remove_port

resize_port_bus

set_package_pin_val

split_diff_pair_ports

Power ()

delete_power_results

power_opt_design

read_saif

report_power

report_power_opt

reset_operating_conditions

reset_switching_activity

set_operating_conditions

set_power_opt

set_switching_activity

Project ()

add_files

add_peripheral_interface

apply_board_connection

archive_project

close_design

close_project

compile_c

copy_ip

create_fileset

create_ip_run

Vivado Design Suite Tcl http://japan.xilinx.com 31UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

create_peripheral

create_project

create_run

create_xps

current_board_part

current_fileset

current_project

current_run

delete_fileset

delete_ip_run

delete_runs

find_top

generate_peripheral

generate_target

get_board_parts

get_boards

get_files

get_filesets

get_ip_upgrade_results

get_ips

get_projects

get_runs

help

import_files

import_ip

import_synplify

import_xise

import_xst

launch_runs

list_targets

lock_design

make_wrapper

move_files

open_checkpoint

open_example_project

open_io_design

open_project

open_run

Vivado Design Suite Tcl http://japan.xilinx.com 32UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

refresh_design

reimport_files

remove_files

reorder_files

report_compile_order

reset_project

reset_run

reset_target

save_constraints

save_constraints_as

save_project_as

set_part

set_speed_grade

synth_ip

update_compile_order

update_design

update_files

wait_on_run

write_hwdef

write_peripheral

write_sysdef

Vivado Design Suite Tcl http://japan.xilinx.com 33UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

PropertyAndParameter ()

create_property

filter

get_param

get_property

list_param

list_property

list_property_value

report_param

report_property

reset_param

reset_property

set_param

set_part

set_property

Report ()

calc_config_time

check_timing

create_drc_violation

create_slack_histogram

delete_clock_networks_results

delete_timing_results

delete_utilization_results

get_msg_config

open_report

report_carry_chains

report_cdc

report_clock_interaction

report_clock_networks

report_clock_utilization

report_clocks

report_config_timing

report_control_sets

report_datasheet

Vivado Design Suite Tcl http://japan.xilinx.com 34UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

report_debug_core

report_design_analysis

report_disable_timing

report_drc

report_environment

report_exceptions

report_high_fanout_nets

report_hw_mig

report_incremental_reuse

report_io

report_operating_conditions

report_param

report_power

report_property

report_pulse_width

report_ram_utilization

report_route_status

report_seu

report_ssn

report_switching_activity

report_synchronizer_mtbf

report_timing

report_timing_summary

report_transformed_primitives

report_utilization

reset_drc

reset_msg_config

reset_msg_count

reset_ssn

reset_timing

set_msg_config

version

SDC

all_clocks

all_inputs

all_outputs

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2 : Tcl ()

all_registers

create_clock

create_generated_clock

current_design

current_instance

get_cells

get_clocks

get_hierarchy_separator

get_nets

get_pins

get_ports

group_path

set_case_analysis

set_clock_groups

set_clock_latency

set_clock_sense

set_clock_uncertainty

set_data_check

set_disable_timing

set_false_path

set_hierarchy_separator

set_input_delay

set_load

set_logic_dc

set_logic_one

set_logic_zero

set_max_delay

set_max_time_borrow

set_min_delay

set_multicycle_path

set_operating_conditions

set_output_delay

set_propagated_clock

set_units

Simulation ()

add_bp

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2 : Tcl ()

add_condition

add_files

add_force

checkpoint_vcd

close_saif

close_sim

close_vcd

compile_simlib

config_compile_simlib

create_fileset

current_scope

current_sim

current_time

current_vcd

delete_fileset

describe

export_ip_user_files

export_simulation

flush_vcd

generate_mem_files

get_objects

get_scopes

get_simulators

get_value

import_files

launch_simulation

limit_vcd

log_saif

log_vcd

log_wave

ltrace

move_files

open_saif

open_vcd

open_wave_database

ptrace

read_saif

relaunch_sim

Vivado Design Suite Tcl http://japan.xilinx.com 37UG835 (v2015.4) 2015 11 18

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2 : Tcl ()

remove_bps

remove_conditions

remove_files

remove_forces

report_bps

report_conditions

report_drivers

report_objects

report_scopes

report_simlib_info

report_values

reset_simulation

restart

run

set_value

setup_ip_static_library

start_vcd

step

stop

stop_vcd

write_sdf

write_verilog

write_vhdl

xsim

SysGen (System Generator)

create_sysgen

make_wrapper

Tcl

report_pipeline_analysis

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2 : Tcl ()

Timing ()

check_timing

config_design_analysis

config_timing_analysis

config_timing_corners

create_slack_histogram

delete_timing_results

get_net_delays

get_timing_arcs

get_timing_paths

report_cdc

report_clock_interaction

report_clock_networks

report_clock_utilization

report_clocks

report_config_timing

report_datasheet

report_design_analysis

report_disable_timing

report_drc

report_exceptions

report_high_fanout_nets

report_pulse_width

report_synchronizer_mtbf

report_timing

report_timing_summary

reset_timing

set_delay_model

set_disable_timing

set_external_delay

update_timing

write_inferred_xdc

write_sdf

write_xdc

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2 : Tcl ()

ToolLaunch ()

get_simulators

launch_chipscope_analyzer

launch_impact

launch_sdk

launch_simulation

Tools ()

iphys_opt_design

link_design

list_features

load_features

opt_design

phys_opt_design

place_design

read_iphys_opt_tcl

register_proc

report_pipeline_analysis

route_design

synth_design

unregister_proc

write_iphys_opt_tcl

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2 : Tcl ()

Waveform ()

add_wave

add_wave_divider

add_wave_group

add_wave_marker

add_wave_virtual_bus

close_wave_config

create_wave_config

current_wave_config

get_wave_configs

open_wave_config

save_wave_config

select_wave_objects

XDC

add_cells_to_pblock

all_clocks

all_cpus

all_dsps

all_fanin

all_fanout

all_ffs

all_hsios

all_inputs

all_latches

all_outputs

all_rams

all_registers

connect_debug_port

create_clock

create_debug_core

create_debug_port

create_generated_clock

create_macro

create_pblock

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2 : Tcl ()

create_property

current_design

current_instance

delete_macros

delete_pblocks

filter

get_bel_pins

get_bels

get_cells

get_clocks

get_debug_cores

get_debug_ports

get_generated_clocks

get_hierarchy_separator

get_iobanks

get_macros

get_nets

get_nodes

get_package_pins

get_path_groups

get_pblocks

get_pins

get_pips

get_pkgpin_bytegroups

get_pkgpin_nibbles

get_ports

get_property

get_site_pins

get_site_pips

get_sites

get_slrs

get_speed_models

get_tiles

get_timing_arcs

get_wires

group_path

remove_cells_from_pblock

reset_operating_conditions

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2 : Tcl ()

resize_pblock

set_case_analysis

set_clock_groups

set_clock_latency

set_clock_sense

set_clock_uncertainty

set_data_check

set_disable_timing

set_external_delay

set_false_path

set_hierarchy_separator

set_input_delay

set_input_jitter

set_load

set_logic_dc

set_logic_one

set_logic_unconnected

set_logic_zero

set_max_delay

set_max_time_borrow

set_min_delay

set_multicycle_path

set_operating_conditions

set_output_delay

set_package_pin_val

set_power_opt

set_propagated_clock

set_property

set_switching_activity

set_system_jitter

set_units

update_macro

XPS

get_board_parts

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2 : Tcl ()

projutils ( )

convert_ngc

export_bd_synth

write_project_tcl

simulation ()

add_bp

add_condition

add_files

add_force

checkpoint_vcd

close_saif

close_sim

close_vcd

compile_simlib

config_compile_simlib

create_fileset

current_scope

current_sim

current_time

current_vcd

delete_fileset

describe

export_ip_user_files

export_simulation

flush_vcd

generate_mem_files

get_objects

get_scopes

get_simulators

get_value

import_files

launch_simulation

limit_vcd

log_saif

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2 : Tcl ()

log_vcd

log_wave

ltrace

move_files

open_saif

open_vcd

open_wave_database

ptrace

read_saif

relaunch_sim

remove_bps

remove_conditions

remove_files

remove_forces

report_bps

report_conditions

report_drivers

report_objects

report_scopes

report_simlib_info

report_values

reset_simulation

restart

run

set_value

setup_ip_static_library

start_vcd

step

stop

stop_vcd

write_sdf

write_verilog

write_vhdl

xsim

synthesis ()

export_bd_synth

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2 : Tcl ()

user-written ()

convert_ngc

export_bd_synth

export_ip_user_files

export_simulation

setup_ip_static_library

write_project_tcl

xilinxtclstore ( Tcl Store)

convert_ngc

export_bd_synth

export_ip_user_files

export_simulation

setup_ip_static_library

write_project_tcl

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3

Tcl () SDC Tcl

add_bp

HDL

add_bp [-quiet] [-verbose]

[-quiet]

[-verbose]

Simulation ()

HDL

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3 : Tcl ()

report_bps remove_bps

: Tcl

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : HDL

() : HDL ()

HDL

add_bp C:/Data/ug937/sources/sinegen.vhd 137

remove_bps

report_bps

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3 : Tcl ()

add_cells_to_pblock

Pblock

add_cells_to_pblock [-top] [-add_primitives] [-clear_locs] [-quiet] [-verbose] [...]

[-top] cells -add_primitivescells -top

[-add_primitives] Pblock

[-clear_locs]

[-quiet]

[-verbose]

Pblock

[] -top cells -top

Floorplan ()XDC

Pblock Pblock

resize_pblock Pblock FPGA resize_pblock Pblock

Pblock remove_cells_from_pblock

-top () : Pblock Pblock -top

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3 : Tcl ()

-add_primitives () : Pblock

Pblock

: -top

-clear_locs () : Pblock LOC

Pblock

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

: Pblock

: Pblock 1

: -top

pb_cpuEngine Pblock cpuEngine

create_pblock pb_cpuEngine

add_cells_to_pblock pb_cpuEngine [get_cells cpuEngine/*] -add_primitives -clear_locs

get_pblocks

place_pblocks

remove_cells_from_pblock

resize_pblock

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3 : Tcl ()

add_condition

Tcl

add_condition [-name ] [-radix ] [-quiet] [-verbose]

[-name] () (condition)

[-radix] defaultdecbinocthexunsignedascii

[-quiet]

[-verbose]

Simulation ()

Tcl

-name () :

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3 : Tcl ()

-radix () : defaultdecbinocthexunsignedascii

: dec 10 unsigned

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : () (==) (!=) = AND (&&) OR (||)

() : () Tcl Tcl ({ }) runrestartstep Tcl Tcl Tcl

({ }) ("")

Vivado Design Suite : Tcl (UG894)

resetLow ( Low )

add_condition -name resetLow {/testbench/reset == 0 } {

puts "Condition Reset was encountered at [current_time]. Stopping simulation."

stop }

add_force clk reset myProc Tcl Low

myProc

proc myProc {} {

add_force clk {0 1} { 1 2} -repeat_every 4 -cancel_after 500

add_force reset 1

run 10 ns

remove_force force2

puts "Reached end of myProc"

}

add_condition -radix unsigned /top/reset==0 myproc

add_force

stop

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3 : Tcl ()

add_drc_checks

DRC

add_drc_checks [-of_objects ] [-regexp] [-nocase] [-filter ]-ruledeck [-quiet] [-verbose] []

drc_check

[-of_objects] drc_ruledeck drc_check

[-regexp]

[-nocase] / (-regexp)

[-filter]

-ruledeck DRC

[-quiet]

[-verbose]

[] drc_check *

DRCObject ()

DRC (drc_ruledeck)

I/O

report_drc create_drc_ruledeck

get_drc_ruledecks report_drc

create_drc_check get_drc_ruledecks

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3 : Tcl ()

remove_drc_checks

: DRC set_property IS_ENABLED false report_drc reset_drc_check

-of_objects () : drc_ruledeck

: -of_objects get_* (get_cellsget_pins ) -of_objects

-regexp () : -filter Tcl

.*

http://www.tcl.tk/man/tcl8.5/TclCmd/re_syntax.htm

: Tcl regexp Tcl http://www.tcl.tk/man/tcl8.5/TclCmd/regexp.htm

-nocase () : /-regexp

-filter () :

report_property list_property

.*

:

(*) ""

(==) (!=) (=~) (!~)

= AND (&&) OR (||)

RESET

get_pins * -filter {DIRECTION == IN && NAME !~ "*RESET*"}

(bool) True False

-filter {IS_PRIMITIVE && !IS_LOC_FIXED}

-ruledeck () :

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3 : Tcl ()

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : (*)

: ( { } ) ("") 1

project_rules

add_drc_checks -ruledeck project_rules {*DCI* *BUF*}

placer+ placer_checks

placer+

create_drc_ruledeck placer+

add_drc_checks -of_objects [get_drc_ruledecks placer_checks] -ruledeck placer+

add_drc_checks -ruledeck placer+ *IO*

add_drc_checks -filter {SEVERITY == Warning} -ruledeck warn_only

create_drc_check

create_drc_ruledeck

get_drc_checks

get_drc_ruledecks

list_property

remove_drc_checks

report_drc

report_property

reset_drc_check

set_property

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3 : Tcl ()

add_files

add_files [-fileset ] [-norecurse] [-copy_to ] [-force][-scan_for_includes] [-quiet] [-verbose] [...]

[-fileset]

[-norecurse]

[-copy_to]

[-force] -copy_to

[-scan_for_includes] RTL

[-quiet]

[-verbose]

[] -scan_for_includes

Project ()Simulation ()

1 1

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3 : Tcl ()

Vivado Design Suite

PATH_MODE Vivado

Vivado Design Suite

(UG912)

: 1 1 add_files

add_files {file1 file2 file3 ... fileN}

Vivado add_files

read_xxx

: read_xxx Vivado Design Suite : (UG892)

add_files import_files

-fileset () :

-norecurse () :

-copy_to () :

-force () : -copy_to

-scan_for_includes () : Verilog include include

-quiet () : TCL_OK

:

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3 : Tcl ()

-verbose () :

: set_msg_config

() : 1

:

rtl.v

add_files rtl.v

rtl.v

top.xdc constrs_1 project_1

add_files -fileset constrs_1 -quiet c:/Design/top.xdc c:/Design/project_1

-quiet

-norecurse project_1

IP

add_files -norecurse C:/Data/ip/c_addsub_v11_0_0.xci

: IP import_ip

char_fifo IP

# Read top-level EDIF and IP DCP

read_edif ./sources/wave_gen.edif

add_files ./my_IP/char_fifo/char_fifo.xci

: IP add_files read_ip (DCP) IP

System Generator DSP

add_files C:/Data/model1.mdl

: System Generator DSP create_sysgen

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3 : Tcl ()

create_sysgen

import_files

import_ip

read_ip

read_verilog

read_vhdl

read_xdc

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3 : Tcl ()

add_force

add_force [-radix ] [-repeat_every ] [-cancel_after ] [-quiet][-verbose] ...

force

[-radix] defaultdecbinocthexunsignedascii

[-repeat_every]

[-cancel_after]

[-quiet]

[-verbose]

force

force { [ ] }

Simulation ()

add_force Verilog force/release -cancel_after remove_forcesHDL

: HDL Verilog force/release Tcl add_force Tcl force Verilog force HDL

force

force remove_forces Tcl

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3 : Tcl ()

-radix () : defaultdecbinocthexunsignedascii HDL 2 (bin)

-repeat_every () : add_force force

: { }

-cancel_after () : current_time force remove_forces

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : 1 HDL get_objects

() : HDL 1 -cancel_after remove_forces

HDL logicVHDL VHDL logic -radix

logic HDL VHDL std_logic

Verilog 4

VHDL std_logic

std_logic VHDL ( 0 1 )

logic

logic

0 ()

logic MSB 0

Vivado

logic VHDL (

)

VHDL 10

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3 : Tcl ()

{ } HDL { }

: { } 0 { }

{ } current_time 1000ns 20ns 1000ns 1020ns

:

TIME_UNIT fspsnsusmss 50 50ns

50ps 50

300ns High force

force Tcl

set for10 [ add_force reset 1 300 ]

{ }

add_force mySig {0} {1 50 } {0 100} {1 150 } -repeat_every 200 -cancel_after 10000

: { } 0 0 (current_time)

current_time

get_objects

remove_forces

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3 : Tcl ()

add_hw_probe_enum

hw_probe

add_hw_probe_enum [-quiet] [-verbose]

[-quiet]

[-verbose]

ILA

Hardware ()

Vivado

(hw_probe)

()

hw_probe ENUM.NAME

hw_probe /

: Vivado Vivado Design Suite : (UG908)

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3 : Tcl ()

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : hw_probe ENUM /hw_probe

() : () hw_probe 2 8 16

: 2 x (FBRT)

() : hw_probe

hw_probe

add_hw_probe_enum ZERO eq5h00 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum RED eq5h12 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum GREEN eq5h13 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum BLUE eq5h14 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum WHITE eq5h15 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum YELLOW eq5h16 [get_hw_probes op1 -of_objects [current_hw_ila]]

add_hw_probe_enum GREY eq5h17 [get_hw_probes op1 -of_objects [current_hw_ila]]

hw_probe ENUM

report_property [get_hw_probes op1 -of_objects [current_hw_ila]] ENUM*

Property Type Read-only Visible Value

ENUM.ZERO string true true eq5h00

ENUM.RED string true true eq5h12

ENUM.GREEN string true true eq5h13

ENUM.BLUE string true true eq5h14

ENUM.WHITE string true true eq5h15

ENUM.YELLOW string true true eq5h16

ENUM.GREY string true true eq5h17

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3 : Tcl ()

current_hw_device

current_hw_ila

get_hw_devices

get_hw_ilas

get_hw_probes

get_hw_vios

remove_hw_probe_enum

report_property

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3 : Tcl ()

add_peripheral_interface

add_peripheral_interface -interface_mode -axi_type [-quiet][-verbose]

-interface_mode master slave

-axi_type AXI litefullstream

[-quiet]

[-verbose]

(S1_AXIM1_AXI )

Project ()IPFlow (IP )CreatePeripheral ()

create_peripheral AXI

-interface_mode [ master | slave ] () : AXI AXI

AXI AXI

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3 : Tcl ()

-axi_type () : AXI fulllite stream

AXI4 1 256

AXI4-Lite AXI4

AXI4-Stream

: AXI AXI (UG761)

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() :

() : create_peripheral Tcl

VLNV AXI

Tcl AXI

set perifObj [ create_peripheral {myCompany.com} {user} {testAXI1} {1.3} \

-dir {C:/Data/new_periph} ]

add_peripheral_interface {S0_AXI} -interface_mode {slave} -axi_type {lite} $perifObj

add_peripheral_interface {S1_AXI} -interface_mode {slave} -axi_type {lite} $perifObj

add_peripheral_interface {S2_AXI} -interface_mode {slave} -axi_type {lite} $perifObj

create_peripheral

generate_peripheral

write_peripheral

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3 : Tcl ()

add_wave

add_wave [-into ] [-at_wave ] [-after_wave ] [-before_wave] [-reverse] [-radix ] [-color ] [-name ] [-recursive][-r] [-regexp] [-nocase] [-quiet] [-verbose] ...

[-into]

[-at_wave]

[-after_wave]

[-before_wave]

[-reverse]

[-radix] defaultdecbinocthexunsignedascii

[-color] RRGGBB

[-name] 1

[-recursive]

[-r]

[-regexp]

[-nocase] / (-regexp)

[-quiet]

[-verbose]

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3 : Tcl ()

Waveform ()

1

: HDL () 1Vivado [Objects]

-into () : WCFG

WCFG WCFG

-into

-at_wave () :

-after_wave () :

-before_wave () :

-reverse () : IS_REVERSED true

-radix () : defaultdecbinocthexunsignedascii

-color () : 6 RGB (RRGGBB)

-name () : DISPLAY_NAME

-recursive | -r () :

-regexp () : Tcl .*

http://www.tcl.tk/man/tcl8.5/TclCmd/re_syntax.htm

: Tcl regexp Tcl

http://www.tcl.tk/man/tcl8.5/TclCmd/regexp.htm

-nocase () : /-regexp

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3 : Tcl ()

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : HDL

clk

add_wave clkclk

rsb_design_testbench dout_tvalid

add_wave dout_tvalid/rsb_design_testbench/dout_tvalid

add_wave_divider

add_wave_group

add_wave_marker

add_wave_virtual_bus

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3 : Tcl ()

add_wave_divider

add_wave_divider [-into ] [-at_wave ] [-after_wave ][-before_wave ] [-color ] [-quiet] [-verbose] []

[-into]

[-at_wave]

[-after_wave]

[-before_wave]

[-color] RRGGBB default

[-quiet]

[-verbose]

[] new_divider

Waveform ()

:

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3 : Tcl ()

-into () : WCFG

WCFG WCFG

-into

-at_wave () :

-after_wave () :

-before_wave () :

-color () : 6 RGB (RRGGBB)

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : new_divider

CLK Div1

add_wave_divider -after_wave CLK Div1

add_wave

add_wave_group

add_wave_marker

add_wave_virtual_bus

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3 : Tcl ()

add_wave_group

add_wave_group [-into ] [-at_wave ] [-after_wave ][-before_wave ] [-quiet] [-verbose] []

[-into]

[-at_wave]

[-after_wave]

[-before_wave]

[-quiet]

[-verbose]

[] new_group

Waveform ()

:

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3 : Tcl ()

-into () : WCFG

WCFG WCFG

-into

-at_wave () :

-after_wave () :

-before_wave () :

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() : new_group

clk

add_wave_group clkgroup10

add_wave

add_wave_divider

add_wave_marker

add_wave_virtual_bus

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3 : Tcl ()

add_wave_marker

add_wave_marker [-into ] [-name ] [-quiet] [-verbose] [][]

[-into]

[-name]

[-quiet]

[-verbose]

[] 0

[] fspsnsusms s

Waveform ()

:

-into () : -into

-name () : new_marker

() : 0

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3 : Tcl ()

() : smsusns ps

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

500ns

add_wave_marker 500 ns

add_wave

add_wave_divider

add_wave_group

add_wave_virtual_bus

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3 : Tcl ()

add_wave_virtual_bus

add_wave_virtual_bus [-into ] [-at_wave ] [-after_wave ][-before_wave ] [-reverse] [-radix ] [-color ] [-quiet][-verbose] []

[-into]

[-at_wave]

[-after_wave]

[-before_wave]

[-reverse]

[-radix] defaultdecbinocthexunsignedascii

[-color] RRGGBB default

[-quiet]

[-verbose]

[] new_virtual_bus

Waveform ()

vb###

: name

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3 : Tcl ()

-into () : WCFG WCFG

WCFG

-into

-at_wave () :

-after_wave () :

-before_wave () :

-reverse () : IS_REVERSED true

-radix () : defaultdecbinocthexunsignedascii

-color () : 6 RGB (RRGGBB)

-name () : DISPLAY_NAME

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

dout_tvalid

add_wave_virtual_bus dout_tvalidvbus200

add_wave_divider

add_wave_group

add_wave_marker

add_wave

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3 : Tcl ()

all_clocks

all_clocks [-quiet] [-verbose]

[-quiet]

[-verbose]

SDCXDC

get_clocks filter all_clocks

create_clock create_generated_clock

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

CPU

% all_clocks

cpuClk wbClk usbClk phy_clk_pad_0_i phy_clk_pad_1_i fftClk

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3 : Tcl ()

set_propagated_clock (all_clocks)

% set_propagated_clock [all_clocks]

create_clock

create_generated_clock

filter

get_clocks

set_propagated_clock

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3 : Tcl ()

all_cpus

CPU

all_cpus [-quiet] [-verbose]

CPU

[-quiet]

[-verbose]

XDC

CPU CPU

all_cpus CPU filter CPU list_property report_property

all_cpus

current_instance

: CPU

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

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3 : Tcl ()

CPU

all_cpus

set_false_path -from [all_cpus] -to [all_registers]

all_dsps

all_hsios

all_registers

current_instance

filter

get_cells

list_property

report_property

set_false_path

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3 : Tcl ()

all_dsps

DSP

all_dsps [-quiet] [-verbose]

DSP

[-quiet]

[-verbose]

XDC

DSP

all_dsps DSP filter DSP list_property report_property

all_dsps

current_instance

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

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3 : Tcl ()

DSP

1 DSP

filter [all_dsps] {SITE == DSP48_X1Y6}

set_false_path -from [all_dsps] -to [all_registers]

all_cpus

all_hsios

all_registers

current_instance

filter

get_cells

list_property

report_property

set_false_path

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3 : Tcl ()

all_fanin

all_fanin [-startpoints_only] [-flat] [-only_cells] [-levels ][-pin_levels ] [-trace_arcs ] [-quiet] [-verbose]

[-startpoints_only]

[-flat]

[-only_cells]

[-levels] 0 0

[-pin_levels] 0 0

[-trace_arcs] timingenabledall

[-quiet]

[-verbose]

XDC

all_fanin

current_instance -flat

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3 : Tcl ()

-startpoints_only () :

-flat () :

-only_cells () :

-levels () : 0

-pin_levels () : 0

-trace_arcs () : timingenabled all

-quiet () : TCL_OK

:

-verbose () :

: set_msg_config

() :

led_pins

all_fanin [get_ports led_pins[*] ]

( MMCM )

all_fanin -flat -startpoints_only [get_pins cmd_parse_i0/prescale_reg[7]/C]

IDELAY