VLSI D iVLSI DesignLecture 5: Design Rules andLecture 5: Design Rules and

Fabrication

ShaahinShaahin HessabiHessabiDepartment of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of Technologyy gyy gyAdapted with modifications from lecture notes prepared by Adapted with modifications from lecture notes prepared by

author (from Prentice Hall PTR)author (from Prentice Hall PTR)

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Topicsp

SCMOS scalable design rules.g Reliability. Stick diagrams Stick diagrams.

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MOSIS SCMOS design rulesg

Designed to scale across a wide range of technologies.g g g Designed to support multiple vendors. Designed for educational use Designed for educational use. Therefore, fairly conservative.

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and design rulesg

is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in units Parasitics are generally not specified in units

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Wires

metal 36

metal 233

metal 133

pdiff/ndiff3

poly2

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Transistors

22

3 2

3

15

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Vias

Types of via: metal1/diff, metal1/poly, metal1/metal2.yp , p y,Material on both layers to be connected must extend beyond

the SiO2 cut itself; and2

The cut must be of a fixed size.

4 41

22

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Metal 3 via

Type: metal3/metal2.yp Rules: cut: 3 x 3 cut: 3 x 3overlap by metal2: 1minimum spacing: 3minimum spacing: 3minimum spacing to via1: 2

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Tub tie

p-tub tie made of : p2 X 2 cut,4 X 4 metal element,4 X 4 metal element,4 X 4 p+ diffusion

Tub tie must be at least 2 from a diffusion contact Tub tie must be at least 2 from a diffusion contact

441

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Spacingsp g

Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

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Overglassg

Cut in passivation (overglass) layer.p ( g ) y Minimum bonding pad: 100 m. Pad overlap of glass opening: 6 Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active:

15

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SCMOS Variations

SCMOS SCMOS submicron SCMOS deepPoly space 2 3 3Poly space 2 3 3Active extension beyond poly 3 3 4Contact space 2 3 4Via width 2 2 3Metal 1 space 2 3 3Metal 2 space 3 3 4

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Lithography for nanometer processesg p y p

I t f Interference causes drawn features to be di t t d d idistorted during lithography.

Optical proximity correction pre-distorts masks so they create the proper features during lithography.

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3-D integrationg

3-D technology stacks multiple levels of transistors and gy pinterconnect.

Through-silicon-via (TSV) with die stacking uses Through silicon via (TSV) with die stacking uses special via to connect between separately fabricated chipschips.TSV vias must exhibit low resistance, and chips must be carefully aligned chips must be carefully aligned.

Multilayer buried structures build several layers of devices on a substratedevices on a substrate.

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Reliabilityy

F il h l Failures happen early, late in chip’s life.

Infant mortality is caused by marginal components.

Late failures are caused by wear-out (metal y (migration, thermal, etc.). bathtub curve

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Mean-time-to-failure

MTTF for metal wires = time required for 50% of wires qto fail.

Depends on current density: Depends on current density:proportional to j-n e Q/kT

j is current density j is current densityn is constant between 1 and 3Q is diffusion activation energyQ is diffusion activation energy

Can determine lifetime from MTTF.

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Traditional sources of unreliabilityy

Diffusions and junctions: crystal defects, impurity j y , p yprecipitation, mask misalignment, surface contamination.

Oxides: Mobile ions, pinholes, interface states, hot carriers time-dependent dielectric breakdowncarriers, time dependent dielectric breakdown.

Metalization: scratches/voids, mechanical damage, non-ohmic contacts step coverage improper thicknessohmic contacts, step coverage, improper thickness, electromigration, … .

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TDDB

Time-Dependent Dielectric Breakdown: gate voltages p g gcause stress in gate oxides.

More common as oxides become thinner More common as oxides become thinner. TDDB failure rate:MTTF A 10 E Ea/ktMTTF = A 10 E eEa/kt

» A: a constant, Ea: activation energy in eV, E: electric field intensity : electric field intensity coefficientintensity, : electric field intensity coefficient, k:Boltzmann’s constant, t: the absolute temperature.

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Hot carriers

Hot carrier has enough energy to jump from silicon to g gy j poxide.

Accumulated hot carriers create a space charge that Accumulated hot carriers create a space charge that affects threshold voltage.

Several factors such as power supply voltage channel Several factors, such as power supply voltage, channel length, and ambient temperature can affect the rate at which hot carriers are producedwhich hot carriers are produced.

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NTBI

Negative Temperature Bias Instability is particular to g p y ppMOS devices.

Threshold voltage transconductance (g ) change due to Threshold voltage, transconductance (gm) change due to stresses.

Can be reversed by applying a reverse bias to the Can be reversed by applying a reverse bias to the transistor.S t i ifi t f il h i f t t i tSo, not a significant failure mechanism for p-type transistors

whose bias voltages change from forward to reverse regularly but is very important for DC-biased transistors.but is very important for DC biased transistors.

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Electromigration and stress migrationg g

Degenerative failure for wires.g Grains in metal have defects at grain surface that cause

electromigrationelectromigration. Stress migration caused by mechanical stress.C d b th diff t th l i ffi i t f thCaused by the different thermal expansion coefficients of the

wires and the materials in which they reside. Can occur even with zero currentCan occur even with zero current.

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Soft errors

Soft errors cause memory cells to change state.y g Caused by alpha particles. Packages contain small amounts of uranium and Packages contain small amounts of uranium and

thorium, which generate error-inducing radiation.A h i l ( ) d Another cause: gamma particles (neutrons) due to cosmic rays.

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Reliability in Nanometer Technologiesy g

Reliability no longer a Reliability no longer a deterministic problem.

Variations in process Variations in process, supply voltage, temperature (PVT) aretemperature (PVT) are key design challenges in nanometer technologynanometer technology.

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PVT challengesg

Process variations: channel length and threshold voltage g gvary significantly in nanometer technologies. leakage current can vary by huge amountsg y y g

Supply voltage: non-ideal wires introduce variations in supply across chipsupply across chip.

Temperature: higher chip operating temperatures degrade both transistors and interconnectdegrade both transistors and interconnect.

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On-chip temperature sensorsp p

Temperature sensors are used to shut off part or all of p pthe chip to stop thermal runaway.

Use a pn junction from a parasitic bipolar transistor Use a pn junction from a parasitic bipolar transistor.Can also use MOS transistor.

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Stick diagramsg

A stick diagram is a cartoon of a layout.g y Does show all components/vias (except possibly tub

ties) relative placementties), relative placement. Does not show exact placement, transistor sizes, wire

lengths wire widths tub boundarieslengths, wire widths, tub boundaries.

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Stick layersy

metal 3

metal 2metal 2

metal 1

poly

ndiff

pdiffpdiff

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Dynamic latch stick diagramy g

VDD

in out

VSSphiphi’

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phi

Sticks design of multiplexerg p

Start with NAND gate:++

out

ab

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NAND sticks

VDD

a

tout

b

VSS

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One-bit mux sticks

VDDai

t’ out

a

out

a

out

abi

N1(NAND)se

lect N1

(NAND)N1

(NAND)

out

sele

ct

b b b

VSSModern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 31 of 35

VSS

3-bit mux sticks

select’ select

select’ select VDD

select select

m2(one-bit-mux)VSS

oiai

bi

a2

b2

o2

m2(one-bit-mux)select’ select VDD

oiaia1 o1VSSbi

select’ select VDD

b11

m2(one-bit-mux)VSS

oiai

bi

a0

b0

o0

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Layout design and analysis toolsy g y

Layout editors are interactive tools.y Design rule checkers identify DRC errors on the layout.Minimum spacing minimum size composition rulesMinimum spacing, minimum size, composition rules.

Circuit extractors extract the netlist from the layout.C i i ifi i (CVS) Connectivity verification systems (CVS) compare extracted and original netlists.

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Automatic layouty

Cell generators (macrocell generators) create optimized g ( g ) playouts for ALUs, etc.

Standard cell/sea-of-gates layout creates layout from Standard cell/sea of gates layout creates layout from predesigned cells + custom routing.Sea-of-gates allows routing over the cellSea-of-gates allows routing over the cell.

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Standard cell layouty

rea

routing area rouut

ing

aruting are

rou

routing area

ea

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