ADDERS AND SUBTRACTORS AIM:To develop the source code for adders and subtractors by using VHDL/VERILOG and obtain the simulation,synthesis, place and route and implement into FPGA.ALGORITM:Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.BASIC ADDERS & SUBTRACTORS:

HALF ADDER:

LOGIC DIAGRAM

VHDL SOURCE CODE:--Design : HALF ADDER

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadd isPort ( a : in std_logic;b : in std_logic;sum : out std_logic;carry : out std_logic);end hadd;architecture dataflow of hadd isbeginsum <= a xor b;carry <= a and b;end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity haddbehavioral isPort ( a : in std_logic;b : in std_logic;sum : out std_logic;carry : out std_logic);end haddbehavioral;architecture Behavioral of haddbehavioral isbeginp1:process (a,b)beginsum<= a xor b;carry<= a and b;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity haddstructural isPort ( a : in std_logic;b : in std_logic;sum : out std_logic;carry : out std_logic);end haddstructural;architecture structural of haddstructural iscomponent xor2port(a,b:instd_logic;z:out std_logic);end component;component and2port(a,b:instd_logic;z:out std_logic);end component;beginx1: xor2 port map (a,b,sum);a1: and2 port map (a,b,carry);end structural;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end and2;architecture dataflow of and2 is

beginz<= a and b;end dataflow;

xor2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end xor2;architecture dataflow of xor2 isbeginz<= a xor b;end dataflow;

HALF SUBSTRACTOR:

LOGIC DIAGRAM

VHDL SOURCE CODE:

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hsub_dataflow isPort ( a : in std_logic;b : in std_logic;diff : out std_logic;borrow : out std_logic);end hsub_dataflow;architecture dataflow of hsub_dataflowisbegindiff <= a xor b;borrow <= not a and b;end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hsub_behv is

Port ( a : in std_logic;b : in std_logic;diff : out std_logic;borrow : out std_logic);end hsub_behv;architecture Behavioral of hsub_behv isbeginp1:process(a,b)variable abar:std_logic;beginabar:= not a;diff<=a xor b;borrow<=abar and b;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hsub_structural isPort ( a : in std_logic;b : in std_logic;diff : out std_logic;borrow : out std_logic);end hsub_structural;architecture structural of hsub_structural iscomponent xor2port(a,b:instd_logic;z:out std_logic);end component;component and2port(a,b:instd_logic;z:out std_logic);end component;component not1port(a:instd_logic;z:out std_logic);end component;signal abar:std_logic;beginx1:xor2 port map (a,b,diff);a1:and2 port map (abar,b,borrow);n1:not1 port map (a,abar);end structural;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end and2;

architecture dataflow of and2 isbeginz<= a and b;end dataflow;

xor2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end xor2;architecture dataflow of xor2 isbeginz<= a xor b;end dataflow;not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 isPort ( a : in std_logic;z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

FULL ADDER:LOGIC DIAGRAM:

VHDL SOURCE CODE:

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_dataflow isPort ( a : in std_logic;b : in std_logic;c : in std_logic;sum : out std_logic;carry : out std_logic);

end fadd_dataflow;architecture dataflow of fadd_dataflow issignal p,q,r,s:std_logic;beginp<= a xor b;q<= a and b;r<= b and c;s<= c and a;sum<= p xor c;carry<= q or r or s;end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fadd_behv isPort ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);end fsub_behv;architecture Behavioral of fsub_behv isbeginp1:process(a,b,c)variable abar,r,s,t:std_logic;beginabar:=not a;r:=abar and b;s:=b and c;t:=c and abar;diff<=a xor b xor c;borrow<=r or s or t;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub_structural isPort ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);end fsub_structural;architecture structural of fsub_structural iscomponent xor2port(a,b:instd_logic;z:out std_logic);end component;

component and2port(a,b:instd_logic;z:out std_logic);end component;component not1port(a:instd_logic;z:out std_logic);end component;component or3port(a,b,c:instd_logic;z:out std_logic);end component;signal p,q,r,s,abar:std_logic;beginx1:xor2 port map (a,b,p);x2:xor2 port map (p,c,diff);n1:not1 port map (a,abar);a1:and2 port map (abar,b,q);a2:and2 port map (b,c,r);a3:and2 port map (c,abar,s);o1:or3 port map (q,r,s,borrow);end structural;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end and2;architecture dataflow of and2 isbeginz<= a and b;end dataflow;

or3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or3 isPort ( a : in std_logic;b : in std_logic;c : in std_logic;z : out std_logic);end or3;architecture dataflow of or3 isbeginz<= a or b or c;end dataflow;

xor2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);end xor2;architecture dataflow of xor2 isbeginz<= a xor b;end dataflow;

FULL SUBSTRACTOR:LOGIC DIAGRAM:

VHDL SOURCE CODE:

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub_dataflow isPort ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);end fsub_dataflow;architecture dataflow of fsub_dataflow issignal abar:std_logic;beginabar<=not a;diff<=a xor b xor c;borrow<=(abar and b) or (b and c) or (c and abar);end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub_behv isPort ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);end fsub_behv;architecture Behavioral of fsub_behv isbeginp1:process(a,b,c)variable abar,r,s,t:std_logic;beginabar:=not a;r:=abar and b;s:=b and c;t:=c and abar;diff<=a xor b xor c;borrow<=r or s or t;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fsub_structural isPort ( a : in std_logic;b : in std_logic;c : in std_logic;diff : out std_logic;borrow : out std_logic);end fsub_structural;architecture structural of fsub_structural iscomponent xor2port(a,b:instd_logic;z:out std_logic);end component;component and2port(a,b:instd_logic;z:out std_logic);end component;component not1port(a:instd_logic;z:out std_logic);end component;component or3port(a,b,c:instd_logic;z:out std_logic);end component;signal p,q,r,s,abar:std_logic;beginx1:xor2 port map (a,b,p);x2:xor2 port map (p,c,diff);n1:not1 port map (a,abar);a1:and2 port map (abar,b,q);

a2:and2 port map (b,c,r);a3:and2 port map (c,abar,s);o1:or3 port map (q,r,s,borrow);end structural;

ENCODERS AND DECODERSAIMTo develop the source code for encoders and decoders by using VHDL/VERILOG and obtain thesimulation, synthesis, place and route and implement into FPGA.ALGORITHMStep1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.ENCODERLOGIC DIAGRAM TRUTH TABLE:

VHDL SOURCE CODEDataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_dataflow isPort ( d : in std_logic_vector(7 downto 0);z : out std_logic_vector(2 downto 0));end encoder_dataflow;architecture dataflow of encoder_dataflow isbeginz(2)<= d(4) or d(5) or d(6) or d(7);

z(1)<= d(2) or d(3) or d(6) or d(7);z(0)<= d(1) or d(3) or d(5) or d(7);end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_behv isPort ( d : in std_logic_vector(7 downto 0);e : in std_logic;z : out std_logic_vector(2 downto 0));end encoder_behv;architecture Behavioral of encoder_behv isbeginp1:process(d,e)beginif (e='1') thencase d iswhen "10000000"=>z<="000";when "01000000"=>z<="001";when "00100000"=>z<="010";when "00010000"=>z<="011";when "00001000"=>z<="100";when "00000100"=>z<="101";when "00000010"=>z<="110";when "00000001"=>z<="111";when others=>z<="ZZZ";end case;elsez<="XXX";end if;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity encoder_struct isPort ( d : in std_logic_vector(7 downto 0);z : out std_logic_vector(2 downto 0)); end encoder_struct;architecture structural of encoder_struct iscomponent or4port(a,b,c,d:instd_logic;z:out std_logic);end component;begino1:or4 port map (d(4),d(5),d(6),d(7),z(0));o2:or4 port map (d(2),d(3),d(6),d(7),z(1));o3:or4 port map (d(1),d(3),d(5),d(7),z(2));end structural;or4 component source code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 isPort ( a : in std_logic;b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);end or4;architecture dataflow of or4 isbeginz<=a or b or c or d;end dataflow;

DECODERS:LOGIC DIAGRAM:

VHDL SOURCE CODE:

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_dataflow isPort ( a : in std_logic;b : in std_logic;e : in std_logic;z : out std_logic_vector(3 downto 0));

end decoder_dataflow;architecture dataflow of decoder_dataflow issignal abar,bbar:std_logic;beginabar<= not a;bbar<= not b;z(0)<= not (abar and bbar and e);z(1)<= not (abar and b and e);z(2)<= not (a and bbar and e);z(3)<= not (a and b and e);end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_behv isPort ( a : in std_logic;b : in std_logic;e : in std_logic;z : out std_logic_vector(3 downto 0));end decoder_behv;architecture Behavioral of decoder_behv isbeginp1:process(a,b)beginif (e='1') thenz(0)<= not a and not b ;z(1)<= not a and b;z(2)<= a and not b;z(3)<= a and b;elsez<="1111";end if;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder_struct isPort ( a : in std_logic;b : in std_logic;e : in std_logic;z : out std_logic_vector(3 downto 0));end decoder_struct;architecture structural of decoder_struct iscomponent nand3port(a,b,c:instd_logic;z:out std_logic);end component;component not1port(a:instd_logic;

z:out std_logic);end component;signal abar,bbar:std_logic;beginn1:not1 port map (a,abar);n2:not1 port map (b,bbar);a1:nand3 port map (abar,bbar,e,z(0));a2:nand3 port map (abar,b,e,z(1));a3:nand3 port map (a,bbar,e,z(2));a4:nand3 port map (a,b,e,z(3));end structural;

nand3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity nand3 isPort ( a : in std_logic;b : in std_logic;c : in std_logic;z : out std_logic);end nand3;architecture dataflow of nand3 isbeginz<= not (a and b and c);end dataflow;

not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 isPort ( a : in std_logic;z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

MULTIPLEXER AND DEMULTIPLEXERAIMTo develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and obtain thesimulation, synthesis, place and route and implement into FPGA.ALGORITHMStep1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.

Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.MULTIPLEXER:LOGIC DIAGRAM:

VHDL SOURCE CODE:Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_dataflow isPort ( d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);y : out std_logic);end mux_dataflow;architecture dataflow of mux_dataflow issignal s0bar,s1bar,p,q,r,st:std_logic;beginp<= d(0) and s0bar and s1bar;q<= d(1) and s0bar and s(1);r<= d(2) and s(0) and s1bar;st<= d(3) and s(0) and s(1);s0bar<= not s(0);s1bar<= not s(1);y<= p or q or r or st;end dataflow;Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_behv isPort ( d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);y : out std_logic);end mux_behv;architecture Behavioral of mux_behv is

beginp1:process(d,s)beginif (s(0)<='0' and s(1)<='0') theny<=d(0);elsif (s(0)<='0' and s(1)<='1') theny<=d(1);elsif (s(0)<='1' and s(1)<='0') theny<=d(2);elsey<=d(3);end if;end process p1;end Behavioral;Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_struct isPort ( d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);y : out std_logic);end mux_struct;architecture structural of mux_struct iscomponent not1port(a:instd_logic;z:out std_logic);end component;component and3port(a,b,c:instd_logic;z:out std_logic);end component;component or4port(a,b,c,d:instd_logic;z:out std_logic);end component;signal s0bar,s1bar,p,q,r,st:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d(0),s0bar,s1bar,p);a2:and3 port map (d(1),s0bar,s(1),q);a3:and3 port map (d(2),s(0),s1bar,r);a4:and3 port map (d(3),s(0),s(1),st);o1:or4 port map (p,q,r,st,y);end structural;and3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 isPort ( a : in std_logic;b : in std_logic;

c : in std_logic;z : out std_logic);end and3;architecture dataflow of and3 isbeginz<=a and b and c;end dataflow;not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 isPort ( a : in std_logic;z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

or4 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 isPort ( a : in std_logic;b : in std_logic;c : in std_logic;d : in std_logic;z : out std_logic);end or4;architecture dataflow of or4 isbeginz<=a or b or c or d;end dataflow;DEMULTIPLEXER:LOGIC DIAGRAM:

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_dataflow isPort ( d : in std_logic;s : in std_logic_vector(1 downto 0);z : out std_logic_vector(3 downto 0));end demux_dataflow;architecture dataflow of demux_dataflow issignal s0bar,s1bar:std_logic;begins0bar<= not s(0);s1bar<= not s(1);z(0)<=d and s0bar and s1bar;z(1)<=d and s0bar and s(1);z(2)<=d and s(0) and s1bar;z(3)<=d and s(0) and s(1);end dataflow;Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_behv isPort ( d : in std_logic;s : in std_logic_vector(1 downto 0);z : out std_logic_vector(3 downto 0));end demux_behv;architecture Behavioral of demux_behv isbeginp1:process(d,s)beginif (s(0)<='0' and s(1)<='0') thenz(0)<=d;z(1)<='Z';z(2)<='Z';

z(3)<='Z';elsif (s(0)<='0' and s(1)<='1') thenz(0)<='Z';z(1)<=d;z(2)<='Z';z(3)<='Z';elsif (s(0)<='1' and s(1)<='0') thenz(0)<='Z';z(1)<='Z';z(2)<=d;z(3)<='Z';elsez(0)<='Z';z(1)<='Z';z(2)<='Z';z(3)<=d;end if;end process p1;end Behavioral;Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_struct isPort ( d : in std_logic;s : in std_logic_vector(1 downto 0);z : out std_logic_vector(3 downto 0));end demux_struct;architecture structural of demux_struct iscomponent not1port(a:instd_logic;z:out std_logic);end component;component and3port(a,b,c:instd_logic;z:out std_logic);end component;signal s0bar,s1bar:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d,s0bar,s1bar,z(0));a2:and3 port map (d,s0bar,s(1),z(1));a3:and3 port map (d,s(0),s1bar,z(2));a4:and3 port map (d,s(0),s(1),z(3));end structural;and3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 isPort ( a : in std_logic;b : in std_logic;

c : in std_logic;z : out std_logic);end and3;architecture dataflow of and3 isbeginz<=a and b and c;end dataflow;not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 isPort ( a : in std_logic;z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

FLIP FLOPSAIM:To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation, synthesis,place and route and implement into FPGA.ALGORITHM:Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.SR FLIPFLOP:LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity srff isPort ( s : in std_logic;r : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end srff;architecture Behavioral of srff isbeginprocess(s,r,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (s='0' and r='0') thenq<=q;qbar<=qbar;elsif (s='0' and r='1') thenq<='0';qbar<='1';elsif (s='1' and r='0') thenq<='1';qbar<='0';elseq<='X';qbar<='X';

end if;end if;end process;end Behavioral;

JK FLIPFLOP:LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jkff isPort ( j : in std_logic;k : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end jkff;architecture Behavioral of jkff isbeginprocess(j,k,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (j='0' and k='0') thenq<=q;

qbar<=qbar;elsif (j='0' and k='1') thenq<='0';qbar<='1';elsif (j='1' and k='0') thenq<='1';qbar<='0';elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;

D FLIPFLOP:LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff isPort ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end dff;architecture Behavioral of dff isbeginprocess(d,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) then

if (d='0') thenq<='0';qbar<='1';elseq<='1';qbar<='0';end if;end if;end process;end Behavioral;

T FLIPFLOP:LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff isPort ( t : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (t='0') thenq<=q;qbar<=qbar;

elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;

SHIFT REGISTERSAIM:To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation, synthesis,place and route and implement into FPGA.ALGORITM:Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.

SERIAL-IN SERIAL-OUT SHIFT REGISTER:LOGIC DIAGRAM:

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity siso isPort ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : out std_logic);end siso;architecture Behavioral of siso issignal x:std_logic_vector(7 downto 0);beginprocess(d,clk,rst)beginif (rst='1') thenq<='X';elsif (clk='1' and clk'event) thenx(0)<=d;x(1)<=x(0);x(2)<=x(1);x(3)<=x(2);x(4)<=x(3);

x(5)<=x(4);x(6)<=x(5);x(7)<=x(6);q<=x(7);end if;end process;end Behavioral;

SERIAL IN PARALLEL OUT SHIFT REGISTER:LOGIC DIAGRAM :

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sipo isPort ( d : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic_vector(7 downto 0));end sipo;architecture Behavioral of sipo isbeginprocess(d,clk,rst)beginif (rst='1') then

q<="ZZZZZZZZ";elsif (clk='1' and clk'event) thenq(0)<=d;q(1)<=q(0);q(2)<=q(1);q(3)<=q(2);q(4)<=q(3);q(5)<=q(4);q(6)<=q(5);q(7)<=q(6);end if;end process;end Behavioral;

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:LOGIC DIAGRAM :

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pipo isPort ( d : in std_logic_vector(7 downto 0);clk : in std_logic;rst : in std_logic;q : out std_logic_vector(7 downto 0));

end pipo;architecture Behavioral of pipo isbeginprocess(d,clk,rst)beginif (rst='1') thenq<="ZZZZZZZZ";elsif (clk='1' and clk'event) thenq(0)<=d(0);q(1)<=d(1);q(2)<=d(2);q(3)<=d(3);q(4)<=d(4);q(5)<=d(5);q(6)<=d(6);q(7)<=d(7);end if;end process;end Behavioral;

PARALLEL-IN SERIAL-OUT SHIFT REGISTER:LOGIC DIAGRAM :

VHDL SOURCE CODE:Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity piso isPort ( d : in std_logic_vector(7 downto 0);clk : in std_logic;rst : in std_logic;load : in std_logic;q : out std_logic);end piso;architecture Behavioral of piso isbegin

process(d,clk,rst,load)variable x:std_logic_vector(7 downto 0);beginif (clk='1' and clk'event) thenif (rst='1') thenq<='Z';elseif (load='0') thenx:=d;elseq<=x(0);x(0):=x(1);x(1):=x(2);x(2):=x(3);x(3):=x(4);

x(4):=x(5);x(5):=x(6);x(6):=x(7);x(7):='Z';end if;

end if;end if;end process;end Behavioral;

SYNCHRONOUS AND ASYNCHRONOUS COUNTERAIM:To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG andobtain the simulation, synthesis, place and route and implement into FPGA.ALGORITM:Step1: Define the specifications and initialize the design.Step2: Declare the name of the entity and architecture by using VHDL source code.Step3: Write the source code in VERILOG.Step4: Check the syntax and debug the errors if found, obtain the synthesis report.Step5: Verify the output by simulating the source code.Step6: Write all possible combinations of input using the test bench.Step7: Obtain the place and route report.

SYNCHRONOUS COUNTER:LOGIC DIAGRAM:

VHDL SOURCE CODE:Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity syncounter isPort ( clk : in std_logic;rst : in std_logic;q : inoutstd_logic_vector(3 downto 0));end syncounter;architecture structural of syncounter iscomponent tffport(t,clk,rst:instd_logic;

q,qbar:inoutstd_logic);end component;component and2port(a,b:instd_logic;z:out std_logic);end component;signal x1,x2:std_logic;signal x3,x4,x5,x6:std_logic:='Z';begint1:tff port map ('1',clk,rst,q(0),x3);t2:tff port map (q(0),clk,rst,q(1),x4);t3:tff port map (x1,clk,rst,q(2),x5);t4:tff port map (x2,clk,rst,q(3),x6);a1:and2 port map (q(0),q(1),x1);

a2:and2 port map (x1,q(2),x2);end structural;

tff component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff isPort ( t : in std_logic;clk : in std_logic;

rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq<='0';

qbar<='1';elsif (clk='1' and clk'event) thenif (t='0') thenq<=q;qbar<=qbar;elseq<=not q;qbar<=not qbar;end if;end if;end process;

end Behavioral;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 isPort ( a : in std_logic;b : in std_logic;z : out std_logic);

end and2;architecture dataflow of and2 isbeginz<=a and b;end dataflow;

ASYNCHRONOUS COUNTER:LOGIC DIAGRAM:

VHDL SOURCE CODE:Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity asyncounter isPort ( clk : in std_logic;

rst : in std_logic;q : inoutstd_logic_vector(3 downto 0));end asyncounter;architecture structural of asyncounter iscomponent tffport(t,clk,rst:instd_logic;

q,qbar:inoutstd_logic);end component;signal x1,x2,x3:std_logic;signal x4:std_logic:='Z';begint1:tff port map ('1',clk,rst,q(0),x1);t2:tff port map ('1',x1,rst,q(1),x2);t3:tff port map ('1',x2,rst,q(2),x3);t4:tff port map ('1',x3,rst,q(3),x4);end structural;tff component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff isPort ( t : in std_logic;clk : in std_logic;rst : in std_logic;q : inoutstd_logic;qbar : inoutstd_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (t='0') thenq<=q;qbar<=qbar;elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;