Vlsi Program -Reference Copy

7/21/2019 Vlsi Program -Reference Copy

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//-----------------------------------------------------// Design Name : 8 bit adder using parameter// File Name : nbitadder.v// Function : two binary numbers addition//-----------------------------------------------------N bit adder program

module nBitAdder(! cout! a! b! c"n#$

parameter n % &$

output reg 'n:) $

output reg cout$

input 'n:) a$

input 'n:) b$

input c"n$

always *(a! b! c"n#

+cout! , % a b c"n$

endmodule

// test bench coding starts here

module nbitaddertb(#$

parameter n % &$

//declare o/ps as wire

wire 'n:) t$

wire coutt$

//declare i/ps as reg

reg 'n:) at$

reg 'n:) bt$

reg c"nt$

nBitAdder duttest(t! coutt! at! bt! c"nt#$ //portmapping

rom design to testbenc0initialbegin

// inputs



c"nt1%2b$

at1% 8b2222$

bt1%8b22222$ 32$ // delay

// inputs

c"nt 1%2b$ at1% 8b2222$

bt1%8b22222$ 32$ // delay

// inputs

c"nt1%2b$ at1% 8b222222$

bt1%8b222222$ 32$ // delay

// inputs

c"nt1%2b$ at1% 8b2222222$

bt1%8b22222$ 32$ // delay

// inputs

c"nt 1%2b$ at1% 8b22222222$

bt1%8b$ 32$ // delay

// inputs

c"nt1%2b$

at1% 8b22222222$



bt1%8b22222222$ 32$ // delay

// inputs

c"nt1%2b2$ at1% 8b2222$

bt1%8b22222$ 32$ // delay

// inputs

c"nt 1%2b2$

at1% 8b2222$

bt1%8b22222$ 32$ // delay

// inputsc"nt 1%2b2$

at1% 8b222222$ bt1%8b222222$ 32$ // delay

// inputs

c"nt 1%2b2$ at1% 8b2222222$

bt1%8b22222$ 32$ // delay

// inputs

c"nt 1%2b2$ at1% 8b22222222$

bt1%8b$

32$ // delay



// inputs

c"nt 1%2b2$ at1% 8b22222222$

bt1%8b22222222$ 32$ // delay

end

endmodule

O/P Wave form for test bench

4 bit decoder

//-----------------------------------------------------// Design Name : decoderusingcase// File Name : decoderusingcase.v// Function : decoder using case//-----------------------------------------------------module decoderusingcase (binaryin ! // 4 bit binary inputdecoderout ! // 25-bit outenable // 6nable or t0e decoder

#$input '7:) binaryin $input enable $output '2:) decoderout $

reg '2:) decoderout $

always * (enable or binaryin#begin

decoderout % $ i (enable# begin



case (binaryin# 40 : decoderout % 2502$ 402 : decoderout % 2509$ 409 : decoderout % 2504$ 407 : decoderout % 2508$ 404 : decoderout % 2502$ 40 : decoderout % 2509$ 405 : decoderout % 2504$ 40& : decoderout % 2508$ 408 : decoderout % 2502$ 40 : decoderout % 2509$ 40A : decoderout % 2504$ 40B : decoderout % 2508$ 40; : decoderout % 2502$ 40D : decoderout % 2509$ 406 : decoderout % 2504$

40F : decoderout % 2508$ endcase endend

endmodule// Test Bench Code starts here

module decoderusingcasetb (#$

reg '7:) binaryint $reg enablet $wire '2:) decoderoutt $

decoderusingcase duttest(binaryint !decoderoutt !enablet #$initialbegin

// "nputs // 6NAB<6 <=> enablet %2b$

binaryint % 402$ 32$


binaryint % 407$

32$binaryint % 404$



32$binaryint % 40$

32$binaryint % 405$

32$binaryint % 40&$

32$binaryint % 408$

32$binaryint % 40$

32$binaryint % 40A$

32$binaryint % 40B$

32$binaryint % 40;$

32$binaryint % 40D$

32$binaryint % 406$

32$binaryint % 40F$

// 6NAB<6 ?"@?

32$

enablet %2b2$




binaryint % 404$

32$binaryint % 40$

32$binaryint % 405$

32$binaryint % 40&$

32$binaryint % 408$

32$

binaryint % 40$ 32$



binaryint % 40A$ 32$

binaryint % 40B$ 32$

binaryint % 40;$ 32$

binaryint % 40D$ 32$


binaryint % 40F$

// 6NAB<6 <=> 32$ enablet %2b$

binaryint % 402$

32$binaryint % 409$

32$binaryint % 407$

32$binaryint % 404$

32$

binaryint % 40$ 32$


binaryint % 40&$ 32$


binaryint % 40$

32$binaryint % 40A$

32$binaryint % 40B$

32$binaryint % 40;$

32$binaryint % 40D$

32$




binaryint % 40F$ endendmodule

Test Bench O/P

//-----------------------------------------------------

// Design Name : <C"<E6

// File Name : E.v

// Function : 4:2 E//-----------------------------------------------------

4:1 MU !itho"t defa"#t

module muG (a!b!c!d!sel!y#$input a! b! c! d$input '2:) sel$output y$

reg y$

always * (a or b or c or d or sel#case (sel# : y % a$2 : y % b$9 : y % c$7 : y % d$deault : Hdisplay(I6rror in J6<I#$

endcase



endmodule

// Test bench starts here

module muGtb (#$reg at! bt! ct! dt$

reg '2:) selt$wire yt$

muG duttest(at! bt! ct! dt!selt!yt#$

initialbegin

// "nputs

at1%2b$ bt1%2b2$ ct1%2b$ dt1%2b2$

// selections selt 1% 9d2$ 32$

selt 1% 9d9$

32$selt 1% 9d7$32$selt 1% 9d4$32$selt 1% 9d2$

// "nputsat1%2b2$

bt1%2b2$ ct1%2b2$ dt1%2b2$


selt 1% 9d9$32$selt 1% 9d7$32$



selt 1% 9d4$32$selt 1% 9d2$// "nputsat1%2b2$

bt1%2b$ ct1%2b2$ dt1%2b$


selt 1% 9d9$32$selt 1% 9d7$32$

selt 1% 9d4$32$selt 1% 9d2$// "nputsat1%2b$

bt1%2b2$ ct1%2b$ dt1%2b2$


selt 1% 9d9$32$selt 1% 9d7$32$selt 1% 9d4$32$

selt 1% 9d2$

endendmodule

O/P Wave form



/-----------------------------------------------------

// Design Name : Unsigned Multiplier and Accumulator

// File Name : Multiplier_Accumulator.v

// Function : Accumulator

//-----------------------------------------------------

module unsig_altmult_accum(

input [7:! dataa"input [7:! data#"input cl$" aclr" cl$en" sload"output reg [%&:! adder_out

'

// Declare registers and )iresreg [%&:! dataa_reg" data#_regreg sload_regreg [%&:! old_result)ire [%&:! multa

// *tore t+e results o, t+e operations on t+e current dataassign multa dataa_reg data#_reg

// *tore t+e value o, t+e accumulation (or clear it'al)as 0 (adder_out" sload_reg'

#egini, (sload_reg'

old_result 1 else

old_result 1 adder_outend



// 2lear or update data" as appropriateal)as 0 (posedge cl$ or posedge aclr'

#egini, (aclr'

#egindataa_reg 1

data#_reg 1 sload_reg 1 adder_out 1

end

else i, (cl$en' #egin

dataa_reg 1 dataadata#_reg 1 data#

sload_reg 1 sloadadder_out 1 old_result 3 multa

endend

endmodule

module unsig_altmult_accum_t#('

reg [7:! dataa_treg [7:! data#_treg cl$_t" aclr_t" cl$en_t" sload_t)ire [%&:! adder_out_t

unsig_altmult_accum dut_test(dataa_t"data#_t"cl$_t" aclr_t" cl$en_t"sload_t"adder_out_t'

initial

#egin sload_t1%4#%

aclr_t1%4#% cl$en_t1%4#

dataa_t154d& data#_t154d6

%



sload_t1%4# aclr_t1%4# cl$en_t1%4#%


%

dataa_t154d& data#_t154d& %

dataa_t154d% data#_t154d6

%

dataa_t154d8

data#_t154d6

%

dataa_t154d9

data#_t154d6

%


%

dataa_t154d data#_t154d6 ;stop(' end

initial

cl$_t %4#al)as % cl$_t <cl$_t

endmodule



O/P Wave form

$

4 bit co"nter

module counter (clK! s! L#$ input clK! s$ output '7:) L$ reg '7:) L$ always *(posedge clK# begin i (s# L 1% 4b$

else L 1% L 2b2$ end //assign L % tmp$ endmodule

// Test bench %tarts here

module countertb(#$

reg clKt! st$



wire '7:) Lt$ counter duttest(clKt! st! Lt#$ initial begin clKt%2b$ st1%2b2$

32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$

32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$

32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$

32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$



32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$ 32$

st1%2b$

Hstop(#$ end

always 3 clKt% MclKt$

endmodule

4 bit m"#tip#ier

module multiplier (a! b! out#$

input '7:) a$ input '7:) b$ output '&:) out$ wire '&:) out$

assign out % a b$

endmodule




module multipliertb (#$

reg '7:) at$ reg '7:) bt$ wire '&:) outt$ multiplier duttest(at! bt! outt#$

initial begin

at1%4d2$ bt1%4d9$

32$

at1%4d$

bt1%4d9$

32$ at1%4d5$ bt1%4d9$

32$ at1%4d2$ bt1%4d$

32$

at1%4d2$ bt1%4d8$

32$ at1%4d$ bt1%4d2$

32$ at1%4d99$ bt1%4d77$

32$ at1%4d22$ bt1%4d9$

32$

at1%4d9$ bt1%4d9$



32$

at1%4d$ bt1%4d9$

32$ at1%4d2$ bt1%4d$

32$ at1%4d2$ bt1%4d9$

32$Hstop(#$

end endmodule

Test bench O/P

P&B% 'enerator

module prbs (rand! clK! reset#$input clK! reset$output rand$wire rand$

reg '7:) temp$

always * (posedge reset# begintemp 1% 40$

end



always * (posedge clK# begini (Mreset# begin

temp 1% +temp')Otemp'2)!temp'7)!temp'9)!temp'2),$end

end

assign rand % temp')$endmodule


module prbst$reg clKt! resett$wire randt$

prbs pr (randt! clKt! resett#$

initial beginorever begin

clKt 1% $3clKt 1% 2$3clKt 1% $

end

end

initial beginresett % 2$329resett % $3resett % 2$329

resett % $32$

resett % 2$329resett % $3resett % 2$329resett % $



Hstop(#$ end

endmodule

Test bench O/P

Adder/Subtractor

addSub.v

module add*u#(A" =" sel" >esult'

input selinput [6:! A"=

output [6:! >esult

)ire [6:! >esult

assign >esult (sel'? A 3 = : A - =

endmodule

testAS.v

module main

reg [6:! A" =

reg sel

)ire [6:! >esult

add*u# as%(A" =" sel" >esult'



initial #egin

A 94#%

= 94#%%

end

initial #egin

,orever #egin

%

A A 3 %4#%

= = 3 %4#8

end

end

initial #egin

sel %

8

sel end

endmodule

/-----------------------------------------------------// Design Name : encoder_using_case// File Name : encoder_using_case.v

// Function : @ncoder using 2ase-----------------------------------------------------module encoder_using_case(

#inar_out " // 9 #it #inar utputencoder_in " // %-#it Bnputena#le // @na#le ,or t+e encoder 'output [6:! #inar_out input ena#le

input [%&:! encoder_in



reg [6:! #inar_out al)as 0 (ena#le or encoder_in'

#egin #inar_out i, (ena#le' #egin case (encoder_in'

%4+8 : #inar_out %%4+9 : #inar_out 8%4+5 : #inar_out 6%4+% : #inar_out 9

%4+8 : #inar_out &%4+9 : #inar_out %4+5 : #inar_out 7%4+% : #inar_out 5

%4+8 : #inar_out C

%4+9 : #inar_out %%4+5 : #inar_out %%%4+% : #inar_out %8%4+8 : #inar_out %6%4+9 : #inar_out %9%4+5 : #inar_out %&

endcase endend

endmodule

//-----------------------------------------------------// Design Name : pri_encoder_using_i, // File Name : pri_encoder_using_i,.v// Function : ri @ncoder using B,

-----------------------------------------------------module pri_encoder_using_i, ( #inar_out " // 9 #it #inar outputencoder_in " // %-#it inputena#le // @na#le ,or t+e encoder 'output [6:! #inar_out input ena#le input [%&:! encoder_in

reg [6:! #inar_out



al)as 0 (ena#le or encoder_in'

#egin #inar_out i, (ena#le' #egin i, (encoder_in EE%9E%4#GG"%4#%"E%E%4#GGG' #egin #inar_out %

end else i, (encoder_in EE%6E%4#GG"%4#%"E8E%4#GGG' #egin #inar_out 8end else i, (encoder_in EE%8E%4#GG"%4#%"E6E%4#GGG' #egin #inar_out 6end else i, (encoder_in EE%%E%4#GG"%4#%"E9E%4#GGG' #egin #inar_out 9end else i, (encoder_in EE%E%4#GG"%4#%"E&E%4#GGG' #egin #inar_out &end else i, (encoder_in EECE%4#GG"%4#%"EE%4#GGG' #egin

#inar_out end else i, (encoder_in EE5E%4#GG"%4#%"E7E%4#GGG' #egin #inar_out 7end else i, (encoder_in EE7E%4#GG"%4#%"E5E%4#GGG' #egin #inar_out 5end else i, (encoder_in EEE%4#GG"%4#%"ECE%4#GGG' #egin #inar_out Cend else i, (encoder_in EE&E%4#GG"%4#%"E%E%4#GGG' #egin #inar_out %

end else i, (encoder_in EE9E%4#GG"%4#%"E%%E%4#GGG' #egin #inar_out %%end else i, (encoder_in EE6E%4#GG"%4#%"E%8E%4#GGG' #egin #inar_out %8end else i, (encoder_in EE8E%4#GG"%4#%"E%6E%4#GGG' #egin #inar_out %6end else i, (encoder_in EE%E%4#GG"%4#%"E%9E%4#GGG' #egin #inar_out %9end else i, (encoder_in E%4#%"E%&E%4#GGG' #egin

#inar_out %&end endend

endmodule

/-----------------------------------------------------// Design Name : pri_encoder_using_assign

// File Name : pri_encoder_using_assign.v// Function : ri @ncoder using assign



//-----------------------------------------------------module pri_encoder_using_assign (

#inar_out " // 9 #it #inar outputencoder_in " // %-#it inputena#le // @na#le ,or t+e encoder '

output [6:! #inar_out input ena#le input [%&:! encoder_in

)ire [6:! #inar_out assign #inar_out (Hena#le' ? : ( (encoder_in %4#___%' ? :

(encoder_in %4#___%' ? % :

(encoder_in %4#___%' ? 8 :(encoder_in %4#___%' ? 6 :(encoder_in %4#__%_' ? 9 :(encoder_in %4#__%_' ? & :(encoder_in %4#__%_' ? :(encoder_in %4#__%_' ? 7 :(encoder_in %4#_%__' ? 5 :(encoder_in %4#_%__' ? C :(encoder_in %4#_%__' ? % :

(encoder_in %4#_%__' ? %% :(encoder_in %4#%___' ? %8 :(encoder_in %4#%___' ? %6 :(encoder_in %4#%___' ? %9 : %&'

endmodule

//-----------------------------------------------------// Design Name : decoder_using_case

// File Name : decoder_using_case.v-----------------------------------------------------module decoder (

#inar_in " // 9 #it #inar inputdecoder_out " // %-#it outena#le // @na#le ,or t+e decoder 'input [6:! #inar_in input ena#le output [%&:! decoder_out



reg [%&:! decoder_out

al)as 0 (ena#le or #inar_in' #egin decoder_out i, (ena#le' #egin case (#inar_in'

94+ : decoder_out %4+% 94+% : decoder_out %4+8 94+8 : decoder_out %4+9 94+6 : decoder_out %4+5 94+9 : decoder_out %4+% 94+& : decoder_out %4+8 94+ : decoder_out %4+9 94+7 : decoder_out %4+5 94+5 : decoder_out %4+%

94+C : decoder_out %4+8 94+A : decoder_out %4+9 94+= : decoder_out %4+5 94+2 : decoder_out %4+% 94+D : decoder_out %4+8 94+@ : decoder_out %4+9 94+F : decoder_out %4+5 endcase end

endendmodule

//-----------------------------------------------------// Design Name : decoder_using_assign// File Name : decoder_using_assign.v// Function : decoder using assign//-----------------------------------------------------module decoder_using_assign (

#inar_in " // 9 #it #inar inputdecoder_out " // %-#it outena#le // @na#le ,or t+e decoder 'input [6:! #inar_in input ena#le output [%&:! decoder_out

)ire [%&:! decoder_out

assign decoder_out (ena#le' ? (% 11 #inar_in' : %4#



endmodule

//

module Iest_decoder_8to9

//

)ire J6" J8" J%" J

reg A" =

reg en

// Bnstantiate t+e Decoder (named DUI Edevice under testG'

Decoder (J6" J8" J%" J" A" =" en'

initial #egin

;time,ormat(-C" %" K nsK" ' %

A %4# // time

= %4#

en %4#

C

en %4#% // time %

%

A %4#

= %4#% // time 8

%

A %4#%

= %4# // time 6

%

A %4#%



= %4#% // time 9

&

en %4# // time 9&

&

end

al)as 0(A or = or en'

% ;displa(KtLtK";time"K enL#K"en"K AL#K"A"K =L#K"="K JL#L#L#

L#K"J6"J8"J%"J'

endmodule

module muG2( select! d! L #$

input'2:) select$

input'7:) d$

output L$

wire L$

wire'2:) select$wire'7:) d$

assign L % d'select)$

endmodule

// erilog test#enc+ ,or 9 to % Multipleer module mu_t#

reg[6:! dreg[%:! select)ire

integer i

mu% m_mu( select" d" '



initial #egin % ;monitor(Kd L#K" d" K O select K" select" K O K" '

,or( i i 1 %& i i 3 %' #egin

d i select % select % % select 8 % select 6 % ;displa(K-----------------------------------------K' end

end

endmodule

// erilog code ,or Multipleer implementation using case statement.module mu9( select" d" '

input[%:! selectinput[6:! doutput

reg )ire[%:! select)ire[6:! d

al)as 0( select or d ' #egin case( select '

: d[! % : d[%! 8 : d[8! 6 : d[6! endcaseend

endmodule



/ erilog code ,or Multipleer implementation using conditional statement.

module mu&( select" d" '

input[%:! selectinput[6:! doutput

wire wire[%:! selectwire[6:! d

assign ( select '? d[! : ( select % '? d[%! : ( select 8 '? d[8! :d[6!

endmodule

//-----------------------------------------------------// Design Name : d,,_asnc_reset// File Name : d,,_asnc_reset.v// Function : D ,lip-,lop asnc reset//-----------------------------------------------------module d,,_asnc_reset (data " // Data Bnput

cl$ " // 2loc$ Bnputreset " // >eset input // P output'//-----------Bnput orts---------------input data" cl$" reset

//-----------utput orts---------------output

//------------Bnternal aria#les--------reg

//-------------2ode *tarts Qere---------al)as 0 ( posedge cl$ or negedge reset'i, (<reset' #egin 1 %4#end else #egin 1 data

end



endmodule //@nd , Module d,,_asnc_reset

//-----------------------------------------------------// Design Name : d,,_snc_reset// File Name : d,,_snc_reset.v// Function : D ,lip-,lop snc reset

//-----------------------------------------------------module d,,_snc_reset (data " // Data Bnputcl$ " // 2loc$ Bnputreset " // >eset input // P output'//-----------Bnput orts---------------input data" cl$" reset


//------------Bnternal aria#les--------reg //-------------2ode *tarts Qere---------al)as 0 ( posedge cl$'i, (<reset' #egin

1 %4#end else #egin 1 dataend

endmodule //@nd , Module d,,_snc_reset

//-----------------------------------------------------// Design Name : t,,_asnc_reset

// File Name : t,,_asnc_reset.v// Function : I ,lip-,lop asnc reset//-----------------------------------------------------module t,,_asnc_reset (data " // Data Bnputcl$ " // 2loc$ Bnputreset " // >eset input // P output'

//-----------Bnput orts---------------input data" cl$" reset



//-----------utput orts---------------output //------------Bnternal aria#les--------reg //-------------2ode *tarts Qere---------al)as 0 ( posedge cl$ or negedge reset'i, (<reset' #egin

1 %4#end else i, (data' #egin 1 Hend

endmodule //@nd , Module t,,_asnc_reset

//-----------------------------------------------------

// Design Name : dlatc+_reset// File Name : dlatc+_reset.v// Function : DRAI2Q asnc reset//-----------------------------------------------------module dlatc+_reset (data " // Data Bnputen " // Ratc+Bnputreset " // >eset input // P output

'//-----------Bnput orts---------------input data" en" reset


//------------Bnternal aria#les--------reg

//-------------2ode *tarts Qere---------al)as 0 ( en or reset or data'i, (<reset' #egin 1 %4#end else i, (en' #egin 1 dataend

endmodule //@nd , Module dlatc+_reset



module d,lip,lop (d" cl$" reset"

'

input d" cl$" reset

output

reg

al)as 0 (posedge cl$ or posedge

reset' #egin

i, (reset' #egin

1

end

else #egin

1 SIB2T d

end

end

endmodule

module main

reg d" cl$" rst

)ire

d,lip,lop d,, (d" cl$" rst" '

//Al)as at rising edge o, cloc$

displa t+e signals

al)as 0(posedge cl$'#egin

;displa(KdL#" cl$L#" rstL#"

L#nK" d" cl$" rst" '

end



//Module to generate cloc$ )it+

period % time units

initial #egin

,orever #egin

cl$

&

cl$%

&

cl$

end

end

initial #egin

d rst%

9

d% rst&

d% rst%

8

d rst

end

endmodule

// Design Name : up_counter // File Name : up_counter.v// Function : Up counter //-----------------------------------------------------module up_counter (out " // utput o, t+e counter ena#le " // ena#le ,or counter



cl$ " // cloc$ Bnputreset // reset Bnput'//----------utput orts-------------- output [7:! out//------------Bnput orts-------------- input ena#le" cl$" reset

//------------Bnternal aria#les-------- reg [7:! out//-------------2ode *tarts Qere-------al)as 0(posedge cl$'i, (reset' #egin out 1 54# end else i, (ena#le' #egin out 1 out 3 %end

endmodule

Half adder:

module

+al,adder(a"#"sum"carr'

input a"#

output sum" carr

)ire sum" carr

assign sum aV# // sum #it

assign carr (aW#'

//carr #it

@ndmodule

module main

reg a" #

)ire sum" carr

+al,adder add(a"#"sum"carr'



al)as 0(sum or carr'

#egin

;displa(KtimeLd:L# 3 L# L#"

carr L#nK";time"a"#"sum"carr'

end

initial

#egin

a #

&

a # %

&

a % #

&

a % # %

endendmodule

\\fulladder.v

module ,ulladder(a"#"c"sum"carr'

input a"#"c

output sum"carr

)ire sum"carr

assign sumaV#Vc // sum #it

assign carr((aW#' O (#Wc' O (aWc'' //carr #it

endmodule

\\\testfulladder.v

module main



reg a" #" c

)ire sum" carr

,ulladder add(a"#"c"sum"carr'

al)as 0(sum or carr'

#egin

;displa(KtimeLd:L# 3 L# 3 L# L#" carr

L#nK";time"a"#"c"sum"carr'

end

initial

#egin

a # c

&

a # % c

&

a % # c %&

a % # % c %

end

endmodule

//-----------------------------------------------------// Design Name : up_counter_load// File Name : up_counter_load.v// Function : Up counter )it+ load//-----------------------------------------------------module up_counter_load (out " // utput o, t+e counter data " // arallel load ,or t+e counter

load " // arallel load ena#leena#le " // @na#le counting



cl$ " // cloc$ inputreset // reset input'//----------utput orts--------------output [7:! out//------------Bnput orts--------------input [7:! data

input load" ena#le" cl$" reset//------------Bnternal aria#les--------reg [7:! out//-------------2ode *tarts Qere-------al)as 0(posedge cl$'i, (reset' #egin out 1 54# end else i, (load' #egin out 1 data

end else i, (ena#le' #egin out 1 out 3 %end endmodule

/-----------------------------------------------------// Design Name : up_do)n_counter // File Name : up_do)n_counter.v// Function : Up do)n counter //-----------------------------------------------------module up_do)n_counter (out " // utput o, t+e counter up_do)n " // up_do)n control ,or counter cl$ " // cloc$ inputreset // reset input

'//----------utput orts--------------output [7:! out//------------Bnput orts--------------input [7:! datainput up_do)n" cl$" reset//------------Bnternal aria#les--------reg [7:! out//-------------2ode *tarts Qere-------

al)as 0(posedge cl$'i, (reset' #egin // active +ig+ reset



out 1 54# end else i, (up_do)n' #egin out 1 out 3 %end else #egin out 1 out - %end

endmodule

andom counter:

//-----------------------------------------------------// Design Name : l,sr // File Name : l,sr.v// Function : Rinear ,eed#ac$ s+i,t register //-----------------------------------------------------module l,sr (out " // utput o, t+e counter ena#le " // @na#le ,or counter cl$ " // cloc$ inputreset // reset input'

//----------utput orts--------------output [7:! out

//------------Bnput orts--------------input [7:! datainput ena#le" cl$" reset//------------Bnternal aria#les--------reg [7:! out)ire linear_,eed#ac$

//-------------2ode *tarts Qere-------assign linear_,eed#ac$ H(out[7! V out[6!'

al)as 0(posedge cl$'i, (reset' #egin // active +ig+ reset out 1 54# end else i, (ena#le' #egin out 1 Eout[!"out[&!" out[9!"out[6!" out[8!"out[%!" out[!" linear_,eed#ac$G

end



endmodule // @nd , Module counter

()%& UP*OWN COUNT+&

Sde,ine XBDIQ 5module l,sr_updo)n (cl$ " // 2loc$ inputreset " // >eset inputena#le " // @na#le inputup_do)n " // Up Do)n inputcount " // 2ount outputover,lo) // ver,lo) output'

input cl$ input reset input ena#leinput up_do)n

output [SXBDIQ-% : ! count output over,lo)

reg [SXBDIQ-% : ! count

assign over,lo) (up_do)n' ? (count EESXBDIQ-%E%4#GG" %4#%G' :(count E%4#%" ESXBDIQ-%E%4#GGG'

al)as 0(posedge cl$' i, (reset'

count 1 ESXBDIQE%4#GG else i, (ena#le' #egin i, (up_do)n' #egin

count 1 E<(V(count W SXBDIQ4#%%%%''"count[SXBDIQ-%:%!G end else #egin count 1 Ecount[SXBDIQ-8:!"<(V(count W SXBDIQ4#%%%%''G end end

endmodule

T+%T B+NC,:



module t#(' reg cl$ reg reset reg ena#le reg up_do)n

)ire [SXBDIQ-% : ! count

)ire over,lo)

initial #egin ;monitor(Krst L# en L# updo)n L# cnt L# over,lo) L#K" reset"ena#le"up_do)n"count" over,lo)' cl$ reset % ena#le up_do)n

% reset % ena#le % 8 up_do)n % 6 ;,inis+end

al)as % cl$ <cl$

l,sr_updo)n U(

.cl$ ( cl$ '"

.reset ( reset '"

.ena#le ( ena#le '"

.up_do)n ( up_do)n '"

.count ( count '"

.over,lo) ( over,lo) ''

endmodule

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Vlsi Program -Reference Copy