VLSI System Design for Automotive Control

8/13/2019 VLSI System Design for Automotive Control

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1050 IEEE J O U R N A L OF S OL I D- S T A T E C I R C U I T S , VOL . 2 7 , NO. 7. JU L Y 1992

VLSI System Design for Automotive ControlA n d r e a s L a u d e n b a c h a n d M a n f r e d G l e s n e r

Abstract-This paper presents a novel VLSI approach forcombustion engine control. The approach is based on a real-time solution of a thermodynamical differential equation. Thecontrol system calculates an optimum ignition point by fastmeasurement and real-time processing of signals as tempera-ture, pressure, and volume of the combustion chamber. Therequired computational power cannot be met with standardsignal processors. We present the design of a mechatronic sys-tem that is based on an application-specific vector architecture.Each design step from the analysis of the heat release algo-rithm, the optimization of the algorithm and the dataform, themapping on an architecture, the physical design of the test chipset and the single chip, the chip test, and the system integrationis presented. Finally, the application at an engine test-standand results are shown.

I . INTRODUCTIONN this long-term research project activities are focusedI n a novel approach for combustion engine control,which is based on the measurem ent of the pressure in thecombustion chamber and on the real-time calculation ofthe heat release. The first realization of the microelec-tronic subsystem for thermodynamical analysis was im-plemented with a commercial DSP. Because of the lim-ited computational power of this solution, a heat releasealgorithm with many simplifications had to be used. Thephysical behavior of the combustion is modeled with moreaccuracy if energy losses over the chamber wall are in-corporated and if the combustion-dependent gas constantis described more exactly. In this case the heat release isdefined implicitly and the calculation is based on the so-

lution of a nonlinear differential equation. The real-timesolution is not possible with a commercial processor. A sa consequence a parallel VLSI architecture tuned to thisspecific application was developed.For working with the comp uter system as an evaluationtool for mechanical engineering, some requirements hadto be met:high computat ional power is provided by parallelprocessing arithmetic units;high data throughput is ensured with a multiplexedand pipelined data path w ith three data memory m od-ules on the chip;

Manuscript received December 2, 1991; revised February 28, 1992. Thiswork was supported by the German National Science Foundation (Deutsch eForschungs-gemeinschaft) under Project SFB 24 1 IMES (Integrated Me-chano-Electronic Systems).The authors are with the Institute of Microelectronic Systems, DarmstadtUniversity of Technology, D-6100 Darmstadt, Germany.IEEE Log Number 9200153.

optimized program code is generated with a ma-croassembler that supports arithmetic operations onscalar and vector data;ful l f lexibi l i ty is provided with off-chip programmemory. The actual program code is stored in faststatic R A M .11. M A T H E M A T I C A LODELOF A COMBUSTIONNGINE

State-of-the-art combustion engine control systems [11determine the ignition point either in open-loop controldepending on the load of the engine and the revolutionsper minute or in closed-loop control by knock detection.Thermodynamical parameters of the combustion are nottaken into account. In a novel approach for engine control[ 2 ] , ach combustion is analyzed thermo dynam ically. Thefundamental parameter of the control algorithm is the heatrelease dQ,/dcp as a function of the crank shaft angle cpThe heat release has a great influence on the engine'seconomy and on the exha ust. Th e heat release can be cal-culated w ith the pressure p(cp) in the combust ion chamberand the volume V p) and the differentials of these func-tions dp(cp) and dV(cp).With the law of conservation of energ y, the heat releasebecomes

(1)where U is the internal energy of the air/fuel mixture,Q w a l l s the heat due to energy losses over the cylinderwalls, and p dV is the mechanical work on the piston.From the ideal gas equation follows:

dQ8 = dU + dV + dQwall

(2)= - P ' VR mwhere Tis the gas temperature, R, is the gas constant, an dm is the mass of the air/fuel mixture.With an empirical power series expansion [3], the in-ternal energy becomes

U = ko k l . T k2 * T 2 k 3 . T 3 . ( 3 )The energy loss over the chamber walls , which is inducedby convection, is calculated as

(4)where A w a l ls the combustion cham ber surface, T w a l ls thecylinder wall temperature, wh ich is set constant, an d w isthe angular speed. With the average piston speed c , ~ ,hecoefficient (Y of heat conductivity [4] is

* ( c , + 1.4)O. . ( 5 )130 . V 0 . 06 . PO.' *0018-9200/9 2 03.00 992 IEEE


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L AUDE NBACH A N D G L E S N E R : VLSI SY STEM D ESI G N FOR AUT OM OT IVE CONTROL 1051

At this point the heat release could directly be calcu-lated. But in the burning fuel mixture the ideal gas con-stant R , is not constant; it is still a function of the com-bustion ra te. Th e resulting differential equ ation is of firstorder and nonlinear. The differential equation is solvedwith an iterative method which can be processed in par-allel. The iterative algorithm calculates a start solutiondQF' with constant R, and the heat due to energy lossesover the cylinder walls set to zero (dewall 0). In the ithiteration we use the old integral h eat release

c p ) = d Q $ - dp (6))and the old maximum Q ,,QIo calculate the new air/ex-haust ratio r ( p ) ( ' ) :

The parameters rendand r , tan re calculated in the initialphase before the combustion starts. Now the gas constantR, = R,( p(cp), r ( p ) , T(cp))can be calculated as2 9 . 0 + A(cp) p(cp)

A , B , and C are power functions of r with a fractionalexponent between zero and one. W ith R (p) and (1)-(5)a new heat release dQB c p ) (' ) can be calculated. Th e anal-ysis is done over a range of 128 crank shaft angle witha step size of 1 Th e iteration is repeated until the vari-ation of the integral heat release is less than 0.1 :(9)

111. DEVELOPMENTF A L G O R I T H MND ARCHITECTUREA. Computation Time Requirements

Heat release calculations with sampled input data aredemonstrating that with two runs through the iterative loopthe variation of the integral heat release is always lessthan 0.1 . This is the iteration stopping criterion. Forgenerating the start solution and two times runningthrough the iteration loop it is necessary to do 218 addi-tions, subtractions, and multiplications and 14 divisions.Since the analysis is done over a range of 1 28 crank shaftwith a resolution of 1 , each operation has to be per-formed 128 times. A sequential calculation of the heatrelease must not be long er than the tim e for sampling onepressure signal. T he signals are samp led with a resolutionof 1 crank shaft. If the engine is running with the m ax-imum revolution speed of 6000 rpm, the resulting com-putation time will be about 20 p s which is not sufficientfor the sequential calculation of 232 mathematical oper-ations including 14 divisions. If the algorithm is pro-cessed after the sampling period, real-time capability will

be reached, if the computation has finished after 50 crankshaft. At a maximum revolution speed of 6000 rpm the50 angular interval corresponds to 1 .35 ms. T he requiredcomputational power can be reached only with parallelprocessing, either with a multiprocessor board or with asingle chip that has parallel processing units. Since theaim of the project is an integrated solution, the develop-ment of a single-chip parallel processor is the only ac-ceptable w ay.B. Data Format

Simulations on behavioral level with different sampledinput signals demonstrate that the intermediate results canvary over 12 orders of magnitude. This dynam ic is causedby variations of the input signals, which are amplified byarithmetic operations. For example, the pressure inputsignal has a range from 0.01 to 10 MP a. Th e internal dataformat must be abl e to represent each va lue with sufficientaccuracy. The simulations have shown that a fixed-pointrepresentation requires 52 b, whereas a floating-point for-mat with 20 b provides sufficient accuracy and dynamicfor the heat release algorithm. Th e floating-point formatwas preferred because a 52-b bus would result in a bigarea and power consumption. The optimized floating pointdata format has 12 mantissa bits, a sign bit, and sevenexponent bits. The dynamic of the number rep resentationis 38 orders of magnitude.C . Architecture

Due to the use of a floating-point data format, the arith-metic units get quite complex because mantissa and ex-ponent must be processed in a different way and costlyerror handling bec omes necessary. This influences the ar-chitecture because it is not possible to integrate manyarithmetic units on a single chip. The heat release algo-rithm cou ld easily be m apped on a parallel sing le-instruc-tion multiple-data (SIM D) architecture with next-neigh -bor connections. But since the SIMD architecture isworking efficiently only if a great number of arithmeticunits are realized, the integration on a single chip is notpossible.Another parallel processing concept to map the algo-rithm easily is vector processing. Here the data are pro-cessed very efficiently with the principle of an assemblyline [5], [6]. The implementation of the heat release al-gorithm on a vector architecture, as shown in Fig. l , im-plies that the input signals and intermediate results areprocessed as vectors. Each degree of crank shaft anglerepresents one vector component. T he vector size is 128.All algorithmic operations except the integration are vec-tor operations. The long vectors make the design of arith-metic units (AU's) with deep pipelines of four to ten stagesvery efficient. The first A U is able to perform a multipli-cation o r division alternatively, while the second o ne canalternatively add or subtract two floating-point numbers.The most frequent operations are of the multiply-add,multiply-subtract, divide -add, or divide-subtract typ e.


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1052 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 7 . J U L Y 1992

Adder/Subtractor

Fig. 1. Architecture and paritioning of the vector processor

This is the reason why the output of the mu ltiplier/dividerunit is connected to the input of the adder/subtractor unit.The advan tage of this connection is that only three insteadof four data memory accesses per clock cycle are neces-sary. If the pipeline is filled, tw o floating-point o perationsper clock period will be processed. The memory is di-vided in on-chip memory modules and an off-chip RAM.The need to feed three data into the AUs requires eitherone high-speed on-chip RAM with a high-speed bus orseveral vector memories with a crossbar network. Thecrossbar switch was realized with bus multiplexers; thevector mem ories were realized with shift registers of 128words times 20-b size. The shift registers can store threesignal vectors o r result vectors. Th e advantage of this so-lution is a relative moderate clock, while in each clockperiod two floating-point operations are processed .

D. Algori thmThe differentiation df c p ) is approximated by the secantthrough the points cp + 1) and cp 1). The integra-tion is performed with the trapezoidal method. The ap-proximation of power functions with fractional exponentand exponential functions is performed with power seriesexpansion. A special tool for the determination of the ap-proximation constants with least-squares optimizationtechnique was developed. The user has to specify thefunctions that will be approximated , the range of possible

arguments , and the a l lowed error tolerance. The globalapproximations are based on orthogonal polynomials thatmeet the required accuracy over the whole argumentrange. Therefore the approximations are calculated easilyin parallel becau se for each argument the approxim ationconstants are identical. Compared to Spline interpolationmethods, which also could be possible, the processor has

to calculate polynomials of higher o rder. But this is not adrawback because t ime-consuming memory accesses forthe fetching of Spline coefficients that are different foreach vector component are avoided.I V . P H Y S I C A LESIGN N D TEST

Due to the comp lexity of the different processor blocks,which mainly resulted from the floating-point data for-mat, no commercial library was available. As a conse-quence a library of macrocells has been designed. Thelibrary contains module generator based cells like float-ing-point multiplier/divider and adder/subtractor, vectormemory modules, static and dynamic registers, and busmultiplexers. A set of input, output, tristate, bidirec-tional, and supply pads has been designed w ith the layouteditor and extractor of the Cadence design framework.Each macrocell must be parametrizable with regard to thefloating-point format in order to permit the optimizationof computation accuracy, floorplaning, and the data for-mat of the vector architecture in parallel to the macrocelldesign process.For that purpose, and also to be independent from de-sign rule variations, the macrocells we re designed by us-ing a symbolic design environment [7]. The layout s t ruc-ture of the different blocks was describ ed with a symb oliclayout language on a virtual grid. Th e language offers theuse of procedural statements to permit an efficient pa-rametrization. The transformation of this description tothe final coordinates is performed by two one-d imensionalcompaction steps which are based on a modified most re-cent layer algorithm. A local two-dimensional compac-tion step follows to improve the overall result. A com-pacted layout and netlists for SPICE and switch-levelsimulation are gen erated.

A . Design of Complex Modules1 ) Multiplier/Divider Unit: The mult ipl icat ion anddivision unit con tains a full pipelined circuit which is ded-icated to floating-point computations. The implementedalgorithms are a space expanded add-shift algorithm formultiplication and a restoring division algorithm. Formonitoring the operation s, a set of five error flags is pro-vided: overjlow, underjlow, division by zero , i l legal op-erat ion , and operation aborted. The mult ipl icat ion anddivision unit is designed to generate one result per clockcycle. Th ere are no restrictions on the interlacing of mul-tiplications or divisions in consecutive clo ck cycles.F ig. 2shows that the multiplier/divider unit is subdi-vided into the mantissa data path and the exponent datapath, including sign bit processing and error flags gener-

ation.a) Mant issa data path: The mantissa data path con-tains an initialization stage, the adde r a rray , and a pos t -normalization circuit . The structure of the adder array isbasically restricted by the restoring division algorithm: thequotient bits have to be calculated in a most significantbit to least significant bit order. Based on this circuit


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LAUDENBACH AND GLESNER: VLSI SYSTEM DESIGN FOR AUTOMOTIVE CONTROL I053

Mantissamantissa initial.

mantissaadder array

mantissapostnormalization

Exponent Sign

exponentcalculation

exponentadjustmenterror flags

8

n

Fig. 2. Multiplieridivider block structure

structure the multiplier bits also have to be evaluated inthe same order. As a result of this strategy the carry-outbit of each adder row must b e taken into account by a finaladdition creating the most significant half of the productword. Fo r division, the sign of each generated partial re-mainder must be accessible from the adders for use in thecontrol circuit. This prohibits the use of carry-save add-ers. For that purpose carry-select adders are used to pre-vent both the high wiring cost of carry lookahead tech-niques and the low speed of carry ripple adders.

b Exponent data path: The exponen t data path con-sists mainly of two carry-select adde r rows (for exponentcalculation a nd adjustment) and a lot of random logic forthe generation of the error flags. The first adder row isexecuting the addition and subtraction of the exponentswhich is required for multiplication and division of thetwo operands, respectively. The second is used to gener-ate a correct biased exponent (bias = 2 ' - ' 1) and ittakes a possible mantissa postnormalization into accoun t.The random logic circuit is able to detect overflow or un-derflow of the result as well as ope rations with illegal o p-erands (e .g. , 03 . 0, O / O 03/03). On overflow, the cor-responding flag is set and the result is set to 03 (representedby an exponent e = 2' 1); underflow causes the resultto be zero (represented by an exponent e = 0). If an il-legal operation is detected the illegal flag will be set andthe result outputs will be undefined .2 ) AdderlSubtractor Unit: The addition/subtractionunit is divided into three sections seperated by pipelineregister stages which represent the basic operations offloating-point addition o r subtraction:

1) denormalization,2) kernel calculate operation,3) normalization.

The inherent equality of addition and subtraction is usedto reduce the complexity of the arithmetic unit. Th e equa-tions of the sum and the difference bit are identical. Theequations of the carry and the borrow bit differ only bythe value of X:addition: subtraction:s = x e y e c i , D = X e Y e B , ,CO,,= X(Y v Gin) v YCln Bo , = l X ( Y V Bin) V YBin.

The sam e circuit will be used for addition and subtraction,if the negation of X is available for the calculation of theborrow bit. By multiplexing the absolute input values itis always guaranteed that the smaller value is subtractedfrom (or added to) the greater value [8]. Th e result of theoperation cannot be negative. Logic for complementationand an addit ional adder are saved.Th e kernel of the added subtra ctor unit is a carry-selectadder. The carry-select adder combines the advantages ofhigh calculation performance power and simple parame-trization. Th e basic adder that is designed in pass-transis-tor logic is modified with three 2 : 1 multiplexers to allowaddition and subtraction with the sam e circuit.The multiplier/divider unit and the added subtra ctor unitcan operate in test mode. Then all the pipeline registersare sequentially linked to form several scan paths.3) Vector Memory Module: The vector memory is re-alized with shift registers that provide a sequential mem-ory organization. It is not possible to fetch one arbitraryvector componen t in one cycle. But this is not a drawbackbecause all operations of the algorithm are vector opera-tions. The sequential memory organization instead ofRAM has the advantage that no address calculation is nec-essary. This saves either area for on-chip address calcu-lation logic or additional pads and prog ram mem ory if theaddresses are generated from a compiler.The basic shift-register cell for storing 1 b is a semi-static flip-flop. The information will be shifted into themaster if 4 and a shift signal are at logic high level. Ifthe shift signal is at logic low level the information willbe stored statically in the master. The master is able tohold information statically over a long period of tim e, be-cause two inverters are connected ring-like and build apositive feed back loop. T he slave stores information onlydynamically. The logic value is refreshed from the signalin the master in each cy cle with 42at logic high level.Several vector variables are used more than o ne time inthe algorithm. This is the reason why a feedback modeand a multiplexer at the input of the shift register are pro-vided. If the feedback signal and the shift signal are setto logic high level, the outpu t of the shift register will beconnected to its input. After 128 shift operations in thefeedback mode the vector variable is in the original stateagain. Since a vector in the combu stion rate algorithm has128 components and the optimized data format has 20 b ,the shift registers have 128-word X 20-b organization.The layout of the generated shift register is extremely reg-ular. T he transistor density of the macrocell is more than7000 t rans is tors /mm2 in a 1.2-p m CMO S process .B. Multichip Project

For the first realization of the vector processor, thewhole architecture has been partitioned into differentmodules, as shown with the dotted lines in F ig . 1 . Thefabrication of the partitioned processor blocks has the ad-vantage that each module can be tes ted independentlyfrom each other. Together with test chips from other pro-jects a m ultichip wafer with eig ht test chips was processed


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Fig. 3 . Microphotograph of the multichip wafer.

Chip Type Macrocell Size Chip Sire Trans sto rs Clockvector memory 4098 pin x 814 p m 5040 p x I S84 p 26 no0 6 M H 7adderisubtractor 1703 pni x 1846 pni 5264 pni x 4168 p m moo S M H rmultiplieridivider 5212 p x 3462 pni 5928 pni x 4160 pni 31 000 36 M H z

in a 1.2-p m CMO S technology. In Fig. 3the micropho-tograph of the multichip project is shown. The multichipwafer contains three modules of the vector processor:floating-point multiplier/divider (right side at thebottom),floating-point addedsubtractor with some circuitryfor fast integration a nd search of a maximu m vectorcomponent (left side at the bottom),vector memory (right side in the middle).

In the test phase the correct function of each test chip wasverified successfully. The sizes of the test chips and themaximum clock frequencies are shown in Table I . T h emaximum clock frequency of the addedsubtractor is lowcompared to the other modules. This is caused by power-ground bouncing induced by the buffers in the output pads.The multiplier/divide r unit is operating with a clock of 36MHz. This is the highest possible two-phase nonoverlap-ping clock that can be generated with the tester.

C. Single-Chip V ector ProcessorThe different blocks of the whole vector architecture,shown in Fig. 1, are placed and the signal lines betweenthem are routed by a floorplanning tool that is based onsimulated annealing [7], [9]. The underlying layout model

used in this tool is the well-known slicing structure. Thefloorplanner and the macrocell generator are stronglylinked to permit a fast design cycle. The floo rplanner gen-erates a layout, in which all the signal lines of the corecells as well as the signal lines to the pad cells are routed.The supply rails of the macrocells must be inserted byhand. Desing improvements over the test-chip set include

Fig. 4. Microphoto of the single-chip vector processoi

a physical seperation betw een the power supply of the padcells and the powe r supply of the core cells. In the adder/subtractor macrocell two buffers that drive critical nodesare designed with low er impedance. T he layout of the sin-gle-chip vector processor is shown in Fig. 4.The layoutof the whole vector processor as a single chip generatedin a 1.2-pm CM OS process has a s ize of 7.2 mm X 7 . 3mm and contains 120 000 t rans is tors . The chip has 68pins, including 14 power pins and 5 test pins. The single-chip vector processor has been fabricated and has SUC-cessfully been tested u p to the maxim um clock frequ encyof 33 M H z .


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LAUDENBACH AND GLESNER: VLSI SYSTEM DESIGN FOR AUTOMOTIVE CONTROL ss

control ~code

V . SYSTEMNTEGRATIONN D APPLICATIONFig.5 shows the prototype vector processor board. W iththis board the single-chip vec tor processor is emulated andthe whole system is tested. The partitioned processorblocks, show n with the dotted lines in Fig . 1 , are realizedby the tes t chips . Two programmable logic devices areused for the implementation of the crossbar network andoff-the-shelf registers are used fo r the buffering of fetch edinstructions and data. The programmable logic deviceslimit the system clock to 5 MHz.The heat re lease computer contains a comm ercial mi-crocontroller and the vector processor board with programand data mem ory as shown in F ig. 6 . The microcontrol leris used for controlling the analog-to-digital converterboard and the vector processor board, synchronizationwith the combustion engine, preprocessing of the inputsignals, download of the program code for the vector pro-cessor into the program RAM, and interfacing to aHP9000/series 300 host com puter .The vector processor board is mounted in a PC racktogether with the A/D converter board, the microcon-trol ler board, the vector processor board, and the d ata and

program memory board. Optimized program code for thevector processor is generated with a macroassembler. Themacroassembler supports s imple and com posed ari thmeticinstructions for scalar and vector data types and specialarithmetic functions such as search of a maximum vectorcomponent, integration, and differentiation of a vector.The heat release algorithm is described very efficientlywith the assembler language, which contains symbolicvariables and constants, as well as loop statements. Theassembler generates up to 3 2K l ines l inear machine code.The instruction word contains 35 b. Th e heat release com -puter is a part of a mechatronic system fo r ignition co ntrolwhich is installed at an engine test-stand in the Depart-ment of Mechanical Engineering at Darmstadt Univer-sity.

to the hostadress bus 12 bit)

VI. RESULTSA set of test chips has been fabricated successfully. Aboard with the test chips for the emulation of the single-chip vector processor was built. The system clock of theemulation board is limited to 5 MH z because of the useof programm able logic devices (PLD s). Th e heat releasealgorithm is calculated with the emulation board in 4.6ms with a perform ance of real 6.5 MF LO Ps. Th is is nearlythe same time as used by the implementation on a stan-dard 32-b digital signal processo r with integrated floating-point unit. Th e heat release computer is successfullyworking at an engine test-stand. A single-chip version ofthe vector processor has been fabricated successfully. If

the algorithm is processed on the single-chip vector pro-cessor, the computat ion t ime will be 1.15 ms, so that thereal-time requirem ent of 1.3 5 ms will be met. T he imple-mented heat release algorithm will run with real 25.8MF LOP s , so that the maximum performance of 40MFL OPs of the vector processor is occupied to 64 . Thevector processor contains 120 000 transistors, while a

v

2 portdata

data[l..20]vectorprocessor \

Fig. 5 . Vector processor emulation board

-- data[l..20]

resetcount

crank shaft angleINTEL80960 top dead center

I I

32-b digital signal processor has at least about 400 000transistors. Th e application-specific architecture brings asignificant reduction in transistor count and computationtime. W ith the presented system it will be possible for thefirst time to imp lement control algorithm s for combustionengines which are based on a thermodyn amical evaluationof each combustion in real time.

A C K N O W L E D G M E N TThe VLSI test chip set and the single-chip vector pro-cessor have been fabricated by Intermetall Deutsche ITTIndustr ies company in Freiburg on their 1.2 -pm CM OSprocess . The authors would l ike to express their thanks toIntermetall for the support.

REFERENCES[ l ] U . Adler, Kom biniert es Zuend- und Benzineinspritzsystem mitLambda-Regelung: Motronic, Bosch GmbH: Reihe Technische Un-

terrichtung, Stuttgart, Germany, 1985.[2] A. Laudenbach, M. Glesner, G. Hohenberg, E. Nitzschke, and D.Koehler, Real time heat release calculation for combustion engines,presented at the ISATA Conf. Mechatronics, Florence, Italy, 1991.[3] A . Pischinger, Thermodynamik der Verbrennungskraf tmaschine .Berlin: Springer Verlag, 1989.141 G . Hohenberg, Experimentelle Erfassung der Wandwaerme van Kol-benmotoren, Habilitation thesis, Tech. Univ. Graz, Graz, Austria,1980.


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[S K . Hwang, Computer Architecture and Para llel Processing. NewYork: McGraw-Hill, 1985. chaft.[6] H. S . Stone, High Performance Computer Architecture. Reading,MA: Addison-Wesley, 1990.[7] N. Wehn, Efficient methodologies for the physical design of MOS-VLSI circuits, Ph. D. dissertation, Darmstadt Univ.. Darmstadt, Ger-many, July 1989.

Mr. Laudenbach is l member of the Deutsche Physikalische Gesells-

181 K . Hwang, Comuuter Arirhmetics. New York: Wilev. 1979.191 1. Schuck: N . Wehncompiler system: Ipresented at the 24th

< .I , M. Glesner, and G Kamp, The ALGIC siliconmplementation, design experience and results,I Design Automation Conf.. Miami, FL, June 1987.Andreas Laudenbach received the diploma inphysics from the Darmstadt University of Tech-nology, Darmstadt, Germany, in 1987. He is cur-rently working towards the Ph.D. degree at theInstitute of Microelectronic Systems at the sameuniversity.His research interests cover CMOS VLSI cir-cuit design and the design of application-specificintegrated processors for the development of mi-croelectronic subsystems in mechatronic applica-tions.

Manfred Glesner graduated from the SaarlandUniversity, Saarbruecken, Germany, in appliedphysics and electrical engineerin g in 196 9. In 1975he received the Ph.D. degree from the same uni-versity.Since 198 he has been a Profess or of ElectricalEngineering at Darmstadt University of Technol-ogy, Darmstadt. Germany, where he is engagedin research on CAD tool development and VLSIcircuit design. He has been active in the field ofCAD for electronic circuits for 20 years and haspublished more than 50 papers. Current work cove rs silicon compilation,digital signal processing, and innovative system applications of microelec-tronics.Dr. Glesner is a member of several technical societies.

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VLSI System Design for Automotive Control