vlsi testing

VLSI Design

Chapter 5

CMOS Circuit and Logic DesignJin-Fu Li

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityChapter 5 CMOS Circuit and Logic DesignCMOS Logic Gate DesignPhysical Design of Logic GatesCMOS Logic StructuresClocking StrategiesI/O StructuresLow-Power Design

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design IssuesHierarchical designArchitecture levelRTL/logic gate levelCircuit levelLayout levelCritical paths the path with the longest delay that require attention to timing detailsThe number of Fanins and Fanouts affects the performance of the circuits

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityConcept of Fanin and FanoutFanin The fanin of any complex gate is defined as the number of inputs of this gateFanoutThe fanout of a complex gate is defined as the number of driven inputs attached to the output of this gateNNFanout=NFanin=N

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design NAND GateRp = the effective resistance of p-device in a minimum-sized invertern = width multiplier for p-devices in this gatek = the fanout m = fanin of gateCg = gate capacitance of a minimum-sized inverterCd = source/drain capacitance of a minimum-sized inverterCr = routing capacitance

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design Fanins and Fanouts

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design NAND Gate Rise TimeSeparate delay into internal delay and external delay caused by fanouts

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design NAND Gate Fall TimeWe want the rise time to be equal to the fall timeHence we must design , thus the delay time is

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityTypical CMOS NAND & NOR DelaysCapacitive load (pf)Delay (ns)Delay (ns)Capacitive load (pf)

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design Gate Delays

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design Efficient Resistance

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design 8-Input AND GateApproach 1Approach 2Approach 3ABCDEFABCDEFGHGHBCDEFGHACLCLCL

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLogic Gate Design 8-Input AND Gate

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityBasic Physical Design Gates: Inverter, NAND, and NORComplex GatesStandard CellsGate ArraySea of GatesLayout OptimizationTransmission Gates2-Input Multiplexer

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design CMOS Inverter azVssVddazVssVdd

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design NAND Gate azVssVddazVssVddbb

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design NOR Gate azVssVddbazVssVddb

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Complex GatesAll complex gates can be designed using a single row of N-transistors and a single row of P-transistors, aligned at common gate connectionsDesign procedureDraw two dual graphs to P transistor tree and N transistor treeFind all Euler paths that cover the graphFind a P and an N Euler path that have identical labelingIf not found, break the gate in the minimum numbers of places to achieve step 3

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Complex Gates AZI2I1BABCDCDI3I3I1I2ZABCDVDDZVss

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Complex GatesABCDABCDzVddVssABCD

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design XNOR Gate (1)ABZzVddVssABZZABZABZ

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design XNOR Gate (2)ABZzVddVssAB

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Automated ApproachABEDCEABEDCVddVssVddVssABEDCABEDCPN

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Standard-Cell ApproachWVddWpWnWVssDnpabczd

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Standard-Cell LayoutVddVddVssVssabcabczz

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Gate Array Layout (1)VddVss

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Gate Array Layout (2)VddVssGate array cellsRouting channels

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Sea-of-Gate LayoutVddVsssupplysupplywell contactssubstrate contactspoly gatesP-transistorsN-transistors

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Sea-of-Gate (NAND3)abczabcabcz

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design CMOS Layout GuidelinesRun VDD and VSS in metal at the top and bottom of the cellRun a vertical poly line for each gate inputOrder the poly gate signals to allow the maximal connection between transistors via abutting source-drain connection.Place n-gate segments close to VSS and p-gate segments close to VDDConnection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Improvement in DensityBetter use of routing layers routes can occurs over cellsMore merged source-drain connectionsMore usage of white space in sparse gatesUse of optimum device sizes the use of smaller devices leads to smaller layouts

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Layout OptimizationFclkAAAAFVddVssAAAAclk

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Layout OptimizationZABCDVddVssABCDRightWrong

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design Transmission Gate

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhysical Design 2-Input Multiplexerabczc-cabzzc-c

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic Pseudo-nMOS Logic for

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic Dynamic CMOS Logic

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic Clocked CMOS Logic

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic Pass-Transistor Logic ComplementarySingle-polarityCross-coupled

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic CMOS Domino Logic Basic gate

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic CMOS Domino Logic Static versionLatched version

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic CMOS Domino Logic

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic NP Domino Logic

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS LogicAdvantages of Dynamic LogicSmaller area than fully static gatesSmaller parasitic capacitance, hence higher speedGlitch free operation if designed carefully

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic CVSLBasic versionA particular function

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCMOS Logic CVSLClocked versionA 4-way XOR gate

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Clocked SystemsA simple finite state machineCombinational Logic

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Clocked SystemsA pipeline system

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Latches and Reg.

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Latches

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Registers

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies JK RegistersA B J=K=0; Q=DJN=KN=1; A=QN, B=1; D=AN=QJ=0;K=1KN=0,JN=1; A=1, B=1; D=0J=1; K=0KN=1, JN=0; A=QN, B=Q; D=1;J=1; K=1KN=0, JN=0; A=1, B=Q; D=QN

KJQNQ

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies System Timing

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies System Timing: the clock-to-Q time of latch A: the setup time of latch BSimilarly,Finally,

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Setup & Hold TimePadPadFor an ideal DFF,If is high when , then Q should be highIf becomes to low when , then Q still is high

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Setup & Hold TimeWhen , should become high earlier and Q can become highWhen , should retain at high longer and Q can be still at high

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Setup & Hold TimeTdc Tdq Tdl q1 d2 Tdc 1. When Tdc>Tdq+Tdl, M2 latches the New data2. When Tdq+Tdl-Tdc>TC , M2 latches Old data twiceTherefore, 0

*EE613 VLSI DesignNational Central UniversityClocking Strategies D Register

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Clock Skew

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking StrategiesSkew Clock Pipelineclkclk1clk2-2ns0nsCL1(5ns)CL2(9ns)CL3(5ns)FFFFFFFF7nsclkclk1clk2ABCDABCDAB-2nsclk3Aclk3CDBC

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Latches-clkclkLow area costDriving capability of D must override the feedback inverter-clkclkclk-clk

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Latches-clkclkVssVdd

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies DETDFFclkclkD-DQ1-Q1Latch 1Q1clk

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies DETDFFclkclkD-DQ2-Q2Latch 2Q2clk

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies DETDFFclkLatch 1 enabledLatch 2 enabledQ2=-Q2=lowQ1=-Q1=highLatch 2-QQQ2-Q2DLatch 1-Q1Q1clk

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Registerclk-clkclk-clk-clk-clkclk-clk-resetDQAsynchronously resettable register clk-resetQ

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Registerclk-clkclk-clk-clk-clkclk-clk-resetDQAsynchronously settable and resettable register -set

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Dynamic Registersclk-clkDDDclk-clkclk-clk-QDclk-clk-Q-clkclkQclk-clkD-clkclkQDynamic single clock latchesDynamic single clock registers

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Strategies Single ClockLogicLogicL1L2clock

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityDynamic Latches Single-Phase ClockingCLKDXQXnQnDnCLK0110HHLL10 101 Xn-1Qn-1Qn-1CLKDX-QClock active high latchClock active high latch with buffer

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityDynamic Latches Single-Phase ClockingCLKDXQXnQnDnCLK0110LLHH10 101 Xn-1Qn-1Qn-1Clock active low latchCLKDX-QClock active low latch with buffer

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityDynamic Latches Single-Phase ClockingCLKDXQClock active high latch without feedbackClock active low latch without feedbackCLKDXQAssume that the capacitance of node Xis 0.002pF and the leakage current I is 1nA.Therefore, T=CV/I=0.002pFx5V/1nA=100us.That is, the latch needs to be refreshed each 100us.Otherwise, the output Q will become high.

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityDynamic Registers TSPCPositive edge trigger registerCLKDA-QBCLKDAB-QThe value of the hold time of this flip flop is close to zero.tftr

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPLL for synchronizationPhase Locked Loop Clock TechniquesT1T2clockdclkdata outclockdclkoutput paddclk+dpadclock padclock routechipclockdclkdata outT2T1=Input buffer delay+routing RC delayT2=Clock-to-Q delay+output buffer delayPLLclock

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhase Locked Loop Clock Multiplyingdclkoutput paddclk+dpadclock padclock routechipPLL/4clockdclkclockPLLPLLsystem clockclockclockbusClock-multiplying PLLSynchronize data transfer between chipsSynchronize the output enable signalsReduce tristate fightsImprove overall timing

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityTypical Phase Locked LoopPhase DetectorCharge PumpFilterVCOProgrammableFrequency divider(/n) reference clock fnUDnxfnVcVdd

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhase Locked Loop Phase DetectorclkextclkUPDNNOPclkextclkclkextclkRSQ

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityCharge pump circuitsPhase Locked Loop Charge PumpOutOutVrefpVrefnPrefNrefBiased by current mirrorThe output current of the charge pump can be adjusted through the control of the current mirror.

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversitySimple implementation of low-pass filter

The two capacitors C1 and C2 are in the order of tens of pFThe capacitor C2 is added in parallel to the simple RC low-pass filter to form a second order filterThe stability of the system is maintained even with the process variation of these on-chip componentsNote that these capacitors can occupy a large portion of the PLLPhase Locked Loop Low-Pass FilterInOutTGNC2NC1

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhase Locked Loop VCOOdd number of stagesControl voltagefVCOCurrent-starved inverter type VCOIIVIControl voltagetintin+tVoltage-Controlled Delay Line (VCDL) type VCOV-I converterDelay cell

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhase Locked LoopUDVcLow-pass filterVCOfoutfinfoutfinDPhase Detector

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityPhase Locked Loop Programmable VCOVCV-I converterDelay cellDelay cellDelay cellShift registerGenerated clock

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityNP-Domino LogicAllow pipelined system architecture

Single-Phase Logic NP Domino LogicnMOSLogicpMOSLogicclk-clkclk-clkclk sectionThe circuit performs precharge-discharge operation when clock is low, and all stage evaluate output levels when the clock is high.

EE613 VLSI Design

*EE613 VLSI DesignNational Central University-clk section

Single-Phase Logic NP-Domino Logic nMOSLogicpMOSLogic-clkclk-clkclkThe circuit performs precharge-discharge operation when clock is high, and all stage evaluate output levels when the clock is low.

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityA pipelined NP-Domino CMOS system

Single-Phase Logic NP-Domino Logic clksection-clksectionclksectionABCa0a1AclkBCc0b0b1b2a2b1b2

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityUses of clock skew to extend clock cycle (not recommended)

Single-Phase Logic Clock SkewLogicdelayTd2Tc1clockold datanew dataTc1Td2clock< Tc1Td2

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityLock-up Latch

Contra-data-direction clock

Single-Phase Logic Avoiding Clock SkewLogicdelayclockLock-up latchLogicclockdelay

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityDynamic register

Two-Phase ClockingQD-ph1ph1-ph2ph2ph1ph2ph1=1,ph2=0ph1=0,ph2=1C1C2C1C2

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityFailure due to clock skew

Two-Phase Clockingph1ph2ph1=1,ph2=1C1C2

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityTwo-phase registers with single-polarity clocks

Two-Phase Clockingph1ph2ph1ph2

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityIn a large CMOS chip, clock distribution is a serious problemVdd=5VCreg=2000pF (20K register bits @ 0.1pF)Tclk=10nsTrise/fall=1nsIpeak=Cdv/dt=(2000px5)/1n=10APd=CVdd2f=2000px25x100=5WMethods for reducing the values of Ipeak and Pd Reduce CInterleaving the rise/fall time

Clock Distribution

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking is a floorplanning problem because clock delay varies with position on the chipWays to improve clock distributionPhysical designMake clock delays more evenAt least more predictableCircuit designMinimizing delays using several stages of driversTwo most common types of physical clocking networksH treeBalanced treeClock Distribution

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Distribution H Tree clock

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Distribution Balanced Tree clock

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Distribution Reducing Power Techniques used to reduce the high dynamic power dissipationUse a low capacitance clock routing line such as metal3. This layer of metal can be, for example, dedicated to clock distribution onlyUsing low-swing drivers at the top level of the tree or in intermediate levels

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityClocking Distribution Half-Swing Driver C1C3C2C4CACBVddGndClockVoutclknclkp-clkn-clkp

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityTypes of padsVdd, Vss padInput pad (ESD)Output pad (driver)I/O pad (ESD+driver)All pads need guard ring for latch-up protectionCore-limited pad & pad-limited pad

I/O Structures Pads PADPADI/O circuitryI/O circuitryCore-limited padPad-limited pad

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityInput Pads ESD Protection PADInput pad without ESD protectionAssume I=10uA, Cg=0.03pF, and t=1usThe voltage that appears on the gate is about 330voltsInput pad with ESD protectionPAD

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityI/O Pads Tristate & Bidirectional Pads PADTristate padPADBidirectional padOUTPNOEDdataoutput-enableOUTPNOED011X01010110Z01

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityInput Pads Schmitt Trigger CircuitTransfer characteristic of Schmitt triggerVoutVinVT-VT+VDDVDDHysteresis voltage VH=VT+-VT-When the input is rising, it switches when Vin=VT+When the input is falling, it switches when Vin=VT-

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityInput Pads Schmitt Trigger CircuitVoltage waveforms for slow inputVoutTimeVT-VT+VDDSchmitt trigger turns a signal with a very slow transition into a signal with a sharptransitionVin

EE613 VLSI Design

*EE613 VLSI DesignNational Central UniversityInput Pads Schmitt Trigger CircuitA CMOS version of the Schmitt trigger VoutN1VFPVDDVinVFNN2P2P1N3P31. When the input is rising, the VGS of the transistor N2 is given by2. When , N2 enters in conduction mode which means 3. Then

EE613 VLSI Design

Documents

vlsi testing