294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006

A Voltage-Mode PWM Buck RegulatorWith End-Point Prediction

Man Siu, Philip K. T. Mok, Senior Member, IEEE, Ka Nang Leung, Member, IEEE,Yat-Hei Lam, Student Member, IEEE, and Wing-Hung Ki, Member, IEEE

AbstractThe end-point prediction (EPP) scheme forvoltage-mode buck regulators is proposed. Internal nodal voltagesof the regulator controller are predicted and set automaticallyby the proposed algorithms and circuits. The settling time of theregulator can therefore be significantly reduced for faster dy-namic responses, even with dominant-pole compensation. Provenexperimentally by a voltage-mode buck regulator implemented ina 0.35- m CMOS technology, the reference-tracking speed usingthe EPP scheme is faster than the conventional buck regulator byabout six times.

Index TermsAdaptive supply, buck regulator, dominant-polefrequency compensation, reference tracking.

I. INTRODUCTION

ADAPTIVE power supply is an effective power-manage-ment solution for performance-power optimization inboth digital and mixed-signal systems [1][10]. Therefore,switched-mode regulators with fast reference tracking to pro-vide fast change of regulated supply voltages are becomingimportant for future integrated circuit (IC) systems [6]. Thepulsewidth-modulated (PWM) switched-mode regulator iswell-accepted in many mixed-signal systems, as the switchingperiod is fixed and can be designed so that switching noise willnot seriously degrade the signal-to-noise ratio of mixed-signalsystems. However, PWM regulators generally have slowerreference tracking due to the large off-chip compensationcapacitors for the regulators stability. As a result, extensiveparametric design on power stage and compensation network isgenerally required to improve the tracking speed, and thereforethe robustness of this approach is not high.

In this paper, a simple and efficient voltage-mode controlscheme, end-point prediction (EPP), is proposed. Internal nodalvoltages of the feedback controller are predicted and set auto-matically by the proposed algorithms and circuits. Therefore,

Manuscript received March 22, 2005; revised June 22, 2005. This work wassupported by the Research Grant Council of Hong Kong SAR Governmentunder Project HKUST 6150/03E. This paper was recommended by AssociateEditor S. Banerjee.

M. Siu was with Department of Electrical and Electronic Engineering, TheHong Kong University of Science and Technology, Hong Kong. She is currentlywith Fujitsu Microelectronics Pacific Asia Ltd., World Commerce Centre, TsimSha Tsui, Hong Kong (e-mail: eesman@ee.ust.hk).

P. K. T. Mok, Y.-H. Lam, and W.-H. Ki are with Department of Electrical andElectronic Engineering, The Hong Kong University of Science and Technology,Hong Kong (e-mail: eemok@ee.ust.hk; hylas@ee.ust.hk; eeki@ee.ust.hk).

K. N. Leung was with Department of Electrical and Electronic Engineering,The Hong Kong University of Science and Technology, Hong Kong. He is cur-rently with Department of Electronic Engineering, The Chinese University ofHong Kong, Shatin, Hong Kong (e-mail: knleung@ee.cuhk.edu.hk).

Digital Object Identifier 10.1109/TCSII.2005.862024

Fig. 1. Generic voltage-mode PWM buck regulator.

the settling time of the converter can be significantly reducedfor faster dynamic responses. The proposed EPP scheme willbe demonstrated and proven by a voltage-mode buck regulator.Problems on the slow tracking speed of conventional buck con-verter will firstly be addressed in Section II, and then the pro-posed EPP scheme will be introduced in Section III with theoret-ical analysis and required circuit implementation. The improvedtracking speed will finally be proven by experimental results in-cluded in Section IV.

II. TRACKING SPEED OF VOLTAGE-MODE BUCK REGULATORA generic voltage-mode PWM buck regulator to provide a

regulated voltage from an unregulated voltage isshown in Fig. 1. The power stage is formed by two power tran-sistors (MP and MN), an inductor and a filtering capac-itor . The error amplifier compares the reference voltage

with scaled generated by and . Thus,

(1)where . An error voltage is thengenerated to PWM controller to determine duty cycle in aswitching period for voltage regulation, according to [11]. Abuck regulator operated in continuous-conduction mode (CCM)has a conversion relationship given by

(2)where and are upper and lower bounds of the ramp signalin the PWM controller. As in Fig. 2, when is changed,

is changed by changing with different according to(2). Since a large compensation capacitor is connected at

1057-7130/$20.00 2006 IEEE

SIU: et al. A VOLTAGE-MODE PWM BUCK REGULATOR WITH END-POINT PREDICTION 295

Fig. 2. Transient response at reference tracking.

Fig. 3. Proposed buck regulator with EPP.

the error-amplifier output for dominant-pole compensation, thelarge-signal response of is poor and the change of is slow.

III. PROPOSED EPP SCHEMEThe proposed voltage-mode buck converter with the EPP

scheme is shown in Fig. 3. A voltage adder is used to sumthe error-amplifier output voltage and to form ,inputting into the PWM controller. In this case, , a nodeconnected with a large compensation capacitor, needs not toexperience large voltage transients during reference tracking.

A. Structure and Operational PrincipleFrom (1) and (2), the required to determine is given by

(3)

When is designed such that , the relationof and is given by

(4)Referring to Fig. 3, the error-amplifier output voltage isequal to . During reference tracking, and willchange rapidly while the error-amplifier output voltage willbe constant. However, the relationship stated in (2) occurs onlywith ideal power transistors and ideal inductor. As a result, thereis a small change on during tracking in practice, and thiswill be shown by experimental results in the next section. Since

Fig. 4. Fixed-frequency VCO with supply-controlled ramp and clock signalsamplitude.

there is nearly no large-signal transient at , the referencetracking is much improved.

B. Loop GainStability of power converters is studied by loop-gain analysis.

The open-loop gain of a voltage-mode buck converter inCCM is given by [11], [12]

(5)

where and are the transfer functions of the error am-plifier and power stage, respectively. As isused in the proposed EPP scheme, the loop gain of the proposedstructure is given by

(6)The stability of the voltage-gain buck regulator is independentof . Stability of the proposed buck regulator can be achievedby dominant-pole compensation. A low frequency pole, whichensures complex poles from the power stage located after theunity-gain frequency of the loop gain, is created at the error-amplifier output.

C. Circuit ImplementationAdvanced circuit implementation is needed to achieve the

EPP scheme successfully. The circuit implementation involvesdesigns of voltage-controlled oscillator (VCO) to provide aramp signal with , and a constant switchingfrequency, voltage summation circuit to sum and toform , and over-current protection circuit. The circuit designsof these three important building blocks are introduced below.

1) VCO: The VCO design is the key of the EPP scheme.The ramp signal amplitude needs to change from to

with a constant switching frequency. Theproposed VCO design is shown in Fig. 4. When the resistorratio is designed as , as stated in (1), isgiven by

(7)

This current is copied by the current mirror into two currentbranches. One is to charge a capacitor to form the ramp

296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006

Fig. 5. Inverted linear regulator to generate V independent of current level.

signal, while another is converted to . The hysteretic com-parator compares the amplitude of the ramp signal with and

to turn on and off the nMOS transistor that is connected inparallel with to discharge the ramp voltage back to . Thecharge stored in is given by

(8)

where is the switching frequency of the designed buck con-verter, and hence

(9)

to give the relationship of switching frequency of

(10)

From (8), the switching frequency is independent of andis fixed by the design of and , and the ramp amplitudechanges between and .

In the design, is set to about 0.2 V so that Vto allow the error amplifier to operate in the high-gain region.Moreover, to provide that is independent of injected current

, an inverted linear regulator is used, as shown in Fig. 5.The output voltage is defined by the input of the error amplifier,while regulation is continuously achieved by negative feedback.Since there are two high-impedance nodes, Miller compensationis used. The design of the compensation capacitor used, , canbe evaluated by [13]

(11)

where and are transconductance of the error amplifierand the nMOS transistor, respectively, at minimum , andis the worst-case parasitic capacitance at the drain of the nMOStransistor. Since this circuit is to provide a stable DC voltage,the speed is not important and large provides more stableoperation.

2) Voltage Summation Circuit: The proposed current-modevoltage summation circuit is shown in Fig. 6. The input isfrom the error-amplifier output, while at is generatedby the circuit in Fig. 5. Thus, is converted into given by

, and is copied to another current branch toform by

(12)

Fig. 6. Current-mode voltage adder.

Fig. 7. Inductor-current sensing circuit for over-current protection [14].

3) Over-Current Protection Circuit: During referencetracking, may change to a higher voltage. A higher outputcurrent is needed to charge the output filtering capacitor andan over-current protection circuit is required to avoid damagesof the buck regulator. The over-current protection circuit usedis shown in Fig. 7. Instead of using a series sensing-resistorto sense the inductor current , the drain current of powerpMOS transistor is sensed during the on-period for betterpower-conversion efficiency. The of both power pMOSand sensing pMOS are equal (i.e., ) using a highly-ac-curate voltage clamping circuit [14]. The sensed currentis thus proportional to determined by the transistor ratio. Inthe proposed design, a ratio of 2000 is used. With a small biascurrent , is approximately equal to and inputsinto control logics of the PWM controller.

IV. EXPERIMENTAL RESULTS

A voltage-mode PWM buck converter with the EPP schemehas been implemented in AMS (Austria Mikro System Group,Austria) double-poly triple-metal 0.35- m CMOS technology.The micrograph is shown in Fig. 8, and the chip area is

m m, including the chip area of test pads.

SIU: et al. A VOLTAGE-MODE PWM BUCK REGULATOR WITH END-POINT PREDICTION 297

Fig. 8. Micrograph of the buck regulator with EPP control.

Fig. 9. Measured ramp signals of the buck regulator with EPP by the proposedVCO in Fig. 4 at different input voltages.

The measured ramp signals at V and Vare shown in Fig. 9. The preset is 0.2 V and is set to 1/3.Therefore, is 1.2 V and 1.5 V, respectively, which agreeswith the experimental results well using the stated algorithm.

A comparison of reference tracking is made using twovoltage-mode buck converters. One uses conventional control,while another uses the EPP scheme. As a remark, all circuits arethe same in the same technology except the added circuits forthe EPP control. The input voltage of the measurement is 2.4 Vat 500 kHz. The load current is kept at 160 mA by electronicload. The reference voltage is then changed from 0.1 to 0.7 Vto provide from 0.3 to 2.1 V (noted that ). Fig. 10shows the reference tracking of both positive and negativeedges of for both of the conventional and the EPPcontrols. The tracking speed by EPP, which is measured atless by 10%, is faster than the conventional control by about6 times.

Fig. 10. Measured response of regulated output voltage (V ) at referencetracking. (a) Step up. (b) Step down.

Fig. 11 shows (input of the PWM controller) for the con-ventional and the EPP controls. As predicted, is slowed downby the large compensation capacitor to generate new slowly.However, in EPP changes much faster to provide quickly.It is noted that there is a small change on due to the nonidealpower transistors and inductor on nonzero on-resistance and se-ries-equivalent resistance. Since the change is small, it does notdegrade the tracking speed significantly.

V. CONCLUSIONFast reference tracking feature is very important for systems

powered up by adaptive supply voltages. Voltage-mode PWMpower converters compensated by dominant-pole approach hasslow dynamic response, which is mainly limited by the largeoff-chip compensation capacitor. In this paper, this problem issolved by the proposed End-Point Prediction scheme and circuitimplementation. With the EPP scheme, the simplicity and therobustness of a voltage-mode buck converter with dominant-pole compensation are retained, while the dynamic response isgreatly improved by just an additional adder circuit. Moreover,a buck converter using the proposed idea and implementationmethod has been designed and fabricated. Measurement resultssupport the proposed idea.

298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006

Fig. 11. Measured responses of the error-amplifier output (V ) at referencetracking. (a) Conventional. (b) EPP.

ACKNOWLEDGMENT

The authors would like to thank S. F. Luk and F. Kwok fortheir technical support.

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tocA Voltage-Mode PWM Buck Regulator With End-Point PredictionMan Siu, Philip K. T. Mok, Senior Member, IEEE, Ka Nang Leung, MI. I NTRODUCTION

Fig.1. Generic voltage-mode PWM buck regulator.II. T RACKING S PEED OF V OLTAGE -M ODE B UCK R EGULATOR

Fig.2. Transient response at reference tracking.Fig.3. Proposed buck regulator with EPP.III. P ROPOSED EPP S CHEMEA. Structure and Operational Principle

Fig.4. Fixed-frequency VCO with supply-controlled ramp and clocB. Loop GainC. Circuit Implementation1) VCO: The VCO design is the key of the EPP scheme. The ramp si

Fig.5. Inverted linear regulator to generate $V_{L}$ independen2) Voltage Summation Circuit: The proposed current-mode voltage

Fig.6. Current-mode voltage adder.Fig.7. Inductor-current sensing circuit for over-current protec3) Over-Current Protection Circuit: During reference tracking, $IV. E XPERIMENTAL R ESULTS

Fig.8. Micrograph of the buck regulator with EPP control.Fig.9. Measured ramp signals of the buck regulator with EPP by Fig.10. Measured response of regulated output voltage $(V_{O})$V. C ONCLUSION

Fig.11. Measured responses of the error-amplifier output $(V_{aE. A. Vittoz, Low-power design ways to approach the limits, in PF. Ichiba, K. Suzuki, S. Mita, T. Kuroda, and T. Furuyama, VariaT. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Broderson, G. Hanington, P. Chen, P. Asbeck, and L. Larson, High-efficiencyM. Ranjan, K. H. Koo, G. Hanington, C. Fallesen, and P. Asbeck, D. Ma, W.-H. Ki, and C.-Y. Tsui, An integrated one-cycle controlJ. Kim and R. Horowitz, An efficient digital sliding controller T. Fuse, A. Kameyama, M. Ohta, and K. Ohuchi, A 0.5 V power-suppS. K. Mazumder, A. H. Nayfeh, and A. Borojevic, Robust control oS. K. Mazumder and S. L. Kamisetty, Experimental validation of aR. W. Erickson, Fundamentals of Power Electronics . Norwell, MA:W.-H. Ki, Signal flow graph in loop gain analysis of DC DC PWM CK. N. Leung and P. K. T. Mok, Analysis of multi-stage amplifier Y.-H. Lam, W.-H. Ki, and D. Ma, Loop gain analysis and developme