VSC7511 Datasheet 4-Port Layer-2 Gigabit Ethernet Switch · VMDS-10488 4.2 5/19 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113

VSC7511 Datasheet 4-Port Layer-2 Gigabit Ethernet Switch

VMDS-10488 42 519

Microsemi HeadquartersOne Enterprise Aliso ViejoCA 92656 USAWithin the USA +1 (800) 713-4113 Outside the USA +1 (949) 380-6100Sales +1 (949) 380-6136Fax +1 (949) 215-4996Email salessupportmicrosemicomwwwmicrosemicom

copy2019 Microsemi a wholly owned subsidiary of Microchip Technology Inc All rights reserved Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation All other trademarks and service marks are the property of their respective owners

Microsemi makes no warranty representation or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications Any performance specifications are believed to be reliable but are not verified and Buyer must conduct and complete all performance and other testing of the products alone and together with or installed in any end-products Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi It is the Buyerrsquos responsibility to independently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided ldquoas is where isrdquo and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or anything described by such information Information provided in this document is proprietary to Microsemi and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice

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VMDS-10488 VSC7511 Datasheet Revision 42 iii

Contents

1 Revision History 111 Revision 42 112 Revision 41 113 Revision 40 114 Revision 21 115 Revision 20 2

2 Product Overview 321 General Features 3

211 Layer 2 Switching 3212 Layer 2 Multicast 4213 Quality of Service 4214 Security 4215 Management 5216 Product Parameters 5

22 Applications 623 Functional Overview 6

231 Frame Arrival 7232 Basic and Advanced Frame Classification 8233 Versatile Content Aware Processor (VCAP) 9234 Policing 10235 Layer-2 Forwarding 11236 Shared Queue System and Egress Scheduler 11237 Rewriter and Frame Departure 13238 CPU Port Module 14239 Synchronous Ethernet and Precision Time Protocol 142310 CPU System and Interfaces 15

3 Functional Descriptions 1631 Port Numbering and Mappings 16

311 Supported SerDes Interfaces 17312 PCIe Mode 17313 Logical Port Numbers 17

32 Port Modules 17321 MAC 17322 PCS 22

33 SERDES1G 25331 SERDES1G Basic Configuration 25332 SERDES1G Loopback Modes 26333 Synchronous Ethernet 26334 SERDES1G Deserializer Configuration 27335 SERDES1G Serializer Configuration 27336 SERDES1G Input Buffer Configuration 28337 SERDES1G Output Buffer Configuration 28338 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX 29339 Energy Efficient Ethernet 293310 SERDES1G Data Inversion 29

34 SERDES6G 29341 SERDES6G Basic Configuration 30342 SERDES6G Loopback Modes 30343 Synchronous Ethernet 31

VMDS-10488 VSC7511 Datasheet Revision 42 iv

344 SERDES6G Deserializer Configuration 31345 SERDES6G Serializer Configuration 32346 SERDES6G Input Buffer Configuration 32347 SERDES6G Output Buffer Configuration 33348 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX 34349 Energy Efficient Ethernet 343410 SERDES6G Data Inversion 343411 SERDES6G Signal Detection Enhancements 343412 High-Speed IO Configuration Bus 34

35 Copper Transceivers 35351 Register Access 35352 Cat5 Twisted Pair Media Interface 36353 Wake-On-LAN and SecureOn 38354 Ethernet Inline Powered Devices 39355 IEEE 8023af PoE Support 40356 ActiPHYtrade Power Management 40357 Testing Features 42358 VeriPHYtrade Cable Diagnostics 43

36 Statistics 44361 Port Statistics 44362 Accessing and Clearing Counters 48

37 Basic Classifier 49371 General Data Extraction Setup 49372 Frame Acceptance Filtering 50373 QoS DP and DSCP Classification 53374 VLAN Classification 55375 Link Aggregation Code Generation 57376 CPU Forwarding Determination 58

38 VCAP 60381 Port Configuration 62382 VCAP IS1 65383 VCAP IS2 78384 VCAP ES0 92385 Range Checkers 94386 VCAP Configuration 94387 Advanced VCAP Operations 99

39 Analyzer 101391 MAC Table 101392 VLAN Table 108393 Forwarding Engine 109394 Analyzer Monitoring 118

310 Policers 1183101 Policer Allocation 1193102 Policer Burst and Rate Configuration 120

311 Shared Queue System 1213111 Buffer Management 1223112 Frame Reference Management 1233113 Resource Depletion Condition 1243114 Configuration Example 1243115 Watermark Programming and Consumption Monitoring 1253116 Advanced Resource Management 1263117 Ingress Pause Request Generation 1263118 Tail Dropping 1273119 Test Utilities 12731110 Energy Efficient Ethernet 127

312 Scheduler and Shapers 1283121 Scheduler Element 130

VMDS-10488 VSC7511 Datasheet Revision 42 v

3122 Egress Shapers 1313123 Deficit Weighted Round Robin 1313124 Round Robin 1323125 Shaping and DWRR Scheduling Examples 132

313 Rewriter 1333131 VLAN Editing 1333132 DSCP Remarking 1373133 FCS Updating 1373134 PTP Time Stamping 1383135 Special Rewriter Operations 140

314 CPU Port Module 1413141 Frame Extraction 1423142 Frame Injection 1433143 Node Processor Interface (NPI) 1463144 Frame Generation Engine for Periodic Transmissions 147

315 VRAP Engine 1483151 VRAP Request Frame Format 1493152 VRAP Response Frame Format 1503153 VRAP Header Format 1503154 VRAP READ Command 1503155 VRAP WRITE Command 1513156 VRAP READ-MODIFY-WRITE Command 1513157 VRAP IDLE Command 1513158 VRAP PAUSE Command 152

316 Layer 1 Timing 152317 Hardware Time Stamping 154

3171 Time Stamp Classification 1543172 Time of Day Generation 1543173 Hardware Time Stamping Module 1563174 Configuring IO Delays 157

318 Clocking and Reset 1573181 Pin Strapping 157

4 VCore-Ie System and CPU Interfaces 15941 VCore-Ie Configurations 15942 Clocking and Reset 160

421 Watchdog Timer 16143 Shared Bus 161

431 VCore-Ie Shared Bus Arbitration 161432 Chip Register Region 162433 SI Flash Region 163434 PCIe Region 163435 Starting the VCore-Ie CPU 165436 Accessing the VCore-Ie Shared Bus 167437 Paged Access to VCore-Ie Shared Bus 168438 Software Debug and Development 169

44 VCore-Ie CPU 16945 Load on-chip memory with code-image For more information see External CPU Support 170

451 Register Access and Multimaster Systems 170452 Serial Interface in Slave Mode 170453 MIIM Interface in Slave Mode 173454 Access to the VCore Shared Bus 175455 Mailbox and Semaphores 176

46 PCIe Endpoint Controller 177461 Accessing Endpoint Registers 177462 Enabling the Endpoint 177

VMDS-10488 VSC7511 Datasheet Revision 42 vi

463 Base Address Registers Inbound Requests 179464 Outbound Interrupts 179465 Outbound Access 180466 Power Management 181467 Device Reset Using PCIe 182

47 Frame DMA 183471 DMA Control Block Structures 184472 Enabling and Disabling FDMA Channels 185473 Channel Counters 186474 FDMA Events and Interrupts 187475 FDMA Extraction 188476 FDMA Injection 188477 Manual Mode 189

48 VCore-Ie System Peripherals 191481 SI Boot Controller 191482 SI Master Controller 193483 Timers 197484 UARTs 197485 Two-Wire Serial Interface 199486 MII Management Controller 201487 GPIO Controller 203488 Serial GPIO Controller 205489 Fan Controller 2114810 Temperature Sensor 2124811 Memory Integrity Monitor 2124812 Interrupt Controller 215

5 Features 22151 Switch Control 221

511 Switch Initialization 22152 Port Module Control 221

521 Port Reset Procedure 221522 Port Counters 222

53 Layer-2 Switch 225531 Basic Switching 225532 Standard VLAN Operation 228533 Provider Bridges and Q-in-Q Operation 231534 Private VLANs 235535 Asymmetric VLANs 238536 Spanning Tree Protocols 239537 IEEE 8021X Network Access Control 244538 Link Aggregation 246539 Simple Network Management Protocol (SNMP) 2495310 Mirroring 249

54 IGMP and MLD Snooping 251541 IGMP and MLD Snooping Configuration 251542 IP Multicast Forwarding Configuration 252

55 Quality of Service (QoS) 252551 Basic QoS Configuration 253552 IPv4 and IPv6 DSCP Remarking 254553 Voice over IP (VoIP) 255

56 VCAP Applications 256561 Notation for Control Lists Entries 256562 Ingress Control Lists 257563 Access Control Lists 258564 Source IP Filter (SIP Filter) 259565 DHCP Application 261

VMDS-10488 VSC7511 Datasheet Revision 42 vii

566 ARP Filtering 262567 Ping Policing 262568 TCP SYN Policing 263

57 CPU Extraction and Injection 263571 Forwarding to CPU 264572 Frame Extraction 265573 Frame Injection 266574 Frame Extraction and Injection Using An External CPU 266

6 Registers 267

7 Electrical Specifications 26871 DC Specifications 268

711 Internal Pull-Up or Pull-Down Resistors 268712 Reference Clock Inputs 268713 PLL Clock Outputs 268714 SERDES1G 269715 SERDES6G 269716 GPIO SI JTAG and Miscellaneous Signals 270717 Thermal Diode 271

72 AC Specifications 271721 REFCLK Reference Clock (1G and 6G Serdes) 271722 PLL Clock Outputs 272723 SERDES1G 273724 SERDES6G 274725 Reset Timing Specifications 277726 MIIM Timing Specifications 278727 SI Boot Timing Master Mode Specifications 279728 SI Timing Master Mode Specifications 279729 SI Timing Slave Mode Specifications 2807210 JTAG Interface Specifications 2827211 Serial IO Timing Specifications 2827212 Recovered Clock Outputs Specifications 2827213 Two-Wire Serial Interface Specifications 2837214 IEEE1588 Time Tick Output Specifications 284

73 Current and Power Consumption 28474 Operating Conditions 285

741 Power Supply Sequencing 28575 Stress Ratings 286

8 Pin Descriptions 28781 Pin Diagram 28782 Pins by Function 287

9 Package Information 30091 Package Drawing 30092 Thermal Specifications 30193 Moisture Sensitivity 302

10 Design Guidelines 303101 Power Supplies 303102 Power Supply Decoupling 303

1021 Reference Clock 3031022 Single-Ended REFCLK Input 303

103 Interfaces 3041031 General Recommendations 304

VMDS-10488 VSC7511 Datasheet Revision 42 viii

1032 SerDes Interfaces (SGMII 25GQSGMII) 3051033 Serial Interface 3051034 PCI Express Interface 3051035 Two-Wire Serial Interface 3061036 DDR3 SDRAM Interface 3061037 Thermal Diode External Connection 307

11 Ordering Information 309

VMDS-10488 VSC7511 Datasheet Revision 42 ix

Figures

Figure 1 Block Diagram 7Figure 2 Basic and Advanced Frame Classification 8Figure 3 Versatile Content Aware Processor 10Figure 4 Default Egress Scheduler and Shaper Configuration 12Figure 5 Alternative Egress Scheduler and Shaper Configuration 13Figure 6 Advanced Frame Rewriting 14Figure 7 SERDES1G Loopback Modes 26Figure 8 SERDES6G Loopback Modes 31Figure 9 Register Space Layout 35Figure 10 Cat5 Media Interface 36Figure 11 Low Power Idle Operation 38Figure 12 Wake-On-LAN Functionality 39Figure 13 Inline Powered Ethernet Switch 40Figure 14 ActiPHY State Diagram 41Figure 15 Far-End Loopback 43Figure 16 Near-End Loopback 43Figure 17 Connector Loopback 43Figure 18 Counter Layout (SYSSTATCNT) Per View 49Figure 19 VLAN Acceptance Filter 52Figure 20 QoS and DP Basic Classification Flow 54Figure 21 Basic DSCP Classification Flow Chart 55Figure 22 Basic VLAN Classification Flow 57Figure 23 VCAP Functional Overview 60Figure 24 IS1 Entry Type Overview 66Figure 25 IS2 Half Entry Type Overview 79Figure 26 IS2 Half Entry Type Overview 80Figure 27 SMAC_SIP Entry Type Overview 90Figure 28 VCAP Configuration Overview 95Figure 29 Entry Layout in Register Example 97Figure 30 Entry Layout in Register using Subwords Example 98Figure 31 Action Layout in Register Example 98Figure 32 Move Down Operation Example 100Figure 33 MAC Table Organization 102Figure 34 Analysis Steps 110Figure 35 Policer Pool Layout 119Figure 36 Queue System Overview 121Figure 37 Frame Reference 123Figure 38 Watermark Layout 125Figure 39 Low Power Idle Operation 128Figure 40 Egress Scheduler Port 0 129Figure 41 Scheduler Element 130Figure 42 Tagging Overview 134Figure 43 Tag Construction (port tag ES0 tag A ES0 tag B) 136Figure 44 CPU Injection and Extraction 141Figure 45 CPU Injection and Extraction Prefixes 147Figure 46 VRAP Request Frame Format 149Figure 47 VRAP Response Frame Format 150Figure 48 VRAP Header Format 150Figure 49 READ Command 151Figure 50 WRITE Command 151Figure 51 READ-MODIFY-WRITE Command 151Figure 52 IDLE Command 151Figure 53 PAUSE Command 152Figure 54 Timing Distribution 155

VMDS-10488 VSC7511 Datasheet Revision 42 x

Figure 55 VCore-Ie System Block Diagram 159Figure 56 Shared Bus memory 161Figure 57 Chip Registers Memory Map 163Figure 58 VCore-Ie Block Diagram 164Figure 59 SI Slave Mode Register 170Figure 60 Write Sequence for SI 171Figure 61 Read Sequence for SI_CLK Slow 172Figure 62 Read Sequence for SI_CLK Pause 172Figure 63 Read Sequence for One-Byte Padding 172Figure 64 MIIM Slave Write Sequence 174Figure 65 MIIM Slave Read Sequence 174Figure 66 FDMA DCB Layout 185Figure 67 FDMA Channel States 186Figure 68 FDMA Channel Interrupt Hierarchy 188Figure 69 Extraction Status Word Encoding 189Figure 70 Injection Status Word Encoding 190Figure 71 SI Boot Controller Memory Map in 24-Bit Mode 191Figure 72 SI Boot Controller Memory Map in 32-Bit Mode 191Figure 73 SI Read Timing in Normal Mode 192Figure 74 SI Read Timing in Fast Mode 192Figure 75 SIMC SPI Clock Configurations 195Figure 76 SIMC SPI 3x Transfers 195Figure 77 UART Timing 198Figure 78 Two-Wire Serial Interface Timing for 7-bit Address Access 200Figure 79 MII Management Timing 202Figure 80 SIO Timing 207Figure 81 SIO Timing with SGPIOs Disabled 207Figure 82 SGPIO Output Order 208Figure 83 Link Activity Timing 210Figure 84 Monitor State Diagram 214Figure 85 Memory Detection Logic 215Figure 86 Interrupt Source Logic 218Figure 87 Interrupt Destination Logic 219Figure 88 Port Module Interrupt Logic 219Figure 89 MAN Access Switch Setup 233Figure 90 ISP Example for Private VLAN 236Figure 91 DMZ Example for Private VLAN 237Figure 92 Asymmetric VLANs 238Figure 93 Spanning Tree Example 240Figure 94 Multiple Spanning Tree Example 242Figure 95 Link Aggregation Example 248Figure 96 Port Mirroring Example 250Figure 97 Resulting ACL for Lookup with PAG = (A) and IGR_PORT_MASK = (1ltlt8) 259Figure 98 CPU Extraction and Injection 264Figure 99 Thermal Diode 271Figure 100 Reset Signal Timing 278Figure 101 SI Timing Diagram for Master Mode 279Figure 102 SI Input Data Timing Diagram for Slave Mode 280Figure 103 SI Output Data Timing Diagram for Slave Mode 281Figure 104 Two-Wire Serial Interface Timing 284Figure 105 Pin Diagram 287Figure 106 Package Drawing 301Figure 107 25 V CMOS Single-Ended REFCLK Input Resistor Network 304Figure 108 33 V CMOS Single-Ended REFCLK Input Resistor Network 304Figure 109 16-Bit DDR3 SDRAM Point-to-Point Routing 306Figure 110 External Temperature Monitor Connection 308

VMDS-10488 VSC7511 Datasheet Revision 42 xi

Tables

Table 1 Main Port Configurations 3Table 2 Product Parameters 5Table 3 Default Port Numbering and Port Mappings 16Table 4 Interface Macro to IO Pin Mapping 16Table 5 Supported SerDes Interfaces 17Table 6 MAC Configuration Registers 17Table 7 Priority-Based Flow Control Configuration Registers 20Table 8 Frame Aging Configuration Registers 21Table 9 Rx and Tx Time Stamping Register 21Table 10 PCS Configuration Registers 22Table 11 Test Pattern Registers 23Table 12 Low Power Idle Registers 24Table 13 100BASE-FX Registers 24Table 14 SERDES1G Registers 25Table 15 SERDES1G Loop Bandwidth 27Table 16 SERDES6G Registers 29Table 17 PLL Configuration 30Table 18 SERDES6G Frequency Configuration Registers 30Table 19 SERDES6G Loop Bandwidth 32Table 20 De-Emphasis and Amplitude Configuration 33Table 21 Supported MDI Pair Combinations 37Table 22 Counter Registers 44Table 23 Receive Counters in the Statistics Block 44Table 24 Tx Counters in the Statistics Block 46Table 25 FIFO Drop Counters in the Statistics Block 48Table 26 General Data Extraction Registers 50Table 27 Frame Acceptance Filtering Registers 50Table 28 QoS DP and DSCP Classification Registers 53Table 29 VLAN Configuration Registers 55Table 30 Aggregation Code Generation Registers 58Table 31 CPU Forwarding Determination 58Table 32 Frame Type Definitions for CPU Forwarding 59Table 33 IS1 and IS2 VCAP Frame Types 61Table 34 Port Module Configuration of VCAP 63Table 35 Hierarchy of IS2 Entry Types 64Table 36 Overview of IS1 Keys 65Table 37 Specific Fields for IS1 Quad Key S1_DBL_VID 67Table 38 IS1 Common Key Fields for Half keys 68Table 39 Specific Fields for IS1 Half Key S1_NORMAL 69Table 40 Specific Fields for IS1 Half Key S1_5TUPLE_IP4 71Table 41 IS1 Common Key Fields for Full keys 72Table 42 Specific Fields for IS1 Full Key S1_NORMAL_IP6 73Table 43 Specific Fields for IS1 Full Key S1_7TUPLE 74Table 44 Specific Fields for IS1 Full Key S1_5TUPLE_IP6 75Table 45 IS1 Action Fields 76Table 46 IS2 Common Key Fields for Half keys 81Table 47 IS2 MAC_ETYPE Key 81Table 48 IS2 MAC_LLC Key 82Table 49 IS2 MAC_SNAP Key 82Table 50 IS2 ARP Key 82Table 51 IS2 IP4_TCP_UDP Key 83Table 52 IS2 IP4_OTHER Key 84Table 53 IS2 Common Key Fields for Full keys 85Table 54 IS2 IP6_STD Key 85

VMDS-10488 VSC7511 Datasheet Revision 42 xii

Table 55 IS2 OAM Key 85Table 56 IS2 IP6_TCP_UDP Key 86Table 57 IS2 IP6_OTHER Key 87Table 58 IS2 CUSTOM Key 87Table 59 IS2 Action Fields 88Table 60 MASK_MODE and PORT_MASK Combinations 90Table 61 SMAC_SIP6 Key 91Table 62 SMAC_SIP4 Key 91Table 63 SMAC_SIP4 and SMAC_SIP6 Action Fields 91Table 64 ES0 Key 92Table 65 ES0 Action Fields 92Table 66 Range Checker Configuration 94Table 67 VCAP Configuration Registers 94Table 68 VCAP Constants 95Table 69 VCAP Parameters 96Table 70 Entry Type and Type-Group Parameters 96Table 71 Action and Type Field Parameters 98Table 72 Internal Mapping of Entry and Mask 99Table 73 MAC Table Access 101Table 74 MAC Table Entry 102Table 75 MAC Table Commands 104Table 76 IPv4 Multicast Destination Mask 105Table 77 IPv6 Multicast Destination Mask 105Table 78 VIDPortDomain Filters 106Table 79 FID Definition Registers 106Table 80 Learn Limit Definition Registers 107Table 81 VLAN Table Access 108Table 82 Fields in the VLAN Table 108Table 83 VLAN Table Commands 108Table 84 DMAC Analysis Registers 111Table 85 Forwarding Decisions Based on Flood Type 111Table 86 VLAN Analysis Registers 112Table 87 Analyzer Aggregation Registers 113Table 88 VCAP IS2 Action Processing 114Table 89 SMAC Learning Registers 114Table 90 Storm Policer Registers 116Table 91 Storm Policers 116Table 92 sFlow Sampling Registers 117Table 93 Mirroring Registers 117Table 94 Analyzer Monitoring 118Table 95 Policer Control Registers 118Table 96 Reservation Watermarks 122Table 97 Sharing Watermarks 122Table 98 Watermark Configuration Example 124Table 99 Resource Management 126Table 100 Energy Efficient Ethernet Control Registers 127Table 101 Scheduler and Egress Shaper Control Registers 128Table 102 Scheduler Elements Numbering 129Table 103 Example of Mixing DWRR and Shaping 132Table 104 Example of Strict and Work-Conserving Shaping 133Table 105 VLAN Editing Registers 133Table 106 Tagging Combinations 135Table 107 DSCP Remarking Registers 137Table 108 FCS Updating Registers 137Table 109 PTP Time Stamping Registers 138Table 110 PTP Time Stamping for One-step PTP 139Table 111 PTP Time Stamping for Two-step PTP 139Table 112 PTP Time Stamping for Origin PTP 140Table 113 Frame Extraction Registers 142

VMDS-10488 VSC7511 Datasheet Revision 42 xiii

Table 114 CPU Extraction Header 142Table 115 Frame Injection Registers 143Table 116 CPU Injection Header 144Table 117 Node Processor Interface Registers 146Table 118 Frame Generation Engine 147Table 119 VRAP Registers 148Table 120 Layer 1 Timing Configuration Registers 152Table 121 Layer 1 Timing Recovered Clock Pins 152Table 122 Recovered Clock Settings for 1 Gbps and Lower 153Table 123 Recovered Clock Settings for 25 Gbps 153Table 124 Recovered Clock Settings for PLL 153Table 125 Squelch Configuration for Sources 153Table 126 LoadStore Controller 155Table 127 Hardware Time Stamping Registers 156Table 128 Strapping 158Table 129 Clocking and Reset Configuration Registers 160Table 130 Shared Bus Configuration Registers 161Table 131 Special Function Registers (SFR) 165Table 132 VCore-Ie CPU Startup Registers 166Table 133 Shared Bus Access (SBA) Registers 167Table 134 Paged Access to VCore-Ie Shared Bus 168Table 135 8051 Status Registers 169Table 136 SI Slave Mode Pins 171Table 137 MIIM Slave Pins 173Table 138 MIIM Registers 173Table 139 VCore Shared Bus Access Registers 175Table 140 Mailbox and Semaphore Registers 176Table 141 Manual PCIe Bring-Up Registers 178Table 142 Base Address Registers 179Table 143 PCIe Outbound Interrupt Registers 179Table 144 Outbound Access Registers 180Table 145 PCIe Access Header Fields 180Table 146 FDMA PCIe Access Header Fields 181Table 147 Power Management Registers 182Table 148 PCIe Wake Pin 182Table 149 FDMA Registers 183Table 150 SI Boot Controller Configuration Registers 191Table 151 Serial Interface Pins 192Table 152 SI Master Controller Configuration Registers Overview 193Table 153 SI Master Controller Pins 194Table 154 Timer Registers 197Table 155 UART Registers 198Table 156 UART Interface Pins 198Table 157 Two-Wire Serial Interface Registers 199Table 158 Two-Wire Serial Interface Pins 200Table 159 MIIM Registers 201Table 160 MIIM Management Controller Pins 202Table 161 GPIO Registers 203Table 162 GPIO Overlaid Functions 204Table 163 Parallel Signal Detect Pins 205Table 164 SIO Registers 206Table 165 SIO Controller Pins 206Table 166 Blink Modes 209Table 167 SIO Controller Port Mapping 209Table 168 Fan Controller 211Table 169 Fan Controller Pins 211Table 170 Temperature Sensor Registers 212Table 171 Integrity Monitor Registers 213Table 172 Memories with Integrity Support 215

VMDS-10488 VSC7511 Datasheet Revision 42 xiv

Table 173 Interrupt Controller Registers 216Table 174 Interrupt Sources 216Table 175 Interrupt Destinations 218Table 176 External Interrupt Pins 220Table 177 Mapping of RMON Counters to Port Counters 222Table 178 Mandatory Counters 223Table 179 Optional Counters 223Table 180 Mapping of SNMP Interfaces Group Counters to Port Counters 224Table 181 Recommended MAC Control Counters 224Table 182 Pause MAC Control Recommended Counters 224Table 183 Mapping of SNMP Ethernet-Like Group Counters to Port Counters 225Table 184 Port Group Identifier Table Organization 226Table 185 Port Module Registers for Standard VLAN Operation 228Table 186 Analyzer Registers for Standard VLAN Operation 228Table 187 Rewriter Registers for Standard VLAN Operation 229Table 188 Port Module Configurations for Provider Bridge VLAN Operation 231Table 189 System Configurations for Provider Bridge VLAN Operation 231Table 190 Analyzer Configurations for Provider Bridge VLAN Operation 231Table 191 Private VLAN Configuration Registers 235Table 192 Analyzer Configurations for RSTP Support 240Table 193 RSTP Port State Properties 240Table 194 RSTP Port State Configuration for Port p 241Table 195 Analyzer Configurations for MSTP Support 242Table 196 MSTP Port State Properties 243Table 197 MSTP Port State Configuration for Port p and VLAN v 243Table 198 Configurations for Port-Based Network Access Control 244Table 199 Configurations for MAC-Based Network Access Control with Secure CPU-Based Learning 245Table 200 Configurations for MAC-Based Network Access Control with No Learning 245Table 201 Link Aggregation Group Configuration Registers 246Table 202 Configuration Registers for LACP Frame Redirection to the CPU 249Table 203 System Registers for SNMP Support 249Table 204 Analyzer Registers for SNMP Support 249Table 205 Configuration Registers for Mirroring 250Table 206 Configuration Registers for IGMP and MLD Frame Redirection to CPU 251Table 207 IP Multicast Configuration Registers 252Table 208 Basic QoS Configuration Registers 253Table 209 Configuration Registers for DSCP Remarking 254Table 210 Control Lists and Application 256Table 211 Advanced QoS Configuration Register Overview 257Table 212 Configurations for Redirecting or Copying Frames to the CPU 264Table 213 Configuration Registers When Using An External CPU 266Table 214 Internal Resistor Characteristics 268Table 215 Reference Clock Input Characteristics 268Table 216 PLL Clock Outputs Characteristics 268Table 217 SERDES1G Characteristics for 1G Transmitter 269Table 218 SERDES1G Characteristics for 1G Receiver 269Table 219 SERDES6G Characteristics for 6G Transmitter 269Table 220 GPIO SI JTAG and Miscellaneous Signals Characteristics 270Table 221 SERDES6G Characteristics for 6G Receiver 270Table 222 Thermal Diode Parameters 271Table 223 Reference Clock Input Characteristics 271Table 224 PLL Clock Outputs Characteristics 272Table 225 SERDES1G Characteristics for 100BASE-FX SGMII SFP 1000BASE-KX Transmitter 273Table 226 SERDES1G Characteristics for 100BASE-FX SGMII SFP 1000BASE-KX Receiver 273Table 227 SERDES6G Characteristics for 100BASE-FX SGMII SFP 25G 1000BASE-KX Transmitter 274Table 228 SERDES6G Characteristics for 100BASE-FX SGMII SFP 25G 1000BASE-KX Receiver 275Table 229 SERDES6G Characteristics for QSGMII Transmitter 276Table 230 SERDES6G Characteristics for QSGMII Receiver 276Table 231 SERDES6G Characteristics for PCIe Transmitter 277

VMDS-10488 VSC7511 Datasheet Revision 42 xv

Table 232 SERDES6G Characteristics for PCIe Receiver 277Table 233 Reset Timing Characteristics 278Table 234 MIIM Timing Characteristics 278Table 235 SI Boot Timing Master Mode Characteristics 279Table 236 SI Timing Master Mode Characteristics 279Table 237 SI Timing Slave Mode Characteristics 281Table 238 JTAG Interface Characteristics 282Table 239 Serial IO Timing Characteristics 282Table 240 Recovered Clock Outputs Characteristics 282Table 241 Two-Wire Serial Timing Characteristics 283Table 242 IEEE1588 Time Tick Output Characteristics 284Table 243 Current and Power Consumption 284Table 244 Recommended Operating Conditions 285Table 245 Stress Ratings 286Table 246 Pin Type Symbol Definitions 287Table 247 Pins by Function 288Table 248 Thermal Resistances 302Table 249 Recommended Skew Budget 306Table 250 Ordering Information 309

Revision History

VMDS-10488 VSC7511 Datasheet Revision 42 1

1 Revision History

This section describes the changes that were implemented in this document The changes are listed by revision starting with the most current publication

Revision 42Revision 42 of this datasheet was published in May 2019 The following is a summary of the changes in revision 42 of this document

bull VeriPHY descriptions were updated For functional details of the VeriPHY suite and operatinginstructions see the ENT-AN0125 PHY Integrated PHY-Switch VeriPHY - Cable DiagnosticsApplication Note

12 Revision 41Revision 41 of this datasheet was published in January 2018 The following is a summary of the changes in revision 41 of this document

bull The recovered clock settings table has been split into two For more information see Table 122page 153 and Table 123 page 153

bull The SI timing master and slave mode specification sections were updated For more informationsee SI Timing Master Mode Specifications page 279 and SI Timing Slave Mode Specificationspage 280

bull The power supply sequencing sections were updated For more information see Power SupplySequencing page 285 and SI Timing Slave Mode Specifications page 280

13 Revision 40The following is a summary of the changes in revision 40 of this document

bull Product overview was updated to add feature highlights For more information see GeneralFeatures page 3

bull Port modules description was updated to reflect available functionality For more information seePort Modules page 17

bull Information about configuring IO delays was added For more information see Configuring IODelays page 157

bull Fan controller information was updated For more information see Fan Controller page 211bull Electrical specifications were updated For more information see Electrical Specifications

bull Pin type symbols were defined and the pins by function table was updated For more information

see Table 245 page 286 and Pins by Function page 287bull Moisture sensitivity level (MSL) is level 3bull ESD (electrostatic discharge) was added For human body model (HBM) it is a Class 2 rating For

charged device model (CDM) it is plusmn250 Vbull Information on design guidelines was added For more information see Design Guidelines

bull Information on power supply sequencing was added For more information see Power Supply

Sequencing page 285

bull References to DDR3DDR3L were removed For more information see Electrical Specificationspage 268

bull Current and power consumption values were updated For more information see Table 243page 284

Revision History

15 Revision 20Revision 20 was the first publication of this document

Product Overview

2 Product Overview

The VSC7511 Industrial IoT Ethernet switch contains four ports each configurable as either an integrated 101001000BASE-T PHY or a 1G SGMIISerDes In addition there is an option for either a 1G25G SGMIISerDes Node Processor Interface (NPI) or a PCIe interface for external CPU connectivity The NPIPCIe can operate as a standard Ethernet port The device provides a rich set of Industrial Ethernet switching features such as fast protection switching 1588 precision time protocol and synchronous Ethernet Advanced TCAM-based VLAN and QoS processing enable delivery of differentiated services Security is assured through frame processing using Microsemirsquos TCAM-based Versatile Content Aware Processor In addition the device contains an 8051 CPU for simple operation of the switch

The device supports the following main port configurations

21 General Featuresbull 175 megabits of integrated shared packet memorybull 4 x 1G SGMII or integrated copper PHY portsbull Fully nonblocking wire-speed switching performance with weighted random early detection (WRED)

for all frame sizesbull Eight QoS classes and eight queues per port with strict or deficit weighted round robin schedulingbull Dual leaky bucket policers per QoS class and per portbull Dual leaky bucket policers flow-based through TCAM matchingbull DWRR and strict priority egress schedulershaper and 9 dual leaky bucket shapers per egress portbull TCAM-based classification entries for Quality of Service (QoS) and VLAN membershipbull TCAM-based host identity entries for source IP guardingbull TCAM-based security enforcement entriesbull TCAM-based egress tagging entriesbull L1 Synchronous Ethernetbull VeriTimetrademdashMicrosemirsquos patent-pending distributed timing technology that delivers the industryrsquos

most accurate IEEE 1588v2 timing implementation for both one-step and two-step clocksbull AudioVideo bridging (AVB) with support for time-synchronized low-latency audio and video

streaming servicesbull Energy Efficient Ethernet (IEEE 8023az)bull VCore-Ietrade CPU system with integrated 250 MHz 8051 CPU with 64 KB internal storagebull PCIe and 25G SGMII NPI for external CPU register accessbull Device overheat protectionbull Hardware loop detectionbull Integrated fan controllerbull Internal shared memory buffer (8 queues per port) Integrated 101001000BASE-T Ethernet copper

transceiver (IEEE 8023ab compliant) with the industrys only non-TDR-based VeriPHYtrade cablediagnostics algorithm

bull Patented line driver with low EMI voltage mode architecture and integrated line-side terminationresistors

bull Wake-on-LAN using magic packetsbull HP Auto-MDIX and manual MDIMDIX support

211 Layer 2 Switchingbull 4096 MAC addressesbull 4096 VLANs (IEEE 8021Q)

Table 1 bull Main Port Configurations

Ports 1G CuPHYSGMII 25G NPI PCIe4 + NPI 4 1

4 + PCIe 4 1

Product Overview

bull Pushpoptranslate up to three VLAN tags translation on ingress andor on egressbull TCAM-based VLAN classification and translation with pattern matching against Layer 2 through

Layer 4 information such as MAC addresses VLAN tag headers EtherType DSCP IP addresses and TCPUDP ports and ranges

bull QoS and VLAN TCAM entriesbull VLAN egress tagging TCAM entriesbull Link aggregation (IEEE 8023ad)bull Link aggregation traffic distribution is programmable and based on Layer 2 through Layer 4

informationbull Wire-speed hardware-based learning and CPU-based learning configurable per portbull Independent and shared VLAN learningbull Provider Bridging (VLAN Q-in-Q) support (IEEE 8021ad)bull Rapid Spanning Tree Protocol support (IEEE 8021w)bull Multiple Spanning Tree Protocol support (IEEE 8021s)bull Jumbo frame support up to 122 KB with per-port programmable MTUbull Q-in-Q tagging support

212 Layer 2 Multicastbull IPv4IPv6 multicast Layer-2 switching with up to 4096 groups and 64 port masksbull Internet Group Management Protocol version 2 (IGMPv2) supportbull Internet Group Management Protocol version 3 (IGMPv3) support with source specific multicast

forwardingbull Multicast Listener Discovery (MLDv1) supportbull Multicast Listener Discovery (MLDv2) support with source specific forwarding

213 Quality of Servicebull Eight QoS classes and two drop precedence levelsbull Eight QoS queues per port with Deficit Weighted Round-robin (DWRR) or Frame Based Round-

robin (FBRR) schedulingbull TCAM-based QoS and VLAN classification with pattern matching against Layer 2 through Layer 4

informationbull DSCP translation both ingress andor egressbull DSCP remarking based on QoS class and drop precedence levelbull VLAN (PCP DEI and VID) translation both ingress and egressbull PCP and DEI remarking based on QoS class and drop precedence levelbull Policers selectable per QoS class per queue per port and per security entry through TCAM-based

pattern matching programmable in steps of 333 kbpsbull Dual leaky bucket shaping per port and per QoS class programmable in steps of 100 kbpsbull Full-duplex flow control (IEEE 8023X) and half-duplex backpressure symmetric and asymmetricbull Priority-based full-duplex flow control (IEEE 8021Qbb)bull Multicast and broadcast storm control with flooding controlbull QoS classification based on IEEE 8021p and IPv4IPv6 DSCP

214 Securitybull Versatile Content Aware Processor (VCAP) packet filtering engine using ACLs for ingress and

egress packet inspectionbull Security VCAP entriesbull Source IP guarding entriesbull Shared VCAP rate policers with rate measurements in frames per second or bits per secondbull Eight shared range checkers supporting ranges based on TCPUDP port numbers DSCP

values and VLAN identifiersbull VCAP match patterns supporting generic MAC ARP IPv4 and IPv6 protocolsbull VCAP actions including permitdeny police count CPU-copy and mirrorbull Special support for IP fragments UDPTCP port ranges and ARP sanity checkbull Extensive CPU DoS prevention by VCAP rate policers and hit-me-once functionsbull Surveillance functions supported by 32-bit VCAP counters

bull Generic storm controllers for flooded broadcast flooded multicast and flooded unicast traffic

Product Overview

bull Selectable CPU extraction queues for segregation of CPU redirected traffic with 8 extraction queues supported

bull Per-port per-address registration for copyingredirectingdiscarding of reserved IEEE MAC addresses (BPDU GARP CCMLink trace)

bull Port-based and MAC-based access control (IEEE 8021X)bull Per-port CPU-based learning with option for secure CPU-based learningbull Per-port ingress and egress mirroringbull Mirroring per VLAN and per VCAP match

215 Managementbull VCore-Ietrade CPU system with integrated 250 MHz 8051 CPUbull PCIe 1x CPU interfacebull CPU frame extraction (eight queues) and injection (two queues) through DMA which enables

efficient data transfer between Ethernet ports and CPUPCIebull Twenty-two pin-shared general-purpose IOs

bull Serial GPIO and LED controller controlling up to 32 ports with four LEDs eachbull Dual PHY management controller (MIIM)bull Dual UART

Built-in two wire serial interface multiplexerbull External interruptsbull 1588 synchronization IOsbull SFP loss of signal inputs

bull External access to registers through PCIe SPI MIIM or through an Ethernet port with inline Microsemirsquos Versatile Register Access Protocol (VRAP)

bull Per-port counter set with support for the RMON statistics group (RFC 2819) and SNMP interfaces group (RFC 2863)

bull Energy Efficient Ethernet (EEE) (IEEE 8023az)bull Synchronous Ethernet with two clock outputs recovered from any portbull Support for CPU modes with internal CPU only external CPU only or dual CPU

216 Product ParametersAll SerDes copper transceivers packet memory and configuration tables necessary to support network applications are integrated The following table lists the primary parameters for the device

Table 2 bull Product Parameters

Features and Port Configurations VSC7511Maximum IO bandwidth excluding 25G NPI port 4 Gbps

Maximum number of ports 4 + NPI4 + PCIe

Maximum number of 25G SGMII ports including NPI port 1

25G SGMII NPI port (also capable of 1G SGMII or PCIe) 1

CuPHYs 4

SERDES1G lanes 2

SERDEDS6G lanes including 25G NPI 3

Layer 2 SwitchingPacket buffer 175 Mbits

MAC table size 4K

VLAN table size 4K

Layer 2 multicast port masks 64

Quality of Service and Security

Product Overview

22 ApplicationsVSC7511 targets unmanaged applications in industrial Ethernet Internet of Things (IoT) Enterprise SMB Customer-premises Equipment (CPE) and Network Termination Equipment (NTE)

23 Functional OverviewThis section provides an overview of all major blocks and functions involved in the forwarding operation in the same order as a frame traverses through the VSC7511 device It also outlines other major functionality of the device such as the CPU port module the CPU system and CPU interfaces

The following illustration is a block diagram for the device

VCAP IS1 entries 64 full 128 half or256 quad

VCAP ES0 entries 256

Table 2 bull Product Parameters (continued)

Features and Port Configurations VSC7511

Product Overview

Figure 1 bull Block Diagram

231 Frame ArrivalThe Ethernet interfaces receive incoming frames and forwards these to the port modules The 25G SGMII ports support both 100BASE-X and 1000BASE-X-SERDES

Each port module contains a Media Access Controller (MAC) that performs a full suite of checks such as VLAN Tag aware frame size checking Frame Check Sequence (FCS) checking and Pause frame identification

Each port module that connects to a SerDes block contains a Physical Coding Sublayer (PCS) which perform 8 bits10 bits encoding auto-negotiation of link speed and duplex mode and monitoring of the link status

Full-duplex is supported for all speeds and half-duplex is supported for 10 Mbps and 100 Mbps Symmetric and asymmetric pause flow control are both supported as well as priority-based flow control (IEEE 8021Qbb)

All Ethernet ports support Energy Efficient Ethernet (EEE) according to IEEE 8023az The shared queue system is capable of controlling the operating states active or low-power of the PCS The PCS understands the line signaling as required for EEE This includes signaling of active sleep quiet refresh and wake

AnalyzerIngress Processing

RewriterEgress Processing

Shared Memory Pool

Memory Controller

Shaper and Scheduler

nRESET

GPIO functions

LED serial GPIO UART two-wire serial interface

IRQ MIIM LOS SyncE 1588 RefClk

Discard StatisticsShared Queue System

Automated Frame Injection

CuPHY 1G Port Modules

MAC1588 Time Stamping

Frame Bus

VCore Arbiter VCore CPU Bus

Switch Core Registers

VCore SBA Access Block

Temperature Sensor

Interrupt Controller

TimersSwitch Core

Access Block

SI SlaveFrame DMA

(FDMA)

Manual FrameInjectExtract

MIIM Slave

VRAPEthernet Register

Access

Port L2CP Handling

Ingress Classification(VLAN QoS class)

QoS Mapping

Access Control Lists

Policing(Port QoS ACL)

Forwarding L2

IEEE1588 Engine

Egress VCAP Lookup

IEEE1588 Engine

Frame EditingVLAN tags

DSCPIEEE1588L2L3L4

Protection Switching

PCIE(Optional instead of NPI)PCIe

1G CuPHY

1000BASE-T

SerDes6G Lane

25G Port Modules

MAC PCS1588 Time Stamping

NPI25G SGMII1G SGMII

100BASE-FX

1G Port Modules

SerDes1G6GLane

1G SGMII100BASE-FX

Product Overview

232 Basic and Advanced Frame ClassificationThe basic and advanced frame classification in the ingress processing module receive all frames The basic and advanced classifiers determine a range of frame properties such as VLAN Quality of Service (QoS) class and drop precedence level This information is carried through the switch together with the frame and affects policing drop precedence marking statistics collecting security enforcement Layer-2 forwarding and rewriting

The classification is a combination of a basic classification using configurable logic and more advanced classification using a TCAM

The classification engine understands up to two VLAN tags and can look for Layer-3 and Layer-4 information behind two VLAN tags If frames are triple tagged the higher-layer protocol information is not extracted

The following illustration shows the basic and advanced frame classification

Figure 2 bull Basic and Advanced Frame Classification

The basic classification classifies each frame to a VLAN a QoS class a drop precedence (DP) level DSCP value and an aggregation code The basic classification also performs a general frame acceptance check The output from the basic classification may be overwritten or changed by the more intelligent advanced classification using the IS1 TCAM

Frame Acceptance The frame acceptance filter checks for valid combinations of VLAN tags against the ingress portrsquos VLAN acceptance filter where it is possible to configure rules for accepting untagged priority-tagged C- and S-tagged frames In addition the filter also enables discarding of frames with illegal MAC addresses (for instance null MAC address or multicast source MAC address)

VLAN Every incoming frame is classified to a VLAN by the basic VLAN classification This is based on the VLAN in the frame or if the frame is untagged or the ingress port is VLAN unaware it is based on the ingress portrsquos default VLAN A VLAN classification includes the whole TCI (PCP DEI and VID) and also the TPID (C-tag or S-tag)

For double-tagged frames it is selectable whether the inner or the outer tag is used

The device can recognize S-tagged frames with the standard TPID (0x88A8) or S-tagged frames using a custom programmable value One custom value is supported by the device

QoS DP and DSCP Each frame is classified to a Quality of Service (QoS) class and a drop precedence level (frame color greenyellow) The QoS class and DP level are used throughout the device for providing queuing scheduling and congestion control guarantees to the frame according to what is configured for that specific QoS class and color

Basic ClassificationFrame Data Advanced Classification

IS1 First Lookup

Key - port mask- inner and outer VLAN tags (VID PCP DEI TPID)- SMAC DMAC- SIP DIP- TCPUDP ports- frame type DSCP range checkers

IS1 Third Lookup

IS1 Second Lookup

QoS class

DP level

VLAN tag header

Discard

Aggregation code

VLAN pop count

Frame data

Classified VLAN

DP level

Classified DSCP

VLAN pop cnt

QoS DP and DSCP

PCP from tag (inner or outer)DSCP from frame trusted values onlyRemaprewrite of DSCPPort default

VLAN tag from framePort VLAN

Frame Acceptance

Untagged S-tagged C-taggedSpecial frames

Aggregation Code

L2-L4 frame data

DSCP value

QoS class

Custom lookup

Product Overview

The QoS class and DP level in the basic classification are based on the class of service information in the framersquos VLAN tags (PCP and DEI) andor the DSCP values from the IP header Both IPv4 and IPv6 are supported If the frame is non-IP or untagged the portrsquos default QoS class and DP level are used

The DSCP values can be remapped before being used for QoS This is done using a common table mapping the incoming DSCP to a new value Remapping is enabled per port In addition for each DSCP value it is possible to specify whether the value is trusted for QoS purposes

Each IP frame is also classified to an internal DSCP value By default this value is taken from the IP header but it may be remapped using the common DSCP mapping table or rewritten based on the assigned QoS class The classified DSCP value may be written into the frame at egress ndash this is programmable in the rewriter

Aggregation Code The basic classification calculates an aggregation code which is used to select between ports that are member of a link aggregation group The aggregation code is based on selected Layer-2 through Layer-4 information such as MAC addresses IP addresses IPv6 flow label and TCPUDP port numbers The aggregation code ensures that frames belonging to the same conversation are using the same physical ports in a link aggregation group

2321 Advanced ClassificationFollowing basic classification Layer-2 and Layer-4 information is extracted from each frame and matched against a TCAM IS1 with one of the following six different IS1 keys

bull NORMAL Up to 128 entries with primary fields in key consisting of SMAC outer VLAN tag 32-bit source IP address IP protocol TCPUDP source and destination port

bull NORMAL_IP6 Up to 64 entries with primary fields in key consisting of SMAC inner and outer VLAN tags 128-bit source IP address IP protocol TCPUDP source and destination port

bull 7TUPLE Up to 64 entries with primary fields in key consisting of source and destination MAC addresses inner and outer VLAN tags 64-bit source and destination IP addresses IP protocol TCPUDP source and destination port

bull 5TUPLE_IP4 Up to 128 entries with primary fields in key consisting of inner and outer VLAN tags 32-bit source and destination IP addresses IP protocol TCPUDP source and destination port

bull S1_DBL_VID Up to 256 entries with primary fields in key consisting of inner and outer VLAN tags The TCAM embeds powerful protocol awareness for well-known protocols such as LLC SNAP IPv4 IPv6 and UDPTCP For each frame three keys are generated and matched against the TCAM The keys are selectable per ingress port per frame type (IPv4 IPv6 non-IP) per IS1 lookup

The actions associated with each entry (programmed into the TCAM action RAM) include the ability to overwrite or translate the classified VLAN overwrite the priority code point (PCP) or the drop eligibility indicator (DEI) overwrite the QoS class and DP level or overwrite the DSCP value Each of these actions is enabled individually for each of the three lookup

In addition a policy association group (PAG) is assigned to the frame The PAG identifies a security profile to which the frame belongs The PAG is used in the succeeding security frame processor IS2 to select which access control lists to apply to the frame The PAG enables creating efficient ACLs that only are applicable to frames with the same PAG

A lookup in IS1 can enable the use of a custom lookup in IS2 the security enforcement TCAM The custom lookup can match against selectable frame fields from the incoming frame In total 40 bytes from the frame are matched against the TCAM This is a powerful future-proofing feature enabling handling of new protocols

233 Versatile Content Aware Processor (VCAP)All frames are inspected by the VCAP IS2 before they are passed on to the Layer-2 forwarding The following illustration depicts VCAP security enforcement

Product Overview

Figure 3 bull Versatile Content Aware Processor

The VCAP uses a TCAM-based frame processor enabling implementation of a rich set of security features The flexible VCAP engine supports wire-speed frame inspection based on Layer 2-4 frame information including the ability to perform longest prefix matching and identifying port ranges The action associated with each VCAP entry (programmed into the VCAP action RAM) includes the ability to do frame filtering dual leaky bucket rate limitation (frame or byte based) snooping to CPU redirection to CPU mirroring 1588 time stamping and accounting Even though the VCAP is located in the ingress path of the device it possesses both ingress and egress capabilities

The VCAP embeds powerful protocol awareness for well-known protocols such as LLC SNAP ARP IPv4 IPv6 and UDPTCP IPv6 is supported with full matching against both the source and the destination IP addresses

Each frame is looked up three times in IS2 The first lookup is a host match lookup for IPv4 and IPv6 frames enabling MACIP binding and IP source guarding The key consists of information identifying the source host ingress port number source MAC address and full source IP address The output is an action informing the following two lookups in IS2 of whether the host is accepted into the network The following two lookups in IS2 construct a key based on the frame type (LLC SNAP ARP IPv4 IPv6 UDPTCP OAM custom) extracting relevant information IS2 supports up to 256 host match entries 128 LLC SNAP ARP IPv4-TCPUDP or OAM entries and 64 IPv6-TCPUDP and custom entries

234 PolicingEach frame is subject to a number of different policing operations The device features 192 programmable policers The policers are split into the followings groups

bull Queue policers ingress port number and QoS class determine which policer to usebull Port policers ingress port number determines which policer to usebull VCAP IS2 policers an IS2 action can point to a policerThe internal CPU port is the 12th port and also includes port and queue policers The policers can measure frame rates or bit rates

Each frame can trigger up to three policers a queue policer a port policer and a VCAP IS2 policer

Each policer is a MEF-compliant dual leaky bucket policer supporting both color-blind and color-aware operation The initial frame color is derived from the drop precedence level from the frame classification For color-aware operation a coupling mode is configurable for each policer

VCAP-II Security Enforcement

IS2 Host Match Lookup

IS2 First Lookup

Classified VLAN

Custom lookup

Security profile (PAG)

Frame DataACL Actions

PermitDenyPolice

RedirectCPU copy

MirrorTimestamp

Classified DSCP

Key L2-L4 frame data depending on frame type

IS2 Second Lookup

Key SMAC and SIP

Product Overview

Each frame is counted in statistics reflecting the ingress port the QoS class and whether the frame was discarded by one of the policers or not

Finally the analyzer contains a group of storm control policers that are capable of policing various kinds of flooding traffic as well as CPU directed learn traffic These policers are global policers working on all frames received by the switch Storm policers measure frame rates

235 Layer-2 ForwardingAfter the policers the Layer-2 forwarding block (the analyzer) handles all fundamental forwarding operations and maintains the associated MAC table the VLAN table and the aggregation table The device implements an 4K MAC table and a 4K VLAN table

The main task of the analyzer is to determine the destination port set of each frame This forwarding decision is based on various information such as the framersquos ingress port the source MAC address the destination MAC address the VLAN identifier as well as the framersquos VCAP action mirroring and the destination portrsquos link aggregation configuration

The switch performs Layer-2 forwarding of frames For unicast and Layer-2 multicast frames this means forwarding based on the destination MAC address and the VLAN For IPv4 and IPv6 multicast frames the switch performs Layer-2 forwarding but based on Layer-3 information such as the source IP address The latter enables source-specific IPv4 multicast forwarding (IGMPv3) and source-specific IPv6 multicast forwarding (MLDv2)

The following are some of the contributions to the Layer-2 forwarding

bull VLAN classification VLAN-based forward filtering includes source port filtering destination port filtering VLAN mirroring asymmetric VLANs and so on

bull Security enforcement The security decision made by the VCAP can for example redirect the frame to the CPU based on some abnormality detection filters

bull MSTP The VLAN identifier maps to a Multiple Spanning Tree instance which determines MSTP-based destination port filtering

bull MAC addresses Destination and source MAC address lookups in the MAC table determine if a frame is a learn frame a flood frame a multicast frame or a unicast frame

bull Learning By default the device performs wire-speed learning on all ports However certain ports could be configured with secure learning enabled where an incoming frame with unknown source MAC address is classified as a ldquolearn framerdquo and is redirected to the CPU The CPU performs the learning decision and also decides whether the frame is forwardedLearning can also be disabled In that case it does not matter if the source MAC address is in the MAC table

bull Link aggregation A frame targeted at a link aggregate is further processed to determine which of the link aggregate group ports the frame must be forwarded to

bull Mirroring Mirror probes may be set up in different places in the forwarding path for monitoring purposes As part of a mirror a copy of the frame is sent either to the CPU or to another port

236 Shared Queue System and Egress SchedulerThe analyzer provides the destination port set of a frame to the shared queue system It is the queue systemrsquos task to control the frame forwarding to all destination ports

The shared queue system embeds 175 megabits of memory that can be shared between all queues and ports The queue system implements egress queues per priority per ingress port The sharing of resources between queues and ports is controlled by an extensive set of thresholds The overall frame latency through the switch is low due to the shared queue system storing the frame only once

Each egress port implements a scheduler and shapers as shown in the following illustration Per egress port the scheduler sees the outcome of aggregating the egress queues (one per ingress port per QoS class) into eight QoS classes The aggregation is done in a frame based round-robin fashion (FBRR) per QoS class serving all ingress ports equally By default strict scheduling is performed between QoS classes for the port QoS class 7 has strict highest priority while QoS class 0 has strict lowest priority

Product Overview

Figure 4 bull Default Egress Scheduler and Shaper Configuration

Scheduling between QoS classes within the port can use one of three methods

bull Strict Frames with the highest QoS class are always transmitted before frames with lower QoS class This is shown in Figure 4 page 12

bull Combination of strict and Deficit Weighted Round Robin (DWRR) scheduling Any split of strict and DWRR QoS classes can be configured Figure 3 page 10 shows an example where QoS classes 6 and 7 are strict while QoS classes 0 through 5 are weighted Each QoS class sets a DWRR weight ranging from 0 to 31

bull Combination of strict and Frame Based Round Robin (FBRR) scheduling Any split between strict and FBRR QoS classes can be configured

All shapers shown in the following illustrations are single leaky bucket shapers

SE 146

STRICT

Input port 0

Input port 1

Input port 2

Input port 3

Input port 4

Input port 5

Input port 6

Input port 7

Input port 8

Input port 9

Input port 10

ICPU (11)

Input port 0

Input port 1

Input port 2

Input port 3

Input port 4

Input port 5

Input port 6

Input port 7

Input port 8

Input port 9

Input port 10

ICPU (11)

Output Port Shaper

QoS Class 7 Shaper

Virtual Input QueuesQoS Class 0

QoS Class 0 Shaper

Product Overview

Figure 5 bull Alternative Egress Scheduler and Shaper Configuration

237 Rewriter and Frame DepartureBefore transmitting the frame on the egress line the rewriter can modify selected fields in the frame such as VLAN tags DSCP value time stamping and FCS

The rewriter controls the final VLAN tagging of frames based on the classified VLAN the VLAN pop count and egress-determined VLAN actions from the ES0 TCAM lookup The egress VLAN actions are by default given by the egress port settings These include normal VLAN operations such as pushing a VLAN tag untagging for specific VLANs and simple translations of DEI and PCP

SE 146

STRICT

Input port 0

Input port 1

Input port 2

Input port 3

Input port 4

Input port 5

Input port 6

Input port 7

Input port 8

Input port 9

Input port 10

ICPU (11)

Input port 0

Input port 1

Input port 2

Input port 3

Input port 4

Input port 5

Input port 6

Input port 7

Input port 8

Input port 9

Input port 10

ICPU (11)

Output Port Shaper

QoS Class 7 Shaper

QoS Class 0 Shaper

Product Overview

Figure 6 bull Advanced Frame Rewriting

By using the egress TCAM ES0 much more advanced VLAN tagging operations can be achieved ES0 enables pushing up to two VLAN tags and allows for a flexible translation of the VLAN tag header The key into ES0 is the combination of the ingress port the egress port and the classified VLAN tag header

The PCP and DEI bits in the VLAN tag are subject to remarking based on translating the classified tag header or by using the classified QoS value and the framersquos drop precedence level from ingress

In addition the DSCP value in IP frames can be updated using the classified DSCP value and the framersquos drop precedence level from ingress The DSCP value can be remapped at egress before writing it into the frame

Finally the rewriter updates the FCS if the frame was modified before the frame is transmitted

The egress port module controls the flow control exchange of pause frames with a neighboring device when the interconnection link operates in full-duplex flow control mode When the connected device triggers flow control through transmission of a pause frame the MAC stops the egress schedulerrsquos forwarding of frames out of the port Traffic then builds up in the queue system but sufficient queuing is available to ensure wire speed loss-less operation

In half-duplex operation the port modulersquos egress path responds to back pressure generation from a connected device by collision detection and frame retransmission

238 CPU Port ModuleThe CPU port module contains eight CPU extraction queues and two CPU injection queues These queues provide an interface for exchanging frames between the internal CPU system and the switch core An external CPU using the serial interface can also inject and extract frames to and from the switch core by using the CPU port module Any Ethernet interface on the device can also be used for extracting and injecting frames

The switch core can intercept a variety of different frame types and copy or redirect these to the CPU extraction queues The classifier can identify a set of well-known frames such as IEEE reserved destination MAC addresses (BPDUs GARPs CCMLink trace) and IP-specific frames (IGMP MLD) The security TCAM IS2 provides another very flexible way of intercepting all kinds of frames for instance specific OAM frames ARP frames or explicit applications based on TCPUDP port numbers In addition frames can be intercepted based on the MAC table the VLAN table or the learning process

Whenever a frame is copied or redirected to the CPU a CPU extraction queue number is associated with the frame and used by the CPU port module when enqueuing the frame into the 8 CPU extraction queues The CPU extraction queue number is programmable for every interception option in the switch core

239 Synchronous Ethernet and Precision Time ProtocolThe device supports Layer-1 ITU-T G8261 Synchronous Ethernet and Layer-2 IEEE 1588 Precision Time Protocol for synchronizing network timing throughout a network

Advanced Frame Rewriting

ES0 Egress Lookup

Classified VLAN

Ingress port

VLAN ActionsTagging (pushpop 0-2 tags)

Translateoverwrite VLANSelect S-tagC-tag

Key Ingress portEgress portClassified VLAN

Egress port

VLAN pop count

Product Overview

Synchronous Ethernet allows for the transfer of network timing from one reference to all network elements In the device each port can recover its ingress clock and output the recovered clock to one of up to two recovered clock output pins External circuitry can then generate a stable reference clock input used for egress and core logic timing in the device

The Precision Time Protocol (PTP) allows for the network-wide synchronization of precise time of day It is also possible to derive network timing PTP can operate with a one-step clock or a two-step clock For one-step clocks a framersquos residence time is calculated and stamped into the frame at departure For two-step clocks a framersquos residence time is simply recorded and provided to the CPU for further processing The CPU can then initiate a follow-up message with the recorded timing

PTP is supported for a range of encapsulations including PTP over EthernetIEEE 8023 and PTP over UDP over IPv4IPv6

2310 CPU System and InterfacesThe device contains a fast 250 MHz 8051 and a high bandwidth Ethernet Frame DMA engine

The device supports external CPU register access through the on-chip PCIe 1x endpoint controller through specially formatted Ethernet frames on the NPI port (Microsemirsquos Versatile Register Access Protocol) or through register access interface using SPI protocol External CPUs can inject or extract Ethernet frames through NPI port through PCIe DMA access or through register readwrites (using any register-access interface)

Functional Descriptions

3 Functional Descriptions

This section provides information about the functional aspects of the VSC7511 Industrial IoT Ethernet switch device available configurations operational features and testing functionality

31 Port Numbering and MappingsThe switch core contains an internal port numbering domain where ports are numbered from 0 through 11 A port connects to a port module which connects to an interface macro which connects to IO pins on the device The interface macros are SERDES6G or copper transceivers

Some ports are internal to the device and do not connect to port modules or interface macros For example internal ports are used for frame injection and extraction to the CPU queues

The following table shows the default port numbering and how the ports map to port modules and interface macros

Ports 11 is an internal port used for injection and extraction of frames towards a CPU It does not have an associated port module and interface macro

The following table shows the fixed mapping from interface macros to the device IO pins

Table 3 bull Default Port Numbering and Port Mappings

Port Number Port Module MaximumPort Speed Default Interface Macro

0 DEV[0] 1 Gbps CUPHY_0

4 DEV[4] 1 Gbps SERDES1G_4

10 (NPI) DEV[10] 25 Gbps SERDES6G_2

11 (CPU) No port module No macro No macro

Table 4 bull Interface Macro to IO Pin Mapping

SERDES Macros IO Pin NamesCUPHY_0 to CUPHY_3 P0_D[30]N P0_D[30]P - P3_D[30]N P3_D[30]P

SERDES1G_4 to SERDES1G_5 S4_RXN S4_RXP S4_TXN S4_TXP - S5_RXN S5_RXP S5_TXN S5_TXP

311 Supported SerDes InterfacesThe device support a range of SerDes interfaces The following table lists the SerDes interfaces supported by the SerDes ports including standards data rates connectors medium and coding for each interface

312 PCIe ModeSerDes macro SERDES6G_2 can either be used as a standard Ethernet interface or as a PCIe interface This is controlled in HSIOHW_CFGPCIE_ENA When PCIe is enabled port 10 cannot be used in option 0 as the SerDes is occupied by the PCIe

313 Logical Port NumbersThe analyzer and the rewriter uses in many places a logical port number For instance when link aggregation is enabled all ports within a link aggregation group must be configured to use the physical port number of the port with the lowest port number within the group as logical port group ID The mapping to a logical port number is configured in ANAPORTPORT_CFGPORTID_VAL

32 Port ModulesAll port modules contain a MAC Ports connecting to a high-speed IO SerDes macro also contain a PCS

321 MACThis section provides information about the high-level functionality and the configuration options of the Media Access Controller (MAC) that is used in each of the port modules

The MAC supports the following speeds and duplex modes

bull SERDES1G ports 101001000 Mbps in full-duplex mode and 10100 Mbps in half-duplex modebull SERDES6G ports 1010010002500 Mbps in full-duplex mode and 10100 Mbps in half-duplex

modeThe following table lists the registers associated with configuring the MAC

Table 5 bull Supported SerDes Interfaces

Port Interface Specification Port Speed Data Rate Connector Medium Coding SER

100BASE-FX IEEE 8023 Clause 24 100M 125 Mbps SFP PCB 4B5B x x

SGMII Cisco 1G 125 Gbps PCB 8B10B x x

SFP SFP-MSA 1G 125 Gbps SFP PCB 8B10B x x

1000BASE-KX IEEE8023 Clause 70 1G 125 Gbps PCB backplane

8B10B x x

25G Proprietary (aligned to SFP)

25G 3125 Gbps PCB 8B10B x

Table 6 bull MAC Configuration Registers

Register Description ReplicationDEVCLOCK_CFG Reset and speed configuration Per port

DEVMAC_ENA_CFG Enabling of Rx and Tx data paths Per port

DEVMAC_MODE_CFG Port mode configuration Per port

DEVMAC_MAXLEN_CFG Maximum length configuration Per port

3211 ResetThere are a number of resets in the port module All of the resets can be set and cleared simultaneously By default all blocks are in the reset state With reference to register CLOCK_CFG the resets are as follows

bull MAC_RX_RST Reset of the MAC receiverbull MAC_TX_RST Reset of the MAC transmitterbull PORT_RST Reset of the ingress and egress queuesbull PCS_RX_RST Reset of the PCS decoderbull PCS_TX_RST Reset of the PCS encoderWhen changing the MAC configuration the port must go through a reset cycle This is done by writing register CLOCK_CFG twice On the first write the reset bits are set On the second write the reset bits are cleared Bits that are not reset bits in CLOCK_CFG must keep their new value for both writes

For more information about resetting a port see Port Reset Procedure page 221

3212 Port Mode ConfigurationThe MAC provides a number of handles for configuring the port mode With reference to the MAC_MODE_CFG MAC_IFG_CFG and MAC_ENA_CFG registers the handles are as follows

bull Duplex mode (FDX_ENA) Half or full duplexbull Data sampling (GIGA_MODE_ENA) Must be 1 in 1 Gbps and 25 Gbps and 0 in 10 Mbps and

100 Mbpsbull Enabling transmission and reception of frames (TX_ENARX_ENA) Clearing RX_ENA stops the

reception of frames and further frames are discarded An ongoing frame reception is interrupted Clearing TX_ENA stops the dequeuing of frames from the egress queues which means that frames are held back in the egress queues An ongoing frame transmission is completed

bull Tx-to-Tx inter-frame gap (TX_IFG)The link speed is configured using CLOCK_CFGLINK_SPEED with the following options

bull Link speed (CLOCK_CFGLINK_SPEED)1 Gbps (125 MHz clock)Ports 8 and 9 1 Gbps or 25 Gbps (125 MHz or 3125 MHz clock) The actual clock frequency depends on the SerDes configuration100 Mbps (25 MHz clock)10 Mbps (25 MHz clock)

3213 Half DuplexA number of special configuration options are available for half-duplex (HDX) mode

bull Seed for back-off randomizer Field MAC_HDX_CFGSEED seeds the randomizer used by the backoff algorithm Use MAC_HDX_CFGSEED_LOAD to load a new seed value

DEVMAC_TAGS_CFG VLAN tag length configuration Per port

DEVMAC_ADV_CHK_CFG Type length configuration Per port

DEVMAC_IFG_CFG Interframe gap configuration Per port

DEVMAC_HDX_CFG Half-duplex configuration Per port

SYSMAC_FC_CFG Flow control configuration Per port

DEVMAC_FC_MAC_LOW_CFG LSB of SMAC used in pause frames Per port

DEVMAC_FC_MAC_HIGH_CFG MSB of SMAC used in pause frames Per port

DEVMAC_STICKY Sticky bit recordings Per port

Table 6 bull MAC Configuration Registers (continued)

Register Description Replication

bull Backoff after excessive collision Field MAC_HDX_CFGWEXC_DIS determines whether the MAC backs off after an excessive collision has occurred If set backoff is disabled after excessive collisions

bull Retransmission of frame after excessive collision Field MAC_HDX_CFGRETRY_AFTER_EXC_COL_ENA determines whether the MAC retransmits frames after an excessive collision has occurred If set a frame is not dropped after excessive collisions but the backoff sequence is restarted This is a violation of IEEE 8023 but is useful in non-dropping half-duplex flow control operation

bull Late collision timing Field MAC_HDX_CFGLATE_COL_POS adjusts the border between a collision and a late collision in steps of 1 byte According to IEEE 8023 section 213 this border is permitted to be on data byte 56 (counting frame data from 1) that is a frame experiencing a collision on data byte 55 is always retransmitted but it is never retransmitted when the collision is on byte 57 For each higher LATE_COL_POS value the border is moved 1 byte higher

bull Rx-to-Tx inter-frame gap The sum of MAC_IFG_CFGRX_IFG1 and MAC_IFG_CFGRX_IFG2 establishes the time for the Rx-to-Tx inter-frame gap RX_IFG1 is the first part of half-duplex Rx-to-Tx inter-frame gap Within RX_IFG1 this timing is restarted if carrier sense (CRS) has multiple high-low transitions (due to noise) RX_IFG2 is the second part of half-duplex Rx-to-Tx inter-frame gap Within RX_IFG2 transitions on CRS are ignored

When enabling a port for half-duplex mode the switch core must also be enabled (SYSFRONT_PORT_MODEHDX_MODE)

3214 Frame and TypeLength CheckThe MAC supports frame lengths of up to 16 kilobytes The maximum length accepted by the MAC is configurable in MAC_MACLEN_CFGMAX_LEN

The MAC allows tagged frames to be 4 bytes longer and double-tagged frames to be 8 bytes longer than the specified maximum length (MAC_TAGS_CFGVLAN_LEN_AWR_ENA) The MAC must be configured to look for VLAN tags By default EtherType 0x8100 identifies a VLAN tag In addition a custom EtherType can be configured in MAC_TAGS_CFGTAG_ID The MAC can be configured to look for none one or two tags (MAC_TAG_CFGVLAN_AWR_ENA MAC_TAG_CFGVLAN_DBL_AWR_ENA)

The typelength check (MAC_ADV_CHK_CFGLEN_DROP_ENA) causes the MAC to discard frames with typelength errors (in-range and out-of-range errors)

3215 Flow Control (IEEE 8023x)The device supports both standard full-duplex flow control (IEEE 8023x) and priority-based flow control (IEEE 8021Qbb) This section describes standard full-duplex flow control and Priority-Based Flow Control (IEEE 8021Qbb) page 20 describes priority-based flow control

In full-duplex mode the MAC provides independent support for transmission of pause frames and reaction to incoming pause frames This allows for asymmetric flow control configurations

The MAC obeys received pause frames (MAC_FC_CFGRX_FC_ENA) by pausing the egress traffic according to the timer values specified in the pause frames In order to evaluate the pause time in the incoming pause frames the link speed must be specified (SYSMAC_FC_CFGFC_LINK_SPEED)

The transmission of pause frames is triggered by assertion of a flow control condition in the ingress queues caused by a queue filling exceeding a watermark For more information see Ingress Pause Request Generation page 126 The MAC handles the formatting and transmission of the pause frame The following configuration options are available

bull Transmission of pause frames (MAC_CFG_CFGTX_FC_ENA)bull Pause timer value used in transmitted pause frames (MAC_FC_CFGPAUSE_VAL_CFG)bull Flow control cancellation when the ingress queues de-assert the flow control condition by

transmission of a pause frame with timer value 0 (MAC_FC_CFGZERO_PAUSE_ENA)bull Source MAC address used in transmitted pause frames (MAC_FC_MAC_HIGH_CFG

MAC_FC_MAC_LOW_CFG)The MAC has the option to discard incoming frames when the remote link partner is not obeying the pause frames transmitted by the MAC The MAC discards an incoming frame if a Start-of-Frame is seen after the pause frame was transmitted It is configurable how long reaction time is given to the link partner

(MAC_FC_CFGFC_LATENCY_CFG) The benefit of this approach is that the queue system is not risking being overloaded with frames due to a non-complying link partner

In half-duplex mode the MAC does not react to received pause frames If the flow control condition is asserted by the ingress queues the industry-standard backpressure mechanism is used Together with the ability to retransmit frames after excessive collisions (MAC_HDX_CFGRETRY_AFTER_EXC_COL_ENA) this enables non-dropping half-duplex flow control

3216 Priority-Based Flow Control (IEEE 8021Qbb)The device supports priority-based flow control on all ports for all QoS classes The following table lists the specific registers associated with priority-based flow control

The device provides independent support for transmission of pause frames and reaction to incoming pause frames which allows asymmetric flow control configurations

The device obeys received pause frames per priority (ANAPFC_CFGRX_PFC_ENA) by pausing the egress traffic according to the timer values specified in the pause frames Transmission of frames belonging to QoS class n is paused if bit n is set in the priority_enable_vector in the incoming pause frame The pause time for QoS class n is given by time[n] from the pause frame The link speed must be specified in order to evaluate the pause times (ANAPFC_CFGFC_LINK_SPEED)

The transmission of priority-based pause frames is triggered by assertion of a flow control condition in the ingress queues caused by the memory consumption for a priority for an ingress port exceeding the BUF_Q_RSRV_I watermark For more information about the watermark see Table 96 page 122 The MAC handles the formatting and transmission of the priority-based pause frame The following configuration options are available

bull Transmission of priority-based pause frames per QoS class (QSYSSWITCH_PORT-MODETX_PFC_ENA)

bull Pause timer value used in transmitted priority-based pause frames (SYSMAC_FC_CFGPAUSE_VAL_CFG) All congested priorities use the same pause timer value Uncongested priorities use pause timer value 0

bull Source MAC address used in transmitted priority-based pause frames (MAC_FC_MAC_HIGH_CFG MAC_FC_MAC_LOW_CFG)

bull Priority protection mode (QSYSSWITCH_PORT_MODETX_PFC_MODE) which enables that when a priority congests and causes a pause frame to be sent then the pause frame will also pause all lower priorities

All transmitted priority-based pause frames have the priority_enable_vector set to 0xFF independently of whether a priority is enabled for flow control However the pause timer value time[n] is always 0 for disabled priorities

Table 7 bull Priority-Based Flow Control Configuration Registers

Register Description ReplicationSYSMAC_FC_CFG Flow control configuration Per port

ANAPFC_CFG Configuration of Rx priority-based flow control per priority

Per port

QSYSSWITCH_PORT_MODE Configuration of Tx priority-based flow control per priority

Per port

DEVPORT_MISCFWD_CTRL_ENA Enabling forwarding of priority-based pause frames to analyzer

Per port

ANACPU_FWD_BPDU_CFG Disable forwarding of priority-based pause frames beyond the analyzer

Per port

The MAC generates and transmits a priority-based pause frames whenever a queue is congested The device prevents excessive pause frame generation by waiting half the pause timer value between transmissions of pause frames

When an ingress queue de-asserts the flow control condition the MAC does not generate a priority-based pause frame with pause timer 0 for the priority Instead the timer in the link partner must expire However if another queue asserts flow control then a priority-based pause frame is generated for that priority and for all uncongested queues a pause timer 0 is signaled to the link partner

3217 Frame AgingThe following table lists the registers associated with frame aging

The MAC supports frame aging where frames are discarded if a maximum transit delay through the switch is exceeded All frames including CPU-injected frames are subject to aging The transit delay is time from when a frame is fully received until that frame is scheduled for transmission through the egress MAC The maximum allowed transit delay is configured in SYSFRM_AGING

Frame aging can be disabled per port (REWPORT_CFGAGE_DIS)

Discarded frames due to frame aging are counted in the c_tx_aged counter

3218 Rx and Tx Time StampsThe following table lists the registers associated with Rx and Tx time stamping

The MAC supports Rx and Tx time stamping where a framersquos receive time and transmit time are sampled using a nanoseconds counter The receive and transmit time stamps are shifted in time so that the resulting time stamps align with the exact reception and transmission of the first byte in the frame This adjusts for local delays in the receive path and the transmit path The time stamps are individually adjusted as follows

bull Rx time stamp Sampling of the MACrsquos nanoseconds counter plus DEVPORT_MODERX_PATH_DELAY

bull Tx time stamp Sampling of the MACrsquos nanoseconds counter plus DEVPORT_MODETX_PATH_DELAY

The Rx and Tx path delays are signed so negative adjustments can be achieved by setting the most significant bit

The PTP_PREDICT_CFG register must be configured according to the operating mode of the port

When the ingress port is operating in backplane mode (ANAPORTPTP_CFGPTP_BACKPLANE_MODE) the Rx time stamp is set to the value of the 4-byte reserved field at offset 16 bytes in the incoming framersquos PTP header instead of using the adjusted Rx time stamp from the MAC

Table 8 bull Frame Aging Configuration Registers

Register Description ReplicationSYSFRM_AGING Frame aging time None

REWPORT_CFGAGE_DIS Disable frame aging Per port

Table 9 bull Rx and Tx Time Stamping Register

Register Description ReplicationDEVPORT_MODETX_PATH_DELAY IO delays Per port

ANAPORTPTP_CFGPTP_BACKPLANE_MODE Ingress backplane configuration Per port

DEVPORT_MODERX_PATH_DELAY IO delays Per port

DEVPORT_MODEPTP_PREDICT_CFG IO delays Per port

The Rx time stamp follows the frame to the rewriter where it can be used to calculate the framersquos residence time or it can be sent to the CPU together with the frame The Tx time stamp is used by the rewriter to calculate the framersquos residence time or it can be written to a time stamp FIFO queue accessible by the CPU For more information about hardware time stamping see Configuring IO Delays page 157

322 PCSThis section provides information about the Physical Coding Sublayer (PCS) block where the auto-negotiation process establishes mode of operation for a link The PCS supports both SGMII mode and two SerDes modes 1000BASE-X and 100BASE-FX

The following table lists the registers associated with PCS

The PCS is enabled in PCS1G_CFGPCS_ENA and supports both SGMII and 1000BASE-X SERDES mode (PCS_MODE_CFGSGMII_MODE_ENA) as well as 100BASE-FX For information about enabling 100BASE-FX see 100BASE-FX page 24

The PCS also supports the IEEE 8023 Clause 66 unidrectional mode where the transmission of data is independent of the state of the receive link (PCS_MODE_CFGUNIDIR_MODE_ENA)

3221 Auto-NegotiationAuto-negotiation is enabled in PCS1G_ANEG_CFGANEG_ENA To restart the auto-negotiation process PCS1G_ANEG_CFGANEG_RESTART_ONE_SHOT must be set

The advertised word for the auto-negotiation process (base page) is configured in PCS1G_ANEG_CFGADV_ABILITY The next page information is configured in PCS1G_ANEG_NP_CFGNP_TX

When the auto-negotiation state machine has exchanged base page abilities the PCS1G_ANEG_STATUSPAGE_RX_STICKY is asserted indicating that the link partnerrsquos abilities were received (PCS1G_ANEG_STATUSLP_ADV_ABILITY)

If next page information is exchanged PAGE_RX_STICKY must be cleared next page abilities must be written to PCS1G_ANEG_NP_CFGNP_TX and PCS1G_ANEG_NP_CFGNP_LOADED_ONE_SHOT must be set When the auto-negotiation state machine has exchanged the next page abilities the PCS1G_ANEG_STATUSPAGE_RX_STICKY is asserted again indicating that the link partnerrsquos next page abilities were received (PCS1G_ANEG_STATUSLP_NP_RX) Additional exchanges of next page information are possible using the same procedure

Table 10 bull PCS Configuration Registers

Registers Description ReplicationPCS1G_CFG PCS configuration Per PCS

PCS1G_MODE_CFG PCS mode configuration Per PCS

PCS1G_SD_CFG Signal detect configuration Per PCS

PCS1G_ANEG_CFG Configuration of the PCS auto-negotiation process Per PCS

PCS1G_ANEG_NP_CFG Auto-negotiation next page configuration Per PCS

PCS1G_LB_CFG Loop-back configuration Per PCS

PCS1G_ANEG_STATUS Status signaling of the PCS auto-negotiation process Per PCS

PCS1G_ANEG_NP_STATUS Status signaling of the PCS auto-negotiation next page process

Per PCS

PCS1G_LINK_STATUS Link status Per PCS

PCS1G_LINK_DOWN_CNT Link down counter Per PCS

PCS1G_STICKY Sticky bit register Per PCS

After the last next page is received the auto-negotiation state machine enters the IDLE_DETECT state and the PCS1G_ANEG_STATUSPR bit is set indicating that ability information exchange (base page and possible next pages) is finished and software can now resolve priority Appropriate actions such as Rx or Tx reset or auto-negotiation restart can then be taken based on the negotiated abilities The LINK_OK state is reached one link timer period later

When the auto-negotiation process reaches the LINK_OK state PCS1G_ANEG_STATUSANEG_COMPLETE is asserted

3222 Link SurveillanceThe current link status can be observed through PCS1G_LINK_STATUSLINK_STATUS The LINK_STATUS is defined as either the PCS synchronization state or as bit 15 of PCS1G_ANEG_STATUSLP_ADV_ABILTY which carries information about the link status of the attached PHY in SGMII mode

Link down is defined as the auto-negotiation state machine being in neither the AN_DISABLE_LINK_OK state nor the LINK_OK state for one link timer period If a link down event occurs PCS1G_STICKYLINK_DOWN_STICKY is set and PCS1G_LINK_DOWN_CNT is incremented In SGMII mode the link timer period is 16 ms in SerDes mode the link timer period is 10 ms

The PCS synchronization state can be observed through PCS1G_LINK_STATUSSYNC_STATUS Synchronization is lost when the PCS is not able to recover and decode data received from the attached serial link

3223 Signal DetectThe PCS can be enabled to react to loss of signal through signal detect (PCS1G_SD_CFGSD_ENA) At loss of signal the PCS Rx state machine is restarted and frame reception stops If signal detect is disabled no action is taken upon loss of signal The polarity of signal detect is configurable in PCS1G_SD_CFGSD_POL

The source of signal detect is selected in PCS1G_SD_CFGSD_SEL to either the SerDes PMA or the PMD receiver If the SerDes PMA is used as source the SerDes macro provides the signal detect If the PMD receiver is used as source signal detect is sampled externally through one of the GPIO pins on the device For more information about the configuration of the GPIOs and signal detect see SI Boot Controller page 191

PCS1G_LINK_STATUSSIGNAL_DETECT contains the current value of the signal detect input

3224 Tx LoopbackFor debug purposes the Tx data path in the PCS can be looped back into the Rx data path This feature is enabled through PCS1G_LB_CFGTBI_HOST_LB_ENA

3225 Test PatternsThe following table lists the registers associated with configuring test patterns

PCS1G_TSTPAT_MODE_CFGJTP_SEL overwrites normal operation of the PCS and enables generation of jitter test patterns for debugging The jitter test patterns are defined in IEEE 8023 Annex 36A and the following patterns are supported

bull High frequency test patternbull Low frequency test patternbull Mixed frequency test patternbull Continuous random test pattern with long framesbull Continuous random test pattern with short frames

Table 11 bull Test Pattern Registers

Registers Description ReplicationPCS1G_TSTPAT_MODE_CFG Test pattern configuration Per PSC

PCS1G_TSTPAT_MODE_STATUS Test pattern status Per PCS

PCS1G_TSTPAT_MODE_STATUS register holds information about error and lock conditions while running the jitter test patterns

3226 Low Power IdleThe following table lists the registers associated with low power idle (LPI)

The PCS supports Energy Efficient Ethernet (EEE) as defined by IEEE 8023az The PCS converts Low Power Idle (LPI) encoding between the MAC and the serial interface transparently In addition the PCS provides control signals allowing to stop data transmission in the SerDes macro During low power idles the serial transmitter in the SerDes macro can be powered down only interrupted periodically while transmitting refresh information which allows the receiver to notice that the link is still up but in power down mode

For more information about powering down the serial transmitter in the SerDes macros see SERDES1G page 25 or SERDES6G page 29

It is not necessary to enable the PCS for EEE because it is controlled indirectly by the shared queue system It is possible however to manually force the PCS into the low power idle mode through PCS1G_LPI_CFGTX_ASSERT_LPIDLE During LPI mode the PCS constantly encodes low power idle with periodical refreshes For more information about EEE see Energy Efficient Ethernet page 127

The current low power idle state can be observed through PCS1G_LPI_STATUS for both receiver and transmitter

bull RX_LPI_MODE Set if the receiver is in low power idle modebull RX_QUIET Set if the receiver is in the Quiet state of the low power idle mode If cleared while

RX_LPI_MODE is set the receiver is in the refresh state of the low power idle modeThe same is observable for the transmitter through TX_LPI_MODE and TX_QUIET

If an LPI symbol is received the RX_LPI_EVENT_STICKY bit is set and if an LPI symbol is transmitted the TX_LPI_EVENT_STICKY bit is set These events are sticky

The PCS1G_LPI_WAKE_ERROR_CNT wake-up error counter increments when the receiver detects a signal and the PCS is not synchronized This can happen when the transmitter fails to observe the wake-up time or if the receiver is not able to synchronize in time

3227 100BASE-FXThe following table lists the registers associated with 100BASE-FX configuration

The PCS supports a 100BASE-FX mode in addition to the SGMII and 1000BASE-X SerDes modes The 100BASE-FX mode uses 4-bit5-bit coding as specified in IEEE 8023 Clause 24 for fiber connections The 100BASE-FX mode is enabled through PCS_FX100_CFGPCS_ENA which masks out all PCS1G related registers

The following options are available

Table 12 bull Low Power Idle Registers

Registers Description ReplicationPCS1G_LPI_CFG Configuration of the PCS low power idle process Per PSC

PCS1G_LPI_WAKE_ERROR_CNT Error counter Per PCS

PCS1G_LPI_STATUS Low Power Idle status Per PCS

Table 13 bull 100BASE-FX Registers

Registers Description ReplicationPCS_FX100_CFG Configuration of the PCS 100BASE-FX mode Per PSC

PCS_FX100_STATUS Status of the PCS 100BASE-FX mode Per PCS

Far-End Fault facility In 100BASE-FX the PCS supports the optional Far-End Fault facility Both Far-End Fault generation (PCS_FX100_CFGFEF_GEN_ENA) and Far-End Fault Detection (PCS_FX100_CFGFEF_CHK_ENA) are supported An Far-End Fault incident is recorded in PCS_FX100_STATUSFEF_FOUND

Signal Detect 100BASE-FX has a similar signal detect scheme to the SGMII and SerDes modes For 100BASE-FX PCS_FX100_CFGSD_ENA enables signal detect PCS_FX100_CFGSD_POL controls the polarity and PCS_FX100_CFGSD_SEL selects the input source The current status of the signal detect input can be observed through PCS_FX100_STATUSSIGNAL_DETECT For more information about signal detect see Signal Detect page 23

Link Surveillance The PCS synchronization status can be observed through PCS_FX100_STATUSSYNC_STATUS When synchronization is lost the link breaks and PCS_FX100_STATUSSYNC_LOST_STICKY is set The PCS continuously tries to recover the link

Unidirectional mode 100BASE-FX has a similar unidirectional mode as SGMII and SerDes modes PCS_FX100_CFGUNIDIR_MODE_ENA enables unidirectional mode

33 SERDES1GSERDES1G is a high-speed SerDes interface that operates at 1 Gbps (SGMIISerDes) and 100 Mbps (100BASE-FX) The 100BASE-FX mode is supported by oversampling

The following table lists the registers associated with SERDES1G

For increased performance in specific application environments SERDES1G supports the following

bull Programmable loop-bandwidth and phase regulation of deserializerbull Input buffer signal detectloss of signal (LOS) optionsbull Input buffer with equalizationbull Programmable output buffer features including

bull De-emphasisbull Amplitude drive levelsbull Slew rate controlbull Idle mode

bull Synchronous Ethernet supportbull Loopbacks for system test

331 SERDES1G Basic ConfigurationThe SERDES1G is enabled in SERDES1G_COMMON_CFGENA_LANE By default the SERDES1G is held reset and must be released from reset before the interface is active This is done through SERDES1G_COMMON_CFGSYS_RST and SERDES1G_MISC_CFGLANE_RST

3311 SERDES1G Frequency ConfigurationTo operate the SERDES1G block at 125 GHz (corresponding to 1 Gbps data rate) the internal macro PLL must be configured as follows

Table 14 bull SERDES1G Registers

Registers Description ReplicationSERDES1G_COMMON_CFG Common configuration Per SerDes

SERDES1G_DES_CFG Deserializer configuration Per SerDes

SERDES1G_IB_CFG Input buffer configuration Per SerDes

SERDES1G_SER_CFG Serializer configuration Per SerDes

SERDES1G_OB_CFG Output buffer configuration Per SerDes

SERDES1G_PLL_CFG PLL configuration Per SerDes

SERDES1G_MISC_CFG Miscellaneous configuration Per SerDes

1 Configure SERDES1G_PLL_CFGPLL_FSM_CTRL_DATA to 2002 Set SYS_RST = 0 (active) and PLL_FSM_ENA = 0 (inactive)3 Set SYS_RST = 1 (deactive) and PLL_FSM_ENA = 1 (active)

332 SERDES1G Loopback ModesThe SERDES1G interface supports two different loopback modes for testing and debugging data paths equipment loopback and facility loopback

3321 Equipment Loopback (SERDES1G_COMMON_CFGENA_ELOOP)Data is looped back from serializer output to deserializer input and the receive clock is recovered The equipment loopback includes all transmit and receive functions except for the input and output buffers The Tx data can still be observed on the output

3322 Facility Loopback (SERDES1G_COMMON_CFGENA_FLOOP)The clock and parallel data output from deserializer are looped back to the serializer interface Incoming serial data passes through the input buffer the CDR the deserializer back to the serializer and finally out through the output buffer

Only one of the loopbacks can be enabled at the same time

The following illustration shows the loopback paths

Figure 7 bull SERDES1G Loopback Modes

333 Synchronous EthernetThe SERDES1G block can recover the clock from the received data and apply the clock to either a per-SerDes recovered clock output pin (SERDES1G_COMMON_CFGRECO_SEL_A) or a common recovered clock output pin that may also be driven by another SerDes macros as well (SERDES1G_COMMON_CFGRECO_SEL_B) Note that only one macro should drive the common recovered clock output pin at the same time

In addition it is possible to squelch the recovered clock if the associated PCS cannot detect valid data (SERDES1G_COMMON_CFGSE_AUTO_SQUELCH_A_ENA and SERDES1G_COMMON_CFGSE_AUTO_SQUELCH_B_ENA)

For more information about Synchronous Ethernet see Layer 1 Timing page 152

Equipment

Tx (PN)

Rx (PN)ESD Input

Buffer

Output Buffer

EquipmentLoop

Rx Path

Tx Path

Facility Loop

Deserializer

Serializer

Equipment

334 SERDES1G Deserializer ConfigurationThe SERDES1G block includes digital control logic that interacts with the analog modules within the block and compensates for the frequency offset between the received data and the internal high-speed reference clock To gain high jitter performance the phase regulation is a PI-type regulator whose proportional (P) and integrative (I) characteristics can be independently configured The integrative part of the phase regulation loop is configured inSERDES1G_DES_CFGDES_PHS_CTRL The limits of the integrator are programmable allowing different settings for the integrative regulation while guaranteeing that the proportional part still is stronger than the integrative part Integrative regulation compensates frequency modulation from DC up to cut-off frequency Frequencies above the cut-off frequency are compensated by the proportional part The time constant of the integrator is controlled independently of the proportional regulation by SERDES1G_DES_CFGDES_BW_HYST The DES_BW_HYST register field is programmable in a range from 3 to 7 The lower the configuration setting the smaller the time-constant of the integrative regulation For normal operation configure DES_BW_HYST to 5

The cut-off-frequency is calculated to

fco = 1(2 times PI times 128 times PLL period times 32 times 2^(DES_BW_HYST + 1 ndash DES_BW_ANA))

PLL period = 1(data rate)

The integrative regulator can compensate a static frequency offset within the programmed limits down to a remaining frequency error of below 4 ppm In steady state the integrator toggles between two values around the exact value and the proportional part of the phase regulation takes care of the remaining phase error

The loop bandwidth for the proportional part of the phase regulation loop is controlled by configuring SERDES1G_DES_CFGDES_BW_ANA

The fastest loop bandwidth setting (lowest configuration value) results in a loop bandwidth that is equal to the maximum frequency offset compensation capability For improved jitter performance use a setting with sufficient margin to track the expected frequency offset rather than using the maximum frequency offset For example if a 100 ppm offset is expected use a setting that is four times higher than the offset

The following table provides the limits for the frequency offset compensation The values are theoretical limits for input signals without jitter because the actual frequency offset compensation capability is dependent on the toggle rate of the input data and the input jitter Note that only applicable configuration values are listed

In the event of an 180deg phase jump of the incoming data signal the sampling stage of the deserializer may become stuck To prevent this situation the SERDES1G provides a 180deg deadlock protection mechanism (SERDES1G_DES_CFGDES_MBTR_CTRL) If this mechanism is enabled a small frequency offset is applied to the phase regulation loop The offset is sufficient to move the sampling point out of the 180deg deadlock region while at the same time small enough to allow the regulation loop to compensate when the sample point is within the data eye

335 SERDES1G Serializer ConfigurationThe serializer provides the ability to align the phase of the internal clock and data to a selected source (SERDES1G_SER_CFGSER_ENALI) The phase align logic is used when SERDES1G operates in the facility loopback mode

Table 15 bull SERDES1G Loop Bandwidth

DES_BW_ANA Limits4 1953 ppm

5 977 ppm

6 488 ppm

7 244 ppm

336 SERDES1G Input Buffer ConfigurationThe SERDES1G input buffer supports the following configurable options

bull 100BASE-FX mode supportbull Signal detection threshold configurablebull Configurable equalization including corner frequency configuration for the equalization filterbull DC voltage offset compensationbull Configurable common mode voltage (CMV) terminationbull Selectable hysteresis configurable hysteresis levelsWhen the SerDes interface operates in 100BASE-FX mode the input buffer of the SERDES1G macro must also be configured for 100BASE-FX (SERDES1G_IB_CFGIB_FX100_ENA)

The input buffer provides an option to configure the threshold level of the signal detect circuit to adapt to different input amplitudes The signal detect circuit can be configured by SERDES1G_IB_CFGIB_ENA_DETLEV and SERDES1G_IB_CFGIB_DET_LEV

The SERDES1G block offers options to compensate for channel loss Degraded signals can be equalized and the corner frequency of the equalization filter can be adapted to the channel behavior The equalization settings are configured by SERDES1G_IB_CFGIB_EQ_GAIN and SERDES1G_IB_CFGIB_CORNER_FREQ

The SERDES1G block can compensate for possible DC-offset which can distort the received input signal by enabling SERDES1G_IB_CFGIB_ENA_OFFSET_COMP during normal reception

The common-mode voltage (CMV) input termination can be set to either an internal reference voltage or to VDD_A To allow external DC-coupling of the input buffer to an output buffer set the CMV input termination to the internal reference voltage with internal DC-coupling disabled SERDES1G_IB_CFGIB_ENA_DC_COUPLING controls internal DC-coupling and SERDES1G_IB_CFGIB_ENA_CMV_TERM controls CMV input termination The following modes are defined by CMV input termination and DC-coupling

bull SGMII compliant mode with external AC coupling (IB_ENA_DC_COUPLING = 0 IB_ENA_CMV_TERM = 1)

bull Microsemi-mode with external DC-coupling to another Versatile output buffer which can operate DC-coupled to the input buffer (IB_ENA_DC_COUPLING = 0 IB_ENA_CMV_TERM = 0)

bull 100BASE-FX low frequency mode (IB_ENA_DC_COUPLING = 1 IB_ENA_CMV_TERM = 1)The SERDES1G macro supports input hysteresis which is required for some standards (SGMII) The hysteresis function is enabled by SERDES1G_IB_CFGIB_ENA_HYST and hysteresis levels are defined by SERDES1G_IB_CFGIB_HYST_LEV

Note Hysteresis and DC offset compensation cannot be enabled at the same time For more information see IB_ENA_OFFSET_COMP in the SERDES1G_IB_CFG register

337 SERDES1G Output Buffer ConfigurationThe SERDEDS1G output buffer supports the following configurable options

bull Configurable amplitude settingsbull Configurable slew rate controlbull 3 dB de-emphasis selectablebull Idle modeThe output amplitude of the output buffer is controlled by SERDES1G_OB_CFGOB_AMP_CTRL It can be adjusted in 50 mV steps from 04 V to 11 V peak-to-peak differential The output amplitude also depends on the output bufferrsquos supply voltage For more information about dependencies between the maximum achievable output amplitude and the output bufferrsquos supply voltage refer to the electrical section for the dependencies between the maximum achievable output amplitude and the output bufferrsquos supply voltage

Adjust the slew rate adjustment using SERDES1G_OB_CFGOB_SLP

The output buffer supports a fixed 3 dB de-emphasis (SERDES1G_SER_CFGSER_DEEMPH)

The output buffer supports an idle mode (SERDES1G_SER_CFGSER_IDLE) which results in an differential peak-to-peak output amplitude of less than 30 mV

338 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX To enable clock and data recovery when operating the SERDES1G in 100BASE-FX mode set the following registers

bull SERDES1G_MISC_CFGDES_100FX_CPMD_ENA = 1bull SERDES1G_IBJ_CFGIB_FX100_ENA = 1bull SERDES1G_DES_CFGDES_CPMD_SEL = 2

339 Energy Efficient EthernetThe SERDES1G block supports Energy Efficient Ethernet as defined in IEEE 8023az To enable the low power modes SERDES1G_MISC_CFGTX_LPI_MODE_ENA and SERDES1G_MISC_CFGRX_LPI_MODE_ENA must be set At this point the attached PCS takes full control over the high-speed output and input buffer activity

3310 SERDES1G Data InversionThe data streams in the transmit and the receive direction can be inverted using SERDES1G_MISC_CFGTX_DATA_INV_ENA and SERDES1G_MISC_CFGRX_DATA_INV_ENA Effectively this allows for swapping the P and N lines of the high-speed serial link

34 SERDES6GThe SERDES6G is a high-speed SerDes interface that operates at 100 Mbps (100BASE-FX) 1 Gbps (SGMIISerDes) 25 Gbps (SGMII) and 5 Gbps (QSGMII) The 100BASE-FX mode is supported by oversampling

bull Baud rate support configurable from 1 Gbps to 25 G for quarter and half rate modesbull Programmable loop bandwidth and phase regulation for the deserializerbull Configurable input buffer feature such as signal detectloss of signal (LOS) optionsbull Configurable output buffer features such as programmable de-emphasis amplitude drive levels and

slew rate controlbull Synchronous Ethernet supportbull Loopbacks for system test

SERDES6G_IB_CFG1 Input buffer configuration Per SerDes

SERDES6G_OB_CFG1 Output buffer configuration Per SerDes

3411 SERDES6G PLL Frequency ConfigurationTo operate the SERDES6G block at the correct frequency configure the internal macro as follows PLL calibration is enabled through SERDES6G_PLL_CFGPLL_FSM_ENA

bull Configure SERDES6G_PLL_CFGPLL_FSM_CTRL_DATA in accordance with data rates listed in the following tables

bull Set SYS_RST = 0 (active) and PLL_FSM_ENA = 0 (inactive)bull Set SYS_RST = 1 (deactive) and PLL_FSM_ENA = 1 (active)

3412 SERDES6G Frequency ConfigurationThe following table lists the range of data rates that are supported by the SERDES6G block

3421 Equipment Loopback (SERDES6G_COMMON_CFGENA_ELOOP)Data is looped back from serializer output to the deserializer input and the receive clock is recovered The equipment loopback includes all transmit and receive functions except for the input and output buffers The Tx data can still be observed on the output

The following illustration shows the loopback paths for the SERDESG6

Table 17 bull PLL Configuration

Mode SERDES6G_PLL_CFGPLL_FSM_CTRL_DATASGMIISerDes 1 Gbps data 60

SGMII 25 Gbps data 48

Table 18 bull SERDES6G Frequency Configuration Registers

ConfigurationSGMIISerDes1 Gbps

SGMII25 Gbps

SERDES6G_PLL_CFGPLL_ROT_FRQ 0 1

SERDES6G_PLL_CFGPLL_ROT_DIR 1 0

SERDES6G_PLL_CFGPLL_ENA_ROT 0 1

SERDES6G_COMMON_CFGQRATE 1 0

SERDES6G_COMMON_CFGHRATE 0 1

343 Synchronous EthernetThe SERDES6G block can recover the clock from the received data and apply the clock to either a per-SerDes recovered clock output pin (SERDES6G_COMMON_CFGRECO_SEL_A) or a common recovered clock output pin that may be driven by another SerDes macros as well (SERDES6G_COMMON_CFGRECO_SEL_B) Note that only one macro should drive the common recovered clock output pin at the same time

344 SERDES6G Deserializer ConfigurationThe SERDES6G block includes digital control logic that interacts with the analog modules within the block and compensates for the frequency offset between the received data and the internal high-speed reference clock To gain high jitter performance the phase regulation is a PI-type regulator whose proportional (P) and integrative (I) characteristics can be independently configured

The integrative part of the phase regulation loop is configured in SERDES6G_DES_CFGDES_PHS_CTRL The limits of the integrator are programmable allowing different settings for the integrative regulation while guaranteeing that the proportional part still is stronger than the integrative part Integrative regulation compensates frequency modulation from DC up to cut-off frequency Frequencies greater than the cut-off frequency are compensated by the proportional part

The DES_BW_HYST register field controls the time constant of the integrator independently of the proportional regulator The range of DES_BW_HYST is programmable as follows

bull Full rate mode = 3 to 7bull Quarter-rate mode = 1 to 7The lower the configuration setting the smaller the time-constant of the integrative regulation For normal operation configure DES_BW_HYST to 5

Equipment

Tx (PN)

Rx (PN)ESD Input

Buffer

Output Buffer

EquipmentLoop

Rx Path

Tx Path

Facility Loop

Deserializer

Serializer

Equipment

PLL period = 1(n times data rate)

where n = 1 (full rate mode) or 4 (quarter-rate mode)

The integrative regulator can compensate a static frequency offset within the programmed limits down to a remaining frequency error of below 4 ppm In steady state the integrator toggles between two values around the exact value and the proportional part of the phase regulation takes care of the remaining phase error The loop bandwidth for the proportional part of the phase regulation loop is controlled by configuring SERDES6G_DES_CFGSWANA

The following table provides the limits for the frequency offset compensation The values are theoretical limits for input signals without jitter because the actual frequency offset compensation capability is dependent on the toggle rate of the input data and the input jitter Note that only applicable configuration values are listed HRATE and QRATE are the configuration settings of SERDES6G_COMMON_CFGHRATE and SERDES6G_COMMON_CFGQRATE

346 SERDES6G Input Buffer ConfigurationThe SERDES6G input buffer supports configurable options for

bull Automatic input voltage offset compensationbull Loss of signal detectionThe input buffer is typically AC-coupled As a result the common-mode termination is switched off (SERDES6G_IB_CFG1IB_CTERM_ENA) In order to support type-2 loads (DC-coupling at 10 V termination voltage) according to the OIF CEI specifications common-mode termination must be enabled

DES_BW_ANA

Limits when HRATE = 1QRATE = 0

2 1953 ppm

3 1953 ppm 977 ppm

4 977 ppm 488 ppm

5 488 ppm 244 ppm

6 244 ppm 122 ppm

7 122 ppm 61 ppm

The sensitivity of the level detect circuit can be adapted to the input signalrsquos characteristics (amplitude and noise) The threshold value for the level detect circuit is set in SERDES6G_IB_CFGIB_VBCOM The default value is suitable for normal operation

When the SerDes interface operates in 100BASE-FX mode the input buffer of the SERDES6G macro must also be configured for 100BASE-FX (SERDES6G_IB_CFGIB_FX100_ENA)

During test or reception of low data rate signals (for example 100BASE-FX) the DC-offset compensation must be disabled For all other modes the DC-offset compensation must be enabled for optimized performance DC-offset compensation is controlled by SERDES6G_IB_CFG1IB_ENA_OFFSAC and SERDES6G_IB_CFG1IB_ENA_OFFSDC

bull Amplitude controlbull De-emphasis and output polarity inversionbull Slew rate controlbull Skew adjustmentbull Idle modeThe maximum output amplitude of the output buffer depends on the output bufferrsquos supply voltage For interface standards requiring higher output amplitudes (backplane application or interface to optical modules for example) the output buffer can be supplied from a 12 V instead of a 10 V supply By default the output buffer is configured for 12 V mode because enabling the 10 V mode when supplied from 12 V must be avoided The supply mode is configured by SERDES6G_OB_CFGOB_ENA1V_MODE

The output buffer supports a four-tap pre-emphasis realized by one pre-cursor the center tap and two post cursors The pre-cursor coefficient C0 is configured by SERDES6G_SER_CFGOB_PREC C0 is a 5-bit value with the most significant bit defining the polarity The lower 4-bit value is hereby defined as B0 The first post-cursor coefficient C2 is configured by SERDES6G_OB_CFGOB_POST0 C2 is a 6-bit value with the most significant bit defining the polarity The lower 5-bit value is hereby defined as B2 The second post-cursor coefficient C3 is configured by SERDES6G_SER_CFGOB_POST1 C3 is 5-bit value with the most significant bit defining the polarity The lower 4-bit value is hereby defined as B3 The center-tap coefficient C1 is a 6-bit value Its polarity can be programmed by SERDES6G_OB_CFGOB_POL which is hereby defined as p1 For normal operation SERDES6G_OB_CFGOB_POL must be set to 1 The value of the 6 bits forming C1 is calculated by the following equation

Equation 1 C1 (64 ndash (B0 + B2 + B3)) times p1

The output amplitude is programmed by SERDES6G_OB_CFG1OB_LEV which is a 6-bit value This value is internally increased by 64 and defines the amplitude coefficient K The range of K is therefore 64 to 127 The differential peak-peak output amplitude is given by 875 mV times K The maximum peak-peak output amplitude depends on the data stream and can be calculated to

Equation 2 H(Z) = 4375 mVpp times K times (C0 times z1 + C1 times z0 + C2 times zndash1 + C3 times zndash2)64

with zn denoting the current bits of the data pattern defining the amplitude of Z The output amplitude also depends on the output bufferrsquos supply voltage

The configuration bits are summarized in the following table

Table 20 bull De-Emphasis and Amplitude Configuration

Configuration Value DescriptionOB_PREC Signed 5-bit value Pre-cursor setting C0 Range is ndash15 to 15

OB_POST0 Signed 6-bit value First post-cursor setting C2 Range is ndash31 to 31

OB_POST1 Signed 5-bit value Second post-cursor setting C3 Range is ndash15 to 15

OB_LEV Unsigned 6-bit value Amplitude coefficient K = OB_LEV + 64 Range is 0 to 63

The output buffer provides the following additional options to configure its behavior

bull Idle mode Enabling idle mode (SERDES6G_OB_CFGOB_IDLE) results in a remaining voltage of less than 30 mV at the buffers differential outputs

bull Slew Rate Slew rate can be controlled by two configuration settings SERDES6G_OB_CFGOB_SR_H provides coarse adjustments and SERDES6G_OB_CFGOB_SR provides fine adjustments

bull Skew control In 1 Gbps SGMII mode skew adjustment is controlled by SERDES6G_OB_CFG1OB_ENA_CAS Skew control is not applicable to other modes

348 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX To enable clock and data recovery when operating SERDES6G in 100BASE-FX mode set the following register fields

349 Energy Efficient EthernetThe SERDES6G block supports Energy Efficient Ethernet as defined in IEEE Draft P8023az To enable the low power modes SERDES6G_MISC_CFGTX_LPI_MODE_ENA and SERDES6G_MISC_CFGRX_LPI_MODE_ENA must be set At this point the attached PCS takes full control over the high-speed output and input buffer activity

3410 SERDES6G Data InversionThe data streams in the transmit and the receive direction can be inverted using SERDES6G_MISC_CFGTX_DATA_INV_ENA and SERDES6G_MISC_CFGRX_DATA_INV_ENA This effectively allows for swapping the P and N lines of the high-speed serial link

3411 SERDES6G Signal Detection EnhancementsSignal detect information from the SERDES6G macro is normally directly passed to the attached PCS It is possible to enable a hysteresis such that the signal detect condition must be active or inactive for a certain time before it is signaled to the attached PCS

The signal detect assertion time (the time signal detect must be active before the information is passed to a PCS) is programmable in SERDES6G_DIG_CFGSIGDET_AST The signal detect de-assertion time (the time signal detect must be inactive before the information is passed to a PCS) is programmable in SERDES6G_DIG_CFGSIGDET_DST

3412 High-Speed IO Configuration BusThe high-speed SerDes macros are configured using the high-speed IO configuration bus (MCB) which is a serial bus connecting the configuration register set with all the SerDes macros The HSIOMCB_SERDES1G_ADDR_CFG register is used for SERDES1G macros and HSIOMCB_SERDES6G_ADDR_CFG register is used for SERDES6G macros The configuration busses are used for both writing to and reading from the macros

The SERDES6G macros are programmed as follows

bull Program the configuration registers for the SERDES6G macro For more information about configuration options see SERDES6G page 29

bull Transfer the configuration from the configuration registers to one or more SerDes macros by writing the address of the macro (MCB_SERDES6G_ADDR_CFGSERDES6G_ADDR) and initiating the write access (MCB_SERDES6G_ADDR_CFGSERDES6G_WR_ONE_SHOT)

OB_POL 01

Non-inverting modeInverting mode

Table 20 bull De-Emphasis and Amplitude Configuration (continued)

Configuration Value Description

bull The SerDes macro address is a mask with one bit per macro so that one or more macros can be programmed at the same time

bull The MCB_SERDES6G_ADDR_CFGSERDES6G_WR_ONE_SHOT are automatically cleared when the writing is done

The configuration and status information in the SERDES6G macros can be read as follows

bull Transfer the configuration and status from one or more SerDes macros to the configuration registers by writing the address of the macro (MCB_SERDES6G_ADDR_CFGSERDES6G_ADDR) and initiating the read access (MCB_SERDES6G_ADDR_CFGSERDES6G_RD_ONE_SHOT)

bull The SerDes macro address is a mask with one bit per macro so that configuration and status information from one or more macros can be read at the same time When reading from more than one macro the results from each macro are ORrsquoed together

bull The MCB_SERDES6G_ADDR_CFGSERDES6G_RD_ONE_SHOT are automatically cleared when the reading is done

The SERDES1G macros are programmed similarly to the SERDES6G macros except that MCB_SERDES1G_ADDR_CFG must be used for register access For more information about configuration options see SERDES1G page 25

35 Copper TransceiversThis section describes the high-level functionality and operation of four built-in copper transceivers The integration is kept as close to multichip PHY and switch designs as possible This allows a fast path for software already running in a similar distributed design while still benefiting from the cost savings provided by the integration

351 Register AccessThe registers of the integrated transceivers are not placed in the memory map of the switch but are attached instead to the built-in MII management controller 0 of the device As a result PHY registers are accessed indirectly through the switch registers For more information see MII Management Controller page 201

In addition to providing the IEEE 8023 specified 16 MII Standard Set registers the PHYs contain an extended set of registers that provide additional functionality The devices support the following types of registers

bull IEEE Clause 22 device registers with addresses from 0 to 31bull Two pages of extended registers with addresses from 16E1 through 30E1 and 16E2 through 30E2bull General-purpose registers with addresses from 0G to 30Gbull IEEE Clause 45 device registers accessible through the Clause 22 registers 13 and 14 to support

IEEE 8023az Energy Efficient Ethernet registersThe memory mapping is controlled through PHY_MEMORY_PAGE_ACCESSPAGE_ACCESS_CFG The following illustration shows the relationship between the device registers and their address spaces

Figure 9 bull Register Space Layout

IEEE 8023 Standard Registers

Main Registers

0x0000

131415

16171819

ExtendedRegisters 1

0x0001

16E117E118E119E1

ExtendedRegisters 2

0x0002

16E217E218E219E2

ExtendedRegisters 3

0x0003

16E317E318E319E3

General Purpose Registers

0x0010

0G1G2G3G

16G17G18G19G

Clause 45Registers

3511 Broadcast WriteThe PHYs can be configured to accept MII PHY register write operations regardless of the destination address of these writes This is enabled in PHY_CTRL_STAT_EXTBROADCAST_WRITE_ENA This enabling allows similar configurations to be sent quickly to multiple PHYs without having to do repeated MII PHY write operations This feature applies only to writes MII PHY register read operations are still interpreted with ldquocorrectrdquo address

3512 Register ResetThe PHY can be reset through software enabled in PHY_CTRLSOFTWARE_RESET_ENA Enabling this field initiates a software reset of the PHY Fields that are not described as sticky are returned to their default values Fields that are described as sticky are only returned to defaults if sticky-reset is disabled through PHY_CTRL_STAT_EXTSTICKY_RESET_ENA Otherwise they retain their values from prior to the software reset A hardware reset always brings all PHY registers back to their default values

352 Cat5 Twisted Pair Media InterfaceThe twisted pair interfaces are compliant with IEEE 8023-2008 and IEEE 8023az for Energy Efficient Ethernet

3521 Voltage-Mode Line DriverUnlike many other gigabit PHYs this PHY uses a patented voltage-mode line driver that allows it to fully integrate the series termination resistors (required to connect the PHYrsquos Cat5 interface to an external 11 transformer) Also the interface does not require placement of an external voltage on the center tap of the magnetic The following illustration shows the connections

Figure 10 bull Cat5 Media Interface

TXVPA_n

TXVNA_n

TXVPB_n

TXVNB_n

TXVPC_n

TXVNC_n

TXVPD_n

TXVND_n

PHY Port_n TransformerA+

Andash

Bndash

Cndash

Dndash

1000 pF2 kV

01 microF

3522 Cat5 Auto-Negotiation and Parallel DetectionThe integrated transceivers support twisted pair auto-negotiation as defined by clause 28 of the IEEE 8023-2008 The auto-negotiation process evaluates the advertised capabilities of the local PHY and its link partner to determine the best possible operating mode In particular auto-negotiation can determine speed duplex configuration and master or slave operating modes for 1000BASE-TX Auto-negotiation also allows the device to communicate with the link partner (through the optional ldquonext pagesrdquo) to set attributes that may not otherwise be defined by the IEEE standard

If the Cat5 link partner does not support auto-negotiation the device automatically use parallel detection to select the appropriate link speed

Auto-negotiation can be disabled by clearing PHY_CTRLAUTONEG_ENA If auto-negotiation is disabled the state of the SPEED_SEL_MSB_CFG SPEED_SEL_LSB_CFG and DUPLEX_MODE_CFG fields in the PHY_CTRL register determine the devicersquos operating speed and duplex mode Note that while 10BASE-T and 100BASE-T do not require auto-negotiation 1000BASE-T does require it (defined by clause 40)

3523 1000BASE-T Forced Mode SupportThe integrated transceivers provides support for a 1000BASE-T forced test mode In this mode the PHY can be forced into 1000BASE-T mode and does not require manual setting of masterslave at the two ends of the link This mode is only for test purposes Do not use in normal operation To configure a PHY in this mode set PHY_EEE_CTRLFORCE_1000BT_ENA = 1 with PHY_CTRLSPEED_SEL_LSB_CFG = 1 and PHY_CTRLSPEED_SEL_LSB_CFG = 0

3524 Automatic Crossover and Polarity DetectionFor trouble-free configuration and management of Ethernet links the integrated transceivers include a robust automatic crossover detection feature for all three speeds on the twisted-pair interface (10BASE-T 100BASE-T and 1000BASE T) Known as HP Auto-MDIX the function is fully compliant with clause 40 of the IEEE 8023-2002

Additionally the device detects and corrects polarity errors on all MDI pairsmdasha useful capability that exceeds the requirements of the standard

Both HP Auto-MDIX detection and polarity correction are enabled in the device by default Default settings can be changed using the POL_INV_DIS and PAIR_SWAP_DIS fields in the PHY_BYPASS_CTRL register Status bits for each of these functions are located in the PHY_AUX_CTRL_STAT register

The integrated transceivers can be configured to perform HP Auto-MDIX even when auto-negotiation is disabled (PHY_CTRLAUTONEG_ENA = 0) and the link is forced into 10100 speeds To enable the HP Auto-MDIX feature set PHY_BYPASS_CTRLFORCED_SPEED_AUTO_MDIX_DIS to 0

The HP Auto-MDIX algorithm successfully detects corrects and operates with any of the MDI wiring pair combinations listed in the following table

3525 Manual MDIMDI-X SettingAs an alternative to HP Auto-MDIX detection the PHY can be forced to be MDI or MDI X using PHY_EXT_MODE_CTRLFORCE_MDI_CROSSOVER_ENA Setting this field to 10 forces MDI and setting 11 forces MDI-X Leaving the bits 00 enables the MDIMDI-X setting to be based on FORCED_SPEED_AUTO_MDIX_DIS and PAIR_SWAP_DIS in the register PHY_BYPASS_CTRL

Table 21 bull Supported MDI Pair Combinations

1 2 3 6 4 5 7 8 ModeA B C D Normal MDI

B A D C Normal MDI-X

A B D C Normal MDI with pair swap on C and D pair

B A C D Normal MDI-X with pair swap on C and D pair

3526 Link Speed DownshiftFor operation in cabling environments that are incompatible with 1000BASE-T the device provides an automatic link speed ldquodownshiftrdquo option When enabled the device automatically changes its 1000BASE-T auto-negotiation advertisement to the next slower speed after a set number of failed attempts at 1000BASE-T No reset is required to exit this state if a subsequent link partner with 1000BASE-T support is connected This is useful in setting up in networks using older cable installations that may include only pairs A and B and not pairs C and D

Link speed downshifting is configured and monitored using SPEED_DOWNSHIFT_STAT SPEED_DOWNSHIFT_CFG and SPEED_DOWNSHIFT_ENA in the register PHY_CTRL_EXT3

3527 Energy Efficient EthernetThe integrated transceivers support IEEE 8023az Energy Efficient Ethernet (EEE) This standard provides a method for reducing power consumption on an Ethernet link during times of low use

Figure 11 bull Low Power Idle Operation

Using LPI the usage model for the link is to transmit data as fast as possible and then return to a low power idle state Energy is saved on the link by cycling between active and low power idle states Power is reduced during LPI by turning off unused circuits and using this method energy use scales with bandwidth utilization

The transceivers use LPI to optimize power dissipation in 100BASE-TX and 1000BASE-T operation In addition IEEE 8023az defines a 10BASE-Te mode that reduces transmit signal amplitude from 5 V to approximately 33 V peak-to-peak This mode reduces power consumption in 10 Mbps link speed and can fully interoperate with legacy 10BASE-T compliant PHYs over 100 m Cat5 cable or better

To configure the transceivers in 10BASE-Te mode set PHY_EEE_CTRLEEE_LPI_RX_100BTX_DIS to 1 for each port Additional Energy Efficient Ethernet features are controlled through Clause 45 registers as defined in Clause 45 registers to Support Energy Efficient Ethernet

353 Wake-On-LAN and SecureOnThe device supports Wake-on-LAN an Ethernet networking standard to awaken hosts by using a ldquomagic packetrdquo that is decoded to ascertain the source and then assert an interrupt pin or an LED The device also supports SecureOn to secure Wake-on-LAN against unauthorized access The following illustration shows an overview of the Wake-on-LAN functionality

Active

Refresh

Active

Active Low-Power Idle Active

TS TQ TR

Quiet Quiet Quiet

Figure 12 bull Wake-On-LAN Functionality

Wake-on-LAN detection is available in 10BASE-T 100BASE-TX and 1000BASE-T modes It is enabled by setting the interrupt mask register PHY_INT_MASK WOL_INT_ENA and its status is read in the interrupt status register PHY_INT_STAT WOL_INT_PEND Wake-on-LAN and SecureOn are configured for each port using the PHY_WOL_MDINT_CTRL register The MAC address for each port is saved in its local register space (PHY_WOL_MAC_ADDRx)

354 Ethernet Inline Powered DevicesThe integrated transceivers can detect legacy inline powered devices in Ethernet network applications The inline powered detection capability can be part of a system that allows for IP-phone and other devices such as wireless access points to receive power directly from their Ethernet cable similar to office digital phones receiving power from a Private Branch Exchange (PBX) office switch over the telephone cabling This can eliminate the need of an external power supply for an IP-phone It also enables the inline powered device to remain active during a power outage (assuming the Ethernet switch is connected to an uninterrupted power supply battery back-up power generator or some other uninterruptable power source)

The following illustration shows an example of this type of application

Tx Path

Rx Path

Wake-on-LAN Detect

WOL_MAC_ADDRADDR_REPEAT_CNT

Secure-On enableSecure-On

password lengthSecure-On password

WoL Detected

Figure 13 bull Inline Powered Ethernet Switch

The following procedure describes the process that an Ethernet switch must perform to process inline power requests made by a link partner (LP) that is in turn capable of receiving inline power

1 Enables the inline powered device detection mode on each transceiver using its serial management interface Set PHY_CTRL_EXT4INLINE_POW_DET_ENA to 1

2 Ensures that the Auto-Negotiation Enable bit (register 012) is also set to 1 In the application the device sends a special Fast Link Pulse (FLP) signal to the LP Reading PHY_CTRL_EXT4INLINE_POW_DET_STAT returns 00 during the search for devices that require Power-over-Ethernet (PoE)

3 The transceiver monitors its inputs for the FLP signal looped back by the LP An LP capable of receiving PoE loops back the FLP pulses when the LP is in a powered down state This is reported when PHY_CTRL_EXT4INLINE_POW_DET_STAT reads back 01 If an LP device does not loop back the FLP after a specific time PHY_CTRL_EXT4INLINE_POW_DET_STAT automatically resets to 10

4 If the transceiver reports that the LP needs PoE the Ethernet switch must enable inline power on this port externally of the PHY

5 The PHY automatically disables inline powered device detection if PHY_CTRL_EXT4INLINE_POW_DET_STAT automatically resets to 10 and then automatically changes to its normal auto-negotiation process A link is then auto-negotiated and established when the link status bit is set (PHY_STATLINK_STAT is set to 1)

6 In the event of a link failure (indicated when PHY_STATLINK_STAT reads 0) the inline power must be disabled to the inline powered device external to the PHY The transceiver disables its normal auto-negotiation process and re-enables its inline powered device detection mode

355 IEEE 8023af PoE SupportThe integrated transceivers are also compatible with switch designs intended for use in systems that supply power to Data Terminal Equipment (DTE) by means of the MDI or twisted pair cable as described in clause 33 of the IEEE 8023af

356 ActiPHYtrade Power ManagementIn addition to the IEEE-specified power-down control bit (PHY_CTRLPOWER_DOWN_ENA) the device also includes an ActiPHY power management mode for each PHY The ActiPHY mode enables support

Control

PHY_port1

InlinePower-Over-Ethernet (PoE)

Power Supply

PHY_port0 PHY_portn

Transformer

RJ-45IF

Transformer

RJ-45IF

Transformer

RJ-45IF

LinkPartner

Gigabit SwitchPHY

for power-sensitive applications It uses a signal detect function that monitors the media interface for the presence of a link to determine when to automatically power-down the PHY The PHY ldquowakes uprdquo at a programmable interval and attempts to wake-up the link partner PHY by sending a burst of FLP over copper media

The ActiPHY power management mode in the integrated transceivers is enabled on a per-port basis during normal operation at any time by setting PHY_AUX_CTRL_STATACTIPHY_ENA to 1

Three operating states are possible when ActiPHY mode is enabled

bull Low power statebull LP wake-up statebull Normal operating state (link up state)The PHY switches between the low power state and the LP wake-up state at a programmable rate (the default is two seconds) until signal energy is detected on the media interface pins When signal energy is detected the PHY enters the normal operating state If the PHY is in its normal operating state and the link fails the PHY returns to the low power state after the expiration of the link status time-out timer After reset the PHY enters the low power state

When auto-negotiation is enabled in the PHY the ActiPHY state machine operates as described If auto-negotiation is disabled and the link is forced to use 10BT or 100BTX modes while the PHY is in its low power state the PHY continues to transition between the low power and LP wake-up states until signal energy is detected on the media pins At that time the PHY transitions to the normal operating state and stays in that state even when the link is dropped If auto-negotiation is disabled while the PHY is in the normal operation state the PHY stays in that state when the link is dropped and does not transition back to the low power state

The following illustration shows the relationship between ActiPHY states and timers

Figure 14 bull ActiPHY State Diagram

3561 Low Power StateAll major digital blocks are powered down in the lower power state

In this state the PHY monitors the media interface pins for signal energy The PHY comes out of low power state and transitions to the normal operating state when signal energy is detected on the media This happens when the PHY is connected to one of the following

bull Auto-negotiation capable link partnerbull Another PHY in enhanced ActiPHY LP wake-up stateIn the absence of signal energy on the media pins the PHY transitions from the low power state to the LP wake-up state periodically based on the programmable sleep timer

Low Power State

LP Wake-upState

NormalOperation State

Signal Energy Detected onMedia

Timeout Timer Expires andAuto-negotiation Enabled

Sleep Timer Expires

FLP Burst orClause 37 Restart

Signal Sent

(PHY_CTRL_EXT3ACTIPHY_SLEEP_TIMER) The actual sleep time duration is random from ndash80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation

After sending signal energy on the relevant media the PHY returns to the low power state

3562 Link Partner Wake-up StateIn the link partner wake-up state the PHY attempts to wake up the link partner Up to three complete FLP bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer which is set using register bits 20E11211

3563 Normal Operating StateIn normal operation the PHY establishes a link with a link partner When the media is unplugged or the link partner is powered down the PHY waits for the duration of the programmable link status time-out timer which is set using ACTIPHY_LINK_TIMER_MSB_CFG and ACTIPHY_LINK_TIMER_LSB_CFG in the PHY_AUX_CTRL_STAT register It then enters the low power state

357 Testing FeaturesThe integrated transceivers include several testing features designed to facilitate performing system-level debugging

3571 Ethernet Packet Generator (EPG)The Ethernet Packet Generator (EPG) can be used at each of the 101001000BASE-T speed settings for copper Cat5 media to isolate problems between the MAC and the PHY or between a local PHY and its remote link partner Enabling the EPG feature effectively disables all MAC interface transmit pins and selects the EPG as the source for all data transmitted onto the twisted pair interface

Important The EPG is intended for use with laboratory or in-system testing equipment only Do not use the EPG testing feature when the PHY is connected to a live network

To use the EPG feature set PHY_1000BT_EPG2EPG_ENA to 1

When PHY_1000BT_EPG2EPG_RUN_ENA is set to 1 the PHY begins transmitting Ethernet packets based on the settings in the PHY_1000BT_EPG1 and PHY_1000BT_EPG2 registers These registers set

bull Source and destination addresses for each packetbull Packet sizebull Inter-packet gapbull FCS statebull Transmit durationbull Payload patternIf PHY_1000BT_EPG1TRANSMIT_DURATION_CFG is set to 0 PHY_1000BT_EPG1EPG_RUN_ENA is cleared automatically after 30000000 packets are transmitted

3572 CRC CountersTwo separate CRC counters are available in the PHY a 14-bit good CRC counter available through PHY_CRC_GOOD_CNTCRC_GOOD_PKT_CNT and a separate 8-bit bad CRC counter in PHY_CTRL_EXT4CRC_1000BT_CNT

3573 Far-End LoopbackThe far-end loopback testing feature is enabled by setting PHY_CTRL_EXT1FAR_END_LOOPBACK_ENA to 1 When enabled it forces incoming data from a link partner on the current media interface into the MAC interface of the PHY to be re-transmitted back to the link partner on the media interface as shown in the following illustration The incoming data also appears on the receive data pins of the MAC interface Data present on the transmit data pins of the MAC interface is ignored when using this testing feature

Note The far-end loopback is only operational in 1Gbps mode

Figure 15 bull Far-End Loopback

3574 Near-End LoopbackWhen the near-end loopback testing feature is enabled (by setting PHY_CTRLLOOPBACK_ENA to 1) data on the transmit data pins (TXD) is looped back in the PCS block onto the device receive data pins (RXD) as shown in the following illustration When using this testing feature no data is transmitted over the network

Figure 16 bull Near-End Loopback

3575 Connector LoopbackThe connector loopback testing feature allows the twisted pair interface to be looped back externally When using the connector loopback feature the PHY must be connected to a loopback connector or a loopback cable Pair A must be connected to pair B and pair C to pair D as shown in the following illustration The connector loopback feature functions at all available interface speeds

Figure 17 bull Connector Loopback

When using the connector loopback testing feature the device auto-negotiation speed and duplex configuration is set using device registers 0 4 and 9 For 1000BASE-T connector loopback the following additional writes are required executed in the following steps

1 Enable the 1000BASE-T connector loopback SetPHY_CTRL_EXT2CON_LOOPBACK_1000BT_ENA to 1

2 Disable pair swap correction Set PHY_CTRL_EXT2CON_LOOPBACK_1000BT_ENA to 1

358 VeriPHYtrade Cable DiagnosticsThe integrated transceivers include a comprehensive suite of cable diagnostic functions that are available through the on-board processor These functions enable cable operating conditions and status to be accessed and checked The VeriPHY suite has the ability to identify the cable length and operating conditions and to isolate common faults that can occur on the Cat5 twisted pair cabling

For the functional details of the VeriPHY suite and the operating instructions see the ENT-AN0125 PHY Integrated PHY-Switch VeriPHY - Cable Diagnostics Feature Application Note

36 StatisticsThe following table lists the registers for the statistics module

The device implements a statistics block containing the following counter groups

bull Receive statistics available per physical ingress portbull Transmit statistics available per physical egress portbull FIFO Drop statistics available per physical ingress portEach counter is 32 bits wide which is large enough to ensure a wrap-around time longer than 13 seconds for port statistics on a 25G port and longer than 30 seconds for port statistics on a 1G port

Each switch core port has 44 Rx counters 18 FIFO drop counters and 31 Tx counters The following lists the counters

361 Port StatisticsThe following table defines the per-port available Rx counters and lists the counterrsquos address in the common statistics block

Table 22 bull Counter Registers

Register Description ReplicationSYSSTATCNT Data register for reading port counters

The current view is specified in SYSSTAT_CFGSTAT_VIEW

Per counter for specified port

SYSSTAT_CFGSTAT_VIEW Sets the current counter view None

SYSSTAT_CFGSTAT_CLEAR_SHOT Clears counters per counter group None

QSYSSTAT_CNT_CFGTX_GREEN_CNT_MODEQSYSSTAT_CNT_CFGTX_YELLOW_CNT_MODE

Controls whether to counts bytes or frames for Tx priority counters

QSYSSTAT_CNT_CFGDROP_GREEN_CNT_MODEQSYSSTAT_CNT_CFGDROP_YELLOW_CNT_MODE

Controls whether to counts bytes or frames for drop priority counters

ANAAGENCTRLGREEN_COUNT_MODEANAAGENCTRLYELLOW_COUNT_MODEANAAGENCTRLRED_COUNT_MODE

Controls whether to counts bytes or frames for Rx priority counters

Table 23 bull Receive Counters in the Statistics Block

Type Short NameCounter Address Description

Rx c_rx_oct 0x00 Received octets in good and bad frames

Rx c_rx_uc 0x01 Number of good broadcasts

Rx c_rx_mc 0x02 Number of good multicasts

Rx c_rx_bc 0x03 Number of good unicasts

Rx c_rx_short 0x04 Number of short frames with valid CRC (lt64 bytes)

Rx c_rx_frag 0x05 Number of short frames with invalid CRC (lt64 bytes)

Rx c_rx_jabber 0x06 Number of long frames with invalid CRC (according to MAXLENMAX_LENGTH)

Rx c_rx_crc 0x07 Number of CRC errors alignment errors and RX_ER events

Rx c_rx_symbol_err 0x08 Number of frames with RX_ER events

Rx c_rx_sz_64 0x09 Number of 64-byte frames in good and bad frames

Rx c_rx_sz_65_127 0x0A Number of 65-127-byte frames in good and bad frames

Rx c_rx_sz_128_255 0x0B Number of 128-255-byte frames in good and bad frames

Rx c_rx_sz_256_511 0x0C Number of 256-511-byte frames in good and bad frames

Rx c_rx_sz_512_1023 0x0D Number of 512-1023-byte frames in good and bad frames

Rx c_rx_sz_1024_1526 0x0E Number of 1024-1526-byte frames in good and bad frames

Rx c_rx_sz_jumbo 0x0F Number of 1527-MAXLENMAX_LENGTH-byte frames in good and bad frames Counter is only applicable if MAXLENMAX_LENGTH gt 1526

Rx c_rx_pause 0x10 Number of received pause frames

Rx c_rx_control 0x11 Number of MAC control frames received

Rx c_rx_long 0x12 Number of long frames with valid CRC (according to MAXLENMAX_LENGTH)

Rx c_rx_cat_drop 0x13 Number of frames dropped due to classifier rules

Rx c_rx_red_prio_0 0x14 Number of received frames classified to QoS class 0 and discarded by a policer

Rx c_rx_red_prio_6 0x1A Number of received frames classified to QoS class 6 and discarded by a policer

Rx c_rx_red_prio_7 0x1B Number of received frames classified to QoS class 7 and discarded by a policer

Rx c_rx_yellow_prio_0 0x1C Number of received frames classified to QoS class 0 and marked yellowby a policer

Rx c_rx_yellow_prio_1 0x1D Number of received frames classified to QoS class 1 and marked yellowby a policer

Rx c_rx_yellow_prio_2 0x1E Number of received frames classified to QoS class 2 and marked yellowby a policer

Rx c_rx_yellow_prio_3 0x1F Number of received frames classified to QoS class 3 and marked yellowby a policer

Rx c_rx_yellow_prio_4 0x20 Number of received frames classified to QoS class 4 and marked yellowby a policer

Table 23 bull Receive Counters in the Statistics Block (continued)

The following table defines the per-port available Tx counters and lists the counter address

Rx c_rx_green_prio_0 0x24 Number of received frames classified to QoS class 0 and marked green by a policer

Rx c_rx_green_prio_2 0x26 Number of received frames classified to QoS class 2 and marked greenby a policer

Rx c_rx_green_prio_6 0x2A Number of received frames classified to QoS class 6 and marked green by a policer

Rx c_rx_green_prio_7 0x2B Number of received frames classified to QoS class 7 and marked green by a policer

Table 24 bull Tx Counters in the Statistics Block

Tx c_tx_oct 0x40 Transmitted octets in good and bad frames

Tx c_tx_uc 0x41 Number of good unicasts

Tx c_tx_mc 0x42 Number of good multicasts

Tx c_tx_bc 0x43 Number of good broadcasts

Tx c_tx_col 0x44 Number of transmitted frames experiencing a collision An excessive collided frame gives 16 counts

Tx c_txdrop 0x45 Number of frames dropped due to excessive collisions or late collisions

Tx c_txpause 0x46 Number of transmitted pause frames

Tx c_tx_sz_64 0x47 Number of 64-byte frames in good and bad frames

Tx c_tx_sz_65_127 0x48 Number of 65-127-byte frames in good and bad frames

Tx c_tx_sz_256_511 0x4A Number of 256-511-byte frames in good and bad frames

Tx c_tx_sz_512_1023 0x4B Number of 512-1023-byte frames in good and bad frames

Tx c_tx_sz_1024_1526 0x4C Number of 1024-1526-byte frames in good and bad frames

Tx c_tx_sz_jumbo 0x4D Number of 1527-MAXLENMAX_LENGTH-byte frames in good and bad frames

Tx c_tx_yellow_prio_0 0x4E Number of transmitted frames classified to QoS class 0 with DP level 1

Tx c_tx_yellow_prio_1 0x4F Number of transmitted frames classified to QoS class 1 with DP level 1

Tx c_tx_yellow_prio_2 0x50 Number of transmitted frames classified to QoS class 2 with DP level 1

Tx c_tx_green_prio_0 0x56 Number of transmitted frames classified to QoS class 0 with DP level 0

Tx c_tx_green_prio_4 0x5A Number of transmitted frames classified to QoS class 4 with DP level 0

Tx c_tx_green_prio_5 0x5B Number of transmitted frames classified to QoS class 5 with DP level 0

Tx c_tx_green_prio_6 0x5C Number of transmitted frames classified to QoS class 6 with DP level 0

Tx c_tx_green_prio_7 0x5D Number of transmitted frames classified to QoS class 7 with DP level 0

Tx c_tx_aged 0x5E Number of frames dropped due to frame aging

Table 24 bull Tx Counters in the Statistics Block (continued)

The following table defines the per-port available FIFO drop counters and lists the counter address

362 Accessing and Clearing CountersThe counters are accessed through SYSSTATCNT using the counter address given for each counter in the tables in the preceding sections Only a subset of the counters for all ports are addressable at the same time The current subset is programmed in STAT_CFGSTAT_VIEW and includes port counters (Rx Tx drop) for the port number programmed in STAT_CFGSTAT_VIEW

The following illustration shows the layout of the counter subset that are addressable through SYSSTATCNT To change the view write a new port number to STAT_CFGSTAT_VIEW

Table 25 bull FIFO Drop Counters in the Statistics Block

Drop c_dr_local 0x80 Number of frames discarded due to no destinations

Drop c_dr_tail 0x81 Number of frames discarded due to no more memory in the queue system (tail drop)

Drop c_dr_yellow_prio_0 0x82 Number of FIFO discarded frames classified to QoS class 0 with DP level 1

Drop c_dr_green_prio_0 0x8A Number of FIFO discarded frames classified to QoS class 0 with DP level 0

Drop c_dr_green_prio_1 0x8B Number of FIFO discarded frames classified to QoS class 1 with DP level 0

Drop c_dr_green_prio_2 0x8C Number of FIFO discarded frames classified to QoS class 2 with DP level 0

Drop c_dr_green_prio_3 0x8D Number of FIFO discarded frames classified to QoS class 3 with DP level 0

Drop c_dr_green_prio_4 0x8E Number of FIFO discarded frames classified to QoS class 4 with DP level 0

Drop c_dr_green_prio_5 0x8F Number of FIFO discarded frames classified to QoS class 5 with DP level 0

Drop c_dr_green_prio_6 0x90 Number of FIFO discarded frames classified to QoS class 6 with DP level 0

Figure 18 bull Counter Layout (SYSSTATCNT) Per View

Read Example To read the number of good unicast frames transmitted on port 3 (counter c_tx_uc) set the current view in STAT_CFGSTAT_VIEW to 3 and read SYSSTATCNT[0x41] Note that with the current view one could also read Rx and drop counters on port 3

The counters can be cleared per counter group per view Writing to register STAT_CFGSTAT_CLEAR_SHOT clears all counters associated with the counter groups specified by STAT_CFGSTAT_CLEAR_SHOT for the view specified in STAT_CFGSTAT_VIEW

It is possible to select whether to count frames or bytes for the following specific counters

bull The Rx priority counters (c_rx_red_prio_ c_rx_yellow_prio_ c_rx_green_prio_ where x is 0 through 7)

bull The Tx priority counters (c_tx_yellow_prio_ c_tx_green_prio_ where x is 0 through 7)bull The Drop priority counters (c_dr_yellow_prio_ c_dr_green_prio_ where x is 0 through 7)The Rx priority counters are programmed through ANAAGENCTRL and the Tx and drop priority counters are programmed through QSYSSTAT_CNT_CFG When counting bytes the frame length excluding inter frame gap and preamble is counted

For testing purposes all counters are both readable and writable All counters wrap around to 0 when reaching the maximum

For more information about how the counters map to relevant MIBs see Port Counters page 222

37 Basic ClassifierThe switch core includes a common basic classifier which determines a number of properties affecting the forwarding of each frame through the switch These properties are

bull Frame acceptance filtering Drop illegal frame typesbull QoS classification Assign one of eight QoS classes to the framebull Drop precedence (DP) classification Assign one of two drop precedence levels to the framebull DSCP classification Assign one of 64 DSCP values to the framebull VLAN classification Extract tag information from the frame or use the port VLANbull Link aggregation code generation Generate the link aggregation codebull CPU forwarding determination Determine CPU Forwarding and CPU extraction queue numberThe outcome of the classifier is the basic classification result which can be overruled by more intelligent frame processing in the VCAP IS1 For more information see VCAP page 60

371 General Data Extraction SetupThis section provides information about the overall settings for data extraction that provides the data input to the classifier VCAP analyzer and rewriter

Rx Port=STAT_CFGSTAT_VIEW

Bit 31 Bit 00x000

c_rx_oct

c_rx_green_prio_7

TX Port=STAT_CFGSTAT_VIEW

c_tx_oct

c_tx_aged

Drop Port=STAT_CFGSTAT_VIEW

c_dr_local

c_dr_green_prio_7

Unused

Counter Groups

The following table lists the registers associated with general data extraction

It is programmable which VLAN tags are recognized The use of Layer-3 and Layer-4 information for classification and forwarding can also be controlled

The device recognizes three different VLAN tags

bull Customer tags (C-TAGs) which use TPID 0x8100bull Service tags (S-TAGs) which use TPID 0x88A8 (IEEE 8021ad)bull Service tags (S-TAGs) which use a custom TPID programmed in SYSVLAN_ETYPE_CFGThe device can parse and use information from up to two VLAN tags of any of the kinds described above

By default the outer VLAN tag is extracted and used for both the basic classification and the VCAP IS1 key generation However for both the basic classification and the VCAP IS1 there is an option to use the inner VLAN tag instead for frames with at least two VLAN tags For basic classification this is controlled in VLAN_CFGVLAN_INNER_TAG_ENA and affects both QoS DP and VLAN classification as well as the frame acceptance filter For IS1 this is controlled per lookup in S1_VLAN_INNER_TAG_ENA Note that several keys in IS1 always contain both the inner VLAN tag and the outer VLAN tag

Various blocks in the device uses Layer-3 and Layer-4 information for classification and forwarding Layer-3 and Layer-4 information can be extracted from a frame with up to two VLAN tags Frames with more than two VLAN tags are considered non-IP frames

The actual use of Layer-3 and Layer-4 information for classification forwarding and rewriting is enabled in SYSPORT_MODEL3_PARSE_CFG The following blocks are affected by this functionality

bull Basic classification QoS DP and DSCP classification link aggregation code generation CPU forwarding

bull VCAP TCAM keys (IS1 IS2) using Layer 3 and Layer4 information bull Analyzer Flooding and forwarding of IP multicast framesbull Rewriter Rewriting of IP information

372 Frame Acceptance FilteringThe following table lists the registers associated with frame acceptance filtering

Based on the configurations in the DROP_CFG and PORT_MISC registers the classifier instructs the queue system to drop or forward certain frames types such as

bull Frames with a multicast source MAC address

Table 26 bull General Data Extraction Registers

Register Description ReplicationSYSPORT_MODEL3_PARSE_CFG Enables the use of Layer 3 and 4 protocol

information for classification and frame processing

Per port

SYSVLAN_ETYPE_CFG Ethernet Type for S-tags in addition to default value 0x88A8

ANAPORTVLAN_CFGVLAN_INNER_TAG_ENA Enables using inner VLAN tag for basic classification if available in incoming frame

Per port

ANAPORTS1_VLAN_INNER_TAG_ENA Enables using inner VLAN tag for IS1 key generation if available in incoming frame

Per port per IS1 lookup

Table 27 bull Frame Acceptance Filtering Registers

Register Description ReplicationDEVPORT_MISC Configures forwarding of special frames Per port

ANAPORTDROP_CFG Configures discarding of illegal frame types Per port

bull Frames with a null source or null destination MAC address (address = 0x000000000000)bull Frames with errors signaled by the MAC (for example an FCS error)bull MAC control framesbull Pause frames after flow control processing in the MACbull Untagged frames (excluding frames with reserved destination MAC addresses from the BPDU

GARP and Link traceCCM address ranges)bull Priority S-tagged framesbull Priority C-tagged framesbull VLAN S-tagged framesbull VLAN C-tagged framesBy default MAC control frames pause frames and frames with errors are dropped by the classifier

The VLAN acceptance filter decides whether a framersquos VLAN tagging is allowed on the port By default the outer VLAN tag is used as input to the filter however there is an option to use the inner VLAN tag instead for double tagged frames (VLAN_CFGVLAN_INNER_TAG_ENA)

The following illustration shows the flowchart for the VLAN acceptance filter

Figure 19 bull VLAN Acceptance Filter

If the frame is accepted by the VLAN acceptance filter it can still be discarded in other places of the switch such as the following

bull Policers due to traffic exceeding a peak information ratebull IS2 Security TCAM due to permitdeny rulesbull Analyzer due to forwarding decisions such as VLAN ingress filteringbull Queue system due to lack of resources frame aging or excessive collisions

S-Tagged Frame(VID gt 0)

INGRESS

C-Tagged Frame(VID gt 0)

Priority S-tagged Frame (VID=0)

Priority C-tagged Frame (VID=0)

DROP_UNTAGGED_ENA[port] and not reserved address

(BPDU GARP CCM)

Frame is Accepted

DROP_S_TAGGED_ENA[port]

Discard

DROP_C_TAGGED_ENA[port]

Discard

DROP_PRIO_S_TAGGED_ENA[port]

Discard

DROP_PRIO_C_TAGGED_ENA[port]

Discard

Y Discard

373 QoS DP and DSCP ClassificationThis section provides information about the functions in the QoS DP and DSCP classification The three tasks are described as one because the tasks have a significant amount of functionality in common

The following table lists the registers associated with QoS DP and DSCP classification

The basic classification provides the user with control of the QoS DP and DSCP classification algorithm The result of the basic classification are the following frame properties which follow the frame through the switch

bull The framersquos QoS class This class is encoded in a 3-bit field where 7 is the highest priority QoS class and 0 is the lowest priority QoS class The QoS class is used by the queue system when enqueuing frames and when evaluating resource consumptions for policing statistics and rewriter actions

bull The framersquos DP level This level is encoded in a 1-bit field where frames with DP = 1 have the highest probability of being dropped and frames with DP = 0 have the lowest probability The DP level is used by the dual leaky bucket policers for measuring committed and peak information rates for restricting memory consumptions in the queue system for collecting statistics and for rewriting priority information in the rewriter The DP level is incremented by the policers if a frame is exceeding a programmed committed information rate

bull The framersquos DSCP This value is encoded in a 6-bit fields The DSCP value is forwarded with the frame to the rewriter where it is translated and rewritten into the frame The DSCP value is only applicable to IPv4 and IPv6 frames

The classifier looks for the following fields in the incoming frame to determine the QoS DP and DSCP classification

bull Port default QoS class and DP level The default DSCP value is the framersquos DSCP value For non-IP frames the DSCP is 0 and it is not used elsewhere in the switch

bull Priority Code Point (PCP) when the frame is VLAN tagged or priority tagged There is an option to use the inner tag for double tagged frames (VLAN_CFGVLAN_INNER_TAG_ENA) Both S-tagged and C-tagged frames are considered

bull Drop Eligible Indicator (DEI) when the frame is VLAN tagged or priority tagged There is an option to use the inner tag for double tagged frames (VLAN_CFGVLAN_INNER_TAG_ENA) Both S-tagged and C-tagged frames are considered

bull DSCP (all 6 bits both for IPv4 and IPv6 packets) The classifier can look for the DSCP value behind up to two VLAN tags

The following illustration shows the flow chart of basic QoS and DP classification

Table 28 bull QoS DP and DSCP Classification Registers

Register Description ReplicationANAPORTQOS_CFG Configuration of the overall classification

flow for QoS DP and DSCPPer port

ANAPORTQOS_PCP_DEI_MAP_CFG Mapping from (DEI PCP) to (DP QoS) Per port per DEI per PCP

ANADSCP_CFG DSCP configuration per DSCP value Per DSCP

ANADSCP_REWR_CFG DSCP rewrite values per DP level and QoS class

Per DP and per QoS

Figure 20 bull QoS and DP Basic Classification Flow

The following illustration shows the flow chart for basic DSCP classification

QOS = QOS_DEFAULT_VAL[port]DP = DP_DEFAULT_VAL[port]

DSCP = 0

rdquoFrame is IPv4 or IPv6

QOS_DSCP_ENA[port]

DSCP_TRANSLATE_ENA[port]

DSCP = FrameDSCP

DSCP = DSCP_TRANSLATE_VAL[DSCP]

DSCP_TRUST_ENA[DSCP]

QOS = QOS_DSCP_VAL[DSCP]DP = DP_DSCP_VAL[DSCP]

Y rdquoFrame has inner tagrdquo and QOS_PCP_ENA[port] and

VLAN_INNER_TAG_ENA[port]=1

QOS = QOS_PCP_DEI_VAL[port][FrameInnerDEI][FrameInnerPCP]DP = DP_PCP_DEI_VAL[port][FrameInnerDEI][FrameInnerPCP]

Basic classified QoSBasic classified DP

rdquoFrame has outer tagrdquo and QOS_PCP_ENA[port]

QOS = QOS_PCP_DEI_VAL[port][FrameOuterDEI][FrameOuterPCP]DP = DP_PCP_DEI_VAL[port][FrameOuterDEI][FrameOuterPCP]

Figure 21 bull Basic DSCP Classification Flow Chart

The translation part of the DSCP classification is common for both QoS DP and DSCP classification

The basic classified QoS DP and DSCP can be overwritten by more intelligent decisions made in the VCAP IS1

374 VLAN ClassificationThe following table lists the registers associated with VLAN classification

Table 29 bull VLAN Configuration Registers

DSCP = 0

QOS_DSCP_ENA[port]

DSCP = FrameDSCP

The VLAN classification determines a tag header for all frames The tag header includes the following information

bull Priority Code Point (PCP)bull Drop Eligible Indicator (DEI)bull VLAN Identifier (VID)bull Tag Protocol Identifier (TPID) type (TAG_TYPE) This field informs whether tag used for

classification was a C-tag or an S-tagThe tag header determined by the classifier is carried with the frame through the switch and is used in various places such as the analyzer for forwarding and the rewriter for egress tagging operations

The device recognizes three kinds of tags based on the TPID which is the EtherType in front of the tag

bull Customer tags (C-TAGs) which use TPID 0x8100bull Service tags (S-TAGs) which use TPID 0x88A8 (IEEE 8021ad)bull Service tags (S-TAGs) which use a custom TPID programmed in SYSVLAN_ETYPE_CFGFor customer tags and service tags both VLAN tags (tags with nonzero VID) and priority tags (tags with VID = 0) are processed

The tag header is either retrieved from a tag in the incoming frame or from a default port-based tag header The port-based tag header is configured in ANAPORTVLAN_CFG

For double tagged frames there is an option to use the inner tag instead of the outer tag (VLAN_CFGVLAN_INNNER_TAG_ENA)

In addition to the tag header the port decides the number of VLAN tags to pop at egress (VLAN_POP_CNT) If the configured number of tags to pop is greater than the actual number of tags in the frame the number is reduced to the number of actual tags in the frame

The following illustration shows the flow chart for basic VLAN classification

ANAPORTVLAN_CFG Configures the portrsquos processing of VLAN information in VLAN-tagged and priority-tagged frames Configures the port-based VLAN

Per port

Table 29 bull VLAN Configuration Registers (continued)

Figure 22 bull Basic VLAN Classification Flow

The basic classifier can overwrite the basic classified PCP value with the framersquos basic classified QoS class coming from the basic QoS classification This option is enabled in ANAPORTPTP_DLY1_CFGUSE_QOS_AS_PCP_ENA The basic classified tag header can be overwritten by more intelligent decisions made in the VCAP IS1

375 Link Aggregation Code GenerationThis section provides information about the functions in link aggregation code generation

VLAN_AWARE_ENA[port] andrdquoFrame has outer tagrdquo

VLAN_INNER_TAG_ENA[port] and rdquoFrame has inner tagrdquo

TAG_TYPE = VLAN_CFGVLAN_TAG_TYPEPCP = VLAN_CFGVLAN_PCPDEI = VLAN_CFGVLAN_DEIVID = VLAN_CFGVLAN_VIDVLAN_POP_CNT = VLAN_CFGVLAN_POP_CNT

TAG_TYPE = (FrameInnerTPID ltgt 0x8100)PCP = FrameInnerPCPDEI = FrameInnerDEIVID = FrameInnerVID

VID == 0

VID = VLAN_CFGVLAN_VID

Basic classified tag header (TAG_TYPE PCP DEI VID)

TAG_TYPE = (FrameOuterTPID ltgt 0x8100)PCP = FrameOuterPCPDEI = FrameOuterDEIVID = FrameOuterVID

The following table lists the registers associated with aggregation code generation

The classifier generates a link aggregation code which is used in the analyzer when selecting to which port in a link aggregation group a frame is forwarded

The following contributions to the link aggregation code is configured in the AGGR_CFG register

bull Destination MAC addressmdashuse the lower 12 bits of the DMACbull Source MAC addressmdashuse the lower 12 bits of the SMACbull IPv6 flow labelmdashuse the 20 bits of the flow labelbull IPv4 source and destination IP addressesmdashuse the lower 8 bits of the SIP and DIPbull TCPUDP source and destination port for IPv4 and IPv6 framesmdashuse the lower 8 bits of the SPORT

and DPORTbull Random aggregation codemdashuse a pseudo-random number instead of the frame informationEach of the enabled contributions are XORrsquoed together yielding a 4-bit aggregation code ranging from 0 to 15 For more information about how the aggregation code is used see Link Aggregation page 246

376 CPU Forwarding DeterminationThe following table lists the registers associated with CPU forwarding in the basic classifier

The classifier has support for determining whether certain frames must be forwarded to the CPU extraction queues Other parts of the device can also determine CPU forwarding for example the analyzer or the VCAP IS2 All events leading to CPU forwarding are ORrsquoed together and the final CPU extraction queue mask which is available to the user contains the sum of all events leading to CPU extraction For more information see CPU Extraction and Injection page 263

Upon CPU forwarding by the classifier the frame type determines whether the frame is redirected or copied to the CPU Any frame type or event causing a redirection to the CPU cause all front ports to be removed from the forwarding decision - only the CPU receives the frame When copying a frame to the CPU the normal forwarding of the frame is unaffected

Table 30 bull Aggregation Code Generation Registers

Register Description ReplicationANAAGGR_CFG Configures use of Layer-2 through Layer-4 flow

information for link aggregation code generationCommon

Table 31 bull CPU Forwarding Determination

Register Description ReplicationCPU_FWD_CFG Enables CPU forwarding for various frame types Per port

CPU_FWD_BPDU_CFG Enables CPU forwarding per BPDU address Per port

CPU_FWD_GARP_CFG Enables CPU forwarding per GARP address Per port

CPU_FWD_CCM_CFG Enables CPU forwarding per CCMLink trace address

Per port

CPUQ_CFG and CPUQ_CFG2

CPU extraction queues for various frame types None

CPUQ_8021_CFG CPU extraction queues for BPDU GARP and CCM addresses

VRAP_CFG VLAN configuration of VRAP filter None

VRAP_HDR_DATA Data match against VRAP header None

VRAP_HDR_MASK Mask used to donrsquot care bits in the VRAP header None

The following table lists the standard frame types with respect to CPU forwarding that are recognized by the classifier

In addition the classifier can recognize Versatile Register Access Protocol (VRAP) frames and redirect such frames to the CPU This is a proprietary frame format which is used for reading and writing switch configuration registers through ethernet frames For more information see VRAP Engine page 148

To determine if a frame is a VRAP frame the VRAP filter in the classifier performs three checks

bull VLAN check The filter can be either VLAN unaware or VLAN aware (ANAVRAP_CFGVRAP_VLAN_AWARE_ENA) If VLAN unaware VRAP frames must be untagged If VLAN aware VRAP frames must be VLAN tagged and the framersquos VID must match a configured value (ANAVRAP_CFGVRAP_VID) Double VLAN tagged frames always fail this check

bull EtherType and EPID check The EtherType must be 0x8880 and the EPID must be 0x0004 (bytes 0 and 1 after the EtherType)

bull VRAP header check The VRAP header (bytes 0 1 2 and 3 after the EPID) must match a 32-bit configured value (ANAVRAP_HDR_DATA) where any bits can be donrsquot cared by a mask (ANAVRAP_HDR_MASK)

If all three checks are fulfilled frames are redirected to CPU extraction queue ANACPUQ_CFG2CPUQ_VRAP

The VRAP filter is enabled in ANAPORTCPU_FWD_CFG

Table 32 bull Frame Type Definitions for CPU Forwarding

Frame Condition CopyRedirectBPDU framesReserved Addresses (IEEE 8021D 7126)

DMAC = 0x0180C2000000 to 0x0180C20000F (BPDUs and various Slow protocols supporting spanning tree link aggregation port authentication)

RedirectCopyDiscard

Reserved ALLBRIDGE address

DMAC = 0x0180C2000010 RedirectCopyDiscard

GARP Application Addresses (IEEE 8021D 125)

DMAC = 0x0180C2000020 to 0x0180C200002F RedirectCopyDiscard

CCMLink Trace Addresses (IEEE P8021ag)

IGMP DMAC = 0x01005E000000 to 0x01005E7FFFFFEtherType = IPv4IP Protocol = IGMP

Redirect

MLD DMAC = 0x333300000000 to 0x3333FFFFFFFFFEtherType = IPv6IPv6 Next Header = 0Hop-by-hop options header with the first option being a Router Alert option with the MLD message (Option Type = 5 Opt Data Len = 2 Option Data = 0)

Redirect

IPv4 Multicast Ctrl DMAC = 0x01005E000000 to 0x01005E7FFFFFEtherType = IPv4IP protocol is not IGMPIPv4 DIP inside 22400x

Source port All frames received on enabled ingress port Copy

All other frames

38 VCAPThe VCAP is a content-aware packet processor for wire-speed packet inspection for rich implementation of for example advanced VLAN and QoS classifications and manipulations IP source guarding and security features for wireline and wireless applications

The following describes three VCAPs implemented in the device IS1 IS2 and ES0 IS1 and IS2 are generic ingress VCAPs working on the incoming frames while ES0 is an egress VCAP working on all outgoing frames

When a VCAP is enabled each frame is examined to determine the frame type (for example IPv4 TCP frame) so that the frame information is extracted according to the frame type Together with port-specific configuration and classification results from the basic classification the extracted frame information makes up an entry key which is passed to a TCAM and matched against entries in the TCAM

An entry in the TCAM consists of a pattern and a mask where the mask allows pattern-matching with the use of ldquodonrsquot caresrdquo The first matching entry is then used to select an action The following illustration provides a functional overview of a general TCAM

Figure 23 bull VCAP Functional Overview

Each frame results in up to six ingress VCAP lookups and one egress lookup per destination port The lookups use different keys and the results determine the framersquos ingress classification security handling and egress VLAN manipulation The six ingress lookups and the associated VCAPs are

bull Advanced ingress classification first lookup bull VCAP IS1bull Key IS1bull Entry IS1 Control Entry

bull Advanced ingress classification second lookup bull VCAP IS1bull Key IS1bull Entry IS1 Control Entry

bull Advanced ingress classification third lookupbull VCAP IS1bull Key IS1bull Entry IS1 Control Entry

bull IP source guarding checkbull VCAP IS2bull Key SMAC_SIP4 (IPv4 frames) or SMAC_SIP6 (IPv6 frames)bull Entry SMAC_SIP4 Control Entry or SMAC_SIP6 Control Entry

bull Security enforcement first lookupbull VCAP IS2

TCAM RAM

Default Actions

ActionEntry

Entry DataEntry Mask

bull Key MAC_ETYPE MAC_LLC MAC_SNAP ARP IP4_OTHER IP4_TCP_UDP IP6_STD IP6_OTHER IP6_TCP_UDP OAM CUSTOM depending on frame type

bull Entry Access Control Entrybull Security enforcement second lookup

bull VCAP IS2bull Key MAC_ETYPE MAC_LLC MAC_SNAP ARP IP4_OTHER IP4_TCP_UDP IP6_STD

IP6_OTHER IP6_TCP_UDP OAM CUSTOM depending on frame typebull Entry Access Control Entry

The egress lookup per destination port and associated VCAP is

bull Egress tagging and frame manipulationsbull VCAP ES0bull Key ES0bull Entry Egress Control Entry

The IP source guarding check is only carried out for IP frames

CPU injected frames are subject to all the above VCAP lookups in IS1 IS2 and ES0

With respect to IS1 and IS2 each frame is classified to one of seven overall VCAP frame types The frame type determines the information to extract from the frame and also which VCAP entries to match against The following table lists which frame types are used and which VCAP entries the frame types are matched against in IS1 and IS2 Note The lookup in ES0 is independent of the frame type and all frames match against all entries in the TCAM

Table 33 bull IS1 and IS2 VCAP Frame Types

Frame Type Condition IS1 Entries IS2 EntriesIPv6 Frame The TypeLen field is equal to 0x86DD

The IP version is 6Special IPv6 framesbullIPv6 TCP frame Next header is TCP (0x6)bullIPv6 UDP frame Next header is UDP (0x11)

bullIPv6 Other frame Next header is neither TCP nor UDP

Frame type flags ETYPE_LEN = 1IP_SNAP = 1IP4 = 0TCP_UDPTCP

IP6_TCP_UDPIP6_OTHERIP6_STD

IPv4 Frame The TypeLen field is equal to 0x800The IP version is 4Special IPv4 framesbullIPv4 TCP frame IP protocol is TCP (0x6)bullIPv4 UDP frame IP protocol is UDP (0x11)bullIPv4 Other frame IP protocol is neither TCP nor UDP

IP4_TCP_UDPIP4_OTHER

(R)ARP Frame The TypeLen field is equal to 0x0806 (ARP) or 0x8035 (RARP)

Frame type flags ETYPE_LEN = 1IP_SNAP = 0

OAM Frame The TypeLen field is equal to 0x8902 0x8809 or 0x88EEIn particular the following protocol data units use this EtherTypebullIEEE 8021ag (CFM)bullIEEE 8023 (EFM)bullITU-T Y1731 (ETH-OAM)bullMEF-16 (E-LMI)

In addition Precision Time Protocol (PTP) frames are handled by IS2 The following encapsulations of PTP frames are supported

bull PTP over EthernetETYPE frame with TypeLen = 0x88F7Matched against MAC_ETYPE entries

bull PTP over UDP over IPv4IPv4 UDP frame with UDP destination port numbers 319 or 320Matched against IP4_TCP_UDP entries

PTP frames may be untagged single tagged or double tagged

For PTP over Ethernet the following PTP fields are always extracted

bull TransportSpecific (byte 0)bull MessageType (byte 0)bull VersionPTP (byte 1)bull DomainNumber (byte 4)bull FlagField flags 1 2 and 7 (byte 6)Note Byte 0 is the byte immediately following the EtherType then byte 1 byte 2 and so on

For PTP over UDP the following PTP fields are always extracted

bull MessageType (byte 0)bull VersionPTP (byte 1)bull DomainNumber (byte 4)bull FlagField flags 1 2 and 7 (byte 6)Note Byte 0 is the byte immediately following the UDP header then byte 1 byte 2 and so on

381 Port ConfigurationThis section provides information about special port configurations that control the key generation for the VCAPs

SNAP Frame The TypeLen field is less than 0x600The Destination Service Access Point field DSAP is equal to 0xAAThe Source Service Access Point field SSAP is equal to 0xAAThe Control field is equal to 0x3

MAC_SNAP

LLC Frame The TypeLen field is less than 0x600The LLC header does not indicate a SNAP frame

MAC_LLC

ETYPE Frame The TypeLen field is greater than or equal to 0x600The Type field does not indicate any of the previously mentioned frame types that is ARP RARP IPv4 or IPv6

MAC_ETYPE

Table 33 bull IS1 and IS2 VCAP Frame Types (continued)

Frame Type Condition IS1 Entries IS2 Entries

The following table lists the registers associated with port configuration for VCAP

Each port module affects the key generation for VCAPs IS1 and IS2 through the VCAP_CFG VCAP_S1_KEY_CFG and VCAP_S2_CFG registers and the rewriter affects VCAP ES0 through the REWPORTPORT_CFGES0_ENA register

3811 VCAP IS1 Port ConfigurationThe following port configurations are available for IS1

bull Enable lookups in IS1 (VCAP_CFGS1_ENA) If disabled frames received by the port module are not matched against rules in VCAP IS1

bull Use destination information rather than source information (VCAP_CFGS1_DMAC_DIP_ENA) By default the two advanced classification lookups in IS1 use the source MAC address and source IP address from the incoming frame when generating the key Through S1_DMAC_DIP_ENA the corresponding destination information destination MAC address and destination IP address can be used instead This can be controlled per lookup so that for example the first lookup applies source information and the second applies destination information

bull Use inner VLAN tag rather than outer VLAN tag (VCAP_CFGS1_VLAN_INNER_TAG_ENA) By default the two advanced classification lookups in IS1 use the outer VLAN tag from the incoming frame when generating the key Through S1_VLAN_INNER_TAG_ENA the inner tag for double tagged frames can be used This can be controlled per lookup so that for example the first lookup applies the outer tag and the second lookup applies the inner tag For single tagged frames the outer VLAN tag is always used

bull Select which IS1 key to use for IPv6 frames (VCAP_S1_CFGS1_KEY_IP6_CFG) This can be controlled per lookup in IS1 IPv6 frames can use any of the six supported keys in IS1 For more information about the IS1 keys see VCAP IS1 page 65

bull Select which IS1 key to use for IPv4 frames (VCAP_S1_CFGS1_KEY_IP4_CFG) This can be controlled per lookup in IS1 IPv4 frames can use S1_NORMAL S1_7TUPLE S1_5TUPLE_IP4 or S1_DBL_VID keys

bull Select which IS1 key to use for non-IP frames (VCAP_S1_CFGS1_KEY_OTHER_CFG) This can be controlled per lookup in IS1 Non-IP frames can use S1_NORMAL S1_7TUPLE or S1_DBL_VID keys

bull Enable lookups in IS2 (VCAP_S2_CFGS2_ENA) If disabled frames received by the port module are not matched against rules in VCAP IS2

bull Default PAG value (VCAP_CFGPAG_VAL) This PAG value is the initial value Actions out of IS1 can change the PAG value before it is used in the key for IS2

Each port module can control a hierarchy of which entry types in IS2 to use for different frame types This is controllable per lookup For instance it is controllable whether IPv6 TCP frames are matched against IP6_TCP_UDP entries IP6_STD entries IP4_TCPUDP entries or MAC_ETYPE entries Note that matching against an entry type controls how the key is generated

Table 34 bull Port Module Configuration of VCAP

Register Description ReplicationANAPORTVCAP_CFG Configuration of the key generation for

the VCAPsPer port

ANAPORTVCAP_S1_KEY_CFG Configuration of the key generation for the VCAP IS1 per lookup

Per port

ANAPORTVCAP_S2_CFG Configuration of the key generation for the VCAP IS2

Per port

REWPORTPORT_CFG Enables VCAP ES0 Per port

With reference to the VCAP_S2_CFG register the following table lists the hierarchy for different frame types

Table 35 bull Hierarchy of IS2 Entry Types

Frame Type DescriptionIPv6 TCP and UDP frames

Configuration S2_IP6_CFGIf S2_IP6_CFG is set to 0 IPv6 TCP and UDP frames are matched against IP6_TCP_UDP entries If S2_IP6_CFG is set to 1 IPv6 TCP and UDP frames are matched against IP6_STD entries If S2_IP6_CFG is set to 2 IPv6 TCP and UDP frames are matched against IP4_TCP_UDP entries If S2_IP6_CFG is set to 3 IPv6 TCP and UDP frames are matched against MAC_ETYPE entries

Note S2_IP6_CFG also controls the keys generation for IPv6 Other frames

IPv6 Other frames (non-TCP and non-UDP)

Configuration S2_IP6_CFGIf S2_IP6_CFG is set to 0 IPv6 Other frames are matched against IP6_OTHER entries If S2_IP6_CFG is set to 1 IPv6 Other frames are matched against IP6_STD entries If S2_IP6_CFG is set to 2 IPv6 Other frames are matched against IP4_OTHER entries If S2_IP6_CFG is set to 3 IPv6 Other frames are matched against MAC_ETYPE entries

Note S2_IP6_CFG also controls the keys generation for IPv6 TCP and UDP frames

IPv4 TCP and UDP frames

Configuration S2_IP_TCPUDP_DISIf S2_IP_TCPUDP_DIS is cleared IPv4 TCP and UDP frames are matched against IP4_TCPUDP entries If S2_IP_TCPUDP_DIS is set IPv4 TCP and UDP frames are matched against MAC_ETYPE entries

Configuration S2_IP_OTHER_DISIf S2_IP_OTHER_DIS is cleared IPv4 Other frames are matched against IP4_OTHER entries If S2_IP_OTHER_DIS is set IPv4 Other frames are matched against MAC_ETYPE entries

ARP frames Configuration S2_ARP_DISIf S2_ARP_DIS is cleared ARP frames are matched against ARP entries If S2_ARP_DIS is set ARP frames are matched against MAC_ETYPE entries

OAM frames Configuration S2_OAM_DISIf S2_OAM_DIS is cleared OAM frames are matched against OAM entries If S2_OAM_DIS is set OAM frames are matched against MAC_ETYPE entries

SNAP frames Configuration S2_SNAP_DISIf S2_SNAP_DIS is cleared SNAP frames are matched against SNAP entries If S2_SNAP_DIS is set SNAP frames are matched against LCC entries

3813 VCAP ES0 Port ConfigurationThe rewriter configures VCAP ES0 through REWPORTPORT_CFGES0_ENA If ES0 is disabled frames transmitted on the port are not matched against rules in ES0

382 VCAP IS1This section provides information about the IS1 keys and associated actions

IS1 supports six different keys The main characteristics of these keys are listed in the following table

3821 IS1 Entry Key EncodingAll frame types are subject to the three IS1 lookups The VCAP IS1 port configuration (VCAP_S1_CFG) determines the key generated for each lookup Keys that are applicable to multiple frame types (for instance S1_NORMAL) contain frame type flags inside the key that indicate the originating frame type In addition certain key fields are overloaded with different frame fields depending on the frame type flag settings

The following illustration shows the entry fields are available for quad half and full keys in IS1

Table 36 bull Overview of IS1 Keys

IS1 Key Size Frame Types Key OverviewS1_NORMAL Half Applicable to all

frame typesSource MAC addresssource IP address (32 bits)outer VLAN DSCP IP protocol source and destination TCPUDP ports

S1_5TUPLE_IP4 Half Applicable to IPv4 and IPv6 frames

Inner and outer VLAN source and destination IP addresses (32 bits) DSCP IP protocol source and destination TCPUDP ports

S1_NORMAL_IP6 Full Applicable to IPv6 frames only

Similar to S1_NORMAL but with full IPv6 source IP address Source MAC addresssource IPv6 address (128 bits)inner and outer VLAN DSCP IP protocol source and destination TCPUDP ports

S1_7TUPLE Full Applicable to all frame types

Source and destination MAC addressesinner and outer VLAN source and destination IP addresses (64 bits)DSCP IP protocol source and destination TCPUDP ports

S1_5TUPLE_IP6 Full Applicable to IPv6 frames only

Similar to S1_5TUPLE_IP4 but with full IPv6 addresses Inner and outer VLAN source and destination IP addresses (128 bits) DSCP IP protocol source and destination TCPUDP ports

S1_DBL_VID Quad Applicable to all frame types

Subset of S1_7TUPLE without addressesInner and outer VLAN DSCP IP protocolDestination TCPUDP port

Figure 24 bull IS1 Entry Type Overview

VCAP IS1 can hold the following number of IS1 entries

bull S1_NORMAL Up to 128 entriesbull S1_5TUPLE_IP4 Up to 128 entriesbull S1_NORMAL_IP6 Up to 64 entriesbull S1_7TUPLE Up to 64 entriesbull S1_5TUPLE_IP6 Up to 64 entriesbull S1_DBL_VID Up to 256 entries

(not T

IPv4 D

IPv6 S

DP) IP

s (full k

DP) IP

The following table provides information about how the quad key S1_DBL_VID is generated

Table 37 bull Specific Fields for IS1 Quad Key S1_DBL_VID

Field Name Bit Width DescriptionLookup InformationLOOKUP 0 2 0 First lookup

1 Second lookup2 Third lookup

Interface and Miscellaneous InformationIGR_PORT_MASK 2 12 Ingress port mask VCAP generated with one bit set in the

mask corresponding to the ingress port

RESERVED 14 9 Reserved Must be set to donrsquot care

OAM_Y1731 23 1 Set if frame is a Y1731 OAM frame with EtherType = 0x8902

L2_MC 24 1 Set if framersquos destination MAC address is a multicast address (bit 40 = 1)

L2_BC 15 1 Set if framersquos destination MAC address is the broadcast address (FF-FF-FF-FF-FF-FF)

IP_MC 26 1 Set if frame is IPv4 frame and framersquos destination MAC address is an IPv4 multicast address (0x01005E0 25)Set if frame is IPv6 frame and framersquos destination MAC address is an IPv6 multicast address (0x333316)

Tagging InformationVLAN_TAGGED 27 1 Set if frame has one or more Q-tags Independent of port

VLAN awareness

VLAN_DBL_TAGGED

28 1 Set if frame has two or more Q-tags Independent of port VLAN awareness

TPID 29 1 0 Customer TPID1 Service TPID (88A8 or programmable)S1_NORMAL TPID is derived from tag pointed to by VCAP_CFGS1_VLAN_INNER_TAG_ENA

VID 30 12 Framersquos VID if frame is tagged otherwise port default S1_NORMAL VID is taken from tag pointed to by VCAP_CFGS1_VLAN_INNER_TAG_ENA

DEI 42 1 Framersquos DEI if frame is tagged otherwise port default S1_NORMAL DEI is taken from tag pointed to by VCAP_CFGS1_VLAN_INNER_TAG_ENA

PCP 43 3 Framersquos PCP if frame is tagged otherwise port default S1_NORMAL PCP is taken from tag pointed to by VCAP_CFGS1_VLAN_INNER_TAG_ENA

INNER_TPID 46 1 TPID for inner tag0 Customer TPID1 Service TPID (88A8 or programmable)

INNER_VID 47 12 Framersquos inner VID if frame is double tagged

INNER_DEI 59 1 Framersquos inner DEI if frame is double tagged

INNER_PCP 60 3 Framersquos inner PCP if frame is double tagged

Layer 2 Information

The following three tables provide information about how the half keys S1_NORMAL and S1_5TUPLE_IP4 are generated The first table lists the common fields between the half keys

ETYPE_LEN 63 1 Frame type flag Set if frame has EtherType gt= 0x600 (Frame is type encoded) Otherwise cleared (Frame is length encoded)

ETYPE 64 16 Overloaded field for different frame typesLLC frame ETYPE = [DSAP SSAP]SNAP frame ETYPE = PID[43]IPv4 or IPv6 TCPUDP frame ETYPE = DPORTIPv4 or IPv6 Other frame ETYPE = IP protocolARP or ETYPE frame ETYPE = Framersquos EtherTypeY1731 OAM frames (EtherType = 0x8902) ETYPE[158] = 0x89ETYPE[7] Set if the frames was injected with masqueradingETYPE[60] Encodes the framersquos MEG level For more information see OAM_MEL_FLAGS Table 54 page 85To indicate the overloading of the ETYPE field OAM_Y1731 is set to 1

IP_SNAP 80 1 Frame type flag Set if frame is IPv4 IPv6 or SNAP frame

IP4 81 1 Frame type flagSet if frame is IPv4 frame

Layer 3 InformationL3_FRAGMENT 82 1 Set if IPv4 frame is fragmented (More Fragments flag = 1 or

Fragments Offset gt 0)Layer 4 information cannot not be trusted

L3_FRAG_OFS_GT0

83 1 Set if IPv4 frame is fragmented and it is not the first fragment (Fragments Offset gt 0) Layer 4 information cannot not be trusted

L3_OPTIONS 84 1 Set if IPv4 frame contains options (IP len gt 5) IP options are not skipped nor parsedLayer 4 information cannot not be trusted

L3_DSCP 85 6 Framersquos DSCP value The DSCP value may have been translated during basic classification See QoS DP and DSCP Classification page 53

Layer 4 InformationTCP_UDP 91 1 Frame type flag

Set if frame is IPv4IPv6 TCP or UDP frame

TCP 92 1 Frame type flag Set if frame is IPv4IPv6 TCP frame

Table 38 bull IS1 Common Key Fields for Half keys

Field Name Bit Width DescriptionLookup InformationIS1_TYPE_HALF 0 1 0 S1_NORMAL entries

1 S1_5TUPLE_IP4 entries

Table 37 bull Specific Fields for IS1 Quad Key S1_DBL_VID (continued)

Field Name Bit Width Description

LOOKUP 1 2 0 First lookup1 Second lookup2 Third lookup

OAM_Y1731 24 1 Set if frame is Y1731 OAM frame with EtherType = 0x8902

VLAN awareness

VLAN_DBL_TAGGED 29 1 Set if frame has two or more Q-tags Independent of port VLAN awareness

Table 39 bull Specific Fields for IS1 Half Key S1_NORMAL

Field Name Bit Width DescriptionLayer-2 InformationL2_SMAC 47 48 Framersquos source MAC address

Use destination MAC address if VCAP_CFGS1_DMAC_DIP_ENA is set for ingress port

Table 38 bull IS1 Common Key Fields for Half keys (continued)

IP_SNAP 112 1 Frame type flagSet if frame is IPv4 IPv6 or SNAP frame

Layer-3 InformationL3_FRAGMENT 114 1 Set if IPv4 frame is fragmented (More Fragments flag = 1 or

L3_FRAG_OFS_GT0 115 1 Set if IPv4 frame is fragmented and it is not the first fragment (Fragments Offset gt 0) Layer 4 information cannot not be trusted

L3_IP4_SIP 123 32 Overloaded fields for different frame typesLLC frame L3_IP4_SIP = [CTRL PAYLOAD[02]]SNAP frame L3_IP4_SIP = [PID[20] PAYLOAD[0]]IPv4 or IPv6 frame L3_IP4_SIP = source IP address bits [310]OAM ARP or ETYPE frame L3_IP4_SIP = PAYLOAD[03]For IPv4 or IPv6 frames use destination IP address if VCAP_CFGS1_DMAC_DIP_ENA is set for ingress port

Layer-4 InformationTCP_UDP 155 1 Frame type flag

L4_SPORT 157 16 TCPUDP framersquos source port

Table 39 bull Specific Fields for IS1 Half Key S1_NORMAL (continued)

L4_RNG 173 8 Range mask with one bit per range A bit is set if the corresponding range is matchedRange types SPORT DPORT SPORT or DPORT VID DSCPInput to range checkers

SPORTDPORT From frameVID From frame if tagged otherwise portrsquos VIDDSCP Translated DSCP from the basic classification

See Range Checkers page 94

Table 40 bull Specific Fields for IS1 Half Key S1_5TUPLE_IP4

Field Name Bit Width DescriptionTagging InformationINNER_TPID 47 1 TPID for inner tag

0 Customer TPID1 Service TPID (88A8 or programmable)

Layer-3 InformationIP4 64 1 Frame type flag

Set if frame is IPv4 frame

L3_FRAGMENT 65 1 Set if IPv4 frame is fragmented (More Fragments flag = 1 or Fragments Offset gt 0)Layer 4 information cannot not be trusted

L3_DSCP 68 6 Framersquos DSCP value The DSCP value may have been translated during basic classification For more information see QoS DP and DSCP Classification page 53

L3_IP4_DIP 74 32 IPv4 destination IP addressIPv6 destination IP address bits [310]

L3_IP4_SIP 106 32 IPv4 source IP addressIPv6 source IP address bits [310]

L3_PROTO 138 8 IPv4 IP protocolIPv6 next header

The following four tables provide information about how the full keys S1_NORMAL_IP6 S1_7TUPLE and S1_5TUPLE_IP6 are generated The first table lists the common fields between the full keys

IP_PAYLOAD_S1_5TUPLE 156 32 Payload after IPv4 or IPv6 header For TCP and UDP frames this field contains the source and destination port numbers

Table 41 bull IS1 Common Key Fields for Full keys

Field Name Bit Width DescriptionLookup InformationIS1_TYPE_FULL 0 2 0 S1_NORMAL_IP6 entries

1 S1_7TUPLE entries2 S1_5TUPLE_IP6 entries

OAM_Y1731 25 1 Set if frame is a Y1731 frame with EtherType = 0x8902

VLAN awareness

Table 40 bull Specific Fields for IS1 Half Key S1_5TUPLE_IP4 (continued)

Table 42 bull Specific Fields for IS1 Full Key S1_NORMAL_IP6

Field Name Bit Width DescriptionLayer 2 InformationL2_SMAC 65 48 Framersquos source MAC address

Layer 3 InformationL3_DSCP 113 6 Framersquos DSCP value The DSCP value may have been

translated during basic classification For more information see QoS DP and DSCP Classification page 53

L3_IP6_SIP 119 128 Source IP addressUse destination IP address if VCAP_CFGS1_DMAC_DIP_ENA is set for ingress port

L3_PROTO 247 8 IPv6 next header

Table 41 bull IS1 Common Key Fields for Full keys (continued)

IP_PAYLOAD_S1_IP6 265 112 Payload after IPv6 header For TCP and UDP frames this field contains the source and destination port numbers

Table 43 bull Specific Fields for IS1 Full Key S1_7TUPLE

Field Name Bit Width DescriptionLayer-2 InformationL2_DMAC 65 48 Framersquos destination MAC address

L2_SMAC 113 48 Framersquos source MAC address

L3_IP6_DIP_MSB 189 16 IPv6 frame L3_IP6_SIP_MSB = destination IP address bits [127112]

Table 42 bull Specific Fields for IS1 Full Key S1_NORMAL_IP6 (continued)

L3_IP6_DIP 205 64 Overloaded fields for different frame typesLLC frame L3_IP6_DIP = PAYLOAD[714]SNAP frame L3_IP6_DIP = PAYLOAD[512]IPv4 frame L3_IP6_DIP = destination IP address bits [310]IPv6 frame L3_IP6_DIP = destination IP address bits [630]OAM ARP or ETYPE frame L3_IP6_DIP = PAYLOAD[815]

L3_IP6_SIP_MSB 269 16 IPv6 frame L3_IP6_SIP_MSB = source IP address bits [127112]

L3_IP6_SIP 285 64 Overloaded fields for different frame typesLLC frame L3_IP6_SIP = [CTRL PAYLOAD[06]]SNAP frame L3_IP6_SIP = [PID[20] PAYLOAD[04]]IPv4 frame L3_IP6_SIP = source IP address bits [310]IPv6 frame L3_IP6_SIP = source IP address bits [630]OAM ARP or ETYPE frame L3_IP6_SIP = PAYLOAD[07]

Table 44 bull Specific Fields for IS1 Full Key S1_5TUPLE_IP6

Field Name Bit Width DescriptionLayer-3 InformationL3_DSCP 65 6 Framersquos DSCP value The DSCP value may have been

translated during basic classification See QoS DP and DSCP Classification page 53

L3_IP6_DIP 71 128 IPv6 destination IP address

L3_IP6_SIP 199 128 IPv6 source IP address

Set if frame is IPv6 TCP or UDP frame

TCP 336 1 Frame type flag Set if frame is IPv6 TCP frame

Table 43 bull Specific Fields for IS1 Full Key S1_7TUPLE (continued)

Fields not applicable to a certain frame type (for example L3_OPTIONS for an IPv6 frame) must be set to donrsquot care for entries the frame type can match

If L3_FRAGMENT or L3_OPTIONS are set to 1 or set to donrsquot care Layer 4 information cannot be trusted and should be set to donrsquot-care for such entries

3822 IS1 Action EncodingThe VCAP generates an action vector from each of the three IS1 lookups All matches return the same action vector independently of the match entry type The action vectors are combined into one action vector which is applied to the classification of the frame

There are no default action vectors for the IS1

The following table lists the available fields for the IS1 action vector

IP_PAYLOAD_S1_5TUPLE 345 32 Payload after IPv6 header For TCP and UDP frames this field contains the source and destination port numbers

Table 45 bull IS1 Action Fields

Action Field Bit Width DescriptionDSCP_ENA 0 1 If set use DSCP_VAL as classified DSCP value

Otherwise DSCP value from basic classification is used

DSCP_VAL 1 6 See DSCP_ENA

QOS_ENA 7 1 If set use QOS_VAL as classified QoS class Otherwise QoS class from basic classification is used

QOS_VAL 8 3 See QOS_ENA

DP_ENA 11 1 If set use DP_VAL as classified drop precedence level Otherwise drop precedence level from basic classification is used

DP_VAL 12 1 See DP_ENA

PAG_OVERRIDE_MASK 13 8 Bits set in this mask will override PAG_VAL from port profile New PAG =(PAG (input) AND ~PAG_OVERRIDE_MASK) OR(PAG_VAL AND PAG_OVERRIDE_MASK)

PAG_VAL 21 8 See PAG_OVERRIDE_MASK

RESERVED 29 9 Reserved Must be set to 0

Table 44 bull Specific Fields for IS1 Full Key S1_5TUPLE_IP6 (continued)

Each lookup returns an action vector if there is a match The potentially three IS1 action vectors are applied in three steps First the action vector from the first lookup is applied then the action vector from the second lookup is applied to the result from the first action vector and finally the action vector from the third lookup is applied to the result from the second action vector This implies that if two or more lookups return an action of DP_ENA = 1 for example the DP_VAL from the last lookup is used

The CUSTOM_ACE_TYPE_ENA action in IS1 enables the use of custom keys in IS2 Two different custom keys are supported

bull CUSTOM_IP 40 bytes are extracted from the frame starting from byte-position 34 This position corresponds to the first byte after the IPv4 header if the frame is IPv4 The 40 bytes are matched against the CUSTOM entries in IS2

bull CUSTOM_SMAC 40 bytes are extracted from the frame starting from byte-position 12 This position corresponds to the first byte after the source MAC address The 40 bytes are matched against the CUSTOM entries in IS2

Note Up to two VLAN tags (two for double VLAN tagged frames and one for single VLAN tagged frames) are removed from the frame before extracting the data

VID_REPLACE_ENA 40 1 Controls the classified VID VID_REPLACE_ENA=0 Add VID_ADD_VAL to basic classified VID and use result as new classified VIDVID_REPLACE_ENA = 1 Replace basic classified VID with VID_VAL value and use as new classified VID

VID_ADD_VAL 41 12 See VID_REPLACE_ENA

FID_SEL 53 2 Controls the Filter Identifier (FID) used when looking up the MAC table0 Disabled FID = classified VID prepended 01 Use FID_VAL for SMAC lookup in MAC table2 Use FID_VAL for DMAC lookup in MAC table3 Use FID_VAL for DMAC and SMAC lookup in MAC table

FID_VAL 55 13 See FID_SEL

PCP_DEI_ENA 68 1 If set use PCP_VAL and DEI_VAL as classified PCP and DEI values Otherwise PCP and DEI from basic classification are used

PCP_VAL 69 3 See PCP_DEI_ENA

DEI_VAL 72 1 See PCP_DEI_ENA

VLAN_POP_CNT_ENA 73 1 If set use VLAN_POP_CNT as the number of VLAN tags to pop from the incoming frame This number is used by the Rewriter Otherwise VLAN_POP_CNT from ANAPORTVLAN_CFGVLAN_POP_CNT is used

VLAN_POP_CNT 74 2 See VLAN_POP_CNT_ENA

CUSTOM_ACE_TYPE_ENA 76 4 Enables use of custom keys in IS2 Bits 32 control second lookup in IS2 while bits 10 control first lookup Encoding per lookup0 Disabled1 Extract 40 bytes after position corresponding to the location of the IPv4 header and use as key2 Extract 40 bytes after SMAC and use as key

HIT_STICKY 80 1 If set a frame has matched against the associated entry

Table 45 bull IS1 Action Fields (continued)

Action Field Bit Width Description

383 VCAP IS2This section provides information about the IS2 keys the SMAC_SIP4 and SMAC_SIP6 keys and associated actions

3831 IS2 Entry Key EncodingAll frame types are subject to the two IS2 lookups The frame type determines the key entry type For more information about VCAP frame types see Table 33 page 61 The following illustrations show entry fields available for each frame type (indicated by the field IS2_TYPE_HALF and IS2_TYPE_FULL) for half and full entries

Figure 25 bull IS2 Half Entry Type Overview

E (TYP

48 bitsETYPE16 bits

L2_PAYLO

016 bits

L2_LLC40 bits

LLC (TY

40 bits

48 bitsL3_IP4_D

IP32 bits

L3_IP4_SIP

32 bits1

L4_SPO

16 bitsL4_D

16 bitsL4_R

8 bits

L3_TOS

8 bitsL3_IP4_S

IP32 bits

L3_PAYLO

56bits

L3_IP6_SIP

128 bits

TD (TY

L3_IP4_DIP

32 bits

L3_PRO

TO8 bits

48 bits

48 bitsL2_S

48 bits

48 bitsSM

48 bits

1L3_IP4_S

IP32 bits

L3_IP4_DIP

32 bitsL3_TO

S8 bits

4bits S

2_TYPE_HALF

6 bitsIG

DIP_EQ

18 bits

DIP_EQ

1L3_PR

8 bits1

DIP_EQ

IP4L3_FR

TL3_FR

L3_OPTIO

L3_TTL_GT0

L4_ACK

L4_PSH

L4_RST

L4_SYN

L4_FINL4_1588_D

L4_1588_VER

PACE_O

KARP_PR

KARP_LEN

ARP_TA

ET_MATC

HARP_S

HARP_O

NARP_O

8 bits3

L2_PAYLO

_MEL_FLA

4 bits

48 bits7 bits

48 bits5 bits

8 bits8 bits

_MEPID

16 bits1

L2_PAYLO

12 bits1

12 bits

L3_TTL_GT0

_IS_Y1731

bull MAC_ETYPE Up to 128 entriesbull MAC_LLC Up to 128 entriesbull MAC_SNAP Up to 128 entriesbull ARP Up to 128 entriesbull IP4_TCP_UDP Up to 128 entriesbull IP4_OTHER Up to 128 entriesbull IP6_STD Up to 128 entriesbull IP6_TCP_UDP Up to 64 entries

bull IP6_OTHER Up to 64 entriesbull OAM Up to 128 entriesThe following tables provide information about how the IS2 half keys are generated The first table lists the common fields between the half keys

Field Name Bit Width DescriptionLookup InformationS2_TYPE_HALF 0 4 0 MAC ETYPE entries

1 MAC LLC entries2 MAC SNAP entries 3 ARP entries4 IPv4 TCPUDP entries5 IPv4 OTHER entries6 IPv6 STD entries7 OAM entries(8 SMAC_SIP6 entries)

FIRST 4 1 Set for first lookup and cleared for second lookup

Interface InformationPAG 5 8 Policy association group Action from VCAP IS1

IGR_PORT_MASK 13 12 Ingress port mask VCAP generated with one bit set in the mask corresponding to the ingress port

Tagging and IP Source Guarding InformationRESERVED 26 1 Reserved Must be set to donrsquot care

HOST_MATCH 26 1 The action from the SMAC_SIP4 or SMAC_SIP6 lookups Used for IP source guarding

VLAN_TAGGED 29 1 Set if frame has one or more Q-tags Independent of port VLAN awareness

VID 30 12 Classified VID which is the result of the VLAN classification in basic classification and IS1

DEI 42 1 Classified DEI which is the final result of the VLAN classification in basic classification and IS1

PCP 43 3 Classified PCP which is the final result of the VLAN classification in basic classification and IS1

Table 47 bull IS2 MAC_ETYPE Key

ETYPE 142 16 Framersquos EtherType This is the EtherType after up to two VLAN tags

L2_PAYLOAD0 158 16 Payload bytes 0-1 after the framersquos EtherType

L2_PAYLOAD1 174 8 Payload byte 4 after the framersquos EtherTypeThis is specifically for PTP frames

L2_PAYLOAD2 182 3 Bits 7 2 and 1 from payload byte 6 after the framersquos EtherTypeThis is specifically for PTP frames

Table 48 bull IS2 MAC_LLC Key

L2_LLC 142 40 LLC header and data after up to two VLAN tags and the typelength field

Table 49 bull IS2 MAC_SNAP Key

L2_SNAP 142 40 SNAP header after LLC header (AA-AA-03)

Table 50 bull IS2 ARP Key

Layer-3 InformationARP_ADDR_SPACE_OK 94 1 Set if hardware address is Ethernet

ARP_PROTO_SPACE_OK 95 1 Set if protocol address space is IP

ARP_LEN_OK 96 1 Set if hardware address length = 6 (Ethernet) and IP address length = 4 (IP)

ARP_TARGET_MATCH 97 1 Target hardware address = SMAC (RARP)

ARP_SENDER_MATCH 98 1 Sender hardware address = SMAC (ARP)

ARP_OPCODE_UNKNOWN 99 1 Set if ARP opcode is none of the below are mentioned

ARP_OPCODE 100 2 0 ARP request1 ARP reply2 RARP request3 RARP reply

L3_IP4_DIP 102 32 Target IPv4 address

L3_IP4_SIP 134 32 Sender IPv4 address

Table 47 bull IS2 MAC_ETYPE Key (continued)

DIP_EQ_SIP 166 1 Set if sender IP address is equal to target IP address

Table 51 bull IS2 IP4_TCP_UDP Key

Field Name Bit Width DescriptionLayer-3 and Layer-4 InformationIP4 46 1 Set if frame is IPv4 frame

IPv6 frames can also use IP4_TCP_UDP entries when IP6_STD entries are disabled

L3_FRAGMENT 47 1 Set if IP frame is fragmented (More Fragments flag = 1 or Fragments Offset gt 0)

L3_FRAG_OFS_GT0 48 1 Set if IP frame is fragmented and it is not the first fragment (Fragments Offset gt 0) Such frames do not carry Layer-4 information all Layer-4 information fields in the key are automatically set to donrsquot-care when generating the key

L3_OPTIONS 49 1 Set if IP frame contains options (IP len gt 5) IP options are not skipped nor parsed which implies that Layer-4 information cannot be used All Layer-4 information fields in the key are automatically set to donrsquot-care when generating the key

L3_TTL_GT0 50 1 Set if IP TTL is greater than 0

L3_TOS 51 8 IP TOS field

L3_IP4_DIP 59 32 IPv4 frames Destination IPv4 addressIPv6 frames Source IPv6 address bits 6332

L3_IP4_SIP 91 32 IPv4 frames Source IPv4 addressIPv6 frames Source IPv6 address bit 310

DIP_EQ_SIP 123 1 Set if source IP address is equal to destination IP address Full addresses are checked also for IPv6

TCP 124 1 Set if IP Proto = 6 (TCP)

L4_DPORT 125 16 TCPUDP destination port

L4_SPORT 141 16 TCPUDP source port

SPORT DPORT From frameVID DSCP Classified result from IS1

SPORT_EQ_DPORT 165 1 Set if UDP or TCP source port equals UDP or TCP destination port

SEQUENCE_EQ0 166 1 TCP Set if TCP sequence number is 0PTP over UDP messageType bit 0

L4_FIN 167 1 TCP TCP flag FINPTP over UDP messageType bit 1

Table 50 bull IS2 ARP Key (continued)

Frames with IP options (L3_OPTIONS set to 1 in key) or fragmented frames which are not the initial fragment (L3_FRAG_OFS_GT0 set to 1 in key) do not carry Layer-4 information The Layer-4 fields in the key (L4_SPORT L4_DPORT L4_RNG SPORT_EQ_DPORT SEQUENCE_EQ0 L4_FIN L4_SYN L4_RST L4_PSH L4_ACK L4_URG L4_1588_DOM and L4_1588_VERSION) are automatically set to donrsquot care

L4_SYN 168 1 TCP TCP flag SYNPTP over UDP messageType bit 2

L4_RST 169 1 TCP TCP flag RSTPTP over UDP messageType bit 3

L4_PSH 170 1 TCP TCP flag PSHPTP over UDP flagField bit 1 (twoStepFlag)

L4_ACK 171 1 TCP TCP flag ACKPTP over UDP flagField bit 2 (unicastFlag)

L4_URG 172 1 TCP TCP flag URGPTP over UDP flagField bit 7 (reserved)

L4_1588_DOM 173 8 PTP over UDP domainNumber

L4_1588_VERSION 181 4 PTP over UDP version

Table 52 bull IS2 IP4_OTHER Key

Field Name Bit Width DescriptionLayer-3 InformationIP4 46 1 Set if frame is IPv4 frame

IPv6 frames can also use IP4_OTHER entries when IP6_STD entries are disabled

L3_FRAG_OFS_GT0 48 1 Set if IP frame is fragmented and if it is not the first fragment (Fragments Offset gt 0)

L3_OPTIONS 49 1 Set if IPv4 frame contains options (IP len gt 5) IP options are not skipped nor parsed which implies that L3_PAYLOAD contains data from the IP options for IPv4 frames with IP options

L3_PAYLOAD 132 56 Bytes 0-6 after IP header

Table 51 bull IS2 IP4_TCP_UDP Key (continued)

The following tables provide information about how the IS2 full keys are generated The first table lists the common fields between the full keys

Table 53 bull IS2 IP6_STD Key

Field Name Bit Width DescriptionLayer-3 InformationL3_TTL_GT0 46 1 Set if IP HOPLIMIT is greater than 0

L3_IP6_SIP 47 128 Framersquos source IPv6 address

Table 54 bull IS2 OAM Key

OAM_MEL_FLAGS 142 7 Encoding of MD levelMEG level (MEL)One bit for each level (lowest level encoded as zero)The following keys can be generatedMEL=0 0x0000000MEL=1 0x0000001MEL=2 0x0000011MEL=3 0x0000111MEL=4 0x0001111MEL=5 0x0011111MEL=6 0x0111111MEL=7 0x1111111

Together with the mask the following kinds of rules may be created

Exact match Fx MEL=2 0x0000011Below Fx MELlt=4 0x000XXXXAbove Fx MELgt=5 0xXX11111Between Fx 3lt= MELlt=5 0x00XX111

where lsquoXrsquo means lsquodonrsquot carersquo

OAM_VER 149 5 Framersquos OAM version

OAM_OPCODE 154 8 Framersquos OAM opcode

OAM_FLAGS 162 8 Framersquos OAM flags

OAM_MEPID 170 16 CCM framersquos OAM MEP ID

OAM_CCM_CNTS_EQ0

186 1 Flag indicating whether dual-ended loss measurement counters in CCM frames are used or not The flag OAM_CCM_CNTS_EQ0 is set if the counters TxFCf RxFCb and TxFCb are set to all zeros

OAM_IS_Y1731 187 1 Set if framersquos EtherType = 0x8902

Field Name Bit Width DescriptionLookup Information

S2_TYPE_FULL 0 2 0 IP6_TCP_UDP entries1 IP6_OTHER entries2 Custom entries

Field Name Bit Width DescriptionLayer-3 and Layer-4 InformationL3_TTL_GT0 44 1 Set if IP HOPLIMIT is greater than 0

L3_IP6_DIP 53 128 Destination IPv6 address

L3_IP6_SIP 181 128 Source IPv6 address

DIP_EQ_SIP 309 1 Set if source IP address is equal to destination IP address

Table 58 bull IS2 CUSTOM Key

Field Name Bit Width DescriptionCustom Information

38311 IS2 Action EncodingThe VCAP generates an action vector from each of the two IS2 lookups for each frame

The first IS2 lookup returns a default action vector per ingress port when no entries are matched and the second IS2 lookup returns a common default action vector when no entries are matched There are no difference between an actionvector from a match and a default action vector

The following table lists the available fields for the action vector

CUSTOM_TYPE 44 1 0 CUSTOM_IP - Custom data extracted from byte 34 (corresponds to the first byte after the IPv4 header if the frame is IPv4)1 CUSTOM_SMAC - Custom data extracted from byte 12 (first byte after SMAC)Note that up to two VLAN tags are removed before extracting the data

CUSTOM 45 320 Custom extracted data

Action Field Bit Width DescriptionHIT_ME_ONCE 0 1 Setting this bit to 1 causes the first frame that hits this action

where the HIT_CNT counter is zero to be copied to the CPU extraction queue specified in CPU_QU_NUM The HIT_CNT counter is then incremented and any frames that hit this action later are not copied to the CPU To re-enable the HIT_ME_ONCE functionality the HIT_CNT counter must be cleared

CPU_COPY_ENA 1 1 Setting this bit to 1 causes all frames that hit this action to be copied to the CPU extraction queue specified in CPU_QU_NUM

CPU_QU_NUM 2 3 Determines the CPU extraction queue that is used when a frame is copied to the CPU due to a HIT_ME_ONCE or CPU_COPY_ENA action

MASK_MODE 5 2 Controls how PORT_MASK is applied0 No action from PORT_MASK1 Permitdeny (PORT_MASK ANDrsquoed with destination set)2 Policy forwarding (DMAC lookup replaced with PORT_MASK)3 Redirect (Previous forwarding decisions (classifier IS1 SRC AGGR VLAN and DMAC lookup) are replaced with PORT_MASK)The CPU port is not touched by MASK_MODE

MIRROR_ENA 7 1 Setting this bit to 1 causes frames to be mirrored to the mirror target port (ANAMIRRPORPORTS)

LRN_DIS 8 1 Setting this bit to 1 disables learning of frames hitting this action

POLICE_ENA 9 1 Setting this bit to 1 causes frames that hit this action to be policed by the ACL policer specified in POLICE_IDX Only applies to the first lookup

Table 58 bull IS2 CUSTOM Key (continued)

The two action vectors from the first and second lookups are combined into one action vector which is applied in the analyzer For more information see Forwarding Engine page 109 The actions are combined as follows

bull HIT_ME_ONCE CPU_COPY_ENA CPU_QU_NUMIf any of the two action vectors have HIT_ME_ONCE or CPU_COPY_ENA set CPU_COPY_ENA is

POLICE_IDX 10 9 Selects VCAP policer used when policing frames (POLICE_ENA)

POLICE_VCAP_ONLY 19 1 Disable policing from QoS and port policers Only the VCAP policer selected by POLICE_IDX is active Only applies to the second lookup

PORT_MASK 20 11 Port mask applied to the forwarding decision based on MASK_MODE

REW_OP 31 9 Rewriter operation command The following functions are supportedNo operation REW_OP[30] = 0No operationSpecial Rewrite REW_OP[30]= 8Swap the MAC addresses and clear bit 40 in the new SMAC when transmitting the frameOne-step PTP REW_OP[20] = 2The frames residence time is added to the correction field in the PTP frame The following sub-commands can be encodedREW_OP[7] Enables Addsubtract modeREW_OP[5] Set if egress delay must be added to correction field at egressREW_OP[43] Configures if ingress delay must be subtracted from the framersquos Rx time stamp This is not applicable for ingress ports in backplane mode

Bits 43 = 0 No delay adjustmentsBits 43 = 1 Subtract delay ANAPORTPTP_DLY1_CFGBits 43 = 2 Subtract delay ANAPORTPTP_DLY2_CFG

Two-step PTP REW_OP[20] = 3The frames departure time stamp is saved in the time stamp FIFO queue at egress REW_OP[83] holds the PTP time stamp identifier used by the CPUOrigin PTP REW_OP[20] = 9The time of day at the frames departure time is written into the origin time stamp field in the PTP frameUnspecified bits must be set to 0

SMAC_REPLACE_ENA 40 1 If set framersquos source MAC address is replaced with MAC address defined per egress port (SYSREW_MAC_LOW_CFG SYSREW_MAC_HIGH_CFG)

ACL_ID 43 6 Logical ID for the entry This ID is extracted together with the frame in the CPU extraction header Only applicable to actions with CPU_COPY_ENA or HIT_ME_ONCE set

HIT_CNT 49 32 A statistics counter that is incremented by one each time the given action is hit

forwarded to the analyzer The settings in the action vector from second lookup takes precedence with respect to the CPU extraction queue number

bull MIRROR_ENAIf any of the two action vectors have MIRROR_ENA set MIRROR_ENA is forwarded to the analyzer

bull LRN_DISIf any of the two action vectors have LRN_DIS set LRN_DIS is forwarded to the analyzer

bull REW_OPThe settings in the action vector from the second lookup takes precedence unless the second lookup returns REW_OP[30] = 0

bull ACL_ID If both lookups in IS2 hit an entry with CPU_COPY_ENA set then the resulting value is the addition of the two ACL_ID values This allow for unique identification of both rules in IS2 through ACL_ID if each lookup manipulates its own part of the ACL_ID For instance first lookup returns ACL_ID = 015 and second lookup returns ACL_ID = 0 16 32 or 48

bull POLICE_ENA POLICE_IDX POLICE_VCAP_ONLYOnly applies to actions from the first lookup

The following table lists the combinations for MASK_MODE and PORT_MASK when combining actions from the first and second lookups

Policy forwarding for frames matching an IPv4 and IPv6 multicast entry in the MAC table is not possible Policy forwarding is handled as a permitdeny action for such frames

38312 SMAC_SIP4 and SMAC_SIP6 Entry Key EncodingThe following illustration shows which entry fields are available for SMAC_SIP4 and SMAC_SIP6 keys in IS2

Figure 27 bull SMAC_SIP Entry Type Overview

VCAP IS2 can hold the following number of SMAC_SIP entries

bull SMAC_SIP6 Up to 128 entriesbull SMAC_SIP4 Up to 256 entries

Table 60 bull MASK_MODE and PORT_MASK Combinations

Second LookupFirst Lookup No action Permitdeny Policy RedirectNo action No action Permit

P1 = P22

1 P Resulting PORT_MASK to analyzer2 P2 PORT_MASK from second match

PolicyP = P2

RedirectP = P2

Permitdeny PermitP = P13

3 P1 PORT_MASK from first match

PermitP = P1 and P2

PolicyP = P1 and P2

RedirectP = P2

Policy PolicyP = P1

PolicyP = P1 and P2

RedirectP = P2

Redirect RedirectP = P1

RedirectP = P1 and P2

RedirectP = P2

SMAC_SIP4 (quad entry no type)

L3_IP6_DIP128 bits

IGR_PORT4 bits

SMAC48 bits

L3_IP4_SIP32 bits

SMAC_SIP6 (half entry TYPE=1000)

L3_IP6_DIP128 bits

IGR_PORT4 bits

SMAC48 bits4 bits

S2_TYPE_HALF

L3_IP6_SIP128 bits

All IPv6 frames are subject to a SMAC_SIP6 lookup in IS2 The following table lists the SMAC_SIP6 key

38313 SMAC_SIP4 and SMAC_SIP6 Action EncodingThe VCAP generates an action vector from the SMAC_SIP4 or SMAC_SIP6 lookup if there is a match There is no default action vector if no match

The following table lists the available fields for the action vector from both the SMAC_SIP4 and SMAC_SIP6 lookups

Table 61 bull SMAC_SIP6 Key

Field Name Bit Width DescriptionLookup InformationS2_TYPE_HALF 0 4 8 SMAC_SIP4

Interface InformationIGR_PORT 4 4 The port number where the frame was received (0-11)

Layer-2 InformationL2_SMAC 8 48 Framersquos source MAC address

Layer-3 InformationL3_IP6_SIP 56 128 Framersquos source IPv6 address

Field Name Bit Width DescriptionInterface InformationIGR_PORT 0 4 The port number where the frame was received (0-11)

Table 63 bull SMAC_SIP4 and SMAC_SIP6 Action Fields

Action Field Bit Width DescriptionCPU_COPY_ENA 0 1 Setting this bit to 1 causes all frames that hit this action to

be copied to the CPU extraction queue specified in CPU_QU_NUM

FWD_KILL_ENA 4 1 Setting this bit to 1 denies forwarding of the frame forwarding to any front port The frame can still be copied to the CPU by other actions

HOST_MATCH 5 1 Used for IP source guarding If set it signals that the host is a valid (for instance a valid combination of source MAC address and source IP address) HOST_MATCH is input to the IS2 keys

The HOST_MATCH flag is used as input into the IS2 keys This enables further handling of frames either matching or not matching a host pair in the SMAC_SIP table

384 VCAP ES0This section provides information about the ES0 key and associated actions

3841 ES0 Entry Key EncodingAll frames are subject to one ES0 lookup per destination port The key in ES0 is generated based on the framersquos VLAN classification

VCAP ES0 can hold 256 ES0 entries

The following table lists the ES0 key

3842 ES0 Action EncodingThe VCAP generates one action vector from the ES0 lookup The lookup returns a default action vector per egress port when no entries are matched There are no difference between an action vector from a match and a default action vector

The following table lists the available action fields for ES0 For more information about how the actions are applied to the VLAN manipulations see VLAN Editing page 133

Table 64 bull ES0 Key

Field Name Bit Width DescriptionInterface InformationEGR_PORT 0 4 The port number where the frame is transmitted (0-11)

IGR_PORT 4 4 The port number where the frame was received (0-11)

Tagging InformationVID 12 12 Classified VID that is the result of the VLAN classification in

basic classification and IS1

DP 24 1 Framersquos drop precedence (DP) level after policing

PCP 25 3 Classified PCP that is the final result of the VLAN classification in basic classification and IS1

Table 65 bull ES0 Action Fields

Action Field Bit Width DescriptionPUSH_OUTER_TAG 0 2 Controls outer tagging

0 No ES0 tag A Port tag is allowed if enabled on port1 ES0 tag A Push ES0 tag A No port tag2 Force port tag Always push port tag No ES0 tag A 3 Force untag Never push port tag or ES0 tag A

PUSH_INNER_TAG 2 1 Controls inner tagging0 Do not push ES0 tag B as inner tag1 Push ES0 tag B as inner tag

TAG_A_TPID_SEL 3 2 Selects TPID for ES0 tag A0 0x81001 0x88A82 Custom (REWPORTPORT_VLAN_CFGPORT_TPID)3 If IFHTAG_TYPE = 0 then 0x8100 else custom

TAG_A_VID_SEL 5 1 Selects VID for ES0 tag A0 Classified VID + VID_A_VAL1 VID_A_VAL

TAG_A_PCP_SEL 6 2 Selects PCP for ES0 tag A0 Classified PCP1 PCP_A_VAL2 DP and QoS mapped to PCP (per port table)3 QoS class

TAG_A_DEI_SEL 8 2 Selects PCP for ES0 tag A0 Classified DEI1 DEI_A_VAL2 DP and QoS mapped to PCP (per port table)3 DP

TAG_B_TPID_SEL 10 2 Selects TPID for ES0 tag B0 0x81001 0x88A82 Custom (REWPORTPORT_VLAN_CFGPORT_TPID)3 If IFHTAG_TYPE = 0 then 0x8100 else custom

TAG_B_VID_SEL 12 1 Selects VID for ES0 tag B0 Classified VID + VID_B_VAL1 VID_B_VAL

TAG_B_PCP_SEL 13 2 Selects PCP for ES0 tag B0 Classified PCP1 PCP_B_VAL2 DP and QoS mapped to PCP (per port table)3 QoS class

TAG_B_DEI_SEL 15 2 Selects PCP for ES0 tag B0 Classified DEI1 DEI_B_VAL2 DP and QoS mapped to PCP (per port table)3 DP

VID_A_VAL 17 12 VID used in ES0 tag A See TAG_A_VID_SEL

PCP_A_VAL 29 3 PCP used in ES0 tag A See TAG_A_PCP_SEL

DEI_A_VAL 32 1 DEI used in ES0 tag A See TAG_A_DEI_SEL

VID_B_VAL 33 12 VID used in ES0 tag B See TAG_B_VID_SEL

PCP_B_VAL 45 3 PCP used in ES0 tag B See TAG_B_PCP_SEL

DEI_B_VAL 48 1 DEI used in ES0 tag B See TAG_B_DEI_SEL

HIT_STICKY 73 1 If set a frame has matched the associated entry

Table 65 bull ES0 Action Fields (continued)

385 Range CheckersThe following table lists the registers associated with configuring range checkers

All IS1 entries together with the IP4_TCP_UDP and IP6_TCP_UDP entries in IS2 contain eight range checker flags (L4_RNG) which are matched against an 8-bit range key The range key is generated for each frame based on the extracted frame data and the configuration in ANAVCAP_RNG_TYPE_CFG and ANAVCAP_RNG_VAL_CFG Each of the eight range checkers can be configured to one of the following range types

bull TCPUDP destination port rangeInput to the range is the framersquos TCPUDP destination port number

bull TCPUDP source port rangeInput to the range is the framersquos TCPUDP source port number

bull TCPUDP source and destination ports range Range is matched if either source or destination port is within rangeInput to the range are the framersquos TCPUDP source and destination port numbers

bull VID rangeIS1 Input to the range is the framersquos VID or the port VID if the frame is untaggedIS2 Input to the range is the classified VID

bull DSCP rangeIS1 Input to the range is the translated DSCP value from basic classificationIS2 Input to the range is the classified DSCP value

For IS2 the range key is only applicable to TCPUDP frames For IS1 the range key is generated for any frame types Specific range types not applicable to a certain frame type (for example TCPUDP port ranges for IPv4 Other frames) must be set to donrsquot care in entries the frame type can match

Range start points and range end points are configured in ANAVCAP_RNG_VAL_CFG

386 VCAP ConfigurationThis section provides information about how the VCAPs (IS1 IS2 and ES0) are configured

Each VCAP implements its own set of the registers listed in the following two tables

Entries in a VCAP are accessed indirectly through an entry and action cache The cache is accessible using the VCAP configuration registers listed in following table As shown in the following illustration an entry in the VCAP consists of a TCAM entry and an associated action and counter entry

The following table lists the registers associated with VCAP configuration

Table 66 bull Range Checker Configuration

Register Description ReplicationANAVCAP_RNG_TYPE_CFG Configuration of the range checker types None

ANAVCAP_RNG_VAL_CFG Configuration of range start and end points None

Table 67 bull VCAP Configuration Registers

Register Description ReplicationVCAP_UPDATE_CTRL General configuration register None

VCAP_MV_CFG Move configuration None

VCAP_ENTRY_DAT Entry data cache 64

VCAP_MASK_DAT Entry mask cache 64

VCAP_ACTION_DAT Action data cache 64

VCAP_CNT_DAT Counter data cache 32

VCAP_TG_DAT Type-Group cache None

Each VCAP has defined various constants and are accessed using the registers listed in the following table

Figure 28 bull VCAP Configuration Overview

A TCAM entry consists of entry data an entry mask and a type-group value The type-group value is used internally to differentiate between VCAP lookups of different subword sizes Each TCAM entry has an associated action entry In addition the action RAM has an entry for each of the default actions in the VCAP The entries in the action RAM consists of action data and a counter value

For a write access the TCAM and action entry must be written to the cache and then copied from the cache to the TCAMRAM For a read access the TCAM and action entry must first be retrieved from the TCAMRAM before being read from the cache When a read or write operation is initiated it is possible to individually select if the operation should be applied to the TCAM andor action RAM When data is moved between the cache and the TCAMRAM it is always the entire entry that is moved For VCAPs with several subwords per entry this must be taken into account if only a single subword of a TCAM entry should be updated To modify a single subword the entire TCAM entry must be read then the subword must be modified in the cache and finally the entry must be written back to the TCAM

The cache can hold only one VCAP entry (TCAM and action entry) at a time After the TCAM and action entry are written to the cache the cache must be copied to the TCAM and RAM before new entries can be written to the cache

VCAP_STICKY Sticky-bit indications None

Table 68 bull VCAP Constants

Register Description ReplicationENTRY_WIDTH Width of entry field None

ENTRY_CNT Number of entries None

ENTRY_SWCNT Number of subwords None

ENTRY_TG_WIDTH Width of type-group field None

ACTION_DEF_CNT Number of default actions None

ACTION_WIDTH Width of action field None

CNT_WIDTH Width of counter field None

Table 67 bull VCAP Configuration Registers (continued)

Entry mask

Action

Counter

Type-Group

TCAM entry

Action RAM

Action entry

RDWRMVoperations

RDWR access

to cache

RegisterAccess

The following table lists the different parameters for the four VCAPs available in the device The parameters are needed to format the data to be written to the cache The parameters can also be read in the registers listed in Table 68 page 95

3861 Creating a VCAP Entry in the CacheBefore a VCAP entry can be created in the TCAM and RAM the entry must be created in the cache The cache is accessed through the following 32-bit registers

bull VCAP_ENTRY_DATbull VCAP_MASK_DATbull VCAP_ACTION_DATbull VCAP_CNT_DATbull VCAP_TG_DAT Each of the cache registers is replicated 64 times however only the bits used by the VCAP are mapped to physical registers For example for VCAP IS1 only the lowest 384 bits of VCAP_ENTRY_DAT and VCAP_MASK_DAT is mapped to physical registers As mentioned previously a VCAP entry consists of a TCAM entry and an action entry

The TCAM entry consists of entry data mask data a type value and a type-group value The entry data prefixed with the type value is written to VCAP_ENTRY_DATA The mask data is written to VCAP_MASK_DATA and the type-group value is written to VCAP_TG_DAT The type and type-group values are used internally in the VCAP to distinguish between the different entry types The following table lists the type and type-group value for each of the entry types

Table 69 bull VCAP Parameters

VCAPEntry Width

Number of Entries

Action Width

Number of Default Actions

Counter Width Subwords

Type-Group Width

IS1 384 64 312 1 4x1 (sticky) 4 2

IS2 384 64 99 13 4x32 4 3

ES0 29 256 72 11 1 (sticky) 1 1

Table 70 bull Entry Type and Type-Group Parameters

VCAP Entry Type Entry Width SubwordsType Value [width in ()]

Type-Group Value [width in ()]

IS1 S1_NORMAL 180 2 0 (1) 2 (2)

IS1 S1_5TUPLE_IP4 187 2 1 (1) 2 (2)

IS1 S1_NORMAL_IP6 374 1 0 (2) 1 (2)

IS1 S1_7TUPLE 373 1 1 (2) 1 (2)

IS1 S1_5TUPLE_IP6 374 1 2 (2) 1 (2)

IS1 S1_DBL_VID 93 4 Not used (0) 3 (2)

IS2 MAC_ETYPE 181 2 0 (4) 2 (2)

IS2 MAC_LCC 178 2 1 (4) 2 (2)

IS2 MAC_SNAP 178 2 2 (4) 2 (2)

IS2 ARP 163 2 3 (4) 2 (2)

IS2 IP4_TCP_UCP 181 2 4 (4) 2 (2)

IS2 IP4_OTHER 184 2 5 (4) 2 (2)

IS2 IP6_STD 179 2 6 (4) 2 (2)

IS2 OAM 184 2 7 (4) 2 (2)

Note that the type value is not used for all entry types If the type value is not used for an entry type write the entry data from bit 0 of VCAP_ENTRY_DAT

As an example of how a TCAM entry is laid out in the cache register the following illustration shows a TCAM entry of the IP6_TCP_UDP entry type for the VCAP IS2

Figure 29 bull Entry Layout in Register Example

Generally the type value must never be masked However by masking the type bits a lookup in the VCAP is able to match several different entry types For example the IS2 entry types MAC_ETYPE and MAC_LLC have the binary type values 0000 and 0001 respectively By masking bit 0 a lookup is able to match both entry types

The entry type used in the preceding example only has one subword per entry in the TCAM Creating a TCAM entry with an entry type that has several subwords per TCAM entry is a little more complicated As shown in the following example the ARP entry type of the VCAP IS2 is used The ARP entry type has two subwords per TCAM entry From Table 70 page 96 it can be seen that the ARP entry type has a width of 163 bits per subword A row in the IS2 TCAM is 384 bits wide For more information see Table 69 page 96 Each subword is assigned to half a TCAM row that is subword 0 is assigned to bits 0-187 and subword 1 is assigned to bits 188-375 Because the ARP entry only is 167 bits wide there are 21 unused bits for each subword as shown in the following illustration The layout for VCAP_MASK_DAT is similar to VCAP_ENTRY_DAT In addition a type-group value is associated to each subword The type-group values are laid out back-to-back in VCAP_TG_DAT as shown in the following illustration

IS2 IP6_TCP_UDP 369 1 0 (2) 1 (2)

IS2 IP6_OTHER 372 1 1 (2) 1 (2)

IS2 CUSTOM 363 1 2 (2) 1 (2)

IS2 SMAC_SIP4 84 4 Not used (0) 3 (2)

IS2 SMAC_SIP6 180 2 8 (4) 2 (2)

ES0 VID 28 1 Not used (0) 1 (1)

Table 70 bull Entry Type and Type-Group Parameters (continued)

0326496128160192

donrsquo

idx 0idx 1idx 2idx 3idx 4idx 5

VCAP_ENTRY_DAT

donrsquo

VCAP_MASK_DAT

donrsquo

roupVCAP_TG_DAT

Entry Data

Mask data

224256288320352idx 6idx 7idx 8idx 9idx 10idx 11

032idx 0

Figure 30 bull Entry Layout in Register using Subwords Example

To invalidate an entry in the TCAM (so a lookup never matches the entry) set the type-group for the entry to 0 If there are more subwords in the entry each subword can be individually invalidated by setting its corresponding type-group value to 0

The action entry is written to VCAP_ACTION_DAT Similar to an entry data an action entry also has a prefixed type value The following table lists the parameters for the different action types available in VCAPs

An action that is associated with an entry type with several subwords per entry has an equal number of subwords For actions with several subwords the subwords are simply concatenated together

The following illustration shows the action layout in the VCAP_ACTION_DAT register for an SMAC_SIP action entry The SMAC_SIP has four subwords per row

Figure 31 bull Action Layout in Register Example

The counter value associated to the action is written to VCAP_CNT_DAT VCAP_CNT_DAT contains a counter value for each subword in the TCAM entry For action entries the counter values for each subword are simply concatenated together

3862 Copying Entries Between Cache and TCAMRAMWhen an entry and associated action is created in the cache the data in the cache must be copied to a given address in the TCAM and RAM using the VCAP_UPDATE_CTRL register Use the following procedure

1 Set VCAP_UPDATE_CTRLUPDATE_CMD to copy from cache to TCAMRAM2 Set the address for the entry in VCAP_UPDATE_CTRLUPDATE_ADDR3 Set VCAP_UPDATE_CTRLUPDATE_SHOT to initiate the copy operation The bit is cleared by

hardware when the operation is finished

Table 71 bull Action and Type Field Parameters

VCAP Action TypeAction Width Subwords

Type Value [width in ()]

IS1 S1 80 4 Not used (0)

IS2 BASE_TYPE 51 2 0 (1)

IS2 SMAC_SIP 6 4 1 (1)

ES0 VID 91 1 Not used (0)

188167

donrsquo

355 subword 1 subword 0

donrsquo

VCAP_TG_DAT

VCAP_ENTRY_DAT

IS2SMAC_SIP

donrsquo

032idx 0

Initiating another operation before the UPDATE_SHOT field is cleared is not allowed The delay between setting the UPDATE_SHOT field and the clearing of that field depends on the type of operation and the traffic load on the VCAP

By setting the fields UPDATE_ENTRY_DIS UPDATE_ACTION_DIS andor UPDATE_CNT_DIS in the VCAP_UPDATE_CTRL register the writing of the TCAM action andor the counter entry can be disabled

Copying a VCAP entry from the TCAMRAM to the cache is done in a similar fashion by setting VCAP_UPDATE_CTRLUPDATE_CMD to copy from TCAMRAM to the cache Note that due to internal mapping of the entry data and mask data the values that are read back from the TCAM cannot always match with the values that were originally written to the TCAM The internal mapping that happens is listed in the following table There are differences because a masked 1 is read back as a masked 0 which is functionally the same

If an entry match is not found during a lookup for a given frame a default action is selected by the VCAP Default actions and counter values are copied between the cache and the action RAM similar to a regular VCAP entry The default actions are stored in the RAM right below the last regular action entry for example VCAP IS2 has 256 regular entries so the first default action in VCAP IS2 is stored at address 256 the second at address 257 and so on For more information about the number of regular VCAP entries in each VCAP see Table 69 page 96 When a default action is copied from the cache to the RAM VCAP_UPDATE_CTRLUPDATE_ENTRY_DIS must be set to disable the update of the TCAM If updating of the TCAM is not disabled the operation may overwrite entries in the TCAM

The cache can be cleared by setting VCAP_UPDATE_CTRLCLEAR_CACHE This sets all replications of VCAP_ENTRY_DAT VCAP_MASK_DAT VCAP_ACTION_DAT VCAP_CNT_DAT and VCAP_TG_DAT to zeros The CLEAR_CACHE field is automatically cleared by hardware when the cache is cleared

387 Advanced VCAP OperationsThe VCAP supports a number of advanced operations that allow easy moving and removal of entries and actions during frame traffic

3871 Moving a Block of Entries and ActionsA number of entries and actions can be moved up or down by several positions in the TCAM and RAM This is done using the VCAP_UPDATE_CTRL and VCAP_MV_CFG registers

A Move operation is performed by

bull Setting VCAP_UPDATE_CTRLUPDATE_ADDR equal to the address of the entry with the lowest address among the entries that must be moved

bull Setting VCAP_MV_CFGMV_SIZE to the number of entries that must be moved n + 1 entries are moved

bull Setting VCAP_MV_CFGMV_NUM_POS to the number of positions the entries must be moved The entries are moved n positions up or down

bull Setting UPDATE_ENTRY_DIS UPDATE_ACTION_DIS andor UPDATE_CNT_DIS to only move some parts of the VCAP entry

bull Setting VCAP_UPDATE_CTRLUPDATE_CMD to move up (decreasing addresses) or move down (increasing addresses)

bull Initiating the Move operation by setting VCAP_UPDATE_CTRLVCAP_UPDATE_SHOT

Table 72 bull Internal Mapping of Entry and Mask

Written Entry Written Mask Description Read Entry Read Mask0 0 Match-0 0 0

0 1 Match-Any 0 1

1 0 Match-1 1 0

1 1 Match-Any 0 1

A new command must not be setup until after the VCAP_UPDATE_CTRLVCAP_UPDATE_SHOT field has automatically cleared Also note that the cache is used by the VCAP while a Move operation is being performed As a result any value in cache prior to a Move operation is lost and a write is not permitted to the cache while a Move operation is performed

The following illustration shows an example of a Move operation

Figure 32 bull Move Down Operation Example

A Move operation can be performed hitlessly during frame traffic that is all entries and actions are still available during a Move operation and all hits are counted by the action hit counters The TCAM entries at the original positions are invalidated after the Move operation is complete

During heavy frame traffic it can take some time for a large move operation to complete because the moving of individual rows are restarted each time a lookup is performed If it is not important that the hit counters are accurately updated while the move operation is processed VCAP_UPDATE_CTRLMV_TRAFFIC_IGN can be set This prevents the VCAP from restarting moves and consequently decreases the time it takes for the move operation to complete It may however lead to inaccurate hit counter values Note that even if MV_TRAFFIC_IGN is set the VCAP still processes all lookups correctly

Default actions can also be moved however VCAP_UPDATE_CTRLUPDATE_ENTRY_DIS must be set

If a row is moved to a negative address (above address 0) the row is effectively deleted If a block is partly moved above address 0 the block is also only partially deleted In other words the rows that are effectively moved to an address below 0 are not deleted If one or more rows are deleted during a move operation the sticky bit VCAP_STICKYVCAP_ROW_DELETED_STICKY is set

3872 Initializing A Block of EntriesA block of entries can be set to the value of the cache in a single operation For example it can be used to initialize all TCAM action and counter entries to a specific value The block of entries to initialize can also include the default action and counter entries

To perform an initialization operation

bull Set VCAP_UPDATE_CTRLUPDATE_ADDR equal to the address of the entry with the lowest address among the entries that should be written

bull Set VCAP_MV_CFGMV_SIZE to the number of entries that must be included in the initialization operation n + 1 entries are included

bull Set UPDATE_ENTRY_DIS UPDATE_ACTION_DIS andor UPDATE_CNT_DIS to select if the TCAM action RAM andor the counter RAM should be excluded from the initialization operation

bull Set VCAP_UPDATE_CTRLUPDATE_CMD to the initialization operationbull Start the initialization operation by setting VCAP_UPDATE_CTRLVCAP_UPDATE_SHOT

255254253252251250249248247246

TCAMActionRAM

Entry+Mask+TGEntry+Mask+TGEntry+Mask+TG

Action CounterAction CounterAction Counter

DefaultActions

Originalposition

Newposition

UPDATE_ADDR = 247

MV_NUM_POS = 4

MV_SIZE = 2

A new command must not be set up until after the VCAP_UPDATE_CTRLVCAP_UPDATE_SHOT field is automatically cleared neither must the cache be written to before VCAP_UPDATE_SHOT is cleared

39 AnalyzerThe analyzer module is responsible for a number of tasks

bull Determining the set of destination ports also known as the forwarding decision for frames received by port modules This includes Layer-2 forwarding CPU-forwarding mirroring and SFlow sampling

bull Keeping track of network stations and their MAC addresses through MAC address learning and aging

bull Holding VLAN membership information (configured by CPU) and applying this to the forwarding decision

The analyzer consists of the following main blocks

bull MAC tablebull VLAN tablebull Forwarding EngineThe MAC and VLAN tables are the main databases used by the forwarding engine The forwarding engine determines the forwarding decision and initiates learning in the MAC table when appropriate

The analyzer operates on analyzer requests initiated by the port modules For each received frame the port module requests the analyzer to determine the forwarding decision Initially the analyzer request is directed to the VCAP The result from the VCAP (the IS2 action) is forwarded to the analyzer along with the original analyzer request For more information about VCAP see VCAP page 60

The analyzer request contains the following frame information

bull Destination and source MAC addressesbull Physical port number where the frame was received (referred to as PPORT)bull Logical port number where the frame was received (referred to as LPORT)

By default LPORT and PPORT are the same However when using link aggregation multiple physical ports map to the same logical port The LPORT value is configured in ANAPORTPORT_CFGPORTID_VAL in the analyzer

bull Frame properties derived by the classifier and VCAP IS1bull Classified VIDbull Link aggregation codebull Basic CPU forwardingbull CPU forwarding for special frame types determined by the classifier

Based on this information the analyzer determines an analyzer reply which is returned to the ingress port modules The analyzer reply contains

bull The forwarding decision (referred to as DEST) This mask contains 11 bits 1 bit for each front port DEST does not include the CPU port The CPU port receives a copy of the frame if the CPU extraction queue mask CPUQ has any bits set

bull The CPU extraction queue mask (referred to as CPUQ) This mask contains 8 bits 1 bit for each CPU extraction queue

The terms PPORT LPORT DEST and CPUQ as previously defined are used throughout the remainder of this section

391 MAC TableThis section provides information about the MAC table block in the analyzer The following table lists the registers associated with MAC table access

Table 73 bull MAC Table Access

Register Description ReplicationMACHDATA MAC address and VID when accessing the MAC table None

MACLDATA MAC address when accessing the MAC table None

The analyzer contains a MAC table with 4096 entries containing information about stations learned by the device The table is organized as a hash table with four buckets and 1024 rows Each row is indexed by an 10-bit hash value which is calculated based on the stationrsquos (MAC VID) pair as shown in the following illustration

Figure 33 bull MAC Table Organization

The following table lists the fields for each entry in the MAC table

MACTINDX Direct address into the MAC table for direct read and write None

MACACCESS Flags and command when accessing the MAC table None

MACTOPTIONS Flags when accessing the MAC table None

AUTOAGE Age scan period None

AGENCTRL Controls the default values for new entries in MAC table None

ENTRYLIM Controls limits on number of learned entries per port Per port

LEARNDISC Counts the number of MAC table entries not learned due lack of storage in the MAC table

Table 74 bull MAC Table Entry

Field Bits DescriptionVALID 1 Entry is valid

MAC 48 The MAC address of the station (primary key)

VID 13 VLAN identifier that the station is learned with (primary key)

DEST_IDX 6 Destination mask index pointing to a destination mask in the destination mask table (PGID entries 0 through 63)

Table 73 bull MAC Table Access (continued)

bucket 0 bucket 1 bucket 2 bucket 3Index 0

MACVIDHash Key Value

Index 1

Index XXX

Index 1023

bucket 0 bucket 1 bucket 2 bucket 3

Entries in the MAC table can be added deleted or updated in three ways

bull Hardware-based learning of source MAC addresses (that is inserting new (MAC VID) pairs in the MAC table)

bull Age scans (setting AGED_FLAG and deleting entries)bull CPU commands (for example for CPU-based learning)

3911 Hardware-Based LearningThe analyzer adds an entry to the MAC table when learning is enabled and the MAC table does not contain an entry for a received framersquos (SMAC VID) The new entry is formatted as follows

bull VALID is setbull MAC is set to the framersquos SMACbull VID is set to the framersquos VID prepended with 0bull ENTRY_TYPE is set to 0 (normal entry subject to aging)bull DEST_IDX is set to the framersquos LPORTbull MAC_CPU_COPY is set to AGENCTRLLEARN_CPU_COPYbull SRC_KILL is set to AGENCTRLLEARN_SRC_KILLbull IGNORE_VLAN is set to AGENCTRLLEARN_IGNORE_VLANbull All other fields are clearedWhen a frame is received from a known station that is the MAC table already contains an entry for the received framersquos (SMAC VID) the analyzer can update the entry as follows

For entries of entry type 0 (unlocked entries)

bull The AGED_FLAG is cleared This implies the station is active avoiding the deletion of the entry due to aging

bull If the existing entryrsquos DEST_IDX differs from the framersquos LPORT then the entryrsquos DEST_IDX is set to the framersquos LPORT This implies the station has moved to a new port

For entries of entry type 1 (locked entries)

bull The AGED_FLAG is cleared This implies the station is activeEntries of entry types 2 and 3 are never updated because their multicast MAC addresses are never used as source MAC addresses

For more information about learning see SMAC Analysis page 114

3912 Age ScanThe analyzer scans the MAC table for inactive entries An age scan is initiated by either a CPU command or automatically performed by the device with a configurable age scan period (AUTOAGE) The age scan

ENTRY_TYPE 2 Entry type0 Normal entry subject to aging1 Normal entry not subject to aging (locked)2 IPv4 multicast entry not subject to aging Full port set is encoded in MAC table entry3 IPv6 multicast entry not subject to aging Full port set is encoded in MAC table entry

AGED_FLAG 1 Entry is aged once by an age scan See Age Scan page 103

MAC_CPU_COPY

1 Copy frames from or to this station to the CPU

SRC_KILL 1 Do not forward frames from this station Note This flag is not used for destination lookups

IGNORE_VLAN 1 Do not use the VLAN_PORT_MASK from the VLAN table when forwarding frames to this station

Table 74 bull MAC Table Entry (continued)

Field Bits Description

checks the flag AGED_FLAG for all entries in the MAC table If an entryrsquos AGED_FLAG is already set and the entry is of entry type 0 the entry is removed If the AGED_FLAG is not set it is set to 1 The flag is cleared when receiving frames from the station identified by the MAC table entry For more information see Hardware-Based Learning page 103

3913 CPU CommandsThe following table lists the set of commands that a CPU can use to access the MAC table The MAC table command is written to MACACCESSMAC_TABLE_CMD Some commands require the registers MACLDATA MACHDATA and MACTINDX to be preloaded before the command is issued Some commands return information in MACACCESS MACLDATA and MACHDATA

Table 75 bull MAC Table Commands

Command Purpose UseLEARN Insertlearn new entry

in MAC tablePosition given by (MAC VID)

Configure MAC and VID of the new entry in MACHDATA and MACLDATA Configure remaining entry fields in MACACCESS The location in the MAC table is calculated based on (MAC VID)

FORGET Deleteunlearn entry given by (MAC VID)

Configure MAC and VID in MACHDATA and MACLDATA

AGE Start age scan No preload required Issue command

READ Read entry pointed to by (row column)

Configure row (0-1023) and column (0-3) of the entry to read inMACTINDXINDEX (row)MACTINDXBUCKET (column)MACACCESSVALID must be set to 0When MAC_TABLE_CMD changes to IDLE MACHDATA MACLDATA and MACACCESS contain the information read

LOOKUP Lookup entry pointed to by (MAC VID)

Configure MAC and VID of station to look up in MACHDATA and MACLDATA MACACCESSVALID must be 1 Issue a READ command When MAC_TABLE_CMD changes to IDLE success of the lookup is indicated by MACACESSVALID If successful MACACCESS contains the entry information

WRITE Write entry MAC table position given by (row column)

Configure MAC and VID of the new entry in MACHDATA and MACLDATA Configure remaining entry fields in MACACCESS The location in the MAC table is given by row and column in MACTINDX

INIT Initialize the table No preload required Issue command

GET_NEXT Get the smallest entry in the MAC table numerically larger than the specified (MAC VID) The VID and MAC are evaluated as a 60-bit number with the VID being most significant

Configure MAC and VID of the starting point for the search in MACHDATA and MACLDATAWhen MAC_TABLE_CMD changes to IDLE success of the search is indicated by MACACESSVALID If successful MACHDATA MACLDATA and MACACCESS contain the information read

IDLE Indicate that MAC table is ready for new command

No preload required

3914 Known MulticastsFrom a CPU entries can be added to the MAC table with any content This makes it possible to add a known multicast address with multiple destination ports

bull Set the MAC and VID in MACHDATA and MACLDATAbull Set MACACCESSENTRY_TYPE = 1 because this is not an entry subject to agingbull Set MACACCESSAGED_FLAG to 0bull Set MACACCESSDEST_IDX to an unused valuebull Set the destination mask in the destination mask table pointed to by DEST_IDX to the desired portsExample All frames in VLAN 12 with MAC address 0x010000112233 are to be forwarded to ports 8 9 and 12

This is done by inserting the following entry in the MAC table

VID = 12MAC = 0x010000112233ENTRY_TYPE = 1VALID = 1AGED_FLAG = 0DEST_IDX = 40

and configuring the destination mask table PGID[40] = 0x1300

IPv4 and IPv6 multicast entries can be programmed differently without using the destination mask table This is described in the following subsection

3915 IPv4 Multicast EntriesMAC table entries with the ENTRY_TYPE = 2 settings are interpreted as IPv4 multicast entries

IPv4 multicasts entries match IPv4 frames which are classified to the specified VID and which have DMAC = 0x01005Exxxxxx where xxxxxx is the lower 24 bits of the MAC address in the entry

Instead of a lookup in the destination mask table (PGID) the destination set is programmed as part of the entry MAC address This is shown in the following table

Example All IPv4 multicast frames in VLAN 12 with MAC 01005E112233 are to be forwarded to ports 3 8 and 9 This is done by inserting the following entry in the MAC table entry

VALID = 1VID = 12 MAC = 0x000308112233ENTRY_TYPE = 2DEST_IDX = 0

3916 IPv6 Multicast EntriesMAC table entries with the ENTRY_TYPE = 3 settings are interpreted as IPv6 multicast entries IPv6 multicasts entries match IPv6 frames which are classified to the specified VID and which have DMAC=0x3333xxxxxxxx where xxxxxxxx is the lower 32 bits of the MAC address in the entry

Table 76 bull IPv4 Multicast Destination Mask

Destination Ports Record Bit FieldPorts 10-0 MAC[34-24]

Destination Ports Record Bit FieldPorts 10 through 0 MAC [42-32]

Example All IPv6 multicast frames in VLAN 12 with MAC 333300112233 are to be forwarded to ports 3 8 and 9

This is done by inserting the following entry in the MAC table entry

VID = 12MAC = 0x030800112233ENTRY_TYPE = 3VALID

1DEST_IDX = 0

Port VLAN and Domain Filter

The following table lists the registers associated with the ageing filter

The ANAGEFIL register can be used to only hit specific VLANs or ports when doing certain operations If the filter is enabled it affects the Manual age scan command (MACACCESSMAC_TABLE_CMD = AGE)

The GET_NEXT MAC table command For more information see CPU Commands page 104

When two or more filters are enabled at the same time for example port and domain all conditions must be fulfilled before the operation (aging GET_NEXT) is carried out

3917 Shared VLAN LearningThe following table lists the location of the Filter Identifier (FID) used for shared VLAN learning

In the default configuration the device is set up to do Independent VLAN Learning (IVL) that is MAC addresses are learned separately on each VLAN The device also supports Shared VLAN Learning (SVL) where a MAC table entry is shared among a group of VLANs For shared VLAN learning a MAC address and a Filter Identifier (FID) define each MAC table entry A set of VIDs then map to the FID

The device supports shared VLAN learning in three ways

bull Through the IS1 actions FID_SEL and FID_VAL specifying the FID to usebull Through the per-VID mapping table FID_MAPbull Through the AGENCTRLFID_MASK which controls a general mapping between FID and VIDs

Table 78 bull VIDPortDomain Filters

Register Description ReplicationANAGEFIL Port VLAN and domain filter for limiting the target for aging and

search operations on MAC tableNone

Table 79 bull FID Definition Registers

Register Description ReplicationIS1_ACTIONFID_SEL Specifies the use of IS1_ACTIONFID_VAL

for the DMAC lookup the SMAC lookup or for both lookups

Per IS1 entry

IS1_ACTIONFID_VAL FID value used when FID_SELgt0 This FID takes precedence

Per IS1 entry

ANAFID_MAPFID_C_VAL VID-to-FID mapping table 64 FIDs are programmable FID_C_VAL=0 effectively disables the mapping implying that FID_C_VAL=VID

Per VID

AGENCTRLFID_MASK Combines multiple VIDs in the MAC table None

The IS1 action FID_SEL selects whether to use the FID_VAL for the DMAC lookup for the SMAC lookup (learning) or for both lookups If set for a lookup the FID_VAL replaces the VID when calculating the hash key into the MAC table and when comparing with the entryrsquos VID If used during the SMAC lookup new entries are learned using the FID_VAL If an IS1 action returns a FID_SEL gt 0 it overrules the use of the FID mapping table for the frame In addition FID_SEL gt 0 overrules the use of the FID_MASK for the MAC table lookups specified in FID_SEL

The FID mapping table FID_MAP maps the framersquos classified VID to a FID If the returned FID is larger than 0 then the FID overrules the use of the FID_MASK for both the DMAC and SMAC lookups in the MAC table Learning is done using the returned FID

If neither IS1 nor the FID_MAP table have instructed changes to the FID then the FID_MASK is applied The 12-bit FID_MASK masks out the corresponding bits in the VID The FID used for learning and lookup is therefore calculated as FID = VID AND (NOT FID_MASK) The FID used in the MAC table is 13 bits so the calculated FID is prepended with 0 Bit 13 in the FID in the MAC table is only selectable through the FID_ENA action out of IS1

All VIDs mapping to the same FID share the same MAC table entries

Example Configure all MAC table entries to be shared among all VLANs

This is done by setting FID_MASK to 111111111111

Example Split the MAC table into two separate databases one for even VIDs and one for odd VIDs

3918 Learn LimitThe following table lists the registers associated with controlling the number of MAC table entries per port

The ENTRYLIMENTRYLIM register specifies the maximum number of unlocked entries in the MAC table that a port is allowed to use Locked and IPMC entries are not taken into account

After the limit is reached both auto-learning and CPU-based learning on unlocked entries are denied A learn frame causing the limit to be exceeded can be copied to the CPU (PORT_CFGLIMIT_CPU) and the forwarding to other front ports can be denied (PORT_CFGLIMIT_DROP)

The ENTRYLIMENTRYSTAT register holds the current number of entries in the MAC table MAC table aging and manual removing of entries through the CPU cause the current number to be reduced If a MAC table entry moves from one port to another port this is also reduces the current number If the move causes the new portrsquos limit to be exceeded the entry is denied and removed from the MAC table

The LEARNDISC counts all events where a MAC table entry is not created or updated due to a learn limit

Table 80 bull Learn Limit Definition Registers

Register Description ReplicationENTRYLIM Configures maximum number of unlocked entries in the

MAC table per ingress port Per port

PORT_CFGLIMIT_CPU If set learn frames exceeding the limit are copied to the CPU

Per port

PORT_CFGLIMIT_DROP If set learn frames exceeding the limit are discarded Per port

LEARNDISC The number of MAC table entries that could not be learned due to a lack of storage space

392 VLAN TableThe following table lists the registers associated with the VLAN Table

The analyzer has a VLAN table that contains information about the members of each of the 4096 VLANs The following table lists fields for each entry in the VLAN table

By default all ports are members of all VLANs This default can be changed through a CPU command The following table lists the set of commands that a CPU can issue to access the VLAN table The VLAN table command is written to VLANACCESSVLAN_TBL_CMD

Table 81 bull VLAN Table Access

Register Description ReplicationVLANTIDX VID to access and VLAN flags None

VLANACCESS VLAN port mask for VID and command for access None

Table 82 bull Fields in the VLAN Table

Field Bits DescriptionVLAN_PORT_MASK 11 One bit for each port Set if port is member of VLAN

The CPU port is always a member of all VLANs

VLAN_MIRROR 1 Mirror frames received in the VLAN See Mirroring page 117

VLAN_SRC_CHK 1 VLAN ingress filtering If set frames classified to this VLAN are dropped if PPORT is not member of the VLAN

VLAN_LEARN_DISABLED 1 Disable learning in the VLAN

VLAN_PRIV_VLAN 1 Set VLAN to private

Table 83 bull VLAN Table Commands

Command Purpose UseINIT Initialize the table Issue command When VLAN_TBL_CMD changes to

IDLE initialization has completed and all ports are member of all VLANs All flags are cleared

READ Read VLAN table entry for specific VID

Configure the VLAN to read from in VLANTIDXV_INDEXWhen VLAN_TBL_CMD changes to IDLE VLANACCESS and VLANTIDX contain the information read

WRITE Write VLAN table entry for specific VID

Configure the VLAN to write to in VLANTIDXV_INDEXConfigure the content of the VLAN record in VLANACCESSVLAN_PORT_MASKVLANTIDXVLAN_MIRRORVLANTIDXVLAN_SRC_CHKVLANTIDXVLAN_LEARN_DISABLEDVLANTIDXVLAN_PRIV_VLAN

IDLE Indicate that VLAN table is ready for new command

No preload required

393 Forwarding EngineThe analyzer determines the set of ports to which each frame is forwarded in several configurable steps The resulting destination port set can include any number of front ports excluding the CPU port The CPU port is handled through te CPU extraction queue mask

The analyzer request from the port modules is passed through all the processing steps of the forwarding engine As each step is carried out the destination port set (DEST) and CPU extraction queue mask (CPUQ) are built up

In addition to the forwarding decision the analyzer determines which frames are subject to learning (also known as learn frames) Learn frames trigger insertion of a new entry in the MAC table or update of an existing entry Learning is presented as part of the forwarding because in some cases learning changes the normal forwarding of a frame such as secure learning

During the processing the analyzer determines a local frame property The learning-disabled flag LRN_DIS is used in the SMAC Learning step

bull If the learning-disabled flag is set learning based on (SMAC VID) is disabled bull If the learning-disabled flag is cleared learning is conducted according to the configuration in the

SMAC learning stepThe following illustration shows the configuration steps in the analyzer

Figure 34 bull Analysis Steps

3931 DMAC AnalysisDuring the DMAC analysis step the (DMAC VID) pair is looked up in the MAC table to get the first input to the calculation of the destination port set For more information about the MAC table see MAC Table page 101

DMAC AnalysisForward to known destinations or flood

MACTable

VLAN AnalysisCheck VLAN membership

VLANTable

AggregationSelect one port per aggregation group

VCAP-II IS2Apply IS2 actions IS2

SMAC AnalysisPerform learning

MAC Table

Storm PolicersLimit rate of specific frame types

sFlow SamplingPerform statistical sampling

LRN_DIS

DESTCPUQ

LRN_DIS

Analyzer Reply

Analyzer Request

The following table lists the registers associated with the DMAC analysis step

The (DMAC VID) pair is looked up in the MAC table A match is found when the (DMAC VID) pair matches that of an entry

If a match is found the entry is returned and DEST is determined based on the MAC table entry For more information see MAC Table page 101

If an entry is found in the MAC table entry of ENTRY_TYPE 0 or 1 and the CPU port is set in the PGID pointed to by the MAC table entry CPU extraction queue PGIDDST_PGID is added to the CPUQ

If an entry is not found for the (DMAC VID) in the MAC table the frame is flooded The forwarding decision is set to one of the seven flooding masks defined in ANAFLOODING or ANAFLOODING_IPMC based on one of the flood type definitions listed in the following table

Table 84 bull DMAC Analysis Registers

Register Description ReplicationFLOODINGFLD_UNICAST Index into the PGID table used for flooding

of unicast framesNone

FLOODINGFLD_BROADCAST Index into the PGID table used for flooding of broadcast frames

FLOODINGFLD_MULTICAST Index into the PGID table used for flooding of multicast frames not flooded by the IPMC flood masks

FLOODING_IPMCFLD_MC4_CTRL Index into the PGID table used for flooding of IPv4 multicast control frames

FLOODING_IPMCFLD_MC4_DATA Index into the PGID table used for flooding of IPv4 multicast data frames

PGID[630] Destination and flooding masks table 64

AGENCTRL IGNORE_DMAC_FLAGS

Controls the use of MAC table flags from (DMAC VID) entry and flooding flags

CPUQ_CFG Configuration of CPU extraction queues None

Table 85 bull Forwarding Decisions Based on Flood Type

Frame Type ConditionIPv4 multicast data DMAC = 0x01005E000000 to 0x01005E7FFFFF

EtherType = IPv4IP protocol is not IGMPIPv4 DIP outside 22400x

IPv6 multicast data DMAC = 0x333300000000 to 0x3333FFFFFFFFFEtherType = IPv6IPv6 DIP outside 0xFF0216

IPv4 multicast control DMAC = 0x01005E000000 to 0x01005E7FFFFFEtherType = IPv4IP protocol is not IGMPIPv4 DIP inside 22400x

In addition the MAC table flag MAC_CPU_COPY is processed If MAC_CPU_COPY is set the CPUQ_CFGCPUQ_MAC is added to CPUQ

The processing of this flag can be disabled through AGENCTRLIGNORE_DMAC_FLAGS

Next CPU-forwarding from the basic classifier and the IS2 SMAC_SIP lookup is processed if

bull The basic classifier decided to copy the frame to the CPU the corresponding CPU extraction queue is added to CPUQ

bull The basic classifier decided to redirect the frame to the CPU DEST is cleared and the corresponding CPU extraction queue is added to CPUQ

bull The IS2 SMAC_SIP result decided to copy the frame to the CPU (SMAC_SIP_ACTIONCPU_COPY_ENA) the corresponding CPU extraction queue SMAC_SIP_ACTIONCPU_QU_NUM is added to CPUQ

bull The IS2 SMAC_SIP result decided to discard the frame (SMAC_SIP_ACTIONFWD_KILL_ENA set) DEST is cleared

For more information about frame type definitions for CPU forwarding in the basic classifier see Table 32 page 59

3932 VLAN AnalysisDuring the VLAN analysis step VLAN configuration is taken into account As a result ports can be removed from the forwarding decision For more information about VLAN configuration see VLAN Table page 108

The following table lists the registers associated with VLAN analysis

IPv6 multicast control DMAC = 0x333300000000 to 0x3333FFFFFFFFFEtherType = IPv6IPv6 DIP inside 0xFF0216

Broadcast DMAC = 0xFFFFFFFFFFFFFFnon-IPv4-multicast-datanon-IPv6-multicast-datanon-IPv4-multicast-controlnon-IPv6-multicast-control

Multicast Bit 40 in DMAC = 1non-broadcastnon-IPv4-multicast-datanon-IPv6-multicast-datanon-IPv4-multicast-controlnon-IPv6-multicast-control

Unicast Bit 40 in DMAC = 0

Table 86 bull VLAN Analysis Registers

Register Description ReplicationVLANMASK If PPORT is set in this mask and PPORT is not member

of the VLAN to which the frame is classified DEST is cleared This is also called VLAN ingress filtering

PORT_CFGRECV_ENA If this bit is cleared for PPORT forwarding from this port to other front ports is disabled and DEST is cleared

Per port

PGID[9180] Source port mask Port mask per port which specifies allowed destination ports for frames received on PPORT By default a port can forward to all other ports except itself

Per port

Table 85 bull Forwarding Decisions Based on Flood Type (continued)

Frame Type Condition

The framersquos VID is used as an address for lookup in the VLAN table and the returned VLAN information is processed as follows

bull All ports that are not members of the VLAN are removed from DEST except if the (DMAC VID) match in the MAC table has VLAN_IGNORE set or if there is no match in the MAC table and AGENCTRLFLOOD_IGNORE_VLAN is set

Note These two exceptions are skipped if AGENCTRLIGNORE_DMAC_FLAGS is setbull If the VLAN_PRIV_VLAN flag in the VLAN table is set the VLAN is private and isolated and

community ports must be treated differently An isolated port is identified as an ingress port for which PPORT is cleared in the ISOLATED_PORTS register An community port is identified as an ingress port for which PPORT is cleared in the COMMUNITY_PORTS register For frames received on an isolated port all isolated and community ports are removed from the forwarding decision For frames received on a community port all isolated ports are removed from the forwarding decision

bull If VLAN ingress filtering is enabled it is checked whether PPORT is member of the VLAN (VLAN_PORT_MASK) If this is not the case DEST is cleared

VLAN ingress filtering is enabled per port in the VLANMASK register or per VLAN in the VLAN_SRC_CHK flag in the VLAN table If either is set VLAN ingress filtering is performed

Next it is checked whether the ingress port is enabled to forward frames to other front ports and the source mask (PGID[80+PPORT]) is processed as follows

bull If PORT_CFGRECV_ENA for PPORT is 0 DEST is clearedbull Any ports which are cleared in PGID[80+PPORT] are removed from DESTFinally SMAC learning is disabled by setting the LRN_DIS flag when either of the following two conditions is fulfilled as follows

bull VLAN_LEARN_DISABLED is set in the VLAN table for the VLANbull A frame is subject to VLAN ingress filtering (frame dropped due to PPORT not being member of

VLAN) and ADVLEARNVLAN_CHK is set

3933 AggregationDuring the aggregation step link aggregation is handled The following table lists the registers associated with aggregation

The aggregation step ensures that when a frame is destined for an aggregation group it is forwarded to exactly one of the grouprsquos member ports

For non-aggregated ports there is a one-to-one correspondence between logical port (LPORT) and physical port (PPORT) The aggregation step does not change the forwarding decision

For aggregated ports all physical ports in the aggregation group map to the same logical port and the entry in the destination mask table for the logical port includes all physical ports which are members of

ISOLATED_PORTS Private VLAN mask Isolated ports are cleared in this mask

COMMUNITY_PORTS Private VLAN mask Community ports are cleared in this mask

ADVLEARNVLAN_CHK If set and VLAN ingress filtering clears DEST then SMAC learning is disabled

Table 87 bull Analyzer Aggregation Registers

Register Description ReplicationPGID[7964] Aggregation mask table 16

Table 86 bull VLAN Analysis Registers (continued)

the aggregation group As a result all but one member port must be removed from the destination port set

The link aggregation code generated in the classifier is used to look up an aggregation mask in the aggregation masks table Finally ports that are cleared in the selected aggregation mask are removed from DEST

For more information about link aggregation see Link Aggregation page 246

3934 VCAP Action HandlingVCAP IS2 actions are processed during the VCAP IS2 action handling step The following table lists the processing of the VCAP actions The order of processing is from top to bottom

3935 SMAC AnalysisDuring the SMAC analysis step the MAC table is searched for a match against the (SMAC VID) and the MAC table is updated due to learning Either the B-MAC table or the C-MAC table is searched The learning part is skipped if the LRN_DIS flag was set by any of the previous steps

The following table lists the registers associated with SMAC learning

Table 88 bull VCAP IS2 Action Processing

IS2 Action Field DescriptionCPU_COPY_ENACPU_QU_NUM

If CPU_COPY_ENA is set the CPU_QU_NUM bit is set in CPUQ

HIT_ME_ONCECPU_QU_NUM

If HIT_ME_ONCE is set and the HIT_CNT counter is zero the CPU_QU_NUM bit is set in CPUQ

LRN_DIS If set learning is disabled (LRN_DIS flag is set)

POLICE_ENAPOLICE_IDX

If POLICE_ENA is set (only applies to first lookup) the POLICE_IDX instructs which policer to use for this frame See Policers page 118

POLICE_VCAP_ONLY If POLICE_VCAP_ONLY is set (only applies to first lookup) the only active policer for this frame is the VCAP policer Other policers (QoS port) are disabled See Policers page 118

MASK_MODEPORT_MASK

The following actions are defined for MASK_MODE0 No action1 Permit Ports cleared in PORT_MASK are removed from DEST2 Policy DEST from the DMAC analysis step is replaced with PORT_MASK3 Redirect DEST as the outcome of the DMAC VLAN service and aggregation analysis steps is replaced with PORT_MASK

MIRROR_ENA If MIRROR_ENA is set mirroring is enabled This is used in the mirroring step See Mirroring page 117

Table 89 bull SMAC Learning Registers

Register Description ReplicationPORT_CFGLEARN_ENA If cleared for PPORT learning is skipped (that is

LEARNAUTO LEARNCPU LEARNDROP LIMIT_CPU LIMIT_DROP LOCKED_PORTMOVE_CPU and LOCKED_PORTMOVE_DROP are ignored)

Per port

PORT_CFGLEARNAUTO If set for PPORT hardware-based learning is performed

Per port

PORT_CFGLEARNCPU If set for PPORT learn frames are copied to the CPU

Per port

Three different type of learn frames are identified

bull Normal learn frames Frames for which an entry for the (SMAC VID) is not found in the MAC table or the (SMAC VID) entry in the MAC table is unlocked and has a DEST_IDX different from LPORT In addition the learn limit for the LPORT must not be exceeded (ENTRYLIM)

bull Learn frames exceeding the learn limit Same condition as for normal learn frames except that the learn limit for the LPORT is exceeded (ENTRYLIM)

bull Learn frames triggering a port move of a locked MAC table entry Frames for which the (SMAC VID) entry in the MAC table is locked and has a DEST_IDX different from LPORT

For all learn frames the following must apply before learning related processing is applied

bull Learning is enabled by PORT_CFGLEARN_ENAbull The LRN_DIS flag from previous processing steps must be cleared which implies the following

Learning is not disabled due to VLAN ingress filteringLearning is not disabled due to VCAP IS2 actionLearning is enabled for the VLAN (VLAN_LEARN_DISABLED is cleared in the VLAN table)

In addition learning must not be disabled due to the ingress policer having policed the frame For more information see Policers page 118

If learning is enabled learn frames are processed according to the setting of the following configuration parameters

39351 Normal Learn Framesbull Automatic learning If PORT_CFGLEARNAUTO is set for PPORT the (SMAC VID) entry is

automatically added to the MAC table in the domain being searchedbull Drop learn frames If PORT_CFGLEARNDROP is set for PPORT DEST is cleared for learn frames

Therefore learn frames are not forwarded on any ports This is used for secure learning where the CPU must verify a station before forwarding is allowed

bull Copy learn frames to the CPU If PORT_CFGLEARNCPU is set for PPORT the CPU port is added to DEST for learn frames and CPUQ_CFGCPUQ_LRN is set in CPUQ This is used for CPU based learning

39352 Learn Frames Exceeding the Learn Limitbull Drop learn frames If PORT_CFGLIMIT_DROP is set for PPORT DEST is cleared for learn frames

As a result learn frames are not forwarded on any portsbull Copy learn frames to the CPU ndash If PORT_CFGLIMIT_CPU is set for PPORT the CPU port is added

to DEST and CPUQ_CFGCPUQ_LRN is set in CPUQ for learn frames

39353 Learn Frames Triggering a Port Move of a Locked MAC Table Entrybull Drop learn frames If PORT_CFGLOCKED_PORTMOVE_DROP is set for PPORT DEST is cleared

for learn frames Therefore learn frames are not forwarded on any ports

PORT_CFGLEARNDROP If set for PPORT the CPU drops or forwards learn frames

Per port

PORT_CFGLIMIT_CPU If set for PPORT learn frames for which PPORT exceeds the portrsquos limit are copied to the CPU

Per port

PORT_CFGLIMIT_DROP If set for PPORT learn frames for which PPORT exceeds the portrsquos limit are discarded

Per port

PORT_CFGLOCKED_PORTMOVE_CPU If set for PPORT frames triggering a port move of a locked entry are copied to the CPU

Per port

PORT_CFGLOCKED_PORTMOVE_DROP If set for PPORT frames triggering a port move of a locked entry are discarded

Per port

AGENCTRLIGNORE_SMAC_FLAGS Controls the use of the MAC table flags from (SMAC VID) entry

Table 89 bull SMAC Learning Registers (continued)

bull Copy learn frames to the CPU If PORT_CFGLOCKED_PORTMOVE_CPU is set for PPORT the CPU port is added to DEST and CPUQ_CFGCPUQ_LOCKED_PORTMOVE is added to CPUQ

Finally if a match is found in the MAC table for the (SMAC VID) adjustments can be made to the forwarding decision

bull If the (SMAC VID) match in the MAC table has SRC_KILL set DEST is clearedbull If the (SMAC VID) match in the MAC table has MAC_CPU_COPY set

CPUQ_CFGCPUQ_MAC_COPY is added to CPUQThe processing of the MAC table flags from the (SMAC VID) match can be disabled through AGENCTRLIGNORE_SMAC_FLAGS

3936 Storm PolicersThe storm policers are activated during the storm policers step The following table lists the registers associated with storm policers

The analyzer contains four storm policers that can limit the maximum allowed forwarding frame rate for various frame types The storm policers are common to all ports and as a result measure the sum of traffic forwarded by the switch A frame can activate several policers and the frame is discarded if any of the activated policers exceed a configured rate

Each policer can be configured to a frame rate ranging from 1 frame per second to 1 million frames per second

The following table lists the available policers

For each of the policers a maximum rate is configured in STORMLIMIT_CFG and STORMLIMIT_BURST

bull STORM_UNIT chooses between a base unit of 1 frame per second or 1 kiloframes per second bull STORM_RATE sets the rate to 1 2 4 8 hellip 1024 times the base unit (STORM_UNIT)bull STORM_BURST configures the maximum number of frames in a burstbull STORM_MODE specifies how the policer affects the forwarding decision The options are

bull When policing clear CPUQbull When policing clear DESTbull When policing clear DEST and CPUQ

Frames where the DMAC lookup returned a PGID with the CPU port set are always forwarded to the CPU even when the frame is policed by the storm policers For more information see DMAC Analysis page 110

Table 90 bull Storm Policer Registers

Register Description ReplicationSTORMLIMIT_CFG Enables policing of various frame types 4

STORMLIMIT_BURST Configures maximum allowed rates of the different frame types None

Table 91 bull Storm Policers

Policer DescriptionBroadcast Flooded frames with DMAC = 0xFFFFFFFFFFFF

Multicast Flooded frames with DMAC bit 40 set except broadcasts

Unicast Flooded frames with DMAC bit 40 cleared

Learn Learn frames copied or redirected to the CPU due to learning (LOCKED_PORTMOVE_CPU LIMIT_CPU LEARNCPU)

3937 sFlow SamplingThis process step handles sFlow sampling The following table lists the registers associated with sFlow sampling

sFlow is a standard for monitoring high-speed switch networks through statistical sampling of incoming and outgoing frames Each port in the device can be setup as an sFlow agent monitoring the particular link and generating sFlow data If a frame is sFlow sampled it is copied to the sFlow CPU extraction queue (CPUQ_SFLOW)

An sFlow agent is configured through SFLOW_CFG with the following options

bull SF_RATE specifies the probability that the sampler copies a frame to the CPU Each frame being candidate for the sampler has the same probability of being sampled The rate is set in steps of 14096

bull SF_SAMPLE_RX enables incoming frames on the port as candidates for the samplerbull SF_SAMPLE_TX enables outgoing frames on the port as candidates for the samplerThe Rx and Tx can be enabled independently If both are enabled all incoming and outgoing traffic on the port is subject to the statistical sampling given by the rate in SF_RATE

3938 MirroringThis processing step handles mirroring The following table lists the registers associated with mirroring

Frames subject to mirroring are identified based on the following mirror probes

bull Learn mirroring if ADVLEARNLEARN_MIRROR is set and frame is a learn framebull CPU mirroring if AGENCTRLMIRROR_CPU is set and the CPU port is set in DESTbull Ingress mirroring if PORT_CFGSRC_MIRROR_ENA is setbull Egress mirroring if any port set in EMIRRORMASK is also set in DESTbull VLAN mirroring if VLAN_MIRROR set in the VLAN table entrybull VCAP mirroring if an action is hit that requires mirroring

Table 92 bull sFlow Sampling Registers

Register Description ReplicationSFLOW_CFG Configures sFlow samplers (type and rates) Per port

CPUQ_CFGCPUQ_SFLOW CPU extraction queue for sFLow sampled frames None

Table 93 bull Mirroring Registers

Register Description ReplicationADVLEARNLEARN_MIRROR For learn frames ports in this mask (mirror

ports) are added to DESTNone

AGENCTRLMIRROR_CPU Mirror all frames forwarded to the CPU port module

PORT_CFGSRC_MIRROR_ENA Mirror all frames received on an ingress port (ingress port mirroring)

Per port

EMIRRORMASK Mirror frames that are to be transmitted on any ports set in this mask (egress port mirroring)

VLANTIDXVLAN_MIRROR Mirror all frames classified to a specific VID Per VLAN

IS2_ACTIONMIRROR_ENA Mirror when an IS2 action is hit Per VCAP IS2 entry

MIRRORPORTS When mirroring a frame ports in this mask are added to DEST

AGENCTRLCPU_CPU_KILL_ENA Clear the CPU port if source port is the CPU port and the CPU port is set in DEST

The following adjustment is made to the forwarding decision for frames subject to mirroring

bull Ports set in MIRRORPORTS are added to DESTIf the CPU port is set in the MIRRORPORTS CPU extraction queue CPUQ_CFGCPUQ_MIRROR is added to the CPUQ

For learn frames with learning enabled all ports in ADVLEARNLEARN_MIRROR are added to DEST For more information see SMAC Analysis page 114

For more information about mirroring see Mirroring page 249

Finally if AGENCTRLCPU_CPU_KILL_ENA is set the CPU port is removed if the ingress port is the CPU port itself This is similar to source port filtering done for front ports and prevents the CPU from sending frames back to itself

394 Analyzer MonitoringMiscellaneous events in the analyzer can be monitored which can provide an understanding of the events during the processing steps The following table lists the registers associated with analyzer monitoring

Port moves defined as a known station moving to a new port are registered in the ANMOVED register A port move occurs when an existing MAC table entry for (MAC VID) is updated with new port information (DEST_IDX) Such an event is registered in ANMOVED by setting the bit corresponding to the new port

Continuously occurring port moves may indicate a loop in the network or a faulty link aggregation configuration

A list of events such as frame flooding or policer drop can be monitored in ANEVENTS

The LEARNDISC counter registers every time an entry in the MAC table cannot be made or if an entry is removed due to lack of storage

310 PolicersThe device has 192 policers that can be allocated to ingress ports QoS classes per port and VCAP IS2 entries The policers limit the bandwidth of received frames by discarding frames exceeding configurable rates All policers are MEF compliant dual leaky bucket policers that are capable of handling committed and excess peak information rates

Each frame can hit up to three policers One port policer one VCAP policer and one QoS policer The order in which the policers are applied to a frame is programmable

In addition to the policers the device also supports a number of storm policers and an egress scheduler with shaping capabilities For more information see Storm Policers page 116 and Scheduler and Shapers page 128

The following table lists the registers associated with policer control

Table 94 bull Analyzer Monitoring

Register Description ReplicationANMOVED ANMOVED[n] is set when a known station has moved to port n None

ANEVENTS Sticky bit register for various events None

LEARNDISC The number of learn events that failed due to a lack of storage space in the MAC table

Table 95 bull Policer Control Registers

Register Description ReplicationANAPORTPOL_CFG Enables use of port and QoS policers Per port

3101 Policer AllocationThe different policer types are assigned a policer from the pool of policers the following ways

bull Port policers Frames received on physical port lsquoprsquo use policer lsquoprsquo Each of physical ports can be assigned to its own policer

bull QoS policers Frames classified to QoS class lsquoqrsquo on physical port lsquoprsquo use policer 32 + 8x lsquoprsquo + lsquoqrsquo Each of the eight per-port QoS classes per port can be assigned to its own policer

bull VCAP IS2 policers Policers 128 through 191 can be allocated to VCAP policing The action IS2_ACTIONPOLICE_IDX points to the policer that is used

The policer pool layout is illustrated in the following drawing

Figure 35 bull Policer Pool Layout

By default none of the policers from the pool are allocated

Port policers are allocated through ANAPORTPOL_CFGPORT_POL_ENA per port and QoS policers are allocated through ANAPORTPOL_CFGQUEUE_POL_ENA per QoS class per port

Finally VCAP IS2 policers are allocated by creating IS2 rules with POLICE_ENA and POLICE_IDX actions IS2 policers actions are only valid in the first lookup in IS2 The VCAP can point to any unused policer in addition to the dedicated VCAP policers

Any frame received by the MAC and forwarded to the classifier is applicable to policing Frames with errors pause frames or MAC control frames are not forwarded by the MAC and as a result they are not accounted for in the policers That is they are not policed and are not adding to the rate measured by the policers

In addition the following special frame types can bypass the policers

ANAPOLPOL_PIR_CFG Configures the policerrsquos peak information rate 384

ANAPOLPOL_CIR_CFG Configures the policerrsquos committed information rate 384

ANAPOLPOL_MODE_CFG Configures the policerrsquos mode of operation 384

ANAPOLPOL_PIR_STATE Current state of the peak information rate bucket 384

ANAPOLPOL_CIR_STATE Current state of the committed information rate bucket 384

ANAPORTPOL_FLOWC Flow control settings Per port

ANAPOL_HYST Hysteresis settings None

Table 95 bull Policer Control Registers (continued)

127128

Port Policers (12)

QoS Policers (96)

Unused12

VCAP Policers (64)

bull If ANAPORTPOL_CFGPOL_CPU_REDIR_8021 is set frames being redirected to the CPU due to the classifier detecting the frames as being BPDU ALLBRIDGE GARP or CCMLink trace frames are not policed

bull If ANAPORTPOL_CFGPOL_CPU_REDIR_IP is set frames being redirected to the CPU due to the classifier detecting the frames as being IGMP or MLD frames are not policed

These frames are still considered part of the rates being measured so the frames add to the relevant policer buckets but they are never discarded due to policing

The VCAP IS2 has the option to disable the port policing and QoS class policing This is done with the action POLICE_VCAP_ONLY If POLICE_VCAP_ONLY is set only a VCAP assigned policer can police the frame The other policers are inactive meaning the frame does not add to the policersrsquo buckets and the frame is never discarded due to policing by the policers

The order in which the policers are executed is controlled through ANAPORTPOL_CFGPOL_ORDER The order can take the following main modes

bull Serial The policers are checked one after another If a policer is closed the frame is discarded and the subsequent policer buckets are not updated with the frame The serial order is programmable

bull Parallel with independent bucket updates The three policers are working in parallel independently of each other Each frame is added to a policer bucket if the policer is open otherwise the frame is discarded A frame may be added to one policer although another policer is closed

bull Parallel with dependent bucket updates The three policers are working in parallel but dependent on each other with respect to bucket updates A frame is only added to the policer buckets if all three policers are open

3102 Policer Burst and Rate ConfigurationEach of the policers is MEF-compliant dual leaky bucket policers This implies that each policer supports the following configurations

bull Committed Information Rate (CIR) Specified in POL_CIR_CFGCIR_RATE in steps of 333 kbps Maximum rate is 109 Gbps If higher bandwidths are required the policer for 25G ports must be disabled

bull Committed Burst Size (CBS) Specified in POL_CIR_CFGCIR_BURST in steps of 4 kilobytes Maximum is 252 kilobytes

bull Excess Information Rate (EIR) Specified in POL_PIR_CFGPIR_RATE in steps of 333 kbps Maximum rate is 109 Gbps If higher bandwidths are required the policer for 25G ports must be disabled

bull Excess Burst Size (EBS) Specified in POL_PIR_CFGPIR_BURST in steps of 4 kilobytes Maximum is 252 kilobytes

bull Coupling flag If POL_MODE_CFGDLB_COUPLED is set frames classified as yellow (DP level = 1) are allowed to use of the committed information rate when not fully used by frames classified as green (DP level = 0) If cleared the rate of frames classified as yellow are bounded by EIR

bull Color mode Color-blind or color-aware A policer always obey the frame color assigned by the classifier To achieve color-blindness the classifier must be set up to classify all incoming frames to DP level = 0

The following parameters can also be configured per policer

bull The leaky bucket calculation can be configured to include or exclude preamble and inter-frame gap through configuration of POL_MODE_CFGIPG_SIZE

bull Each policer can be configured to measure frame rates instead of bit rates (POL_MODE_CFGFRM_MODE) The rate unit can be configured to 100 frames per second or 1 frame per second

bull Each policer can operate as a single leaky bucket by disabling POL_MODE_CFGCIR_ENA When operating as a single leaky bucket the POL_PIR_CFG register controls the rate and burst of the policer

By default a policer discards frames while the policer is closed A discarded frame is neither forwarded to any ports (including the CPU) nor is it learned

Each port policer however has the option to run in flow control where the policer instructs the MAC to issue flow control pause frames instead of discarding frames This is enabled in

ANAPORTPOL_FLOWC Common for all port policers POL_HYSTPOL_FC_HYST specifies a hysteresis which controls when the policer can re-open after having closed

To improve fairness between small and large frames being policed by the same policer POL_HYSTPOL_DROP_HYST specifies a hysteresis that controls when the policer can re-open after being closed By setting it to a value larger than the maximum transmission unit it guarantees that when the policer opens again all frames have the same chance of being accepted This setting only applies to policers working in drop mode

The current fill level of the dual leaky buckets can be read in POL_PIR_STATE and POL_CIR_STATE The unit is 05 bits

311 Shared Queue SystemThe device includes a shared queue system with one ingress queue per ingress port and one egress queue per QoS class per egress port per ingress port The queue system has 224 kilobytes of buffer

Frames are linked into the ingress queues after frame analysis Each egress port module selected by the frame analysis receives a link to the frame and stores the link in the appropriate egress queue selected by mapping various frame properties to a queue number The transfer from ingress to egress is extremely efficient with a transfer time of 128 ns per frame copy (equivalent to a transfer rate from ingress to egress of about 50 Gbps for 64-byte frames and about 1 terabit per second (Tbps) for 1518-byte frames) Each egress port module has a scheduler that selects between the egress queues when transmitting frames

The following illustration shows the shared queue system

Figure 36 bull Queue System Overview

Resource depletion can prevent one or more of the frame copies from the ingress queue to the egress queues If a frame copy cannot be made due to lack of resources the ingress portrsquos flow control mode determines the behavior as follows

bull Ingress port is in drop mode The frame copy is discardedbull Ingress port is in flow control mode The frame is held back in the ingress queue and the frame copy

is made when the congestion clearsFor more information about special configurations of the shared queue system with respect to flow control see Ingress Pause Request Generation page 126

Egress TransmitterEgress Port Module (1 per port)

Ingress Queues(1 per port)

Egress Queues

Frame Analysis(Find QoS class and set of destination

ports)

Queue 00

Queue 01

Queue 9511

Scheduler

Ingr Queue 0

Ingr Queue 1

Ingr Queue 11

One or multiple copiesor discard

MAC Tx

Rx MACRx MACRx MAC

Queue M

3111 Buffer ManagementA number of watermarks control how much data can be pending in the egress queues before the resources are depleted There are no watermarks for the ingress queues except for flow control because the ingress queues are empty most of the time due to the fast transfer rates from ingress to egress For more information see Ingress Pause Request Generation page 126 When the watermarks are configured properly congested traffic does not influence the forwarding of non-congested traffic

The memory is split into two main areas

bull A reserved memory area The reserved memory area is subdivided into areas per port per QoS class per direction (ingressegress)

bull A shared memory area which is shared by all traffic For setting up the reserved areas egress watermarks exist per port and per QoS class for both ingress and egress The following table lists the reservation watermarks

All the watermarks including the ingress watermarks are compared against the memory consumptions in the egress queues For example the ingress watermarks in BUF_Q_RSRV_I compare against the total consumption of frames across all egress queues received on the specific ingress port and classified to the specific QoS class The ingress watermarks in BUF_P_RSRV_I compare against the total consumption of all frames across all egress queues received on the specific ingress port

The reserved areas are guaranteed minimum areas A frame cannot be discarded or held back in the ingress queues if the framersquos reserved areas are not yet used

The shared memory area is the area left when all the reservations are taken out The shared memory area is shared between all ports however it is possible to configure a set of watermarks per QoS class and per drop precedence level (greenyellow) to stop some traffic flows before others The following table lists the sharing watermarks

Table 96 bull Reservation Watermarks

Register Description ReplicationBUF_Q_RSRV_E Configures the reserved amount of egress buffer per QoS

class per egress portPer QoS class per egress port

BUF_P_RSRV_E Configures the reserved amount of egress buffer shared among the egress portrsquos allocated egress queues

Per egress port

BUF_Q_RSRV_I Configures the reserved amount of egress buffer per ingress port per QoS class across all egress ports

Per ingress port per QoS class

BUF_P_RSRV_I Configures the reserved amount of egress buffer per ingress port shared among the eight QoS classes

Per ingress port

Table 97 bull Sharing Watermarks

Register Description ReplicationBUF_PRIO_SHR_E Configures how much of the shared memory area that egress

frames with the given QoS class are allowed to usePer QoS class

BUF_COL_SHR_E Configures how much of the shared memory area that egress frames with the given drop precedence level are allowed to use

Per drop precedence level

BUF_PRIO_SHR_I Configures how much of the shared memory area that ingress frames with the given QoS class are allowed to use

Per QoS class

BUF_COL_SHR_I Configures how much of the shared memory area that ingress frames with the given drop precedence level are allowed to use

The sharing watermarks are maximum areas in the shared memory that a given traffic flow can use They do not guarantee anything

When a frame is enqueued into the egress queue system the frame first consumes from the queuersquos reserved memory area then from the portrsquos reserved memory area When all the framersquos reserved memory areas are full it consumes from the shared memory area

The following provides some simple examples on how to configure the watermarks and how that influences the resource management

bull Setting BUF_Q_RSRV_E(egress port = 7 QoS class = 4) to 2 kilobytes guarantees that traffic destined for port 7 classified to QoS class 4 have room for 2 kilobytes of frame data before frames can get discarded

bull Setting BUF_Q_RSRV_I(ingress port = 7 QoS class = 4) to 2 kilobytes guarantees that traffic received on port 7 classified to QoS class 4 have room for 2 kilobytes of frame data before frames can get discarded

bull Setting BUF_P_RSRV_I(ingress port 7) to 10 kilobytes guarantees that traffic received on port 7 have room for 10 kilobytes of data before frames can get discarded

bull The three reservations above reserve 14 kilobytes of memory in total (2 + 2+ 10 kilobytes) for port 7 If the same reservations are made for all ports there are 224 ndash 11 times 14 = 70 kilobytes left for sharing If the sharing watermarks are all set to 70 kilobytes all traffic groups can consume memory from the shared memory area without restrictions

If instead setting BUF_PRIO_SHR_E(QoS class = 7) to 70 kilobytes and the other watermarks BUF_PRIO_SHR_E(QoS class = 06) to 20 kilobytes guarantees that traffic classified to QoS class 7 has 50 kilobytes extra buffer The buffer is shared between all ports

bull The BUF_PRIO_SHR_I BUF_PRIO_SHR_E REF_PRIO_SHR_I and REF_PRIO_SHR_E watermarks can be used for guaranteeing shared resources for each individual QoS class This is done by setting QSYSRES_QOS_MODE so that the watermarks operate on the current consumption of each QoS class instead of the total use of the shared resources

3112 Frame Reference ManagementEach frame in an egress queue consumes a frame reference which is a pointer element that points to the framersquos data in the memory and to the pointer element belonging to the next frame in the queue The following illustrations shows how the frame references are used for creating the queue structure

Figure 37 bull Frame Reference

The shared queue system holds a table of 1911 frame references The consumption of frame references is controlled through a set of watermarks The set of watermarks is the exact same as for the buffer control The frame reference watermarks are prefixed REF_ Instead of controlling the amount of consumed memory they control the number of frame references Both reservation and sharing watermarks are available For more information see Table 96 page 122 and Table 97 page 122

Egress queue port 7 QoS class 4Head Tail

Buffer Memory Frame References

Frame R

eference PointerM

emory Pointer

When a frame is enqueued into the shared queue system the frame consumes first from the queuersquos reserved frame reference area then from the portrsquos reserved frame reference area When all the framersquos reserved frame reference areas are full it consumes from the shared frame reference area

3113 Resource Depletion ConditionA frame copy is made from an ingress port to an egress port when both a memory check and a frame reference check succeed The memory check succeeds when at least one of the following conditions is met

bull Ingress memory is available BUF_Q_RSRV_I or BUF_P_RSRV_I are not exceededbull Egress memory is available BUF_Q_RSRV_E or BUF_P_RSRV_E are not exceededbull Shared memory is available None of BUF_PRIO_SHR_E BUF_COL_SHR_E BUF_PRIO_SHR_I

or BUF_COL_SHR_I are exceededThe frame reference check succeeds when at least one of the following conditions is met

bull Ingress frame references are available REF_Q_RSRV_I or REF_P_RSRV_I are not exceededbull Egress frame references are available REF_Q_RSRV_E or REF_P_RSRV_E are not exceededbull Shared frame references are available None of REF_PRIO_SHR_E REF_COL_SHR_E

REF_PRIO_SHR_I or REF_COL_SHR_I are exceeded

3114 Configuration ExampleThis section provides an example of how the watermarks can be configured for a QoS-aware switch with no color handling and the effects of the settings

Table 98 bull Watermark Configuration Example

Watermark Value CommentBUF_Q_RSRV_I 500 bytes Guarantees that a port is capable of receiving at least one

frame in all QoS classesNote It is not necessary to assign a full MTU because the watermarks are checked before the frame is added to the memory consumption

BUF_P_RSRV_I 0 No additional guarantees for the ingress port

BUF_Q_RSRV_E 200 bytes Guarantees that all QoS classes are capable of sending a non-congested stream of traffic through the switch

BUF_P_RSRV_E 10 kilobytes Guarantees that all egress ports have 10 kilobytes of buffer independently of other traffic in the switch This is the most demanding reservation in this setup reserving 110 kilobytes of the total 224 kilobytes

BUF_COL_SHR_EBUF_COL_SHR_I

Maximum Effectively disables frame coloring as watermark is never reached

BUF_PRIO_SHR_EBUF_PRIO_SHR_I

42 kilobytes to 63 kilobytes

The different QoS classes are cut-off with 3 kilobytes distance (42 45 48 51 54 57 60 and 63 kilobytes) This gives frames with higher QoS classes a larger part of the shared buffer area Effectively this means that the burst capacity is 52 kilobytes for frames belonging to QoS class 0 and up to 73 kilobytes for frame belonging to QoS class 7

REF_Q_RSRV_EREF_Q_RSRV_I

4 For both ingress and egress this guarantees that four frames can be pending from and to each port

REF_P_RSRV_EREF_P_RSRV_I

20 For both ingress and egress this guarantees that an extra 20 frames can be pending shared between all QoS classes within the port

3115 Watermark Programming and Consumption MonitoringThe watermarks previously described are all found in the SYSRES_CFG register The register is replicated 1024 times The following illustration the organization

Figure 38 bull Watermark Layout

The illustration shows the watermarks available for the BUF_xxx_I group of watermarks For the other groups of watermarks (BUF_xxx_I REF_xxx_I BUF_xxx_E and REF_xxx_E) the exact same set of watermarks are available

For monitoring the consumption of resources SYSRES_STAT provides information about current use and the maximum use since the last read of the register The information is available for each of the watermarks listed and the layout of the RES_STAT register follows the layout of the watermarks SYSMMGTFREECNT holds the amount of free memory in the shared queue system and SYSEQ_CTRLFP_FREE_CNT holds the number of free frame references in the shared queue system

REF_COL_SHR_EREF_COL_SHR_I

REF_PRIO_SHR_EREF_PRIO_SHR_I

1350 - 1700 The different QoS classes are cut-off with a distance of 50 frame references (1350 1400 1450 1500 1550 1600 1650 and 1700) This gives frames with higher QoS classes a larger part of the shared reference area

Table 98 bull Watermark Configuration Example (continued)

Watermark Value Comment

BUF_xxx_I

REF_xxx_I

BUF_xxx_E

REF_xxx_E

Port and QoS class reservationwatermarks

(xxx = Q_RSRV)

Port reservationwatermarks

(xxx = P_RSRV)

Color Sharing watermarks

(xxx = COL_SHR)

Port 0Port 1Port 2

Port 10Port 11

QoS class 0QoS class 1QoS class 2

QoS class 6QoS class 7

QoS class sharingwatermarks

(xxx = PRIO_SHR)

Port 0Port 1Port 2

Port 10Port 11

DP 1 (yellow)DP 0 (green)

3116 Advanced Resource ManagementA number of additional handles into the resource management system are available for special use of the device They are described in the following table

3117 Ingress Pause Request GenerationDuring resource depletion the shared queue system either discards frames when the ingress port operates in drop mode or holds back frames when the ingress port operates in flow control mode The following describes special configuration for the flow control mode

The shared queue system is enabled for holding back frames during resource depletion in SYSPORTPAUSE_CFGPAUSE_ENA In addition this enables the generation of pause requests to the port module based on memory consumptions The MAC uses the pause request to generate pause frames or create back pressure collisions to halt the link partner This is done according to the MAC configuration For more information about MAC configuration see MAC page 17

The shared queue system generates the pause request based on the ingress portrsquos memory consumption and also based on the total memory consumption in the shared queue system This enables a larger burst capacity for a port operating in flow control while not jeopardizing the non-dropping flow control

Generating the pause request partially depends on a memory consumption flag TOT_PAUSE which is set and cleared under the following conditions

bull The TOT_PAUSE flag is set when the total consumed memory in the shared queue system exceeds the SYSPORTPAUSE_TOT_CFGPAUSE_TOT_START watermark

bull The TOT_PAUSE flag is cleared when the total consumed memory in the shared queue system is below the SYSPORTPAUSE_TOT_CFGPAUSE_TOT_STOP watermark

The pause request is asserted when both of the following conditions are met

Table 99 bull Resource Management

Resource Management DescriptionForced drop of egress and ingress frames

QSYSEGR_DROP_MODEQSYSSWITCH_PORT_MODEINGRESS_DROP_MODEIf either an ingress port or an egress port in a frame transfer are configured for drop mode congestion results in frame discards Otherwise frames are held back in the ingress queues with potential head-of-line blocking effects Normally all egress ports are set to non-drop-mode while the ingress drop mode reflects whether or not the port is configured for flow control

Prevent ingress port from using of the shared resources

QSYSIGR_NO_SHARINGFor frames received on ports set in this mask the shared watermarks are considered exceeded This prevents the port from using more resources than allowed by the reservation watermarks

Prevent egress port from using of the shared resources

QSYSEGR_NO_SHARINGFor frames switched to ports set in this mask the shared watermarks are considered exceeded This prevents the port from using more resources than allowed by the reservation watermarks

Weighted Random Early Detection (WRED)

QSYSRED_PROFILEIt is possible to discard frames with increasing probability as the consumption of shared resources per QoS class per drop precedence level increases QSYSRED_PROFILE configures a low and a high watermark per QoS class per drop precedence level The probability of discarding a frame increases linearly from 0 when the consumption is at the low watermark to 100 when the consumption exceeds the high watermark

Prevent dequeuing QSYSPORT_MODEDEQUEUE_DISEach egress port can disable dequeuing of frames from the egress queues

bull The TOT_PAUSE flag is setbull The ingress port memory consumption exceeds the SYSPORTPAUSE_CFGPAUSE_START

watermarkThe pause request is deasserted the following condition is met

bull The ingress portrsquos consumption is below the SYSPORTPAUSE_CFGPAUSE_STOP watermark

3118 Tail DroppingThe shared queue system implements a tail dropping mechanism where incoming frames are discarded if the portrsquos memory consumption and the total memory consumption exceed certain watermarks Tail dropping implies that the frame is discarded unconditionally All ports in the device are subject to tail dropping It is independent of whether the port is in flow control mode or in drop mode

Tail dropping can be effective under special conditions For example tail dropping can prevent an ingress port from consuming all the shared memory when pause frames are lost or when the link partner is not responding to pause frames

The shared queue system initiates tail dropping by discarding the incoming frame if the following two conditions are met at any point while writing the frame data to the memory

bull If the Ingress port memory consumption exceeds the SYSPORTATOP_CFGATOP watermarkbull If the total consumed memory in the shared queue system exceeds the

SYSPORTATOP_TOT_CFGATOP_TOT watermark

3119 Test UtilitiesThis section describes some of test utilities that are built into the shared queue system

Each egress port can enable a frame repeater (SYSREPEATER) which means that the head-of-line frames in the egress queues are transmitted but not dequeued after transmission As a result the scheduler sees the same frames again and again while the repeater function is active

The SYSPORTPORT_MODEDEQUEUE_DIS disables both transmission and dequeuing from the egress queues when set

31110 Energy Efficient EthernetThis section provides information about the functions of Energy Efficient Ethernet in the shared queue system The following table lists the registers associated with Energy Efficient Ethernet

The shared queue system supports Energy Efficient Ethernet (EEE) as defined by IEEE Draft P8023az by initiating the Low Power Idle (LPI) mode during periods of low link use EEE is controlled per port by an egress queue state machine that monitors the queue fillings and ensures correct wake-up and sleep timing The egress queue state machine is responsible for informing the PCS in the port module of changes in EEE states (active sleep low power idle and wake up)

Table 100 bull Energy Efficient Ethernet Control Registers

Register Description ReplicationDEVEEE_CFG Enables configuration of Energy Efficient Ethernet Status

bit indicating that egress port is in the LPI statePer port

QSYSEEE_CFG Configures fast queues Per port

QSYSEEE_THRES Configures bytes and frame thresholds None

Energy Efficient Ethernet is enabled per port through DEVEEE_CFGEEE_ENA

By default the egress port is transmitting enqueued data This is the active state If none of the portrsquos egress queues have enqueued data for the time specified in DEVEEE_CFGEEE_TIMER_HOLDOFF the egress port instructs the PCS to enter the EEE sleep state

When data is enqueued in any of the portrsquos egress queues a timer (DEVEEE_CFGEEE_TIMER_AGE) is started If one of the following conditions is met the port enters the wake up state

bull A queue specified as high priority (QSYSPORTEEE_CFGEEE_FAST_QUEUES) has any data to transmit

bull The total number of frames in the portrsquos egress queues exceeds QSYSEEE_THRESEEE_HIGH_FRAMES

bull The total number of bytes in the portrsquos egress queues exceeds QSYSEEE_THRESEEE_HIGH_FRAMES

bull The time specified in DEVEEE_CFGEEE_TIMER_AGE has passed PCS is instructed to wake up To ensure that PCS PHY and link partner are resynchronized after waking up the egress port holds back transmission of data until the time specified in DEVEEE_CFGEEE_TIMER_WAKEUP has passed After this time interval the port resumes transmission of data

The status bit DEVEEE_CFGPORT_LPI is set while the egress port holds back data due to LPI (from the sleep state to the wake up state both included)

312 Scheduler and ShapersThe following table lists the registers associated with the scheduler and egress shaper control

Each egress port contains a two-level priority-fair egress scheduler The first scheduler level towards the egress port schedules between QoS classes while the second scheduler level towards the egress queues schedules between the ingress ports

An egress scheduler is constructed using 9 scheduler elements Each scheduler elements has 12 inputs and 1 output It contains a scheduler which can be strict or mixed with a round robin based scheduling algorithm The round robin based scheduling algorithm can either be frame-based round robin or byte-based deficit weighted round robin The output port of a scheduler elements contains a dual leaky bucket shaper

The following illustration provides an overview of the egress scheduling system for egress port 0

Table 101 bull Scheduler and Egress Shaper Control Registers

Register Description ReplicationQSYSSHAPER_CFG Configuration of egress shaperrsquos rate and burst 158

QSYSSE_CFG Configuration of the scheduling algorithm 158

QSYSSE_DWRR_CFG Configuration of DWRR schedulerrsquos costs 158

QSYSSHAPER_STATE Status of the shaper bucket 158

Active

Refresh

Active

TS TQ TR

Quiet Quiet Quiet

Figure 40 bull Egress Scheduler Port 0

Each egress port features a similar egress scheduler The following table lists which scheduler elements are used by the different ports

Table 102 bull Scheduler Elements Numbering

Egress Port Scheduler Elements - Level 1 Scheduler Elements - Level 20 146 0 through 7

1 147 8 through 15

2 148 16 through 23

3 149 24 through 31

4 150 32 through 39

5 151 40 through 47

6 152 48 through 55

7 153 56 through 63

8 154 64 through 71

9 155 72 through 79

PortLevel 2

QoS ClassLevel 1

Port0 QoS class 7

Port9 QoS class 7

Port10 QoS class 7

Port11 QoS class 7

Port0 QoS class 0

Port9 QoS class 0

Port10 QoS class 0

Port11 QoS class 0

STRICT

SE 146

3121 Scheduler ElementThe following illustration shows the scheduler element

Figure 41 bull Scheduler Element

By default the scheduler operates in strict priority between all 12 inputs The inputs are searched in the following prioritized order Input 11 has highest priority followed by 10 9 8 7 6 5 4 3 2 1 and 0

In addition the scheduler can operate either in a byte-based deficit weighted round robin (DWRR) mode or a frame-based round robin (RR) mode This is an overall configuration for the scheduler element and cannot be selected per input In DWRR mode the participating inputs are given a weight and the scheduler selects frames from these inputs according to the weights The DWRR is byte-based and takes the lengths of the frames into account In RR mode the participating inputs are selected one after another The RR is frame-based and does not take the length of the frames into account

The scheduler supports a mixed mode where some inputs operate in strict priority and others operate in either DWRR or RR Any number of inputs can be assigned to either group but strict priority inputs must always be selected from highest numbered inputs

Each scheduler element has an associated leaky-bucket shaper at the output The shaper limits the overall transmission bandwidth from the scheduler element Frames are only scheduled if the shaper is open

Each scheduling element determines whether it has a frame ready for scheduling based on status information of the scheduling elementrsquos inputs For each input the scheduling element knows if the input has a frame ready for transmission and if the frame is ready due to a work conservation mode The overall scheduling algorithm within a scheduling element is as follows

1 If the output shaper is closed frames are only scheduled from the element if the element is enabled for work conservation Otherwise frames are held back until the shaper opens

2 If the output shaper is open or in work conservation mode the scheduling element schedules between inputs that are not work conserving by following the rules for the scheduler configuration strict inputs are scheduled first then round robin based inputs are scheduled according to either the DWRR algorithm or the RR algorithm

3 If no frames are scheduled during step 2 a second round of scheduling is performed Inputs that are work conserving become candidates for the second round of scheduling

The hierarchy of scheduling elements is traversed from the element connected to the egress port through to the element that connects to an egress queue by recursively deciding which input should be scheduled

10 156 80 through 87

11 (CPU) 157 88 through 95

Table 102 bull Scheduler Elements Numbering (continued)

Egress Port Scheduler Elements - Level 1 Scheduler Elements - Level 2

Byte-basedDWRR

Frame-basedRR

N-Strict

OutputS

Shaper

Inputs

Scheduler

3122 Egress ShapersEach of the scheduling elements contain an output shaper with the following configurations

bull Maximum rate ndash Specified in SHAPER_CFGRATE in steps of 100160 bps Maximum is 3282 Gbpsbull Maximum burst size ndash Specified in SHAPER_CFGBURST in steps of 4 kilobytes Maximum is

252 kilobytesThe shaper can operate byte-based or frame-based (SE_CFGSE_FRM_MODE) When operating as byte-based the frame adjustment value HSCH_MISCFRM_ADJ can be used to program the fixed number of extra bytes to add to each frame transmitted (irrespective of QoS class) in the shaper and DWRR calculations A value of 20 bytes corresponds to line-rate calculation and accommodates for 12 bytes of inter-frame gap and 8 bytes of preamble Data-rate based shaping and DWRR calculations are achieved by programming 0 bytes

Each shaper implements two burst modes By default a leaky bucket is continuously assigned new credit according to the configured shaper rate This implies that during idle periods credit is building up which allows for a burst of data when there are again data to transmit This is not convenient in an AudioVideo Bridging (AVB) environment where this behavior enforces a requirement for larger buffers in end-equipment To circumvent this each shaper can enable an AVB mode (SE_CFGSE_AVB_ENA) in which credit is only assigned during periods where the scheduler element has data to transmit and is waiting for another scheduler element to finish a transmission This AVB mode prevents the accumulation of large amount of credits

3123 Deficit Weighted Round RobinThe DWRR uses a cost-based algorithm compared to a weight-based algorithm A high cost implies a small share of the bandwidth DWRR is enabled when SE_CFGSE_DWRR_CFGgt0 and SE_CFGRR_ENA = 0 The participating inputs are then inputs 0 through SE_CFGSE_DWRR_CFG-1 Anything from 0 to 12 weighted inputs can participate

Each input is programmed with a cost (SE_DWRR_CFGDWRR_COST) A cost is a number between 1 and 32 The programmable DWRR costs determine the behavior of the DWRR algorithm The costs result in weights for each input to the scheduler element The weights are relative to one another and the resulting share of the egress bandwidth for a particular input is equal to the inputrsquos weight divided by the sum of all the inputsrsquo weights The algorithm is byte-based and takes the frame lengths into account

Costs are easily converted to weights and vice versa given the following two algorithms The following algorithms are shown with six participating inputs but can be applied to other configurations as well

Weights to Costs Given a desired set of weights (W0 W1 W2 W3 W4 W5) the costs can be calculated using the following algorithm

1 Set the cost of the queue with the smallest weight (Wsmallest) to cost 322 For any other queue Qn with weight Wn set the corresponding cost Cn to

Cn = 32 times WsmallestWnCosts to Weights Given a set of costs for all queues (C0 C1 C2 C3 C4 C5) the resulting weights can be calculated using the following algorithm

1 Set the weight of the queue with the highest cost (Chighest) to 12 For any other queue Qn with cost Cn set the corresponding weight Wn to Wn = ChighestCnCost and Weight Conversion Examples

Implement the following bandwidth distributions

bull Input 0 5 (W0 = 5)bull Input 1 10 (W1 = 10)bull Input 2 15 (W2 = 15)bull Input 3 20 (W3 = 20)bull Input 4 20 (W4 = 20)bull Input 5 30 (W5 = 30)Given the algorithm to get from weights to costs the following costs are calculated

bull C0 = 32 (Smallest weight)

bull C1 = 32lowast510 = 16bull C2 = 32515 = 1067 (rounded up to 11)bull C3 = 32520 = 8bull C4 = 32520 = 8bull C5 = 32530 = 533 (rounded down to 5)Due to the rounding off these costs result in the following bandwidth distribution which is slightly off compared to the desired distribution

bull Input 0 492bull Input 1 985bull Input 2 1432bull Input 3 1970bull Input 4 1970bull Input 5 3151

3124 Round RobinThe round robin (RR) uses a simple round robin algorithm where each participating input is served one after another RR is enabled when SE_CFGSE_DWRR_CFGgt0 and SE_CFGRR_ENA = 1 The participating inputs are then inputs 0 through SE_CFGSE_DWRR_CFG-1 Anything from 0 to 12 weighted inputs can participate

The RR algorithm is frame-based and does not take the frame lengths into account

3125 Shaping and DWRR Scheduling ExamplesThis section provides examples and additional information about the use of the egress shapers and scheduler The following assumes a scheduler element is connected to the egress queues

31251 Mixing DWRR and Shaping Examplebull Output from scheduler element is shaped down to 500 Mbpsbull Queues 7 and 6 are strict and queues 5 through 0 are weightedbull Queue 7 is shaped to 100 Mbpsbull Queue 6 is shaped to 50 Mbpsbull The following traffic distribution is desired for queue 5 through 0

Q0 5 Q1 10 Q2 15 Q3 20 Q4 20 Q5 30bull Each queue receives 125 Mbps of incoming trafficThe following table lists the DWRR configuration and the resulting egress bandwidth for the various queues

Table 103 bull Example of Mixing DWRR and Shaping

Distribution of Weighted Traffic

Configuration CostsWeights (CnWn) Result Egress Bandwidth

Q0 5 32 1 1(1+2+29+4+4+64) times (500 ndash Mbps ndash 150 Mbps) = 172 Mbps

Q6 50 = Mbps

Q7 100 = Mbps

Sum 100 500 = Mbps

31252 Strict and Work-Conserving Shaping Examplebull Output from scheduler element is shaped down to 500 Mbpsbull All queues are strict bull All queues are shaped to 50 Mbpsbull Queues 6 and 7 are work-conserving (allowed to use excess bandwidth)bull All queues receive 125 Mbps of traffic eachThe following table lists the resulting egress bandwidth for the various queues

313 RewriterThe device includes a rewriter common for all ports that determines how the egress frame is edited before transmission The rewriter performs the following editing

bull VLAN editing tagging of frames and remapping of PCP and DEIbull DSCP remarking rewriting the DSCP value in IPv4 and IPv6 frames based on classified DSCP

valuebull FCS updatingbull Precision Time Protocol time stamp updatingEach port module including the CPU port module (CPU port 11 and CPU port 12) has its own set of configuration in the rewriter Each frame is handled by the rewriter one time per destination port

Most rewriting functions in the rewriter are independent of each other and can co-exist For instance a frame can be VLAN tagged while at the same time being DSCP remarked However precision time protocol time stamp updating and DSCP remarking are mutually exclusive with the former taking precedence If an IS2 action returns any PTP actions then DSCP remarking is automatically disabled for the frame

3131 VLAN EditingThe following table lists the registers associated with VLAN editing

Table 104 bull Example of Strict and Work-Conserving Shaping

Queue Result Egress BandwidthQ0 50 Mbps

Q1 50 Mbps

Q2 50 Mbps

Q3 50 Mbps

Q4 50 Mbps

Q5 50 Mbps

Q6 75 Mbps (Gets the last 25 Mbps of the 100 Mbps in excess not used by queue 7)

Q7 125 Mbps (Gets 75 Mbps of the 100 Mbps in excess limited only by the received rate)

Sum 500 Mbps

Table 105 bull VLAN Editing Registers

Register Description ReplicationPORT_VLAN_CFG Port VLAN for egress port Used for untagged set Per port

TAG_CFG Tagging rules for port tag Per port

PORT_CFGESO_ENA Enable lookups in ES0 Per port

PCP_DEI_QOS_MAP_CFG Mapping tableMaps DP level and QoS class to new PCP and DEI values

Per port per QoS per DP

The rewriter performs five steps related to VLAN editing for each frame and destination

1 VLAN popping - Zero one or two VLAN tags are popped from the frame2 ES0 lookup - ES0 is looked up for each of the framersquos destination ports The action from ES0

controls the pushing of VLAN tags3 VLAN push decision - Deciding the number of new tags to push and which tag source to use for

each tag Tag sources are Port and ES0 (tag A and tag B)4 Constructing the VLAN tags - The new VLAN tags are constructed based on the tag sourcesrsquo

configuration5 VLAN pushing - the new VLAN tags are pushed

31311 VLAN PoppingThe rewriter initially pops the number of VLAN tags specified by the VLAN_POP_CNT parameter received with the frame from the classifier or VCAP IS1 Up to two VLAN tags can be popped The rewriter itself does not influence the number VLAN tags being popped

31312 ES0 LookupFor each of the framersquos destination ports VCAP ES0 is looked up using the ES0 key See VCAP ES0 page 92 for more information about ES0 The action from an ES0 hit is used in the following to determine the framersquos VLAN editing

31313 VLAN Push DecisionAfter popping the VLAN tags the rewriter decides whether to push zero one or two new VLAN tags to the outgoing frame according to the portrsquos tagging configuration in register TAG_CFG and the action from a potential VCAP ES0 hit The up to two tags can originate from either the port (port tag) or ES0 (ES0 tag A and ES0 tag B)

By default the port can push one tag according to the portrsquos configuration in TAG_CFG If the ES0 lookup results in an entry being hit the ES0 action can overrule the port configuration and push two tags by itself (ES0 tag A and ES0 tag B) or it can combine port tagging and ES0 tagging

The following illustration shows an overview of the available tagging options

Figure 42 bull Tagging Overview

DMAC SMAC Outer tag Inner tag EtherType Payload

(1) Port tag is controlled by REWPORTTAG_CFGTAG_CFG

Optional port tag(1)

ES0 tag ANo tag

Force port tagNo tag

ES0 tag B

The following table lists all combinations of port tagging configuration and ES0 actions that control the number of tags to push and which tag source to use (port ES0 tag A or ES0 tag B)

31314 Constructing VLAN TagsWhen pushing a VLAN tag the contents of the tag header including the TPID are highly programmable The starting point is the classified tag header coming from the analyzer containing the PCP DEI VID and

Table 106 bull Tagging Combinations

ES0_ACTION TAG_CFG Tagging actionNo ES0 hit Controls

port tagPort tag is pushed according to TAG_CFG as outer tag Available options are

Tag all frames with port tagTag all frames with port tag except if classified VID=0 or classified VID=PORT_VLANPORT_VIDTag all frames with port tag except if classified VID=0No port tag

No inner tag

PUSH_OUTER_TAG=0PUSH_INNER_TAG=0

Controls port tag

Port tag is pushed according to TAG_CFG as outer tag Available options are

No inner tag

Donrsquot care ES0 tag A is pushed as outer tagNo inner tag

Donrsquot care Port tag is pushed as outer tag This overrules port settings in TAG_CFG No inner tag

Donrsquot care No tags are pushed This overrules port settings in TAG_CFG

Controls port tag

Port tag is pushed according to TAG_CFG as outer tag The following options are available

ES0 tag B is pushed as inner tag ES0 tag B is effectively the outer tag if the port tag is not pushed

Donrsquot care ES0 tag A is pushed as outer tagES0 tag B is pushed as inner tag

Donrsquot care Port tag is pushed as outer tag This overrules port settings in TAG_CFG ES0 tag B is pushed as inner tag

Donrsquot care No outer tag is pushed This overrules port settings in TAG_CFGES0 tag B is pushed as inner tag ES0 tag B is effectively the outer tag because no outer tag is pushed

tag type For each of the fields in the resulting tag it is programmable how the value is determined For more information see ltfigure referencegt

Figure 43 bull Tag Construction (port tag ES0 tag A ES0 tag B)

The port tag ES0 tag A and ES0 tag B have individual configurations For the port tag the available tag field options are

Port tag PCP

bull Use the classified PCPbull Use the egress portrsquos port VLAN (PORT_VLANPORT_PCP)bull Map the DP level and QoS class to a new PCP value using the per-port table

PCP_DEI_QOS_MAP_CFGbull Use the QoS class directlyPort tag DEI

bull Use the classified DEIbull Use the egress portrsquos port VLAN (PORT_VLANPORT_DEI)bull Map the DP level and QoS class to a new DEI value using the per-port table

PCP_DEI_QOS_MAP_CFGbull Use the DP level directlyPort tag VID

bull Use the classified VIDbull Use the egress portrsquos port VLAN (PORT_VLANPORT_VID)Port tag TPID

bull Use Ethernet type 0x8100 (C-tag)bull Use Ethernet type 0x88A8 (S-tag)bull Use custom Ethernet type programmed in PORT_VLANPORT_TPIDbull Use custom Ethernet type programmed in PORT_VLANPORT_TPID unless the incoming tag was a

C-tag in which case Ethernet type 0x8100 is usedSimilar options for the ES0 tag A and ES0 tag B are available

ES0 tag PCP

bull Use the classified PCPbull Use ES0_ACTIONPCP_A_VAL for ES0 tag A and use ES0_ACTIONPCP_B_VAL for ES0 tag Bbull Map the DP level and QoS class to a new PCP using the per-port table PCP_DEI_QOS_MAP_CFGbull Use the QoS class directlyES0 tag DEI

bull Use the classified DEIbull Use ES0_ACTIONDEI_A_VAL for ES0 tag A and use ES0_ACTIONDEI_B_VAL for ES0 tag Bbull Map the DP level and QoS class to a new DEI using the per-port table PCP_DEI_QOS_MAP_CFGbull Use the DP level directly

PCPDEI

VIDTPID

0x8100

0x88A8

Custom

Classified(2)

Classified

Mapped (DP QoS)

QoS class

Classified

Mapped (DP QoS)

DP level

Classified + fixed(1)

(1) For port tag this is classified only(2) Use 0x8100 if classified tag type is 0x8100 otherwise custom

ES0 tag VID

bull Use the classified VID incremented with ES0_ACTIONVID_A_VAL for ES0 tag A and use the classified VID incremented with ES0_ACTIONVID_B_VAL for ES0 tag B

bull Use ES0_ACTIONVID_A_VAL for ES0 tag A and use ES0_ACTIONVID_B_VAL for ES0 tag BES0 tag TPID

C-tag in which case Ethernet type 0x8100 is used

31315 VLAN PushingIn the final VLAN editing step the VLAN tags derived from the previous steps are pushed to the frame

3132 DSCP RemarkingThe following table lists the registers associated with DSCP remarking

The rewriter can remark the DSCP value in IPv4 and IPv6 frames that is write a new DSCP value to the DSCP field in the frame

If a port is enabled for DSCP remarking (DSCP_CFGDSCP_REWR_CFG) the new DSCP value is derived by using the classified DSCP value from the analyzer (the basic classification or the VCAP IS1) in the ingress port This DSCP value can be mapped before replacing the existing value in the frame The following options are available

bull No DSCP remarking - Leave the DSCP value in the frame untouchedbull Update the DSCP value in the frame with the value received from the analyzerbull Update the DSCP value in the frame with the value received from the analyzer remapped through

DSCP_REMAP_CFG This is done independently of the value of the drop precedence levelbull Update the DSCP value in the frame with the value received from the analyzer remapped through

DSCP_REMAP_CFG or DSCP_REMAP_DP1_CFG dependent on the drop precedence level This enables one mapping for green frames and another for yellow frames so that the resulting DSCP value can reflect the color of the frame

In addition the IP checksum is updated for IPv4 frames Note that the IPv6 header does not contain a checksum As a result checksum updating does not apply for IPv6 frames

DSCP remarking is not possible for frames where PTP time stamps are also generated and is automatically disabled

3133 FCS UpdatingThe following table lists the registers associated with FCS updating

Table 107 bull DSCP Remarking Registers

Register Description ReplicationDSCP_CFG Selects how the DSCP remarking is done Per port

DSCP_REMAP_CFG Mapping table from DSCP to DSCP for DP level = 0 None

DSCP_REMAP_DP1_CFG Mapping table from DSCP to DSCP for DP level = 1 None

Table 108 bull FCS Updating Registers

Register Description ReplicationPORT_CFGFCS_UPDATE_NONCPU_CFG FCS update configuration for non-CPU

injected framesPer port

The rewriter updates a framersquos FCS when required or instructed to do so Different handling is available for frames injected by the CPU and for all other frames

For non-CPU injected frames the following update options are available

bull Never update the FCSbull Conditional update Update the FCS if the frame was modified due to PTP time stamping VLAN

tagging or DSCP remarkingbull Always update the FCSIn addition the rewriter can update the FCS for all frames injected from the CPU through the CPU injection queues in the CPU port module

bull Never update the FCSbull Always update the FCS

3134 PTP Time StampingThe following table lists the registers associated with PTP time stamping

The rewriter can do various different PTP time stamping in the egress frame

Residence time Adds the framersquos residence time through the switch to the PTP correction field (byte-offset 8)

Addsubtract Adds the framersquos Tx time to the correction field (byte-offset 8) or subtract the framersquos Rx time from the correction field

Time-of-day Samples and writes the 80-bit time-of-day into the PTP origin time stamp (byte-offset 34)

Set reserved bytes Writes the RxTime into the PTP reserved bytes (byte-offset 16)

Clear reserved bytes Writes zero into the PTP reserved bytes (byte-offset 16)

This can be done for PTP frames over IEEE8023Ethernet PTP frames over UDP over IPv4 and PTP frames over UDP over IPv6 In addition frames can be VLAN tagged The rewriter automatically finds the correct location of the PTP header in the frame

The rewriter takes the following frame properties from the analyzer as input

bull IS2 rewriter action (IS2_ACTIONREW_OP[20]) which can be either one-step two-step or originbull The framersquos Rx time stamp adjusted for IO path delays and ingress delays according to ingress

actionsbull IS2 rewriter actions for one-step PTP Addsubtract mode egress delay adjustmentbull Ingress backplane mode ANAPORTPTP_CFGPTP_BACKPLANE_MODE from the framersquos

ingress portIn addition the following egress port properties are used

bull Egress port delay (REWPORTPTP_DLY1_CFG)bull Egress backplane mode (REWPORTPTP_CFGPTP_BACKPLANE_MODE)

PORT_CFGFCS_UPDATE_CPU_ENA FCS update configuration for CPU injected frames

Per port

Table 109 bull PTP Time Stamping Registers

Register Description ReplicationREWPORTPTP_CFG PTP Configuration of egress port Per port

REWPORTPTP_DLY1_CFG Egress delay configuration Per port

Table 108 bull FCS Updating Registers (continued)

The following table shows the resulting rewriter actions for the one-step PTP action depending on the addsubtract mode and ingress and egress backplane mode settings

All actions associated with one-step or origin can be disabled per egress port through REWPORTPTP_CFGPTP_1STEP_DIS

The following table shows the resulting rewriter actions for the two-step PTP action depending on the ingress and egress backplane mode settings

All actions associated with two-step can be disabled per egress port through REWPORTPTP_CFGPTP_2STEP_DIS

Table 110 bull PTP Time Stamping for One-step PTP

PTP Action(from IS2) AddSubtract

Ingress Backplane

Egress Backplane PTP time stamp Rewriter Actions

One-step Disabled Disabled Disabled Residence time Adds framersquos residence time to PTP correction fieldEgress port delay is added to correction field if specified by IS2

One-step Disabled Disabled Enabled Sets reserved bytes Writes framersquos Rx time stamp into the reserved bytes

One-step Disabled Enabled Disabled Residence time Adds framersquos residence time to PTP correction fieldEgress port delay is added to correction field if specified by IS2Clear reserved bytes

One-step Disabled Enabled Enabled Does not apply

One-step Enabled Disabled Disabled Residence time Adds framersquos residence time to PTP correction field Egress port delay is added to correction field if specified by IS2

One-step Enabled Disabled Enabled Addsubtract Subtracts framersquos Rx time stamp from PTP correction field

One-step Enabled Enabled Disabled Addsubtract Adds framersquos Tx time stamp to PTP correction fieldEgress port delay is added to correction field if specified by IS2Clear reserved bytes

One-step Enabled Enabled Enabled Does not apply

Table 111 bull PTP Time Stamping for Two-step PTP

PTP action(from IS2)

Ingress Backplane

Two-step Disabled Disabled Saves Tx time stamp in PTP time stamp queue

Two-step Disabled Enabled Sets reserved bytes Write the framersquos Rx time stamp into the reserved bytes

Two-step Enabled Disabled Saves Tx time stamp in PTP time stamp queueClear reserved bytes

Two-step Enabled Enabled Does not apply

The following table shows the resulting rewriter actions for the origin PTP action depending on the ingress and egress backplane mode settings

The following describes each of the PTP time stamping rewriter actions

Residence Time The framersquos residence time is calculated as Tx time stamp - Rx time stamp For information about how the Rx and Tx time stamps are derived see Rx and Tx Time Stamps page 21 The residence time is adjusted for an optional egress delay (REWPORTPTP_DLY1_CFG) enabled through IS2_ACTIONREW_OP[5] = 1 The resulting residence time is added to the correction field value in the PTP header The result is written back into the frame

Addsubtract Add the framersquos Tx time to the correction field or subtract the framersquos Rx time from the correction field This is used in backplane applications This mode requires a rollover protection mode to handle the situation where the nanosecond counter rolls over during the backplane transfer The rollover protection mode is configured in SYSPTP_CFGPTP_CF_ROLL_MODE and must be the same in both the ingress and the egress backplane unit

Time-of-Day The time-of-day consists of a 48-bit seconds part and a 32-bit nanoseconds part The current time-of-day is derived by sampling the time-of-day seconds counter (SYSPTP_TOD_LSB SYSPTP_TOD_MSB) and the nanoseconds counter (Tx time stamp) at the time of the framersquos departure from the switch Note that the time-of-day value is adjusted for IO path delay For more information see Rx and Tx Time Stamps page 21

Set Reserved Bytes This action write the framersquos Rx time stamp into the reserved bytes of the PTP header

Clear Reserved Bytes This action clears the reserved byte of the PTP header by setting the four bytes to 0

In addition the UDP checksum is handled for IPv4 frames and IPv6 frames after any PTP modifications by the rewriter For IPv4 the UDP checksum is cleared while for IPv6 the two bytes immediately following the PTP header are updated so that the UDP checksum remains correct

All internal calculations on nanoseconds time stamps are signed and use 48 bits of precision When enabling a port for backplane mode it is possible specify the number of bits to use from the 48-bit counter This is specified in SYSPTP_CFGPTP_STAMP_WID This means that the time stamp values carried in the reserved bytes or in the correction field in the PTP header can be for instance 30 bits instead of the default 32 bits

3135 Special Rewriter OperationsVCAP IS2 can trigger a special rewriter operation through IS2_ACTIONREW_OP[30] = 8 (rewriter special) where the framersquos MAC addresses are swapped

bull The original destination MAC address becomes the new source MAC addressbull The original source MAC address becomes the new destination MAC addressBit 40 is cleared in the new source MAC address to prevent the possibility of transmitting an illegal frame with a multicast source MAC address

Table 112 bull PTP Time Stamping for Origin PTP

PTP Action(from IS2)

Ingress Backplane

Origin Disabled Disabled Time-of-day Write the time-of-day into the PTP origin time stamp field

Origin Disabled Enabled None

Origin Enabled Disabled Time-of-day Write the time-of-day into the PTP origin time stamp field

Origin Enabled Enabled Does not apply

The swapping of MAC addresses is useful when implementing a general hairpinning functionality where an IS2-identified flow is hardware looped back to the source port while swapping the MAC addresses

In addition VCAP IS2 can trigger replacement of the source MAC address by setting IS2_ACTIONSMAC_REPLACE_ENA = 1 The new source MAC address is configurable per egress port through SYSREW_MAC_LOW_CFG and SYSREW_MAC_HIGH_CFG

The operations of swapping of MAC addresses and replacing the source MAC address are mutually exclusive and must not be enabled at the same time

314 CPU Port ModuleThe CPU port module connects the switch core to the CPU system so that frames can be injected from or extracted to the CPU It is also possible to use a regular front port as a CPU port This is known as a Node Processor Interface (NPI)

The following illustration shows how the switch core interfaces to the CPU system through the CPU port module for injection and extraction of frames

Figure 44 bull CPU Injection and Extraction

Switch CoreFDMA VRAP

Engine

CPUPort 11

CPUPort 12

Analyzer

Switch port 11 QoS class 0-7

Injection

CPUPort 11

CPUPort 12

Extraction Group 0

Extraction Group 1

FDMA VRAP Engine

StrictRound robinWeighted(Scheduler Element configuration)

Extraction

Extraction header included(SYSPORT_MODEINCL_XTR_HDR)

Injection header included (SYSPORT_MODEINCL_INJ_HDR)

Queue to port mapping(QSYSCPU_GROUP_MAP)

CPU extraction queues

Switch port 11

Rewriter Rewriter

Fixed per channel

Switch port 11

InjectionGroup 0

Injection Group 1

Register access

3141 Frame ExtractionThe following table lists the registers associated with frame extraction

In the switch core CPU extracted frames are forwarded to one of the eight CPU extraction queues Each of these queues is mapped to one of two CPU ports (port 11 and port 12) through QSYSCPU_GROUP_MAP For each CPU port there is a scheduler working either in strict mode or round robin which selects between the CPU extraction queues mapped to the same CPU port In strict mode higher queue numbers are preferred over smaller queue numbers In round robin all queue are serviced one after another

The two CPU ports contain the same rewriter as regular front ports The rewriter modifies the frames before sending them to the CPU In particular the rewriter inserts an extraction header (SYSPORT_MODEINCL_XTR_HDR) which contains relevant side band information about the frame such as the framersquos classification result (VLAN tag information DSCP QoS class) ingress time stamp and the reason for sending the frame to the CPU For more information about the rewriter see Rewriter page 133

The device CPU contains the functionality for reading out the frames This can be done through the frame DMA or regular register access The Versatile Register Access Protocol (VRAP) Engine can also be attached to one of the CPU extraction groups This allows an external device to access internal registers through Ethernet frames

The following table lists the contents of the CPU extraction header

Table 113 bull Frame Extraction Registers

Register Description ReplicationQSYSCPU_GROUP_MAP Configuration of mapping of extraction

queues to CPU portsNone

SYSPORT_MODEINCL_XTR_HDR Enables insertion of extraction header Configures formatting of outgoing frames

Per CPU port (ports 11 and 12)

Table 114 bull CPU Extraction Header

Field Bit Width DescriptionRESERVED 127 1 Reserved

REW_OP 117 9 Rewriter operation commandREW_OP[20] = 3 implies two-step PTP where REW_OP[83] contains the PTP time stamp identifier Other settings do not apply

REW_VAL 85 32 This field contains the Rx time when the frame was received

LLEN 79 6 Frame length in bytes 60 times WLEN + LLEN ndash 80

WLEN 71 8 See LLEN

RESERVED 47 24 Reserved

SRC_PORT 43 4 The port number where the frame was received (0-11)

ACL_ID 37 6 If ACL_HIT is set this value is the combined ACL_ID action of the rules hit in IS2

3142 Frame InjectionThe following table lists the registers associated with frame injection

The CPU injects frames through the two CPU injection groups that are independent of each other The injection groups connect to the two CPU ports (port 11 and port 12) in the CPU port module In CPU port module each of the two CPU ports have dedicated access to the switch core Inside the switch core all CPU injected frames are seen as coming from CPU port (port 11) This implies that both CPU injection groups consume memory resources from the shared queue system for port 11 and that analyzer configuration for port 11 are applied to all frames

In the switch core the CPU port can be preferred over other ingress ports when transferring frames to egress queues by enabling precedence of the CPU port (QSYSEQ_PREFER_SRC)

SFLOW_ID 32 4 sFlow sampling ID 0-11 Frame was sFlow sampled by a Tx sampler on port given by SFLOW_ID12 Frame was sFlow sampled by an Rx sampler on port given by SRC_PORT13-14 Reserved15 Frame was not sFlow sampled

ACL_HIT 31 1 Set if frame has hit a rule in IS2 which copies the frame to the CPU (IS2 actions CPU_COPY_ENA or HIT_ME_ONCE)

DP 30 1 The framersquos drop precedence (DP) level after policing

LRN_FLAGS 28 2 The source MAC address learning action triggered by the frame 0 No learning1 Learning of a new entry2 Updating of an already learned unlocked entry3 Updating of an already learned locked entry

CPUQ 20 8 CPU extraction queue mask (one bit per CPU extraction queue) Each bit set implies the frame was subjected to CPU forwarding to the specific queue

QOS_CLASS 17 3 The framersquos classified QoS class

TAG_TYPE 16 1 The tag informationrsquos associated Tag Protocol Identifier (TPID) The definitions are0 C-tag EtherType = 0x81001 S-tag EtherType = 0x88A8 or custom value

PCP 13 3 The framersquos classified PCP

DEI 12 1 The framersquos classified DEI

VID 0 12 The framersquos classified VID

Table 115 bull Frame Injection Registers

Register Description ReplicationSYSPORT_MODEINCL_INJ_HDR Enable parsing of injection header

Configures formatting of incoming framesPer CPU port (ports 11 and 12)

QSYSEQ_PREFER_SRC Enable preferred arbitration of the CPU port (port 11) over front ports

CPU port (port 11 only)

Table 114 bull CPU Extraction Header (continued)

Field Bit Width Description

The first 20 bytes of a frame written to a CPU injection group is an injection header containing relevant side band information about how the frame must be processed by the switch core The CPU ports must be enabled to expect the CPU injection header (SYSPORT_MODEINCL_INJ_HDR)

On a per-frame basis the CPU controls whether frames injected through the CPU port module are processed by the analyzer If the frame is processed by the analyzer it is sent through the processing steps to calculate the destination ports for the frame If analyzer processing is not selected the CPU can specify the destination port set and related information to fully control the forwarding of the frame For more information about the analyzerrsquos processing steps see Forwarding Engine page 109

The contents of the CPU injection header is listed in the following table

Table 116 bull CPU Injection Header

Field Bit Width DescriptionBYPASS 127 1 When this bit is set the analyzer processing is skipped for this

frame The destination set is specified in DEST and CPU_QUEUE Forwarding uses the QOS_CLASS and the rewriter uses the tag information (POP_CNT TAG_TYPE PCP DEI VID) for rewriting actionsWhen this bit is cleared the analyzer determines the destination set QoS class and VLAN classification for the frame through normal frame processing including lookups in the MAC table and VLAN table

MASQ 126 1 When this bit is set masquerading is enabled The classifier analyzer and queue system handle the frame as if it was received by the ingress port specified in MASQ_PORT This field overloads the REW_OP field and should only be used when BYPASS = 0

MASQ_PORT 122 4 Masquerading port used when MASQ is set This field overloads the REW_OP field and should only be used when BYPASS = 0

REW_OP 126 1 If set framersquos source MAC address is replaced with source MAC address configured per egress port (SYSREW_MAC_LOW_CFG SYSREW_MAC_HIGH_CFG)

REW_OP 117 9 Rewriter operation command Used when BYPASS = 1 The following commands are supportedNo operation REW_OP[30] = 0No operationSpecial Rewrite REW_OP[30] = 8Swap the MAC addresses and clear bit 40 in the new SMAC when transmitting the frameDSCP remark REW_OP[20] = 1REW_OP[83] contains the framersquos classified DSCP to be used at egress for remarkingOne-step PTP REW_OP[20] = 2The framersquos residence time is added to the correction field in the PTP frame The following sub-commands can be encodedREW_OP[5] Set if egress delay must be added to residence timeTwo-step PTP REW_OP[20] = 3The framersquos departure time stamp is saved in the time stamp FIFO queue at egress REW_OP[83] contains the PTP time stamp identifier used by the time stamp FIFO queue Identifiers 0 through 3 are pre-allocated to be used by CPU injected framesOrigin PTP REW_OP[20] = 5The time of day at the frames departure time is written into the origintime stamp field in the PTP frameUnspecified bits must be set to 0

REW_VAL 85 32 By default this field contains the framersquos receive time stamp For injected frames this can be set by the CPU to indicate when the injection started The rewriter can then calculate a residence time based on REW_VAL and the framersquos transmission time stamp

If TFRM_TIMER gt 0 then REW_VAL contains the transmission slot for periodic frame transmission (0 through 1023)

DEST 56 12 This is the destination set for the frame DEST[11] is the CPU Used when BYPASS = 1

SRC_PORT 43 4 The port number where the frame was injected (0-12)

TFRM_TIMER 37 4 Selects timer for periodic transmissions (1 through 8) If TFRM_TIMER=0 then normal injection

DP 30 1 The framersquos drop precedence (DP) level after policing Used when BYPASS = 1

Table 116 bull CPU Injection Header (continued)

3143 Node Processor Interface (NPI)The following table lists the registers associated with the NPI

Any front port can be configured as an NPI through which frames can be injected from and extracted to an external CPU Only one port can be an NPI at the same time QSYSEXT_CPU_CFGEXT_CPU_PORT holds the port number of the NPI

A dual CPU system is possible where both the internal and the external CPU are active at the same time Through QSYSEXT_CPU_CFGEXT_CPUQ_MSK it is configurable to which of the eight CPU extraction queues are directed to the internal CPU and which are directed to external CPU A frame can be extracted to both the internal CPU and the external CPU if the frame is extracted for multiple reasons

Frames being extracted by the external CPU can have the CPU extraction header inserted in front of the frame (SYSPORT_MODEINCL_XTR_HDR) Similarly frames being injected into the switch core by the external CPU can have the CPU injection header inserted in front of the frame (SYSPORT_MODEINCL_INJ_HDR) In addition there three different options in terms of inserting a prefix in front of the CPU injection or extraction header The following illustration shows the different frame formats supported

POP_CNT 28 2 Number of VLAN tags that must be popped in the rewriter before adding new tags Used when BYPASS = 10 No tags must be popped1 One tag must be popped2 Two tags must be popped3 Disable all rewriting of the frame The rewriter can still update the FCS

CPUQ 20 8 CPU extraction queue mask (one bit per CPU extraction queue) Each bit set implies the frame must be forwarded by the CPU to the specific queueUsed when BYPASS = 1 and DEST[11] = 1

QOS_CLASS 17 3 The framersquos classified QoS classUsed when BYPASS = 1

TAG_TYPE 16 1 The tag informationrsquos associated Tag Protocol Identifier (TPID)Used when BYPASS = 10 C-tag EtherType = 0x81001 S-tag EtherType = 0x88A8 or custom value

PCP 13 3 The framersquos classified PCP Used when BYPASS = 1

DEI 12 1 The framersquos classified DEI Used when BYPASS = 1

VID 0 12 The framersquos classified VID Used when BYPASS = 1

Table 117 bull Node Processor Interface Registers

Register Description ReplicationQSYSEXT_CPU_CFG Configuration of the NPI port number and

configuration of which CPU extraction queues are redirected to the NPI

SYSPORT_MODEINCL_XTR_HDR Enables insertion of extraction header Per port

SYSPORT_MODEINCL_INJ_HDR Configuration of NPI ingress mode Per port

Figure 45 bull CPU Injection and Extraction Prefixes

Note that inserting a CPU extraction header in front of a frame disables all other frame modifications done in the rewriter

When injecting frames with an CPU injection header all incoming frames are expected to adhere to the configured prefix mode The following parsing of the frames takes place

bull No prefix All incoming frames are parsed as if they have a CPU injection header in front of the frame Forwarding is based on the instructions in the CPU injection header

bull Short prefix Incoming frames are checked against the expected format (start of frame must include 0x8880000A) If the prefix does not match then an error indication is set (SYSPORT_MODEINJ_HDR_ERR) Compliant frames are forwarded based on the instructions in the CPU injection header Non-compliant frames are forwarded as normal frames where the prefix and CPU injection header equaling the first 20 bytes of the frame are skipped

bull Long prefix All incoming frames are parsed as if they have a long prefix followed by the CPU injection header in front of the frame The incoming frames are checked against the expected format (start of frame must include 12 bytes of MAC addresses followed by 0x8880000A) If the prefix does not match then an error indication is set (SYSPORT_MODEINJ_HDR_ERR) Both compliant and non-compliant frames are forwarded based on the instructions in the CPU injection header

The external CPU can control forwarding of injected frames by either letting the frame analyze and forward accordingly or directly specifying the destination set This is controlled through the BYPASS field in the CPU injection header

3144 Frame Generation Engine for Periodic TransmissionsThe following table lists the registers associated with the frame generation engine

Table 118 bull Frame Generation Engine

Register Description ReplicationQSYSTFRM_MISC Configuration to cancel ongoing periodic transmissions None

QSYSTFRM_PORT_DLY_ENA Enable spaced-out transmissions when multiple periodic transmissions are scheduled at the same time

Per port

QSYSTFRM_TIMER_CFG_x Period configuration These registers configure the transmission period between frames

FF-FF-FF-FF-FF-FF48 bits

FE-FF-FF-FF-FF-FF48 bits

888016 bits

000A16 bits

CPU Extraction header128 bits

Extraction with long prefix

Extraction with short prefix

Extraction with no prefix

Original frame

Any DMAC48 bits

Any SMAC48 bits

888016 bits

000A16 bits

CPU Injection header128 bits

Injection with long prefix

888016 bits

000A16 bits

CPU Injection header128 bits Original frame

Injection with short prefix

Injection with no prefix

Original frame

888016 bits

000A16 bits

CPU Extraction header128 bits Original frame

Start-of-frame

The device contains a frame generation engine that can periodically transmit frames on a port with a programmable transmission period The transmission period can be as low as 200 ns which implies wire-speed back-to-back transmissions or as high as several minutes Up to 1024 periodic transmissions can coexist with up to eight different transmission periods

To set up a periodic transmission the CPU must inject a setup frame using the following settings in the injection header

bull REW_VAL set to the selected transmission slot (0 through 1023)bull ACL_ID set to the selected timer (1 through 8) The transmission period is programmed in steps of

1982 ns in TFRM_TIMER_CFG_x where x = ACL_ID Note that injecting a frame with ACL_ID gt 0 effectively enables the periodic transmissions To inject a normal frame ACL_ID must be set to 0

bull BYPASS set to 1bull DEST set to the Tx port to which the periodic transmission applies Only one Tx port per

transmission is possiblebull Other fields in the injection header are applicable the same way as for normal injections Note that

the periodic transmissions are subject to normal rewriter operations before being transmitted on the Tx port For more information see Rewriter page 133

After the injection the setup frame is placed into the selected transmission slot and it is periodically transmitted using the transmission period defined by the selected timer Every time the transmission period has passed since the last transmission the frame is scheduled for a new transmission on the associated port The periodic frame transmission takes precedence over other transmissions on the port and as a consequence the frame is transmitted immediately after a potential ongoing transmission has ended

If multiple periodic transmissions on a Tx port use the same timer multiple frames are scheduled for transmission at the same time when the period has passed By default these frames are transmitted in a burst back-to-back However it is also possible to space-out these frames over time and thereby allowing the normal data traffic to be interleaved the periodic transmissions If the spacing is enabled (TFRM_PORT_DLY) timer 8 defines the period between frames in the burst

Periodic transmissions are cancelled again by programming the slot number in TFRM_MISCTIMED_CANCEL_SLOT and setting TFRM_MISCTIMED_CANCEL_1SHOT This removes the injected frame from the transmission slot

Transmission slots 0 through 15 support any transmission periods including back-to-back transmissions while slots 16 through 1023 support transmission periods larger than 30 micros

Frames transmitted from the frame generation engine are counted by the Tx counters just like normal frames using the QoS class specified in the injection header by the setup frame

315 VRAP EngineThe Versatile Register Access Protocol (VRAP) engine allows external equipment to access registers in the device through any of the Ethernet portrsquos on the device The VRAP engine interprets incoming VRAP requests and executes read write and read-modify-write commands contained in the frames The results of the register accesses are reported back to the transmitter through automatically generated VRAP response frames

The device supports version 1 of VRAP All VRAP frames both requests and responses are standard Ethernet frames All VRAP protocol fields are big-endian formatted

The registers listed in the following table control the VRAP engine

Table 119 bull VRAP Registers

TargetRegister_groupRegisterfield Description ReplicationANACPU_FWD_CFGCPU_VRAP_REDIR_ENA Enable redirection of VRAP frames

to CPUPer port

ANACPUQ_CFG2CPUQ_VRAP Configure the CPU extraction queue for VRAP frames

The VRAP engine processes incoming VRAP frames that are redirected to the VRAP CPU extraction queue by the basic classifier For more information about the VRAP filter in the classifier see CPU Forwarding Determination page 58

The VRAP engine is enabled by allocating one of the two CPU ports as a dedicated VRAP CPU port (DEVCPU_QSXTR_GRP_CFGMODE and DEVCPU_QSINJ_GRPMODE) The VRAP CPU extraction queue (ANACPUQ_CFG2CPUQ_VRAP) must be mapped as the only CPU extraction queue to the VRAP CPU port (QSYSCPU_GROUP_MAPCPU_GROUP_MAP) In addition the VRAP CPU port must disable the use of CPU injection and CPU extraction headers (SYSPORT_MODEINCL_INJ_HDR and SYSPORT_MODEINCL_XTR_HDR)

The complete VRAP functionality can be enabled automatically at chip startup by the use of special chip boot modes For more information see VCore-Ie Configurations page 159

The following describes the VRAP frame formats

3151 VRAP Request Frame FormatThe following illustration shows the format of a VRAP request frame

Figure 46 bull VRAP Request Frame Format

VRAP request frames can optionally be VLAN tagged with one VLAN tag The EtherType = 0x8880 and the Ethernet Protocol Identifier (EPID) = 0x0004 identify the VRAP frames The subsequent VRAP header is used in both request and response frames

The VRAP commands included in the request frame are the actual register access commands The VRAP engine supports the following five VRAP commands

bull READ Returns the 32-bit contents of any register in the devicebull WRITE Writes a 32-bit value to any register in the devicebull READ-MODIFY-WRITE Does readmodifywrite of any 32-bit register in the devicebull IDLE Does not access registers but is useful for padding and identification purposesbull PAUSE Does not access registers but causes the VRAP engine to pause between register accessEach of the VRAP commands are described in the following sections Each VRAP request frame can contain multiple VRAP commands Commands are processed sequentially starting with VRAP command 1 2 and so on For more information see ltfigure referencegt There are no restrictions on the order or number of commands in the frame

QSYSCPU_GROUP_MAPCPU_GROUP_MAP Map VRAP CPU extraction queue to a CPU port One CPU port must be reserved for VRAP frames

DEVCPU_QSXTR_GRP_CFGMODE Enable VRAP mode for reserved CPU port

Per CPU port

DEVCPU_QSINJ_GRP_CFGMODE Enable VRAP mode injection for reserved CPU port

Per CPU port

SYSPORT_MODEINCL_INJ_HDR The injection header is not present for VRAP response frames

Per port

SYSPORT_MODEINCL_XTR_HDR The extraction header is not present for redirected VRAP frames

Per port

DEVCPU_GCBVRAP_ACCESS_STAT VRAP access status None

Table 119 bull VRAP Registers (continued)

TargetRegister_groupRegisterfield Description Replication

Any valid DMAC 0x8880

Any valid SMAC

0x0004

EtherType EPID

Valid FCS

VRAP Commands

16 bits16 bits48 bits48 bits 32 bitsvariable length

VRAP HDR (Request)

32 bits

3152 VRAP Response Frame FormatHaving processed a VRAP request frame by executing the register access commands contained in the frame the VRAP engine generates a VRAP response frame The response frame uses the swapped DMAC and SMAC addresses in the VRAP request frame and it is transmitted on port where the VRAP request frame was received If the DMAC in the VRAP request frame is a multicast DMAC then bit 40 is cleared before using the DMAC as the SMAC in the VRAP response frame The results of the VRAP commands are inserted into the response frame in the same order as the VRAP commands were processed

The following illustration shows the format of a VRAP response frame

Figure 47 bull VRAP Response Frame Format

The VRAP response frame follows the VRAP request frame in terms of VLAN tagging If the VRAP request was tagged the VRAP response is also tagged using the same VLAN

Only the READ and IDLE commands require data to be returned to the transmitter of the VRAP request frame However even if the VRAP request frame does not contain READ and IDLE commands a VRAP response frame is generated with enough padding data (zeros) to fulfill the minimum transfer unit size

3153 VRAP Header FormatBoth VRAP request and VRAP response frames contain a 32-bit VRAP header The VRAP header is used to identify the protocol version and to differentiate between VRAP requests and VRAP response frames The device supports VRAP version 1 The following illustration shows the VRAP header

Figure 48 bull VRAP Header Format

A valid VRAP request frame must use Version = 1 and FlagsR = 1 Frames with an invalid VRAP header are discarded and not processed by the VRAP engine

3154 VRAP READ CommandThe VRAP READ command returns the contents of any 32-bit register inside the device The 32-bit read-data result is put into the VRAP response frame

READ and IDLE resultsSMAC from

VRAP request frame 0x8880

DMACDMAC from VRAP request frame

0x0004

EtherType EPID

Valid FCS

VRAP HDR(Response)

32 bits

Version

4 bits

Flags Reserved

4 bits 24 bits

VersionSet to 0x1 in VRAP response framesVRAP request frames are ignored if Version ltgt 1

Flags4 bits are used for Flags Only one flag is defined

R 0=Request 1=ResponseRsv Set to 0 in VRAP response frames and ignored in VRAP request frames

ReservedSet to 0 in VRAP response frames and ignored in VRAP request frames

31 28 27 24 23 0

The READ command is 4 bytes wide and consists of one 32-bit address field which is 32-bit aligned The 2 least significant bits of the address set to 01 The following illustration shows the request command and the associated response result

Figure 49 bull READ Command

3155 VRAP WRITE CommandThe WRITE command writes a 32-bit value to any register inside the device

The WRITE command is 8 bytes wide and consists of one 32-bit address field which is 32-bit aligned The two least significant bits of the address set to 10 followed by one 32-bit write-data field The following illustration shows the command

Figure 50 bull WRITE Command

3156 VRAP READ-MODIFY-WRITE CommandThe READ-MODIFY-WRITE command does readmodifywrite-back on any 32-bit register inside the device

The READ-MODIFY-WRITE command is 12 bytes wide and consists of one 32-bit address field which is 32-bit aligned The two least significant bits of the address set to 11 followed by one 32-bit write-data field followed by one 32-bit overwrite-mask field For bits set in the overwrite mask the corresponding bits in the write data field are written to the register while bits cleared in the overwrite mask are untouched when writing to the register The following figure shows the command

Figure 51 bull READ-MODIFY-WRITE Command

3157 VRAP IDLE CommandThe IDLE command does not access registers in the device Instead it just copies itself (the entire command) into the VRAP response This can be used for padding to fulfill the minimum transmission unit size or an external CPU can use it to insert a unique code into each VRAP request frame so that it can separate different replies from each other

The IDLE command is 4 bytes wide and consists of one 32-bit code word with the four least significant bits of the code word set to 0000 The following illustration depicts the request command and the associated response

Figure 52 bull IDLE Command

Register address bits 312

Request

32 bits

Register read data

Response

32 bits

Register write data10

32 bits

Request

32 bits

Request

Overwrite mask

32 bits

Any 28-bit value

Request

32 bits

Copy of value

Response

32 bits

3158 VRAP PAUSE CommandThe PAUSE command does not access registers in the device Instead it causes the VRAP engine to enter a wait state and remain there until the pause time has expired This can be used to ensure sufficient delay between VRAP commands when this is needed

The PAUSE command is 4 bytes wide and consists of one 32-bit code word with the four least significant bits of the code word set to 0100 The wait time is controlled by the 28 most significant bits of the wait command The time unit is 1 us The following illustration depicts the PAUSE command

Figure 53 bull PAUSE Command

316 Layer 1 TimingThere are eight recovered clocks four outputs that provide timing sources for external timing circuitry in redundant timing implementations and four internal clocks for the timing-recovery circuit The following tables list the registers and pins associated with Layer 1 timing

It is possible to recover receive timing from any 101001000 Mbps and 25 Gbps data streams into the device

The recovered clock outputs have individual divider configuration (through SYNC_ETH_CFGSEL_RCVRD_CLK_DIV) to allow division of SerDes receive frequency by 1 2 4 5 8 16 or 25

The recovered clocks are single-ended outputs and the suggested divider settings in the following tables are selected to make sure to not output too high a frequency through the input and outputs

The four CuPHY ports share two recovered clocks In table Table 122 page 153 the two clock resources are called clk and can take the value 0 or 1 The CLK_SRC_SEL0 and CLK_SRC_SEL1 fields are

Table 120 bull Layer 1 Timing Configuration Registers

Register DescriptionHSIOSYNC_ETH_CFG Configures recovered clocks Replicated per recovered clock

HSIOSYNC_ETH_PLL_CFG Additional PLL recovered clock configuration Replicated per recovered clock

HSIOPLL5G_CFG3 Enables high speed clock output

PHYPHY_GPPHY_RCVD_CLK0_CTRL Configures PHY recovered clock 0

Table 121 bull Layer 1 Timing Recovered Clock Pins

Pin Name IO DescriptionRCVRD_CLK0 O Recovered clock output configured by SYNC_ETH_CFG[0]

This is an overlaid function on GPIO

RCVRD_CLK1 O Recovered clock output configured by SYNC_ETH_CFG[1] This is an overlaid function on GPIO

CLKOUT O PLL high speed clock output

Pause value (micros)

Request

32 bits

programmed with the number of the CuPHY that provides the recovered clock CuPHYcan take the value 0 through 3

The frequency of the PLL can be used as recovered clock The following table shows the configurations

The recovered clock from the PLL can also be sent directly out on the differential high-speed CLKOUT output The recovered clock frequency must be set to copy the switch core using HSIOPLL5G_CFG3CLKOUT_SEL

It is possible to automatically squelch the clock output when the device detects a loss of signal on an incoming data stream This can be used for failover in external timing recovery solutions

The following table lists how to configure squelch for possible recovered clock sources (configured in SYNC_ETH_CFG[n]SEL_RCVRD_CLK_SRC)

When squelching the clock it stops when it detects loss of signal (or PLL lock) The clock stops on either high or low level

The auto squelch function is not supported when 100 Mbit operation on SerDes so in this mode the auto squelch function must be disabled

Table 122 bull Recovered Clock Settings for 1 Gbps and Lower

Interface Output Frequency Register Settings for Output nCuPHYclk 0-1

3125 MHz SYNC_ETH_CFG[n]RCVRD_CLK_ENA=1 SYNC_ETH_CFG[n]SEL_RCVRD_CLK_DIV=1SYNC_ETH_CFG[n]SEL_RCVRD_CLK_SRC=clkPHY_RCVD_CLK[clk]_CTRLRCVD_CLK[clk]_ENA=1PHY_RCVD_CLK[clk]_CTRLCLK_SRC_SEL[clk]=(CuPHY)PHY_RCVD_CLK[clk]_CTRLCLK_FREQ_SEL[clk]=1 andPHY_RCVD_CLK[clk]_CTRLCLK_SEL_PHY[clk]=1

SerDes 0-8

3125 MHz SYNC_ETH_CFG[n]RCVRD_CLK_ENA=1 SYNC_ETH_CFG[n]SEL_RCVRD_CLK_DIV=1 and SYNC_ETH_CFG[n]SEL_RCVRD_CLK_SRC=(SerDes+2)

Table 123 bull Recovered Clock Settings for 25 Gbps

Interface Output Frequency Register Settings for Output nSerDes 7-8

3125 MHz SYNC_ETH_CFG[n]RCVRD_CLK_ENA=1 SYNC_ETH_CFG[n]SEL_RCVRD_CLK_DIV=4 and SYNC_ETH_CFG[n]SEL_RCVRD_CLK_SRC=(Serdes + 2)

Table 124 bull Recovered Clock Settings for PLL

PLL Output Frequency Register Settings for Output nPLL 3125 MHz SYNC_ETH_CFG[n]RCVRD_CLK_ENA=1

SYNC_ETH_CFG[n]SEL_RCVRD_CLK_DIV=1 and SYNC_ETH_CFG[n]SEL_RCVRD_CLK_SRC=11

Table 125 bull Squelch Configuration for Sources

SRC Associated Squelch Configuration0-5 Set SERDES1G_COMMON_CFGSE_AUTO_SQUELCH_ENA in SD macro to enable

squelch when receive signal is lost SD1G macro index is (SRC)

6-8 Set SERDES6G_COMMON_CFGSE_AUTO_SQUELCH_ENA in SD macro to enable squelch when receive signal is lost SD6G macro-index is (SRC-6)

317 Hardware Time StampingHardware time stamping provides nanosecond-accurate frame arrival and departure time stamps which are used to obtain high precision timing synchronization and timing distribution

All frames are Rx time stamped on arrival with a 48-bit time stamp value using a hardware timer (time stamper) that is implemented in the Media Access Control (MAC) block The Rx time stamper provides high time stamp accuracy relative to actual arrival time of the first byte of the frame from the PHY device Within the VCAP IS2 it is decided if the frame and associated Rx time stamp must be redirected or copied to CPU for processing The frame is forwarded as normal otherwise

The VCAP IS2 also decides if a Tx time stamp must be triggered for a frame Given the Rx and Tx time stamps the framersquos residence time inside the switch is calculated The residence time can be stored in a time stamp queue for the CPU to access (two-step time stamping) or the residence time can be used to update the residence time field inside Precision Time Protocol frames (one-step time stamping)

The Tx time stamper is located at the transmit side of the MAC block as close to the PHY device as possible and provides high accuracy of time stamp relative to when the first byte of the frame is actually transmitted to the PHY

The device also implements a time of day counter with nanosecond-accuracy The time of day counter is derived from a one-second timer The one-second timer generates a pulse per second and is either derived from an adjusted system clock or from external timing equipment

3171 Time Stamp ClassificationFrames requiring Rx or Tx time stamping are identified by VCAP IS2 The IS2 action that triggers time stamping is REW_OP[20] with the following options

bull One-step time stamping (REW_OP[20] = 2) which implies adding the framersquos residence time to the correction field

bull Two-step time stamping (REW_OP[20] = 3) which implies saving the framersquos Tx time in a time stamp queue

bull Origin time stamping (REW_OP[20] = 5) which implies writing the time of day into the origintime stamp field

IS2 can be configured to identify the following frame formats from IEEE 1588-2008

bull Transport of PTP over UDP over IPv4bull Transport of PTP over UDP over IPv6Transport of PTP over IEEE 8023Ethernet

3172 Time of Day GenerationThe DEVCPU has connection to four GPIOs to be used for 1588 synchronization shown in the following illustration

Figure 54 bull Timing Distribution

Each block using timing has a TimeOfDay instance included These modules let time pass according to an incoming delta request instructing it to add the nominal clock period in nanoseconds (+0+1ndash1) for each system clock cycle This is controlled by a deltaT function in the DEVCPU which can be configured to do regular adjustments to the time by adding a single nanosecond more or less at specified intervals The absT function in the DEVCPU can set the full TOD time in the system This is controlled by the LoadStore controllers

The DEVCPU includes four LoadStore controllers each using a designated GPIO pin on the GPIO interface LoadStore controller 0 uses PTP_0 pin LoadStore controller 1 uses PTP_1 pin and so forth Before using the LoadStore controller the VCore-III CPU must enable the overlaid functions for the appropriate GPIO pins For more information see GPIO Overlaid Functions page 204

Each controller has CPU accessible registers with the full time of day set and can be configured to load these into the TimeOfDay instances or to store the current values from them The operation can be done on a detected edge on the associated pin or immediately The GPIO pin can also generate a clock with configurable high and low periods set in nanoseconds using the TimeOfDay watches or it can generate a pulse at a configured time with a configurable duration and polarity

Table 126 bull LoadStore Controller

Pin Control Field FunctionAction Load Load TOD_SEC and TOD_NSEC through the absTime bus

Delta Add configured nsec to the current time of day (absT)Store Store the current TOD_SEC and TOD_NSECClock Generate a clock or a pulse on the pin

Sync Execute the loadstore on incoming edge if action is LOAD or STOREGenerate a pulse instead of clock if action is CLOCK

Inverse polarity Falling edges are detectedgenerated

TOD_sec The 48-bit seconds of a time of day set to be loaded or stored

TOD_nsec The 30-bit nanoseconds of a time of day set to be loaded or stored

DeltaTgen

Adjuster

LoadStore CtrlGPIO AbsTgen

LoadStore CtrlLoadStore CtrlLoadStore Ctrl load

TimeOfDay

TimeOfDay TimeOfDayo o o

Four controllers configured for- Load absolute time- Load signed delta time- Store absolute time- Generate pulse or clock on pin

Loadstore can be done on incoming edge or immediately

sec (48 bits) nsec (30 bits)nsf (32 bits)

Analyzer Rewriter Port Modules(only NSF in port module)

In addition the load operation can load a delta to the current time This is done by executing a LOAD action but using the DELTA command

Each operation generates an interrupt when executed For the clock action the interrupt is generated when the output switches to the active level The interrupts from each controller can be masked and monitored by the interrupt controller in the ICPU_CFG register target

The four controllers are completely equal in their capabilities

3173 Hardware Time Stamping ModuleThis section explains the functions of the hardware time stamping module The following table lists the registers associated with the hardware time stamping module

Each port module contains a hardware time stamping module that measures arrival and departure times based on the master timer For information about how the Rx and Tx time stamps are derived see Rx and Tx Time Stamps page 21

31731 Two-Step Time StampingTwo-step time stamping is performed if the IS2 rewriter action is two-step (IS2_ACTIONREW_OP[20] = 3) This action can be applied to any frame also non-PTP frames because the frame itself is not modified The framersquos Tx time stamp is stored in a time stamp FIFO queue which the CPU can access (SYSPTP_STATUS) The time stamp is common for all egress ports and can contain up to 128 time stamps Each entry in the time stamp queue contains the following fields

bull SYSPTP_STATUSPTP_MESS_VLD A 1-bit valid bit meaning the entry is ready for readingbull SYSPTP_STATUSPTP_MESS_ID A 6-bit time stamp identifier A unique time stamp identifier is

assigned to each frame for which one or more Tx time stamps are generated The time stamp identifier is also available in the CPU extraction header for frames extracted to the CPU The time stamp identifier overloads the DSCP value in the CPU extraction header For more information about the CPU extraction header see Table 114 page 142 By providing the time stamp identifier in both the time stamp queue and in the extracted frames the CPU can correlate which time stamps belong to which frames Note that time stamp identifier value 63 implies that no free identifier could be assigned to the frame The time stamp entry can therefore not be trusted

bull SYSPTP_STATUSPTP_MESS_TXPORT The port number where the frame is transmitted When transmitting a frame on multiple ports there are generated multiple entries in the time stamp queue Each entry uses the same time stamp identifier but with different Tx port numbers

bull SYSPTP_TXSTAMP The framersquos Tx time stampThe time stamp queue is a simple FIFO that can be read by the CPU The time stamp queue provides the following handles for reading

Waveform high Number of nanoseconds in the high period for generated clocksDuration of pulse for generated pulse

Waveform_low Number of nanoseconds in the low period for generated clocksDelay from TOD_ns = 0 for generated pulse

Table 127 bull Hardware Time Stamping Registers

Register Description ReplicationSYSPTP_TXSTAMP time stamp value in time stamp queue None

SYSPTP_NXT Advancing the time stamp queue None

SYSPTP_STATUS time stamp queue status and entry data None

ANAPTP_ID_HIGH Release of time stamp identifiers values 32 through 63 None

ANAPTP_ID_LOW Release of time stamp identifiers values 0 through 31 None

Table 126 bull LoadStore Controller (continued)

Pin Control Field Function

bull Overflow of the queue is signaled through SYSPTP_STATUSPTP_OVFL Overflow implies that one or more time stamps could not be enqueued due to all 128 entries being in use time stamps not enqueued are lost

bull The head-of-line entry is read through SYSPTP_STATUS and SYSPTP_TXSTAMP bull Writing to the one-shot register SYSPTP_NXT removes the current head-of-line entry and

advances the pointer to the next entry in the time stamp queueWhen two-step Tx time stamping is performed for a frame destined for the CPU extraction queues no entry in the time stamp FIFO queue is made The framersquos Rx time stamp is available through the CPU extraction header

The time stamp identifiers can take values between 0 to 63 Value 63 implies that all values 0-62 are in use Values 0 ndash 3 are pre-assigned to the CPU to be used for injection of frames The remaining values are assigned by the analyzer to frames requesting time stamping through the VCAP IS2 action The assigned values must be released again by the CPU by writing to the corresponding bit in ANAPTP_ID_HIGH (values 32 through 63) or ANAPTP_ID_LOW (values 0 through 31) The CPU releases a time stamp identifier when it has read the anticipated time stamp entries from the time stamp queue Note that multicasted frames generate a time stamp entry per egress port using the same time stamp identifier Each of these entries must be read before the time stamp identifier is released

Two-step time stamping can be disabled per egress port using REWPORTPTP_CFGPTP_2STEP_DIS This setting overrules the IS2 action

3174 Configuring IO DelaysAfter a valid link is established and detected by the involved PCS logic the IO delays from the internal time stamping points to the serial line must be configured The delays are both mode-specific and interface-specific depending on the core clock frequency

Ingress barrel shifter states that in 1G mode the Rx delays must be added 08 ns times the value of PCS1G_LINK_STATUSDELAY_VAR to adjust for barrel shifting state after link establishment In 25G mode the multiplier is 032 ns In 100FX mode the Rx delays must be subtracted 08 ns times the value of PCS_FX100_STATUSEDGE_POS_PTP to adjust for detected data phase

The Rx and Tx delay values for the different ports and modes are automatically configured in the software API

318 Clocking and ResetThe reference clock for the PLL (REFCLK_PN) is either differential or single-ended The frequency can be 25 MHz 125 MHz 15625 MHz or 250 MHz The PLL must be configured for the appropriate clock frequency by using strapping inputs REFCLK_CONF[20]

The PLL can be used as a recovered clock source for Synchronous Ethernet For information about how to configure PLL clock recovery see Layer 1 Timing page 152

For information about protecting the VCore CPU system during a soft-reset see Clocking and Reset page 157

3181 Pin StrappingConfigure PLL reference clock and VCore startup mode using the strapping pins on the GPIO interface The device latches strapping pins and keeps their value when nRESET to the device is released After

reset is released the strapping pins are used for other functions For more information about which GPIO pins are used for strapping see GPIO Overlaid Functions page 204

By using resistors to pull the GPIOs either low or high software can use these GPIO pins for other functions after reset has been released For more information about overlaid functions on the GPIOs see GPIO Overlaid Functions page 204

Undefined configurations are reserved and cannot be used VCore-III configurations that enable a front port or the PCIe endpoint drive VCore_CFG[32] high when the front port or PCIe endpoint is ready to use

Table 128 bull Strapping

Pin DescriptionREFCLK_CONF[20] Configuration of reference clock frequency for PLL

000 125 MHz001 15625 MHz010 250 MHz100 25 MHzOther values are reserved and must not be used

VCORE_CFG[30] Configuration of VCore system startup conditions

VCore-Ie System and CPU Interfaces

4 VCore-Ie System and CPU Interfaces

This section provides information about the functional aspects of blocks and interfaces related to the VCore-Ie on-chip microprocessor system and an external CPU system

The device contains a fast VCore-Ie CPU system that is based on an embedded 8051-compatible microprocessor and a high bandwidth Ethernet Frame DMA engine The VCore-Ie system can control the device independently or it can support an external CPU relieving the external CPU of the otherwise time consuming tasks of transferring frames maintaining the switch core and handling networking protocols

When the VCore-Ie CPU is enabled it either automatically boots up from serial Flash or an external CPU can manually load a code-image to the device and then start the VCore-Ie CPU

An external CPU can be connected to the device through the PCIe interface serial interface (SI) dedicated MIIM slave interface or through Versatile Register Access Protocol (VRAP) formatted Ethernet frames using the NPI Ethernet port

The following illustration shows the VCore-Ie block diagram

Figure 55 bull VCore-Ie System Block Diagram

41 VCore-Ie ConfigurationsThe behavior of the VCore-Ie system after a reset is determined by four VCore strapping pins that are overlaid on GPIO pins The value of these GPIOs is sampled shortly after releasing reset to the device For more information about the strapping pins see Pin Strapping page 157

Switch Core Register Bus

AccessArbiterSwitch Core Register Bus (CSR)

VCore Shared Bus AccessArbiter VCore Shared Bus (SBA)

GPIO IO Controller

MIIMMasters times 2

Temperature Sensor

Fan Controller

SGPIO IO Controller

Two-Wire Serial Interface UART times 2

SI Flash Boot Master(1)Timers times 3

PCIe Inbound(2)

PCIe Outbound

VRAP(Register access

through Ethernet)

Switch Core Access BlockVCore CPU

MIIM Slave

SI Slave(1)

Frame DMA(FDMA)

1 When the Vcore-III CPU boots up from the SI Flash the SI is reserved as boot interface and cannot be used by an external CPU

2 Inbound PCIe access to BAR0 maps to VCore register space (interrupt controller timers two-wire serial masterslave UARTs and manual frame injectionextraction) Switch core access block is not reachable via PCIe inbound accesses

The strapping value determines the reset value for the ICPU_CFGGENERAL_CTRL register After startup the behavior of the VCore-Ie system can be modified by changing some of the fields in this register The following are common scenarios

bull After starting the device with the VCore-Ie CPU disabled an external CPU can manually boot the VCore-Ie CPU from SI Flash by writing ICPU_CFGGENERAL_CTRLIF_SI_OWNER = 1 ICPU_CFGGENERAL_CTRLBOOT_MODE_ENA = 1 and ICPU_CFGGENERAL_CTRLCPU_DIS = 0 Setting GENERAL_CTRLIF_SI_OWNER disables the SI slave so the external CPU must use another interface than SI

bull After starting the device with the VCore-Ie CPU disabled the 8051 internal memory can be loaded with software and the VCore-Ie CPU can be booted as explained in Starting the VCore-Ie CPU page 165

bull After automatically booting from SI Flash the VCore-Ie CPU can release the SI interface and enable the SI slave by writing ICPU_CFGGENERAL_CTRLIF_SI_OWNER = 0 This enables SI access from an external CPU to the device A special PCB design is required to make the serial interface work for both Flash and external CPU access

bull MIIM slave can be manually enabled by writing ICPU_CFGGENERAL_CTRLIF_MIIM_SLV_ENA = 1 The MIIM slave automatically takes control of the appropriate GPIO pins

42 Clocking and ResetThe following table lists the registers associated with reset and the watchdog timer

The VCore-Ie CPU runs 250 MHz and the rest of the VCore-Ie system runs at 250 MHz

The VCore-Ie can be soft reset by setting RESETCORE_RST_FORCE By default this resets both the VCore-Ie CPU and the VCore-Ie system The VCore-Ie system can be excluded from a soft reset by setting RESETCORE_RST_CPU_ONLY soft reset using CORE_RST_FORCE only then resets the VCore-Ie CPU The frame DMA must be disabled prior to a soft reset of the VCore-Ie system When CORE_RST_CPU_ONLY is set the frame DMA and the PCIe endpoint are not affected by a soft reset and continue to operate throughout soft reset of the VCore-Ie CPU

The VCore-Ie system comprises all the blocks attached to the VCore Shared Bus (SBA) including the PCIe and frame DMAinjectionextraction blocks Blocks attached to the switch core Register Bus (CSR) including VRAP SI and MIIM slaves are not part of the VCore-Ie system reset domain For more information about the VCore-Ie system blocks see Figure 41 page 159

The device can be soft reset by writing SOFT_RSTSOFT_CHIP_RST The VCore-Ie system and CPU can be protected from a device soft reset by writing RESETCORE_RST_PROTECT = 1 before initiating a soft reset In this case a chip-level soft reset is applied to all other blocks except the VCore-Ie system and the CPU When protecting the VCore-Ie system and CPU from a soft reset the frame DMA must be disabled prior to a chip-level soft reset The SERDES and PLL blocks can be protected from reset by writing to SOFT_RSTSOFT_SWC_RST instead of SOFT_CHIP_RST

The VCore-Ie general purpose registers (ICPU_CFGGPR) and GPIO alternate modes (DEVCPU_GCBGPIO_ALT) are not affected by a soft reset These registers are only reset when an external reset is asserted

Table 129 bull Clocking and Reset Configuration Registers

Register DescriptionICPU_CFGRESET VCore-Ie reset protection scheme and initiating soft reset of

the VCore-Ie system andor CPU

DEVCPU_GCBSOFT_RST Initiating chip-level soft reset

ICPU_CFGWDT Watchdog timer configuration and status

421 Watchdog TimerThe VCore system has a built-in watchdog timer (WDT) with a two-second timeout cycle The watchdog timer is enabled disabled or reset through the WDT register The watchdog timer is disabled by default

After the watchdog timer is enabled it must be regularly reset by software Otherwise it times out and cause a VCore soft reset equivalent to setting RESETCORE_RST_FORCE Improper use of the WDTWDT_LOCK causes an immediate timeout-reset as if the watchdog timer had timed out The WDTWDT_STATUS field shows if the last VCore-Ie CPU reset was caused by WDT timeout or regular reset (possibly soft reset) The WDTWDT_STATUS field is updated only during VCore-Ie CPU reset

To enable or to reset the watchdog timer write the locking sequence as described in WDTWDT_LOCK at the same time as setting the WDTWDT_ENABLE field

Note Because watchdog timeout is equivalent to setting RESETCORE_RST_FORCE the RESETCORE_RST_CPU_ONLY field also applies to watchdog initiated soft reset

43 Shared BusThe shared bus is a 32-bit address and 32-bit data bus with dedicated master and slave interfaces that interconnect all the blocks in the VCore-Ie system The VCore-Ie CPU PCIe inbound and VCore SBA access block are masters on the shared bus only they can start access on the bus

The shared bus uses byte addresses and transfers of 8 16 or 32 bits can be made To increase performance bursting of multiple 32-bit words on the shared bus can be performed

All slaves are mapped into the VCore-Ie systemrsquos 32-bit address space and can be accessed directly by masters on the shared bus The SI Flash boot master is mirrored into the lowest address region

Figure 56 bull Shared Bus memory

The Frame DMA has dedicated access to PCIe outbound This means that access on the SBA to other parts of the device such as register access does not affect Frame DMA injectionextraction performance

431 VCore-Ie Shared Bus Arbitration The following table lists the registers associated with the shared bus arbitration

Table 130 bull Shared Bus Configuration Registers

Register DescriptionSBAPL_CPU Master priorities

SBAPL_PCIE Master priorities

Reserved

Mirror of SI Flash

Chip Registers

0x00000000

0x80000000

0x20000000

0xFFFFFFFF

0x10000000256 MB

512 MB

0x00000000

0x80000000

0x20000000

256 MB0x700000000x70000000

SI Flash0x40000000

256 MB

0x40000000

0x50000000256 MB

512 MB0x50000000

PCIe DMA

1 GB0xC0000000 0xC0000000

The VCore-Ie shared bus arbitrates between masters that want to access the bus The default is to use a strict prioritized arbitration scheme where the VCore-Ie CPU has highest priority The strict priorities can be changed using registers PL_CPU PL_PCIE and PL_CSR

bull _CPU registers apply to VCore-Ie CPU accessbull _PCIE registers apply to inbound PCIe accessbull _CSR registers apply to VCore-Ie SBA access block accessIt is possible to enable weighted token arbitration scheme (WT_EN) When using this scheme specific masters can be guaranteed a certain amount of bandwidth on the shared bus Guaranteed bandwidth that is not used is given to other masters requesting the shared bus

When weighted token arbitration is enabled the masters on the shared bus are grated a configurable number of tokens (WT_CPU WT_PCIE and WT_CSR) at the start of each refresh period The length of each refresh period is configurable (WT_TCL) For each clock cycle that the master uses the shared bus the token counter for that master is decremented When all tokens are spent the master is forced to a low priority Masters with tokens always take priority over masters with no tokens The strict prioritized scheme is used to arbitrate between masters with tokens and between masters without tokens

Example Guarantee That PCIe Can Get 25 Bandwidth Configure WT_TCL to a refresh period of 2048 clock cycles the optimal length of the refresh period depends on the scenario experiment to find the right setting Guarantee PCIe access in 25 of the refresh period by setting WT_PCIE to 512 (2048 times 25) Set WT_CPU and WT_CSR to 0 This gives the VCore-Ie CPU and CSR unlimited tokens Configure PCIe to the highest priority by setting PL_PCIe to 15 Finally enable the weighted token scheme by setting WT_EN to 1 For each refresh period of 2048 clock cycles PCIe is guaranteed access to the shared bus for 512 clock cycles because it is the highest priority master When all the tokens are spent it is put into the low-priority category

432 Chip Register RegionRegisters in the VCore-Ie domain and inside the switch core are memory mapped into the chip registers region of the shared bus memory map All registers are 32-bit wide and must only be accessed using 32-bit reads and writes Bursts are supported

Writes to this region are buffered (there is a one-word write buffer) Multiple back-to-back write access pauses the shared bus until the write buffer is freed up (until the previous writes are done) Reads from this region pause the shared bus until read data is available

SBAPL_CSR Master priorities

SBAWT_EN Enable of weighted token scheme

SBAWT_TCL Weighted token refresh period

SBAWT_CPU Token weights for weighted token scheme

SBAWT_PCIE Token weights for weighted token scheme

SBAWT_CSR Token weights for weighted token scheme

Table 130 bull Shared Bus Configuration Registers (continued)

Register Description

Figure 57 bull Chip Registers Memory Map

The registers in the 0x70000000 through 0x70FFFFFF region are physically located inside the VCore-Ie system so read and write access to these registers is fast (done in a few clock cycles) All registers in this region are considered fast registers

Registers in the 0x71000000 through 0x71FFFFFF region are located inside the switch core access to registers in this range takes approximately 1 micros The DEVCPU_ORG and DEVCPU_QS targets are special registers inside these two targets are faster access to these two targets takes approximately 01 micros Registers located inside the switch core are not accessible through PCIe interface

When more than one CPU is accessing registers the access time may be increased For more information see Register Access and Multimaster Systems

Writes to the Chip Registers region is buffered (there is a one-word write buffer) Multiple back-to-back write access pauses the shared bus until the write buffer is freed up (until the previous write is done) A read access pause the shared bus until read data is available Executing a write immediately followed by a read requires the write to be done before the read can be started

433 SI Flash RegionRead access from the SI Flash region initiates Flash formatted read access on the SI pins of the device by means of the SI boot controller

The SI Flash region cannot be written to Writing to the SI interface must be implemented by using the SI master controller For more information see SI Master Controller page 193 For legacy reasons it is also possible to write to the SI interface by using the SI boot masterrsquos software ldquobit-bangingrdquo register interface For more information see SI Boot Controller page 191

434 PCIe RegionRead and write access from or to the PCIe region maps to outbound read and write access on the PCIe interface of the device by means of the PCIe endpoint controller For more information about the PCIe endpoint controller and how to reach addresses in 32-bit and 64-bit PCIe environments see PCIe Endpoint Controller

VCore Registers

UART Registers

TWI Registers

0x70100000

0x70100400

0x70100800

0x70000000

SBA Registers0x70110000

0x701104001 KB

Reserved59 KB

Reserved1 KB

0x70101400SIMC Registers1 KB

0x70101000

Reserved3 KB

UART2 Registers1 KB0x70100C00

0x71000000

0x72000000

PCIe Registers0x70111000

0x701120001 KB

Reserved15 MB

1 Loading On-Chip Memory page 1662 Map on-chip memory For more information see Mapping On-Chip Memory page 167Note When manually booting up the size of the code image is limited by the size of the on-chip memory However when automatically booting up from Flash the VCore-Ie CPU can use paging to access code and data for a total of up to 256 megabytes For more information see Paged Access to VCore-Ie Shared Bus page 168

Figure 58 bull VCore-Ie Block Diagram

The preceding illustration shows the basic blocks of the VCore-Ie 8051 implementation The illustration highlights features such as

bull VCore-Ie CPU frequency of 250 MHz bull Advanced clock gating control that automatically pauses the 8051 during shared bus accessbull Two independent interrupts from dedicated VCore-Ie interrupt controller allows interrupts from all

major VCore-Ie blocks including timers UART and hardware based semaphores (for communication with external CPU)

bull On-chip 256-byte scratchpad The lower 128 bytes are directly and indirectly addressable The upper 128 bytes are indirectly addressable

bull Simple Memory Management Unit maps 8051rsquos code and data access to either on-chip memory or shared bus (with support for paging)

bull Custom SFR registers allows access to the full 32-bit address space of the shared bus direct control of the MMU and other features

bull Easy debugging and development of software using an external CPU through dedicated status registers in the VCore-Ie system domain For more information Software Debug and Development page 169

The UART and three timers have been moved out of the 8051 and into the general VCore-Ie register domain so that they are unaffected by the clock gating of the VCore-Ie CPU The SFR registers related to timers and UART have been removed from the list of SFR registers For more information on how to use the VCore-Ie system UART and timers see UARTs page 197 and Timers page 197

The following table lists the available VCore-Ie CPU SFR registers and associated register fields A ldquo-rdquo means that the register field is available for general read and write access and a 0 or 1 means that the

SBA Access

On-chip RAM

CodeData

On-chip ScratchpadMemory 256 Bytes

Shared BusMaster

Shared Bus

VCore-Ie registers

VCore-Ie CPU clockclk int0_n

int1_n VCore-Ie CPU interruptsClockGating

register field is reserved When writing reserved register fields these must be set to 0 or 1 as indicated in the table

The SFRGPR register is an 8-bit general-purpose register The value of this register is available to external CPU through ICPU_CFGMPU8051_STATMPU8051_GPR

The contents of the SFRMPAGE register are used for the upper eight address bits during ldquoMOVX A Rirdquo and ldquoMOVX Ri Ardquo instructions For legacy 8051 designs the MPAGE register replaces the Port-2-Latch To enable memory access instructions (ldquoMOVX A Rildquo and ldquoMOVX Ri Ardquo) SFR register 0x8E must be written to 0 (ldquoMOV 0x8E 0x00rdquo)

For more information about the SFRMMAP register see Mapping On-Chip Memory page 167

For more information about the SFRRA_ registers see Accessing the VCore-Ie Shared Bus page 167

435 Starting the VCore-Ie CPUThis section provides information about the startup procedures for the VCore-Ie CPU The procedures apply to both manual and automatic booting

Table 131 bull Special Function Registers (SFR)

Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0GPR1

1 This register is not part of the standard 8051 implementation

0x80 - - - - - - - -

SP 0x81 - - - - - - - -

DPL 0x82 - - - - - - - -

DPH 0x83 - - - - - - - -

PCON 0x87 - - 1 1 GF1 GF0 STOP IDLE

TCON 0x88 0 0 0 0 IE1 IT1 IE0 IT0

MPAGE1 0x92 - - - - - - - -

PG1 0xB0 IFP3 IFP2 IFP1 IFP0 OP3 OP2 OP1 OP0

EPG1 0xC0 EIFP3 EIFP2 EIFP1 EIFP0 EOP3 EOP2 EOP1 EOP0

EEPG1 0xC1 EEIFP3 EEIFP2 EEIFP1 EEIFP0 EEOP3 EEOP2 EEOP1 EEOP0

PSW 0xD0 CY AC F0 RS1 RS0 0V F1 P

ACC 0xE0 - - - - - - - -

B 0xF0 - - - - - - - -

MMAP1 0xF2 ACH ACL ADH ADL MCH MCL MDH MDL

RA_AD0_RD1 0xF6 - - - - - - 0 0

RA_AD0_WR1 0xF7 - - - - - - 0 0

RA_AD11 0xF9 - - - - - - - -

RA_AD21 0xFA - - - - - - - -

RA_AD31 0xFB - - - - - - - -

RA_DA01 0xFC - - - - - - - -

RA_DA11 0xFD - - - - - - - -

RA_DA21 0xFE - - - - - - - -

RA_DA31 0xFF - - - - - - - -

The following table lists the registers associated with starting up the VCore-Ie CPU

The VCORE_CFG strapping pins determine if the VCore-Ie CPU boots up automatically or if it is kept in reset after startup For more information see VCore-Ie Configurations page 159

4351 Loading On-Chip MemoryThe basic principle of loading the on-chip memory is the same whether the VCore-Ie CPU is copying from Flash during automatic booting or if an external CPU is manually loading a code-image

The initial step of loading on-chip memory is to set up a source address in the shared bus domain by writing to MEMACC_SBAMEMACC_SBA_START For automatic booting this is typically address 0x00000000 (the first address in the Flash) When manually loading on-chip memory from an external CPU a good choice for transferring data is the eight 32-bit general-purpose registers (GPR) starting at address 0x70000000

The second step is to configure destination-range in the on-chip memory by using MEMACCMEMACC_START and MEMACCMEMACC_STOP

A transfer is started by writing to MEMACC_CTRLMEMACC_DO This field is cleared when all (32-bit) words in the range MEMACC_START through MEMACC_STOP are copied When MEMACC_START is equal to MEMACC_STOP only one word is copied Word addresses are incremented for each word that is copied (the registers are not physically changed) This means that the nrsquoth word in a given transfer is copied between addresses MEMACC_AHB_STARTMEM_ACC_START+n and MEMACCMEMACC_START+n

When loading from Flash the entire on-chip memory can be filled using one long transfer When loading from an external CPU using the GPR registers the external CPU repeat transferring blocks of code until the entire code-image is copied to on-chip memory

The clock of the VCore-Ie CPU is gated during loading of the on-chip memory which means that loading of the on-chip memory is instantaneous (from the point of view of the software running on the VCore-Ie CPU)

By setting MEMACC_CTRLMEMACC_EXAMINE the direction of the transfer can be changed which allows an external CPU to examine the contents of the on-chip memory instead of loading it

Loading of the on-chip memory is not limited to copying code during booting Whenever code or data must be copied from Flash to on-chip memory the hardware for loading the on-chip memory can be used The on-chip memory area can be loaded while the VCore-Ie CPU is operating

Example Manually Loading 58 Bytes of Code to On-Chip Memory This example uses all eight GPR registers for transferring data to on-chip memory Configure the MEMACC_AHB register to 0x70000000 (the address of the first GPR register) Write the first 32 bytes of code to GRP[0] though GPR[7] Set the destination range to the first 8 words of on-chip memory by writing 0x001C0000 to the MEMACC register Write to MEMACC_CTRLMEMACC_DO to start the access make sure that MEMACC_CTRLMEMACC_EXAMINE is cleared The MEMACC_DO field is automatically cleared when the transfer is done when this happens the next 26 bytes can be written to GRP[0] though GPR[6] (only byte addresses 0 and 1 of GPR[6] is used) Update the destination range in on-chip memory by writing 0x00380020 to the MEMACC register Start the second transfer by writing to

Table 132 bull VCore-Ie CPU Startup Registers

Register DescriptionRESET Manual release of VCore-Ie CPU reset

MPU8051_MMAP Mapping of on-chip memory

MEMACC_CTRL Starting copy of memory regions

MEMACC Configuration of on-chip memory address range

MEMACC_SBA Configuration of SBA start address

GPR Set of eight general-purpose 32-bit registers

MEMACC_CTRLMEMACC_DO After this field is cleared the code is copied The on-chip memory can then be mapped and the VCore-Ie CPU can be released from reset

4352 Mapping On-Chip MemoryBy default the on-chip memory is transparent to the VCore-Ie CPU Using the MPU8051_MMAP or the SFRMMAP registers the on-chip memory can be mapped into code and data space of the VCore-Ie CPU

There are two MMAP registers one that is part of the VCore-Ie registers (MPU8051_MMAP) and one that is a part of the 8051rsquos SFR registers (SFRMMAP) The mapping of on-chip memory is the result of a bit-wise OR between these two registers Only one of these registers must be used

When manually loading a code-image from an external CPU the MPU8051_MMAP register must be used When automatically booting up from Flash use the SFRMMAP register The encoding of these two registers are the same and both registers are commonly referred to as MMAP

The MPU8051_MMAP register in the VCore-Ie registers can be protected from VCore-Ie soft-reset When the MPU8051_MMAP register is used and the VCore-Ie system is protected from reset the mapping remains active after soft-reset of the VCore-Ie CPU

The code interface of the 8051 maps to the shared bus by default Setting MMAPMAP_CODE_LOW maps access in the low 32 kilobyte region of the code interface to the on-chip memory Setting MMAPMAP_CODE_HIGH maps access in the high 32 kilobyte region of the code interface to the on-chip memory

MMAPMSADDR_CODE_LOW controls if either the lower or higher half of the on-chip memory is accessed when the low 32 kilobyte region of the code interface maps an access to on-chip memory MMAPMSADDR_CODE_HIGH controls if either lower or higher half of the on-chip memory is accessed when the high 32 kilobyte region of the code interface maps an access to the on-chip memory

The data interface of the 8051 maps to the shared bus by default Setting MMAPMAP_DATA_LOW maps access in the low 32 kilobyte region of the data interface to the on-chip memory Setting MMAPMAP_DATA_HIGH maps access in the high 32 kilobyte region of the data interface to the on-chip memory

MMAPMSADDR_DATA_LOW controls if either the lower or higher half of the on-chip memory is accessed when the low 32 kilobyte region of the data interface maps an access to the on-chip memory

MMAPMSADDR_DATA_HIGH controls if either the lower or higher half of the on-chip memory is accessed when the high 32 kilobyte region of the data interface maps an access to the on-chip memory

Example Map the Complete On-Chip Memory to Both Code and Data Some 8051 compilers support using the same physical memory for both code and data To map the complete 64 kilobyte on-chip memory to both code and data interfaces set MMAP to 0xAF Then a code access on address n and a data access on address n both maps to an access on address n inside the on-chip memory

Example Split On-Chip Memory between Code and Data In some cases it may be desirable to use non-overlapping memory for code and data Setting MMAP to 0x15 maps the lower half of the on-chip memory to the code interface and the higher half to the data interface Code address n then maps to address n inside the on-chip memory and data address n maps to address n+0x8000 inside the on-chip memory

436 Accessing the VCore-Ie Shared BusAccess to the VCore-Ie shared bus is done through registers in the Special Function Registers (SFR) domain of the VCore-Ie CPU

The following table lists the registers associated with the VCore-Ie shared bus

Table 133 bull Shared Bus Access (SBA) Registers

Register DescriptionSFRRA_AD0_RD SBA address[70] and read access initiation

During access to the VCore-Ie shared bus the clock of the VCore-Ie CPU is gated This means that from the point of view of the software access to the shared bus is instantaneous

Although the shared bus is byte-addressable the VCore-Ie always does word access (reading or writing 32 bits of data) As a result the shared bus address must be a word-aligned address meaning that the two least significant bits of the address must always be 0

Reading from the VCore-Ie shared bus requires configuration of read-address by writing to RA_AD3 RA_AD2 RA_AD1 followed by write to RA_AD0_RD The last write initiates the read access The registers RA_DA3 RA_DA2 RA_DA1 and RA_DA0 are overwritten with the result of the read access

Note Because shared bus accesses are instantaneous from software perspective the data is available to the instruction immediately following the write to RA_AD0_RD

Writing to the VCore-Ie shared bus requires setting up write-data in RA_DA3 RA_DA2 RA_DA1 and RA_DA0 configuration of write-address by writing to RA_AD3 RA_AD2 RA_AD1 followed by write to RA_AD0_WR The last write initiates the write access

The only registers that can be modified by hardware are the RA_DA registers and these are only changed during read operations

Example Copy ICPU_CFGGPR[1] to ICPU_CFGGPR[2] with change to 4th byte Perform read by setting RA_AD3=0x70 RA_AD2=0x00 RA_AD1=0x00 and RA_AD0_RD=0x04 The RA_DA3 RA_DA2 RA_DA1 and RA_DA0 registers have now been updated with the value of ICPU_CFGGPR[1] Modify RA_DA3 (the 4th byte) and set RA_AD0_WR=0x08 to save to ICPU_CFGGPR[2]

437 Paged Access to VCore-Ie Shared BusThe VCore-Ie CPU supports paged access to the shared bus Paging extends the address space of the VCore-Ie CPU by 8 bits thereby increasing the addressable region from 64 kilobytes to 16 megabytes

The following table lists the registers associated with paged access to the VCore-Ie shared bus

The paging mechanism of the VCore-Ie CPU only applies to access to the shared bus the paging registers (PG and EPG) does not affect code or data access that are mapped to on-chip memory

The PG register contains two groups IFP[30] and OP[30] The IFP group holds four page bits used for instruction fetches and program memory reads (MOVC instructions) The OP group holds four page bits used for all other types of external memory accesses The layout of the EPG and EEPG registers are

SFRRA_AD0_WR SBA address[70] and write access initiation

SFRRA_AD1 SBA address[158]

SFRRA_DA0 SBA data[70]

Table 134 bull Paged Access to VCore-Ie Shared Bus

Register DescriptionSFRPG Paging Control

SFREPG Extended Paging Control

Table 133 bull Shared Bus Access (SBA) Registers (continued)

similar to the PG register EEIFP[30] EIFP[30] and EEOFP[30] EOFP[30] hold the eight most significant page bits so that the concatenation of EEIFP EIFP and IFP provides the 12 instruction page bits and the concatenation of EEOP EOP and OP provides the 12 other access page bits

Note The IFPEIFPEEIFP and OPEOPEEOP fields are independent which means that the VCore-Ie CPU can execute code and read data from different pages of the Flash

The paging function is useful for accessing small seldom used functions or data directly in Flash However it is sometimes more sensible to copy code or data from Flash to on-chip memory by use of the dedicated loader hardware before accessing it For more information see Loading On-Chip Memory page 166

438 Software Debug and DevelopmentThis section provides information about methods that use combinations of software and hardware to allow debugging code within VCore-Ie CPU

The following table lists the registers associated with 8051 status

The MPU8051_STATMPU8051_GPR field is a read-only copy of the 8-bit SFRGPR registerThe MPU8051_STATMPU8051_STOP field is set when the 8051 enters stop mode (by setting SFRPCONSTOP) By using these fields the 8051 can report up to 256 exit conditions from the 8051 software to the external CPU

The only way for the VCore-Ie CPU to exit the stop mode is by resetting the VCore-Ie CPU In a real-life application the VCore-Ie CPU must not use the stop mode unless it has also enabled the watchdog timer which would bring the system back online after the unlikely event of an error

The GENERAL_STATCPU_SLEEP field is set when the 8051 enters idle mode after setting SFRPCONIDLE As a result an external CPU can determine if the 8051 is in IDLE mode by examining the CPU_SLEEP field

The VCore-Ie registers includes eight 32-bit general-purpose registers (GPR) that can be used for exchanging information between the 8051 and an external CPU This can be combined with the software interrupt and semaphore implementation For more information seeMailbox and Semaphores page 176

The same mechanism that is used for loading code into the on-chip memory can also be used for examining on-chip memory By setting ICPU_CFGMEMACC_CTRLMEMACC_EXAMINE a portion of the on-chip memory can be extracted and placed in SBA domain for access by an external CPU

44 VCore-Ie CPUThe VCore-Ie CPU system is based on a fast embedded 8051-compatible microprocessor

When automatic boot is enabled using the VCORE_CFG strapping pins the VCore-Ie CPU automatically starts to execute code in the Flash at byte address 0 in the SI flash region

A typical automatic boot sequence is as follows

1 Speed up the boot interface For more information see SI boot controller2 Copy code-image from the Flash to on-chip memory For more information see Loading On-Chip

Memory page 166 3 Map on-chip memory For more information see Mapping On-Chip Memory page 167When automatic boot is disabled an external CPU can start the VCore-Ie CPU through the registers A typical manual boot-up sequence is as follows

Table 135 bull 8051 Status Registers

Register DescriptionMPU8051_STAT Status from the 8051

GENERAL_STAT Sleep status from the 8051

GPR Set of 8 general purpose 32-bit registers

45 Load on-chip memory with code-image For more information see External CPU SupportAn external CPU attaches to the device through the PCIe SI MIIM or VRAP Through these interfaces an external CPU can access (and control) the device For more information about interfaces and connections to device registers see VCore-Ie system block diagram

Inbound PCIe access is performed on the VCore Shared Bus (SBA) in the same way as ordinary VCore-Ie CPU access The Switch Core Register (CSR) bus is not accessible from PCIe For more information about supported PCIe BAR regions see PCIe Endpoint Controller

The SI MIIM and VRAP interfaces attach directly to the CSR Through the VCore SBA access block it is possible to access the VCore shared bus For more information see Access to the VCore Shared Bus

The external CPU can coexist with the internal VCore-Ie CPU and hardware-semaphores and interrupts are implemented for inter-CPU communication For more information see Mailbox and Semaphores page 176

451 Register Access and Multimaster SystemsThere are three different groups of registers in the device

bull Switch Corebull Fast Switch Corebull VCoreThe Switch Core registers and Fast Switch Core registers are separated into individual register targets and attached to the Switch Core Register bus (CSR) The Fast Switch Core registers are placed in the DEVCPU_QS and DEVCPU_ORG register targets Access to Fast Switch Core registers is less than 01 micros other Switch Core registers take no more than 1 micros to access

The VCore registers are attached directly to the VCore shared bus The access time to VCore registers is negligible (a few clock cycles)

Although multiple masters can access VCore registers and Switch Core registers in parallel without noticeable penalty to the access time the following exceptions apply

bull When accessing the same Switch Core register target (for example DEVCPU_GCB) the second master to attempt access has to wait for the first master to finish (round robin arbitration applies) This does not apply to Fast Switch Core register targets (DEVCPU_QS and DEVCPU_ORG)

bull If two or more SI MIIM or VRAP masters are performing VCore register access they all need to go through the VCore SBA Access block Ownership has to be resolved by use of software (for example by using the built-in semaphores)

The most common multimaster scenario is with an active VCore-Ie CPU and an external CPU using either SI or VRAP In this case Switch Core register access to targets that are used by both CPUs may see two times the access time (no more than 2 micros)

452 Serial Interface in Slave ModeThis section provides information about the function of the serial interface in slave mode

The following table lists the registers associated with SI slave mode

Figure 59 bull SI Slave Mode Register

Register DescriptionDEVCPU_ORGIF_CTRL Configuration of endianess and bit order

DEVCPU_ORGIF_CFGSTAT Configuration of padding

ICPU_CFGGENERAL_CTRL SI interface ownership

The serial interface implements an SPI-compatible protocol that allows an external CPU to perform read and write access to register targets within the device Endianess and bit order is configurable and several options for high frequencies are supported

The serial interface is available to an external CPU when the VCore-Ie CPU does not use the SI for Flash or external SI access For more information VCore-Ie System and CPU interfaces

The following table lists the serial interface pins when the SI slave is configured as owner of SI interface in GENERAL_CTRLIF_SI_OWNER

SI_DI is sampled on rising edge of SI_CLK SI_DO is driven on falling edge of SI_CLK There are no requirements on the logical values of the SI_CLK and SI_DI inputs when SI_nCS is deasserted they can be either 0 or 1 SI_DO is only driven during read access when read data is shifted out of the device

The external CPU initiates access by asserting chip select and then transmitting one bit readwrite indication one donrsquot care bit 22 address bits and 32 bits of write data (or donrsquot care bits when reading)

With the register address of a specific register (REG_ADDR) the SI address (SI_ADDR) is calculated as

SI_ADDR = (REG_ADDR amp 0x00FFFFFF)gtgt2

Data word endianess is configured through IF_CTRL[0] The order of the data bits is configured using IF_CTRL[1]

The following illustration shows various configurations for write access The order of the data bits during writing as depicted is also used when the device is transmitting data during read operations

Figure 60 bull Write Sequence for SI

When using the serial interface to read registers the device needs to prepare read data after receiving the last address bit The access time of the register that is read must be satisfied before shifting out the

Table 136 bull SI Slave Mode Pins

Pin Name IO DescriptionSI_nCS0 I Active-low chip select

SI_CLK I Clock input

SI_DI I Data input (MOSI)

SI_DO O Data output (MISO)

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

Serial Address (SI_ADDR)

10 9 8 7 6 5 4 3 2 1 02

Serial Data

SI_DI 21

10 9 8 7 6 5 4 3 2 1 0

23 8 9 1

15 0 1 2 3 4 5 6 72

Serial Data

Big endian mode (IF_CTRL[0]=1) Most significant bit first (IF_CTRL[1]=0)

Big endian mode (IF_CTRL[0]=1) Least significant bit first (IF_CTRL[1]=1)

SI_DI 21

10 9 8 7 6 5 4 3 2 1 0

10 9 87 6 5 4 3 2 1 0 2

Serial Data

Little endian mode (IF_CTRL[0]=0) Most significant bit first (IF_CTRL[1]=0)

SI_DI 21

10 9 8 7 6 5 4 3 2 1 0

312 3 4 5 6 7 8 910

Serial Data

Little endian mode (IF_CTRL[0]=0) Least significant bit first (IF_CTRL[1]=1)

first bit of read data For information about access time see Register Access and Multimaster Systems The external CPU must apply one of the following solutions to satisfy read access time

bull Use SI_CLK with a period of minimum twice the access time for the register target For example for normal switch core targets (single master)1(2 times 1 micros) = 500 kHz (maximum)

bull Pause the SI_CLK between shifting of serial address bit 0 and the first data bit with enough time to satisfy the access time for the register target

bull Configure the device to send out padding bytes before transmitting the read data to satisfy the access time for the register target For example 1 dummy byte allows enough read time for the SI clock to run up to 6 MHz in a single master system See the following calculation

The device is configured for inserting padding bytes by writing to IF_CFGSTATIF_CFG These bytes are transmitted before the read data The maximum frequency of the SI clock is calculated as

(IF_CFGSTATIF_CFG times 8 ndash 15)access-time

For example for normal switch core targets (single master) 1-byte padding give(1 times 8 ndash 15) 1 micros = 6 MHz (maximum) The SI_DO output is kept tri-stated until the actual read data is transmitted

The following illustrations show options for serial read access The illustrations show only one mapping of read data little endian with most significant bit first Any of the mappings can be configured and applied to read data in the same way as for write data

Figure 61 bull Read Sequence for SI_CLK Slow

Figure 62 bull Read Sequence for SI_CLK Pause

Figure 63 bull Read Sequence for One-Byte Padding

When dummy bytes are enabled (IF_CFGSTATIF_CFG) the SI slave logic enables an error check that sends out 0x88888888 and sets IF_CFGSTATIF_STAT if the SI master does not provide enough time for register read

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 02

Serial Data

Big endian mode (IF_CTRL[0]=1) Most significant bit first (IF_CTRL[1]=0) no padding (IF_CFGSTATIF_CFG=0)

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 02

Serial Data

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 02

Serial Data

Big endian mode (IF_CTRL[0]=1) Most significant bit first (IF_CTRL[1]=0) one-byte padding (IF_CFGSTATIF_CFG=1)

padding (1 byte)

When using SI the external CPU must configure the IF_CTRL register after power-up reset or chip-level soft reset The IF_CTRL register is constructed so that it can be written no matter the state of the interface For more information about constructing write data for this register see the instructions in IF_CTRLIF_CTRL

453 MIIM Interface in Slave ModeThis section provides the functional aspects of the MIIM slave interface

The MIIM slave interface allows an external CPU to perform read and write access to the device register targets Register access is done indirectly because the address and data fields of the MIIM protocol is less than those used by the register targets Transfers on the MIIM interface are using the Management Frame Format protocol specified in IEEE 8023 Clause 22

The MIIM slave pins on the device are overlaid functions on the GPIO interface MIIM slave mode is enabled by configuring the appropriate VCore_CFG strapping pins For more information see VCore-Ie Configurations page 159 When MIIM slave mode is enabled the appropriate GPIO pins are automatically overtaken For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The following table lists the pins of the MIIM slave interface

MIIM_SLV_MDIO is sampled or changed on the rising edge of MIIM_SLV_MDC by the MIIM slave interface

The MIIM slave can be configured to answer on one of two different PHY addresses using ICPU_CFGGENERAL_CTRLIF_MIIM_SLV_ADDR_SEL or the VCore_CFG strapping pins

The MIIM slave has seven 16-bit MIIM registers defined as listed in the following table

Table 137 bull MIIM Slave Pins

Pin Name IO DescriptionMIIM_SLV_MDCGPIO I MIIM slave clock input

MIIM_SLV_MDIOGPIO IO MIIM slave data inputoutput

Table 138 bull MIIM Registers

Register Address Register Name Description0 ADDR_REG0 Bits 150 of the address to read or write The address

field must be formatted as word address

1 ADDR_REG1 Bits 3116 of the address to read or write

2 DATA_REG0 Bits 150 of the data to read or write Returns 0x8888 if a register read error occurred

3 DATA_REG1 Bits 3116 of the data to read or write The read or write operation is initiated after this register is read or written Returns 0x8888 if read while busy or a register read error occurred

4 DATA_REG1_INCR Bits 3116 of data to read or write The read or write operation is initiated after this register is read or written When the operation is complete the address register is incremented by one Returns 0x8888 if read while busy or a register read error occurred

5 DATA_REG1_INERT Bits 3116 of data to read or write Reading or writing to this register does not cause a register access to be initiated Returns 0x8888 if a register read error occurred

A 32-bit switch core register read or write transaction over the MIIM interface is done indirectly due to the limited data width of the MIIM frame First the address of the register inside the device must be set in the two 16-bit address registers of the MIIM slave using two MIIM write transactions The two 16-bit data registers can then be read or written to access the data value of the register inside the device Thus it requires up to four MIIM transactions to perform a single read or write operation on a register target

The address of the register to readwrite is set in registers ADDR_REG0 and ADDR_REG1 The data to write to the register pointed to by the address in ADDR_REG0 and ADDR_REG1 is first written to DATA_REG0 and then to DATA_REG1 When the write transaction to DATA_REG1 is completed the MIIM slave initiates the switch core register write

With the register address of a specific register (REG_ADDR) the MIIM address (MIIM_ADDR) is calculated as

MIIM_ADDR = (REG_ADDR amp 0x00FFFFFF)gtgt2

The following illustration shows a single MIIM write transaction on the MIIM interface

Figure 64 bull MIIM Slave Write Sequence

A read transaction is done in a similar way First read the DATA_REG0 and then read the DATA_REG1 As with a write operation The switch core register read is not initiated before the DATA_REG1 register is read In other words the returned read value is from the previous read transaction

The following illustration shows a single MIIM read transaction on the MIIM interface

Figure 65 bull MIIM Slave Read Sequence

6 STAT_REG The status register gives the status of any ongoing operationsBit 0 Busy Set while a register readwrite operation is in progressBit 1 Busy_rd Busy status during the last read or write operationBit 2 Err Set if a register access error occurredOthers Reserved

Table 138 bull MIIM Registers (continued)

Register Address Register Name Description

PREAMBLE32 bit

ST2 bit

OP2 bit

PHYAD5 bit

REGAD5 bit

TA2 bit

DATA16 bit

1 0 1 0 1 1 0

PREAMBLE32 bit

ST2 bit

OP2 bit

PHYAD5 bit

REGAD5 bit

TA2 bit

DATA16 bit

Z 01 10 1 0

454 Access to the VCore Shared BusThis section provides information about how to access the VCore shared bus (SBA) from an external CPU attached by means of the VRAP SI or MIIM The following table lists the registers associated with the VCore shared bus access

An external CPU perform 32-bit reads and writes to the SBA through the VCore Access (VA) registers In the VCore-Ie system a dedicated master on the shared bus handles VA access For information about arbitration between masters on the shared bus see VCore Shared Bus Arbitration

The SBA address is configured in VA_ADDR Writing to VA_DATA starts an SBA write with the 32-bit value that was written to VA_DATA Reading from VA_DATA returns the current value of the register and starts an SBA read access when the read access completes the result is automatically stored in the VA_DATA register

The VA_DATA_INCR register behaves similar to VA_DATA except that after starting an access the VA_ADDR register is incremented by four (so that it points to the next word address in the SBA domain) Reading from the VA_DATA_INCR register returns the value of VA_DATA writing to VA_DATA_INCR overwrites the value of VA_DATA

Note By using VA_DATA_INCR sequential word addresses can be accessed without having to manually increment the VA_ADDR register between each access

The VA_DATA_INERT register provides direct access to the VA_DATA value without starting access on the SBA Reading from the VA_DATA_INERT register returns the value of VA_DATA writing to VA_DATA_INERT overwrites the value of VA_DATA

The VCore-Ie shared bus is capable of returning error-indication when illegal register regions are accessed If a VA access results in an error-indication from the SBA the VA_CTRLVA_ERR field is set and the VA_DATA is set to 0x88888888

Note SBA error indications only occur when non-existing memory regions or illegal registers are accessed This will not happen during normal operation so the VA_CTRLVA_ERR indication is useful during debugging only

Example Reading from ICPU_CFGGPR[1] through the VA registers The GPR register is the second register in the SBA VCore-Ie Registers region Set VA_ADDR to 0x70000004 read once from VA_DATA (and discard the read value) Wait until VA_CTRLVA_BUSY is cleared then VA_DATA contains the value of the ICPU_CFGGPR[1] register Using VA_DATA_INERT (instead of VA_DATA) to read the data is appropriate because this does not start a new SBA access

4541 Optimized ReadingVCore-Ie shared bus access is typically much faster than the CPU interface which is used to access the VA registers The VA_DATA register (VA_DATA_INCR and VA_DATA_INERT) return 0x88888888 while VA_CTRLVA_BUSY is set This means that it is possible to skip checking for busy between read access to SBA For example after initiating a read access from SBA software can proceed directly to reading from VA_DATA VA_DATA_INCR or VA_DATA_INERT

bull If the second read is different from 0x88888888 then the second read returned valid read data (the SBA access was done before the second read was performed)

Table 139 bull VCore Shared Bus Access Registers

Register DescriptionDEVCPU_GCBVA_CTRL Status for ongoing access

DEVCPU_GCBVA_ADDR Configuration of shared bus address

DEVCPU_GCBVA_DATA Configuration of shared bus address

DEVCPU_GCBVA_DATA_INCR Data register access increments VA_ADDR

DEVCPU_GCBVA_DATA_INERT Data register access does not start new access

bull If the second read is equal to 0x88888888 then the VA logic may have been busy during the read and additional actions are required First read the VA_CTRLVA_BUSY field until the field is cleared (VA logic is not busy) Then read VA_DATA_INERT If VA_DATA_INERT returns 0x88888888 then read-data is actually 0x88888888 continue to the next read Otherwise repeat the last read from VA_DATA VA_DATA_INCR or VA_DATA_INERT and then continue to the next read from there

Optimized reading can be used for single read and sequential read access For sequential reads the VA_ADDR is only incremented on successful (non-busy) reads

455 Mailbox and SemaphoresThis section provides information about the semaphores and mailbox features for CPU to CPU communication The following table lists the registers associated with mailbox and semaphores

The mailbox is a 32-bit register that can be set and cleared atomically using any CPU interface (including the VCore-Ie CPU) The MAILBOX register allows reading (and writing) of the current mailbox value Atomic clear of individual bits in the mailbox register is done by writing a mask to MAILBOX_CLR Atomic setting of individual bits in the mailbox register is done by writing a mask to MAILBOX_SET

The device implements two independent semaphores The semaphores are part of the Switch Core Register Bus (CSR) block and are accessible by means of the fast switch core registers Semaphore ownership can be taken by interfaces attached to the CSR That is the VCore-Ie VRAP SI and MIIM can be granted ownership

Any CPU attached to an interface can attempt to take a semaphore n by reading SEMA0SEMA0 or SEMA1SEMA1 If the result is 1 the corresponding semaphore was successfully taken and is now owned by that interface If the result is 0 the semaphore was not free After successfully taking a semaphore all additional reads from the corresponding register will return 0 To release a semaphore write 1 to SEMA0SEMA0 or SEMA1SEMA1

Note Any interface can release semaphores it does not have to be the one that has taken the semaphore This allows implementation of handshaking protocols

The current status for a semaphore is available in SEMA0_OWNERSEMA0_OWNER and SEMA1_OWNERSEMA1_OWNER See register description for encoding of owners

Software interrupt is generated when semaphores are free or taken Interrupt polarity is configured through SEMA_CFGSEMA_INTR_POL Semaphore 0 is hooked up to SW0 interrupt and semaphore 1 is hooked up to SW1 interrupt For configuration of software-interrupt see Interrupt Controller

In addition to interrupting on semaphore state software interrupt can be manually triggered by writing directly to the ICPU_CFGINTR_FORCE register

Software interrupts (SW0 and SW1) can be individually mapped to either the VCore-Ie CPU or to external interrupt outputs (to an external CPU)

Table 140 bull Mailbox and Semaphore Registers

Register DescriptionDEVCPU_ORGMAILBOX_SET Atomic set of bits in the mailbox register

DEVCPU_ORGMAILBOX_CLR Atomic clear of bits in the mailbox register

DEVCPU_ORGMAILBOX Current mailbox state

DEVCPU_ORGSEMA_CFG Configuration of semaphore interrupts

DEVCPU_ORGSEMA0 Taking of semaphore 0

DEVCPU_ORGSEMA0_OWNER Current owner of semaphore 0

46 PCIe Endpoint ControllerThe device implements a single-lane PCIe 1x endpoint that can be hooked up to any PCIe capable system Using the PCIe interface an external CPU can access (and control) the device Ethernet frames can be injected and extracted using registers or the device can be configured to DMA Ethernet frames autonomously tofrom PCIe memory

Both the VCore-Ie CPU and Frame DMA can generate PCIe readwrite requests to any 32-bit or 64-bit memory region in PCIe memory space However it is up to software running on an external CPU to set up or communicate the appropriate PCIe memory mapping information to the device

The defaults for the endpoints capabilities region and the extended capabilities region are listed in the registers listrsquos description of the PCIE registers The most important parameters are

bull Vendor (and subsystem vendor) ID 0x101B Microsemibull Device ID 0xB005 device family IDbull Revision ID 0x00 device family revision IDbull Class Code 0x028000 Ethernet Network controllerbull Single function non-Bridge INTA and Message Signaled Interrupt (MSI) capable deviceThe device family 0xB005 covers several register-compatible devices The software driver must determine actual device ID and revision by reading DEVCPU_GCBCHIP_ID from the devicersquos memory mapped registers region

For information about base address registers see Base Address Registers Inbound Requests

The IDs class code revision ID and base address register setups can be customized before enabling the PCIe endpoint However it requires a manual bring-up procedure by software running locally on the VCore-Ie CPU For more information see Enabling the Endpoint

The endpoint is power management capable and implements PCI Bus Power Management Interface Specification Revision 12 For more information see Power Management

The endpoint is MSI capable Up to four 64-bit messages are supported Messages can be generated on rising and falling edges of each of the two external VCore-Ie interrupt destinations For more information see Outbound Interrupts

For information about all PCI Express capabilities and extended capabilities register defaults see the PCIE regionrsquos register descriptions

461 Accessing Endpoint RegistersThe root complex accesses the PCIe endpointrsquos configuration registers by PCIe CfgRdCfgWr requests The VCore-Ie CPU can read configuration registers by means of the PCIE region For more information see Chip Register Region The PCIE region must not be accessed when the PCIe endpoint is disabled

The PCIe region is used during manual bring-up of PCIe endpoint By using this region it is possible to write most of the endpointrsquos read-only configuration registers such as Vendor ID The PCIe endpointrsquos read-only configuration register values must not be changed after the endpoint is enabled

The VCore-Ie has a few dedicated PCIe registers in the ICPU_CFGPCIE register group An external CPU attached through the PCIe interface has to go through BAR0 to reach these registers

462 Enabling the EndpointThe PCIe endpoint is disabled by default It can be enabled automatically or manually by either setting the VCore_CFG strapping pins or by software running in the VCore-Ie CPU

The recommended approach is using VCore_CFG strapping pins because it is fast and does not require special software running on the VCore-Ie CPU The endpoint is ready approximately 50 ms after release of the devicersquos nRESET Until this point the device ignores any attempts to do link training and the PCIe output remains idle (tri-stated)

By using software running on the VCore-Ie CPU it is possible to manually start the PCIe endpoint Note that PCIe standard specifies a maximum delay from nRESET release to working PCIe endpoint so software must enable the endpoint as part of the boot process

The root complex must follow standard PCIe procedures for bringing up the endpoint

4621 Manually Starting MACPCS and SerDesThis section provides information about how to manually start up the PCIe endpoint and customize selected configuration space parameters

The following table lists the registers related to manually bringing up PCIe

Disable automatic link training for PICe endpoint

1 PCIE_CFGLTSSM_DIS = 1Configure and enable PCIe SERDES for 2G5 mode

1 SERDES6G_MISC_CFG = 0x000000312 SERDES6G_OB_CFG = 0x600001713 SERDES6G_OB_CFG1 = 0x000000B04 SERDES6G_DES_CFG = 0x000068A65 SERDES6G_IB_CFG = 0x3D57AC376 SERDES6G_IB_CFG1 = 0x00110FF07 SERDES6G_COMMON_CFG = 0x000240098 MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared9 SERDES6G_PLL_CFG = 0x00030F2010 MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared11 Wait at least 20 ms12 SERDES6G_IB_CFG = 0x3D57AC3F13 SERDES6G_MISC_CFG = 0x0000003014 MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared15 Wait at least 60 ms16 SERDES6G_IB_CFG = 0x3D57ACBF17 SERDES6G_IB_CFG1 = 0x00103FF018 MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is clearedTo optionally disable BAR1

1 PCIE_CFGPCIE_BAR_WR_ENA = 12 BAR1 = 0x00000000

Table 141 bull Manual PCIe Bring-Up Registers

Register DescriptionICPU_CFGPCIE_CFG Disable of automatic link initialization

HSIOSERDES6G_COMMON_CFG SERDES configuration

HSIOSERDES6G_MISC_CFG SERDES configuration

HSIOSERDES6G_IB_CFG SERDES configuration

HSIOSERDES6G_IB_CFG1 SERDES configuration

HSIOSERDES6G_OB_CFG SERDES configuration

HSIOSERDES6G_OB_CFG1 SERDES configuration

HSIOSERDES6G_DES_CFG SERDES configuration

HSIOSERDES6G_PLL_CFG SERDES configuration

HSIOMCB_SERDES6G_ADDR_CFG SERDES configuration

PCIEDEVICE_ID_VENDOR_ID PCIECLASS_CODE_REVISION_ID PCIESUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID

Device parameter customization

PCIEBAR1 PCIEBAR2 Base address register customization

3 PCIE_CFGPCIE_BAR_WR_ENA = 0To optionally change selected PCIe configuration space values

bull Write Vendor IDDevice ID using DEVICE_ID_VENDOR_IDbull Write Class CodeRevision ID using CLASS_CODE_REVISION_IDbull Write Subsystem IDSubsystem Vendor ID using SUBSYSTEM_ID_SUBSYSTEM_VENDOR_IDEnable automatic link training for PCIe endpoint

1 PCIE_CFGLTSSM_DIS = 0The last step enables the endpoint for link training and the root complex will then be able to initialize the PCIe endpoint After this the PCIE parameters must not be changed anymore

463 Base Address Registers Inbound RequestsThe device implements two memory regions Read and write operations using the PCIe are translated directly to read and write access on the SBA When manually bringing up the PCIe endpoint BAR1 can be disabled For more information see Manually Starting MACPCS and SerDes

This region supports all access types

To access the BAR1 region a Flash must be attached to the SI interface of the device For information about how to set up IO timing and to program the Flash through BAR0 the Chip Registers Region see SI Boot Controller page 191

464 Outbound InterruptsThe device supports both Message Signaled Interrupt (MSI) and Legacy PCI Interrupt Delivery The root complex configures the desired mode using the MSI enable bit in the PCIe MSI Capability Register Set For information about the VCore-Ie interrupt controller see Interrupt Controller page 215

The following table lists the device registers associated PCIe outbound interrupts

In legacy mode one interrupt is supported select either EXT_DST0 or EXT_DST1 using PCIE_INTR_COMMON_CFGLEGASY_MODE_INTR_SEL The PCIe endpoint uses Assert_INTA and Deassert_INTA messages when configured for legacy mode

In MSI mode both EXT_DST interrupts can be used EXT_DST0 is configured though PCIE_INTR_CFG[0] and EXT_DST1 through PCIE_INTR_CFG[1] Enable message generation on rising andor falling edges in PCIE_INTR_CFG[n]INTR_RISING_ENA and PCIE_INTR_CFG[n]INTR_FALLING_ENA Different vectors can be generated for rising and falling

Table 142 bull Base Address Registers

Register DescriptionBAR0 32-bit 32 megabytes Chip registers region This region maps to the Chip registers

region in the SBA address space See Chip Register Region This region only supports 32-bit word-aligned reads and writes Single and burst accesses are supported

BAR1 32-bit 16 megabytes SI Flash region This region maps to the SI Flash region in the SBA address space See SI Flash RegionThis region only supports 32-bit word-aligned reads Single and burst access is supported

Table 143 bull PCIe Outbound Interrupt Registers

Register DescriptionICPU_CFGPCIE_INTR_COMMON_CFG Interrupt mode and enable

ICPU_CFGPCIE_INTR_CFG MSI parameters

edges configure these through PCIE_INTR_CFG[n]RISING_VECTOR_VAL and PCIE_INTR_CFG[n]FALLING_VECTOR_VAL Finally each EXT_DST interrupt must be given an appropriate traffic class through PCIE_INTR_CFG[n]TRAFFIC_CLASS

After the root complex has configured the PCIe endpointrsquos MSI Capability Register Set and the external CPU has configured how interrupts from the VCore-Ie interrupt controller are propagated to PCIe interrupts must then be enabled by setting PCIE_INTR_COMMON_CFGPCIE_INTR_ENA

465 Outbound AccessAfter the PCIe endpoint is initialized outbound readwrite access to PCIe memory space is initiated by reading or writing the SBArsquos PCIe DMA region

The following table lists the device registers associated with PCIe outbound access

The PCIe DMA region is 1 gigabyte Access in this region is mapped to any 1 gigabyte region in 32-bit or 64-bit PCIe memory space by using address translation Two address translation regions are supported The recommended approach is to configure the first region for SBA outbound access and the second region for FDMA outbound access

Address translation works by taking bits [290] from the SBAFDMA address adding a configurable offset and then using the resulting address to access into PCIe memory space Offsets are configurable in steps of 64 kilobytes in the ATU_TGT_ADDR_HIGH and ATU_TGT_ADDR_LOW registers

The software on the VCore-Ie CPU (or other SBA masters) can dynamically reconfigure the window as needed however the FDMA does not have that ability so it must be disabled while updating the 1 gigabyte window that is set up for it

Note Although the SBA and FDMA both access the PCIe DMA region by addresses 0xC0000000 though 0xFFFFFFFF the PCIe address translation unit can differentiate between these accesses and apply the appropriate translation

4651 Configuring Outbound SBA Translation RegionConfigure PCIESLV_SBASBA_OFFSET = 0 and select address translation region 0 by writing ATU_REGIONATU_IDX = 0 Set PCIEATU_BASE_ADDR_LOWATU_BASE_ADDR_LOW = 0x0000 and PCIEATU_LIMIT_ADDRATU_LIMIT_ADDR = 0x3FFF

The following table lists the appropriate PCIe headers that must be configured before using the SBArsquos PCIe DMA region Remaining header fields are automatically handled

Table 144 bull Outbound Access Registers

Register DescriptionICPU_CFGPCIESLV_SBA Configures SBA outbound requests

ICPU_CFGPCIESLV_FDMA Configures FDMA outbound requests

PCIEATU_REGION Select active region for the ATU_ registers

PCIEATU_CFG1 Configures TLP fields

PCIEATU_CFG2 Enable address translation

PCIEATU_TGT_ADDR_LOW Configures outbound PCIe address

PCIEATU_TGT_ADDR_HIGH Configures outbound PCIe address

Table 145 bull PCIe Access Header Fields

Header Field RegisterFieldsAttributes ATU_CFG1ATU_ATTR

Poisoned Data PCIESLV_SBASBA_EP

TLP Digest Field Present ATU_CFG1ATU_TD

Configure the low address of the destination window in PCIe memory space as follows

bull Set ATU_TGT_ADDR_HIGHATU_TGT_ADDR_HIGH to bits [6332] of the destination window Set to 0 when a 32-bit address must be generated

bull Set ATU_TGT_ADDR_LOWATU_TGT_ADDR_LOW to bits [3116] of the destination window This field must not be set higher than 0xC000

Enable address translation by writing ATU_CFG2ATU_REGION_ENA = 1 SBA access in the PCIe DMA region is then mapped to PCIe memory space as defined by ATU_TGT_ADDR_LOW and ATU_TGT_ADDR_HIGH

The header fields and the PCIe address fields can be reconfigured on-the-fly as needed however set ATU_REGIONATU_IDX to 0 to ensure that the SBA region is selected

4652 Configuring Outbound FDMA Translation RegionConfigure PCIESLV_FDMAFDMA_OFFSET = 1 and select address translation region 1 by writing ATU_REGIONATU_IDX = 1

Set PCIEATU_BASE_ADDR_LOWATU_BASE_ADDR_LOW = 0x4000 and PCIEATU_LIMIT_ADDRATU_LIMIT_ADDR = 0x7FFF

The FDMA PCIe header must be MRdMWr type reorderable cache-coherent and without ECRC Remaining header fields are automatically handled

Configure low address of destination window in PCIe memory space as follows

Enable address translation by writing ATU_CFG2ATU_REGION_ENA = 1 The FDMA can be configured to make access in the 0xC0000000 - 0xFFFFFFFF address region These accesses will then be mapped to PCIe memory space as defined by ATU_TGT_ADDR_LOW and ATU_TGT_ADDR_HIGH The FDMA must be disabled if the address window needs to be updated

466 Power ManagementThe devicersquos PCIe endpoint supports D0 D1 and D3 device power-management states and associated link power-management states The switch core does not automatically react to changes in the PCIe endpointrsquos power management states It is however possible to enable a VCore-Ie interrupt on device

Traffic Class ATU_CFG1ATU_TC

Type ATU_CFG1ATU_TYPE

Byte Enables PCIESLV_SBASBA_BE

Message Code ATU_CFG2ATU_MSG_CODE

Table 146 bull FDMA PCIe Access Header Fields

Header Field RegisterFields Suggested ValueAttributes ATU_CFG1ATU_ATTR Set to 2

TLP Digest Field Present ATU_CFG1ATU_TD Set to 0

Traffic Class ATU_CFG1ATU_TC Use an appropriate traffic class

Type ATU_CFG1ATU_TYPE Set to 0

Table 145 bull PCIe Access Header Fields (continued)

Header Field RegisterFields

power state changes and then have the VCore-Ie CPU software make application-specific changes to the device operation depending on the power management state

Because the device does not implement a dedicated auxiliary power for the PCIe endpoint the endpoint is operated from the VDD core power supply Before the power management driver initializes the device software can ldquoforcerdquo auxiliary power detection by writing PCIE_AUX_CFG = 3 which causes the endpoint to report that it is capable of emitting Power Management Events (PME) messages in the D3c state

The current device power management state is available using PCIE_STATPM_STATE A change in this fieldrsquos value sets the PCIE_INTRINTR_PM_STATE sticky bit To enable this interrupt set PCIE_INTR_ENAINTR_PM_STATE_ENA The current state of the PCIe endpoint interrupt towards the VCore-Ie interrupt controller is shown in PCIE_INTR_IDENT register (if different from zero then interrupt is active)

The endpoint can emit PMEs if the PME_En bit is set in the PM Capability Register Set and if the endpoint is in power-down mode

bull Outbound request from either SBA or FDMA trigger PMEbull A change in status for an enabled outbound interrupt (either legacy or MSI) triggers PME This

feature can be disabled by setting ICPU_CFGPCIE_INTR_COMMON_CFGWAKEUP_ON_INTR_DIS

In the D3 state the endpoint transmits a beacon The beacon function can be disabled and instead drive the WAKE output using the overlaid GPIO function For more information about the overlaid function on the GPIO for this signal see GPIO Overlaid Functions page 204

Enable WAKE by setting PCIEPCS_CFGBEACON_DIS The polarity of the WAKE output is configured in PCIEPCS_CFGWAKE_POL The drive scheme is configured in PCIEPCS_CFGWAKE_OE

467 Device Reset Using PCIeThe built-in PCIe reset mechanism in the PCIe endpoint resets only the PCIe MAC The device reset is not tied into the MAC reset To reset the complete the device use the following procedure

1 Save the state of the PCIe controller registers using operating system2 Set DEVCPU_GCBSOFT_RSTSOFT_CHIP_RST3 Wait for 100 ms4 Recover state of PCIe controller registers using operating systemSetting SOFT_CHIP_RST will cause re-initialization of the device

Table 147 bull Power Management Registers

Register DescriptionICPU_CFGPCIE_STAT Current power management state

ICPU_CFGPCIEPCS_CFG Configuration of WAKE output and beacon

ICPU_CFGPCIE_INTR PCIe interrupt sticky events

ICPU_CFGPCIE_INTR_ENA Enable of PCIe interrupts

ICPU_CFGPCIE_INTR_IDENT Currently interrupting PCIe sources

ICPU_CFGPCIE_AUX_CFG Configuration of auxiliary power detection

Table 148 bull PCIe Wake Pin

Pin Name IO DescriptionPCIe_WAKEGPIO O PCIe WAKE output

47 Frame DMAThis section describes the Frame DMA engine (FDMA) When FDMA is enabled Ethernet frames can be extracted or injected autonomously to or from PCIe memory space Linked list data structures in memory are used for injecting or extracting Ethernet frames The FDMA generates interrupts when frame extraction or injection is done and when the linked lists needs updating

Table 149 bull FDMA Registers

Register DescriptionDEVCPU_QSXTR_GRP_CFG CPU port ownership extraction direction

DEVCPU_QSINJ_GRP_CFG CPU port ownership injection direction

DEVCPU_QSINJ_CTRL Injection EOF to SOF spacing

SYSPORT_MODE Enables IFH and disables FCS recalculation (forinjected frames)

ICPU_CFGFDMA_CH_CFG Channel configuration priorities and so on

ICPU_CFGFDMA_CH_ACTIVATE Enables channels

ICPU_CFGFDMA_CH_DISABLE Disables channels

ICPU_CFGFDMA_CH_STAT Status for channels

ICPU_CFGFDMA_CH_SAFE Sets when safe to update channel linked lists

ICPU_CFGFDMA_DCB_LLP Linked list pointer for channels

ICPU_CFGFDMA_DCB_LLP_PREV Previous linked list pointer for channels

ICPU_CFGFDMA_CH_CNT Software counters for channels

ICPU_CFGFDMA_INTR_LLP NULL pointer event for channels

ICPU_CFGFDMA_INTR_LLP_ENA Enables interrupt on NULL pointer event

ICPU_CFGFDMA_INTR_FRM Frame done event for channels

ICPU_CFGFDMA_INTR_FRM_ENA Enables interrupt on frame done event

ICPU_CFGFDMA_INTR_SIG SIG counter incremented event for channels

ICPU_CFGFDMA_INTR_SIG_ENA Enables interrupt on SIG counter event

ICPU_CFGMANUAL_INTR Manual injectionextraction events

ICPU_CFGMANUAL_INTR_ENA Enables interrupts on manual injectionextraction events

ICPU_CFGFDMA_EVT_ERR Error event for channels

ICPU_CFGFDMA_EVT_ERR_CODE Error event description

ICPU_CFGFDMA_INTR_ENA Enables interrupt for channels

ICPU_CFGFDMA_INTR_IDENT Currently interrupting channels

DEVCPU_QSXTR_FRM_PRUNING Enables pruning of extraction frames

ICPU_CFGFDMA_CH_INJ_TOKEN_CNT Injection tokens

ICPU_CFGFDMA_CH_INJ_TOKEN_TICK_RLD Periodic addition of injection tokens

ICPU_CFGMANUAL_CFG Configures manual injectionextraction

ICPU_CFGMANUAL_XTR Memory region used for manual extraction

ICPU_CFGMANUAL_INJ Memory region used for manual injection

ICPU_CFGFDMA_GCFG Configures injection buffer watermark

The FDMA implements two extraction channels per CPU port and a total of eight injection channels Extraction channels are hard-coded per CPU port and injection channels can be individually assigned to any CPU port

bull FDMA channel 0 corresponds to port 11(group 0) extraction directionbull FDMA channel 1 corresponds to port 12(group 1) extraction directionbull FDMA channel 2 through 9 corresponds to port 11 (group 0) injection direction when

FDMA_CH_CFG[channel]CH_INJ_GRP is set to 0bull FDMA channel 2 through 9 corresponds to port 12 (group 1) injection direction when

FDMA_CH_CFG[channel]CH_INJ_GRP is set to 1The FDMA implements a strict priority scheme Injection and extraction channels can be assigned individual priorities which are used when the FDMA has to decide between servicing two or more channels Channel priority is configured in FDMA_CH_CFG[ch]CH_PRIO When channels have same priority the higher channel number takes priority over the lower channel number

When more than one injection channel is enabled for injection on the same CPU port then priority determines which channel that is allowed to inject data Ownership is re-arbitrated on frame boundaries

The internal frame header is added in front of extracted frames and provides useful switching information about the extracted frames

Injection frames requires an internal frame header for controlling injection parameters The internal frame header is added in front of frame data The device recalculates and overwrites the Ethernet FCS for frames that are injected through the CPU when requested by setting in the internal frame header

For more information about the extraction and injection IFH see CPU Port Module page 141

The FDMA supports a manual mode where the FDMA decision logic is disabled and the FDMA takes and provides data in the order that was requested by an external master (internal or external CPU) The manual mode is a special case of normal FDMA operation where only few of the FDMA features apply For more information about manual operation see Manual Mode

The following configuration must be performed before enabling FDMA extraction Set XTR_GRP_CFG[group]MODE = 2

The following configurations must be performed before enabling FDMA injection

Set INJ_GRP_CFG[group]MODE = 2 Set INJ_CTRL[group]GAP_SIZE = 0

set PORT_MODE[port]INCL_INJ_HDR = 1

471 DMA Control Block StructuresThe FDMA processes linked lists of DMA Control Block Structures (DCBs) The DCBs have the same basic structure for both injection or for extraction A DCB must be placed on a 32-bit word-aligned address in memory Each DCB must have an associated data block that is placed on a 32-bit word aligned address in memory the length of the data block must be a complete number of 32-bit words

An Ethernet frame can be contained inside one data block (if the data block is big enough) or the frame can be spread across multiple data blocks A data block never contains more than one Ethernet frame Data blocks that contain start-of-frame have set a special bit in the DCBrsquos status word likewise for data blocks that contains end of frame The FDMA stores or retrieves Ethernet frame data in network order This means that the data at byte address (n) of a frame was received just before the data at byte address (n + 1)

Frame data inside the DCBrsquos associated data blocks can be placed at any byte offset and have any byte length as long as byte offset and length does not exceed the size of the data block Byte offset and length is configured using special fields inside the DCB status word Software can specify offset both when setting up extraction and injection DCBs Software only specifies length for injection DCBs the FDMA automatically calculates and updates length for extraction

Example If a DCBrsquos status word has block offset 5 and block length 2 then the DCBrsquos data block contains two bytes of frame data placed at second and third bytes inside the second 32-bit word of the DCBrsquos associated data block

DCBs are linked together by the DCBrsquos LLP field The last DCB in a chain must have LLP = NULL Chains consisting of a single DCB are allowed

Figure 66 bull FDMA DCB Layout

472 Enabling and Disabling FDMA ChannelsTo enable a channel (ch) write a valid DCB pointer to FDMA_DCB_LLP[ch] and enable the channel by setting FDMA_CH_ACTIVATECH_ACTIVATE[ch] This makes the FDMA load the DCB from memory and start either injection or extraction

To schedule a channel for disabling set FDMA_CH_DISABLECH_DISABLE[ch] An active channel does not disable immediately Instead it waits until the current data block is done saves the status word and then disables

Channels can be in one of three states DISABLED UPDATING or ACTIVE Channels are DISABLED by default When the channel is reading a DCB or writing the DCB status word it is considered to be UPDATING The status of individual channels is available in FDMA_CH_STATCH_STAT[ch]

The following illustration shows the FDMA channel states

BLOCKL [150] Number of frame-data bytes in the data block BLOCKL does not

include offset bytes

[3124] For SW use FDMA will not

modify

DATAL [150] Number of bytes available in the data block associated with this DCB

DATAL must be a complete number of words (bit [10] = 00)

DATAP [310] Data block pointer this field points to the data block associated with this DCB DATAP must be =NULL and must point to a word-aligned address (bit [10] = 00)

LLP [310] Linked List Pointer this field points to the next DCB in the list set to NULL for end of list DCBs must be word-aligned which means LLP must point to a word-aligned

address (bit [10] = 00)word-address n

STAT[16] SOF Set to 1 if data block contains start of frame

STAT[17] EOF Set to 1 if data block contains end of frame

STAT[18] ABORT Abort indicationExtraction Set to 1 if the frame associated with the data block was abortedInjection If set to 1 when FDMA loads the DCB it aborts the frame associated with the data block

STAT[19] PD PrunedDone indicationExtraction Set to 1 if the frame associated with the data block was prunedInjection The FDMA set this to 1 when done processing the DCB If set to 1 when FDMA loads the DCB it is treated as ABORT

[2318]Must be 0

DATAL[16] SIG If set to 1 when FDMA loads the DCB the CH_CNT_SIG counter is incremented by one

16171819

BLOCKO [3120] Byte offset from beginning of the data block to the first byte of frame-data

DATAL[17] TOKEN Token indication only used during injectionIf set to 1 the FDMA uses one token (CH_INJ_TOKEN_CNT) when injecting the contents of the DCB If the token counter is 0 when loading the DCB then injection is postponed until tokens are made available

Figure 67 bull FDMA Channel States

A channel that has FDMA_DCB_LLP[ch]DCB_LLP==NULL when going from ACTIVE to UPDATING disables itself instead of loading a new DCB After this it can be re-enabled as previously described Extraction channels emit an INTR_LLP-event when loading a DCB with LLP==NULL Injection channels emit an INTR_LLP-event when saving status for a DCB that has the LLP==NULL

Note Extraction channel running out of DCBs during extraction is a problem that software must avoid A hanging extraction channel will potentially be head-of-line blocking other extraction channels

It is possible to update an active channels LLP pointer and pointers in the DCB chains Before changing pointers software must schedule the channel for disabling (by writing FDMA_CH_DISABLECH_DISABLE[ch]) and then wait for the channel to set FDMA_CH_SAFECH_SAFE[ch] When the pointer update is complete soft must re-activate the channel by setting FDMA_CH_ACTIVATECH_ACTIVATE[ch] Setting activate will cancel the deactivate-request or if the channel has disabled itself in the meantime it will re activate the channel

Note The address of the current DCB is available in FDMA_DCB_LLP_PREV[ch] This information is useful when modifying pointers for an active channel The FDMA does not reload the current DCB when re-activated so if the LLP-field of the current DCB is modified then software must also modify FDMA_DCB_LLP[ch]

Setting FDMA_CH_CFG[ch]DONEEOF_STOP_ENA disables an FDMA channel and emits LLP-event after saving status for DCBs that contains EOF (after extracting or injecting a complete frame) Setting FDMA_CH_CFG[ch]DONE_STOP_ENA disables an FDMA channel and emits LLP-event after saving status for any DCB

473 Channel CountersThe FDMA implements three counters per channel SIG DCB and FRM These counters are accessible through FDMA_CH_CNT[ch]CH_CNT_SIG FDMA_CH_CNT[ch]CH_CNT_DCB and

DISABLED

UPDATING

ACTIVE

Update STAT word at address ICPU_CFGFDMA_DCB_LLP_PREV[ch] + 0xC

Disable when DCBLLP == NULL or user requested DISABLE of channel

Enable when user requested ACTIVATE of channel

Load DCB from address ICPU_CFGFDMA_DCB_LLP[ch]

FDMA_CH_CNT[ch]CH_CNT_FRM respectively For more information about how to safely modify these counters see the register descriptions

bull The SIG (signal) counter is incremented by one each time the FDMA loads a DCB that has the DATALSIG bit set to 1

bull The FRM (frame) counter is incremented by one each time the FDMA store status word for DCB that has EOF set It is a wrapping counter that can be used for software driver debug and development This counter does not count aborted frames

bull The DCB counter is incremented by one every time the FDMA loads a DCB from memory It is a wrapping counter that can be used for software driver debug and development

It is possible to enable channel interrupt whenever the SIG counter is incremented this makes it possible for software to receive interrupt when the FDMA reaches certain points in a DCB chain

474 FDMA Events and InterruptsEach FDMA channel can generate four events LLP-event FRM-event SIG-event and ERR-event These events cause a bit to be set in FDMA_INTR_LLPINTR_LLP[ch] FDMA_INTR_FRMINTR_FRM[ch] FDMA_INTR_SIGINTR_SIG[ch] and FDMA_EVT_ERREVT_ERR[ch] respectively

bull LLP-event occurs when an extraction channel loads a DCB that has LLP = NULL or when an injection channel writes status for a DCB that has LLP=NULL LLP-events are also emitted from channels that have FDMA_CH_CFG[ch]DONEEOF_STOP_ENA or FDMA_CH_CFG[ch]DONE_STOP_ENA set For more information see Enabling and Disabling FDMA Channels

bull FRM-event is indicated when an active channel loads a new DCB and the previous DCB had EOF The FRM-event is also indicated for channels that are disabled after writing DCB status with EOF

bull SIG-event is indicated whenever the FDMA_CH_CNT[ch]CH_CNT_SIG counter is incremented The SIG (signal) counter is incremented when loading a DCB that has the DATALSIG bit set

bull ERR-event is an error indication that is set for a channel if it encounters an unexpected problem during normal operation This indication is implemented to ease software driver debugging and development A channel that encounters an error will be disabled depending on the type of error the channel state may be too corrupt for it to be restarted without system reset When an ERR-event occurs the FDMA_EVT_ERR_CODEEVT_ERR_CODE shows the exact reason for an ERR-event For more information about the errors that are detected see FDMA_EVT_ERR_CODEEVT_ERR_CODE

Each of the events (LLP FRM SIG) can be enabled for channel interrupt through FDMA_INTR_LLP_ENAINTR_LLP_ENA[ch] FDMA_INTR_FRM_ENAINTR_FRM_ENA[ch] and FDMA_INTR_SIGINTR_SIG[ch] respectively The ERR event is always enabled for channel interrupt

The highest numbered extraction channel supports two additional non-sticky events related to manual extraction XTR_SOF_RDY-event and XTR_ANY_RDY-event An active event causes the following fields to be set MANUAL_INTRINTR_XTR_SOF_RDY and MANUAL_INTRINTR_XTR_ANY_RDY respectively For more information see Manual Extraction

bull XTR_SOF_RDY-event is active when the next word to be manually extracted contains an SOF indication This event is enabled in MANUAL_INTR_ENAINTR_XTR_SOF_RDY_ENA

bull XTR_ANY_RDY-event is active when any word is available for manually extraction This event is enabled in MANUAL_INTR_ENAINTR_XTR_ANY_RDY_ENA respectively

The highest numbered injection channel supports one additional non-sticky event related to manual injection INJ_RDY-event This event is active when the injection logic has room for (at least) sixteen 32-bit words of injection frame data When this event is active MANUAL_INTRINTR_INJ_RDY is set The INJ_RDY-event can be enabled for channel interrupt by setting MANUAL_INTR_ENAINTR_INJ_RDY_ENA For more information see Manual Injection

The FDMA_INTR_ENAINTR_ENA[ch] field enables interrupt from individual channels FDMA_INTR_IDENTINTR_IDENT[ch] field shows which channels that are currently interrupting While INTR_IDENT is non-zero the FDMA is indicating interrupting towards to the VCore-Ie interrupt controller

The following illustration shows the FDMA channel interrupt hierarchy

Figure 68 bull FDMA Channel Interrupt Hierarchy

475 FDMA ExtractionDuring extraction the FDMA extracts Ethernet frame data from the Queuing System and saves it into the data block of the DCB that is currently loaded by the FDMA extraction channel The FDMA continually processes DCBs until it reaches a DCB with LLP = NULL or until it is disabled

When an extraction channel writes the status word of a DCB it updates SOFEOFABORTPRUNED-indications and BLOCKL BLOCKO remains unchanged (write value is taken from the value that was read when the DCB was loaded)

Aborting frames from the queuing system will not occur during normal operation If the queuing system is reset during extraction of a particular frame then ABORT and EOF is set Software must discard frames that have ABORT set

Pruning of frames during extraction is enabled per extraction port through XTR_FRM_PRUNING[group]PRUNE_SIZE When enabled Ethernet frames above the configured size are truncated and PD and EOF is set

476 FDMA InjectionDuring injection the FDMA reads Ethernet frame data from the data block of the DCB that is currently loaded by the FDMA injection channel and injects this into the queuing system The FDMA continually processes DCBs until it reaches a DCB with LLP = NULL or until it is disabled

When an injection channel writes the status word of a DCB it sets DONE indication All other status word fields remain unchanged (write value is stored the first time the injection channel loads the DCB)

The rate by which the FDMA injects frames can be shaped by using tokens Each injection channel has an associated token counter (FDMA_CH_INJ_TOKEN_CNT[ich]) A DCB that has the DATALTOKEN field set causes the injection channel to deduct one from the token counter before the data block of the DCB can be injected If the token counter is at 0 the injection channel postpones injection until the channels token counter is set to a value different from 0

INTR_LLP[ch]

INTR_LLP_ENA[ch]AND

ORINTR_IDENT[ch]AND

INTR_ENA[ch]

EVT_ERR[ch]

INTR_FRM[ch]

INTR_FRM_ENA[ch]AND

INTR_SIG[ch]

INTR_SIG_ENA[ch]AND

INTR_XTR_SOF_RDY

INTR_XTR_SOF_RDY_ENAAND

INTR_XTR_ANY_RDY

INTR_XTR_SOF_ANY_ENAAND

INTR_INJ_RDY

INTR_INJ_RDY_ENAAND

Only for highest numbered extraction channel

Only for highest numbered injection channel

Tokens can be added to the token counter by writing the FDMA_CH_INJ_TOKEN_CNT[ich] register Tokens can also be added automatically (with a fixed interval) by using the dedicated token tick counter Setting FDMA_CH_INJ_TOKEN_TICK_RLD[ich] to a value n (different from 0) will cause one token to be added to that injection channel every n x 200 ns

477 Manual ModeThe decision making logic of the FDMA extraction path andor injection paths can be disabled to give control of the FDMArsquos extraction andor injection buffers directly to any master attached to the Shared Bus Architecture When operating in manual mode DCB structure counters and most of the interrupts do not apply

Manual extraction and injection use hard-coded channel numbers

bull Manual extraction mode uses FDMA channel 1 (port 12 extraction direction)bull Manual injection mode uses FDMA channel 9 (port 12 injection direction)To enable manual extraction set MANUAL_CFGXTR_ENA The FDMA must not be enabled for FDMA extraction when manual extraction mode is active To enable manual injection set MANUAL_CFGINJ_ENA and FDMA_CH_CFG[9]CH_INJ_CRP = 1 The FDMA must not be enabled for FDMA injection when manual injection mode is active Extraction and injection paths are independent For example FDMA can control extraction at the same time as doing manual injection by means of the CPU

4771 Manual ExtractionExtraction is done by reading one or more blocks of data from the extraction memory area A block of data is defined by reading one or more data words followed by reading of the extraction status word The extraction memory area is 16 kilobytes and is implemented as a replicated register region MANUAL_XTR The highest register in the replication (0xFFF) maps to the extraction status word The status word is updated by the extraction logic and shows the number of frame bytes read SOF and EOF indications and PRUNEDABORT indications

Note During frame extraction the CPU does not know the frame length This means that the CPU must check for EOF regularly during frame extraction When reading a data block from the device the CPU can burst read from the memory area in such a way that the extraction status word is read as the last word of the burst

Figure 69 bull Extraction Status Word Encoding

The extraction logic updates the extraction status word while the CPU is reading out data for a block Prior to starting a new data block the CPU can write the two least significant bits of the BLOCKO field The BLOCKO value is stored in the extraction logic and takes effect when the new data block is started Reading the status field always returns the BLOCKO value that applies to the current data block Unless

[3120] [150]16171819

BLOCKL The amount of frame data (bytes) that has been read in this block The CPU might have read more data than this only valid frame data (including Extraction Header) is counted here

SOF Start of frame set if this block contains start of a frame

EOF End of frame set if this block contains end of a frame

ABORT Set if this frame has been aborted by the Queuing System Write lsquo1rsquo to discard the remainder of the active frame

PD Pruned indication set if the frame has been pruned to less than original length

BLOCKO The amount of dummy bytes (non-frame data) read before start of frame data

BLOCKLBLOCKO

written (before stating a data block) the BLOCKO is cleared so by default all blocks have 0 byte offset The offset can be written multiple times the last value takes effect

The CPU can abort frames that it has already started to read out by writing the extraction status field with the ABORT field set All other status-word fields will be ignored This causes the extraction logic to discard the active frame and remove it from the queuing system

Reading of block data does not have to be done in one burst As long as the status word is not read multiple reads from the extraction region are treated as belonging to the same block

4772 Manual InjectionInjection is done by writing one or more blocks of data to the injection memory area A block of data is defined by writing an injection status word followed by writing one or more data words The injection memory area is 16 kilobytes and is implemented as a replicated register region MANUAL_INJ The first register in this replication maps to the injection status word The status word for each block defines the following

bull Number of bytes to be injectedbull Optional byte offset before injection databull SOF and EOF indicationsbull Optional ABORT indicationNote In general it makes sense to inject frames as a single large block of data (containing both SOF and EOF) However because offsetlength can be specified individually for each block injecting frames through several blocks is useful when compensating for offsetword misalignment For example when building a frame from different memory regions in the CPU main memory

Figure 70 bull Injection Status Word Encoding

Injection logic updates the PD field of the status word The status word can be read at any time during injection without affecting current data block transfers However a CPU is able to calculate how much data that is required to inject a complete block of data (at least BLOCKO + BLOCKL bytes) so reading the status word is for software development and debug only Writing status word before finishing a previous data block will cause that frame to be aborted Frames are also aborted if they do not start with SOF or end with EOF indications

As long as the status word is not written multiple writes to the injection region are treated as data belonging to the same block This means multiple bursts of data words can be written between each injection status word update

[3120] [150]16171819

BLOCKL The amount of frame data (bytes) that will be written for this block The CPU is allowed to write more data than this additional data will be ignored

SOF Start of frame set to indicate that this block contains start of a frame

EOF End of frame set to indicate that this block contains end of a frame

ABORT Set to abort active frame transfer The current frame will be aborted and removed from Queuing System

PD Injection done is set by the injection logic when enough data has been received for this block of data (BLOCKO+BLOCKL) If set when writing status word then this is treated as if ABORT had been set

BLOCKO The amount of dummy bytes (non-frame data) to expect before the frame data The dummy data will be ignored

BLOCKLBLOCKO

Software can abort frames by writing to injection status with ABORT field set All other status word fields are ignored When a frame is aborted the already injected data is removed from the queuing system

48 VCore-Ie System PeripheralsThis section describes the subblocks of the VCore-Ie system Although the subblocks are primarily intended to be used by the VCore-Ie CPU an external CPU can also access and control them through the shared bus

481 SI Boot ControllerThe SPI boot master allows booting from a Flash that is connected to the serial interface For information about how to write to the serial interface see SI Master Controller page 193 For information about using an external CPU to access device registers using the serial interface see Serial Interface in Slave Mode page 170

The following table lists the registers associated with the SI boot controller

By default the SI boot controller operates in 24-bit address mode In this mode there are four programmable chip selects when the VCore-Ie system controls the SI Each chip select can address up to 16 megabytes (MB) of memory

Figure 71 bull SI Boot Controller Memory Map in 24-Bit Mode

The SI boot controller can be reconfigured for 32-bit address mode through SPI_MST_CFGA32B_ENA In 32-bit mode the entire SI region of 256 megabytes (MB) is addressed using chip select 0

Reading from the memory region for a specific SI chip select generates an SI read on that chip select The VCore-Ie CPU can execute code directly from Flash by executing from the SI boot controllerrsquos memory region For 32-bit capable SI Flash devices the VCore-Ie must start up in 24-bit mode During the boot process it must manually reconfigure the Flash device (and SI boot controller) into 32-bit mode and then continue booting

The SI boot controller accepts 8-bit 16-bit and 32-bit read access with or without bursting Writing to the SI requires manual control of the SI pins using software Setting SW_MODESW_PIN_CTRL_MODE

Table 150 bull SI Boot Controller Configuration Registers

Register DescriptionICPU_CFGSPI_MST_CFG Serial interface speed and address width

ICPU_CFGSW_MODE Legacy manual control of the serial interface pins

SI Controller Memory Map

Chip Select 0 SI_nCS0SI Controller

Chip Select 1 SI_nCS1+0x01000000

Chip Select 2 SI_nCS216 MB

+0x02000000

+0x03000000

SI Controller Memory Map (32- bit)

Chip Select 0 SI_nCS0

SI Controller256 MB

places all SI pins under software control Output enable and the value of SI_CLK SI_DO SI_nCSn are controlled through the SW_MODE register The value of the SI_DI pin is available in SW_MODESW_SPI_SDI The software control mode is provided for legacy reasons new implementations should use the dedicated master controller for writing to the serial interface For more information see SI Master Controller page 193

Note The VCore-Ie CPU cannot execute code directly from the SI boot controllerrsquos memory region at the same time as manually writing to the serial interface

The following table lists the serial interface pins when the SI boot controller is configured as owner of SI interface in GENERAL_CTRLIF_SI_OWNER For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The SI boot controller does speculative pre-fetching of data After reading address n the SI boot controller automatically continues reading address n + 1 so that the next value is ready if requested by the VCore-Ie CPU This greatly optimizes reading from sequential addresses in the Flash such as when copying data from Flash into program memory

The following illustrations depict 24-bit address mode When the controller is set to 32-bit mode (through SPI_MST_CFGA32B_ENA) 32 address bits are transferred instead of 24

Figure 73 bull SI Read Timing in Normal Mode

Figure 74 bull SI Read Timing in Fast Mode

The default timing of the SI boot controller operates with most serial interface Flash devices Use the following process to calculate the optimized serial interface parameters for a specific SI device

Table 151 bull Serial Interface Pins

Pin Name IO DescriptionSI_nCS0SI_nCS[31]GPIO

O Active low chip selects Only one chip select can be active at any time Chip selects 1 through 3 are overlaid functions on GPIO pins

SI_CLK O Clock output

SI_DO O Data output (MOSI)

SI_DI I Data input (MISO)

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

5 4 3 2 1 067

Data Byte 0

24 Bit Address

5 4 3 2 1 067

Data Byte 1

5 4 3 2 1 067

Data Byte 2

5 4 3 2 1 067

Data Byte 3

SI_nCS0

SI_CLK

10 9 8 7 6 5 4 3 2 1 0

FAST_READ

5 4 3 2 1 067

Data Byte 0

24 Bit Address

5 4 3 2 1 067

Data Byte 1

5 4 3 2 1 067

Data Byte 2

5 4 3 2 1 067

Data Byte 3

Dummy Byte

1 Calculate an appropriate frequency divider value as described in SPI_MST_CFGCLK_DIV The SI operates at no more than 25 MHz and the maximum frequency of the SPI device must not be exceeded The VCore-Ie system frequency in the device is 250 MHz

2 The SPI device may require a FAST_READ command rather than normal READ when the SI frequency is increased Setting SPI_MST_CFGFAST_READ_ENA makes the SI boot controller use FAST_READ commands

3 Calculate SPI_MST_CFGCS_DESELECT_TIME so that it matches how long the SPI device requires chip-select to be deasserted between access This value depends on the SI clock period that results from the SPI_MST_CFGCLK_DIV setting

These parameters must be written to SPI_MST_CFG The CLK_DIV field must either be written last or at the same time as the other parameters The SPI_MST_CFG register can be configured while also booting up from the SI

When the VCore-Ie CPU boots from the SI interface the default values of the SPI_MST_CFG register are used until the SI_MST_CFG is reconfigured with optimized parameters This implies that SI_CLK is operating at approximately 81 MHz with normal read instructions and maximum gap between chip select operations to the Flash

Note The SPI boot master does optimized reading SI_DI (from the Flash) is sampled just before driving falling edge on SI_CLK (to the Flash) This greatly relaxes the round trip delay requirement for SI_CLK to SI_DI allowing high Flash clock frequencies

482 SI Master ControllerThis section describes the SPI master controller (SIMC) and how to use it for accessing external SPI slave devices such as programming of a serially attached Flash device on the boot interface VCore booting from serial Flash is handled by the SI boot master

The following table lists the registers associated with the SI master controller

Table 152 bull SI Master Controller Configuration Registers Overview

Register DescriptionSIMCCTRLR0 Transaction configuration

SIMCCTRLR1 Configurations for receive-only mode

SIMCSIMCEN SI master controller enable

SIMCSER Slave select configuration

SIMCBAUDR Baud rate configuration

SIMCTXFTLR Tx FIFO threshold level

SIMCRXFTLR Rx FIFO Threshold Level

SIMCTXFLR Tx FIFO fill level

SIMCRXFLR Rx FIFO fill level

SIMCSR Various status indications

SIMCIMR Interrupt enable

SIMCISR Interrupt sources

SIMCRISR Unmasked interrupt sources

SIMCTXOICR Clear of transmit FIFO overflow interrupt

SIMCRXOICR Clear of receive FIFO overflow interrupt

SIMCRXUICR Clear of receive FIFO underflow interrupt

SIMCDR TxRx FIFO access

SIMCRX_SAMPLE_DLY RXD sample delay

ICPU_CFGGENERAL_CTRL Interface configurations

The SI master controller supports Motorola SPI and Texas Instruments SSP protocols The default protocol is SPI enable SSP by setting CTRLR0FRF = 1 and GENERAL_CTRLSSP_MODE_ENA = 1 The protocol baud rate is programmable in BAUDRSCKDV the maximum baud rate is 25 MHz

Before the SI master controller can be used it must be set as owner of the serial interface This is done by writing GENERAL_CTRLIF_SI_OWNER = 2

The SI master controller has a programmable frame size The frame size is the smallest unit when transferring data over the SI interface Using CTRLR0DFS the frame size is configured in the range of 4 bits to 16 bits When reading or writing words from the transmitreceive FIFO the number of bits that is stored per FIFO-word is always equal to frame size (as programmed in CTRLR0DFS)

The controller operates in one of three following major modes Transmit and receive transmit only or receive only The mode is configured in CTRLR0TMOD

Transmit and receive software paces SI transactions For every data frame that software writes to the transmission FIFO another data frame is made available in the receive FIFO (receive data from the serial interface) Transaction will go on for as long as there is data available in the transmission FIFO

Transmit only Software paces SI transactions The controller transmits only receive data is discarded Transaction will go on for as long as there is data available in the transmission FIFO

Receive only The controller paces SI transactions The controller receives only data software requests a specific number of data frames by means of CTRLR1NDF the transaction will go on until all data frames has been read from the SI interface Transaction is initiated by software writing one data frame to transmission FIFO This frame is not used for anything else than starting the transaction The SI_DO output is undefined during receive only transfers Receive data frames are put into the receive FIFO as they are read from SI

For SPI mode chip select is asserted throughout transfers Transmit transfers end when the transmit FIFO runs out of data frames Software must make sure it is not interrupted while writing data for a multi-frame transfer When multiple distinct transfers are needed wait for SRTFE = 1 and SRBUSY = 0 before initiating new transfer SRBUSY is an indication of ongoing transfers however it is not asserted immediately when writing frames to the FIFO As a result software must also check the SRTFE (transmit FIFO empty) indication

The SI master controller supports up to 5 chip selects Chip select 0 is mapped to the SI_nCS pin of the serial interface The remaining chips selects are available using overlaid GPIO functions Software controls which chip selects to activate for a transfer using the SER register For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

Writing to any DR replication index put data into the transmission FIFO and reading from any DR replication index take out data from the receive FIFO FIFO status indications are available in the SR registerrsquos TFE TFNF RFF and RFNE fields For information about interrupting on FIFO status see SIMC Interrupts page 196

It is important to delay the sample of the RXD input signal by writing to SIMCRX_SAMPLE_DLY Each value represents a single VCore system clock cycle delay on the sample If this field is programmed with a value that exceeds 25 a zero (0) delay will be applied For optimal operation it is suggested to set the value to SIMCBAUD2 but no larger than 25 This will delay sampling of RX-data by half clock cycle for SPI frequencies above 5MHz Below 5 MHz the sampling delay will be 100ns It is impossible to write to this register when the SIMC is enabled

Table 153 bull SI Master Controller Pins

O Active low chip selects Chip selects 1 through 4 are overlaid functions on the GPIO pins

After completing all initial configurations the SI master controller is enabled by writing SIMCENSIMCEN = 1 Some registers can only be written when the controller is in disabled state This is noted in the register-descriptions for the affected registers

4821 SPI ProtocolWhen the SI master controller is configured for SPI mode clock polarity and position is configurable in CTRLR0SCPH and CTRLR0SCPOL The following illustration shows the four possible combinations for 8-bit transfers

Figure 75 bull SIMC SPI Clock Configurations

Data is sampled in the middle of the data-eye

When using SPI protocol and transferring more than one data frame at the time the controller performs one consecutive transfer The following illustration shows a transfer of three data frames of 4 bits each

Note Transmitting transfers end when the transmit FIFO runs out of data frames Receive only transfers end when the pre-defined number of data-frames is read from the SI interface

Figure 76 bull SIMC SPI 3x Transfers

4822 SSP ProtocolThe SSP protocol for transferring two 6-bit data frames is shown in the following illustration When using SSP mode CTRLR0SCPH and CTRLR0SCPOL must remain zero

SI_nCS0

SI_CLK

7 5 4 3 2 1 0

CTRLR0SCPH = 0 CTRLR0SCPOL = 0

SI_nCS0

SI_CLK

7 5 4 3 2 1 0

SI_nCS0

SI_CLK

7 5 4 3 2 1 0

SI_nCS0

SI_CLK

7 5 4 3 2 1 0

7 5 4 3 2 1 06 7 5 4 3 2 1 06

7 5 4 3 2 1 067 5 4 3 2 1 06

SI_nCS0

SI_CLK

3 1 0 3 2 1 0

First frame

3 1 0 3 2 1 02

3 2 1 0

Second frame Third frame

4823 SIMC SSP 2x Transfers

4824 SIMC InterruptsThe SI master controller has five interrupt sources

bull RXF interrupt is asserted when the fill level of the receive FIFO (available in RXFLR) exceeds the programmable level set in RXFTLR This interrupt is non-sticky it is deasserted when fill level is decreased below the programmable level

bull RXO interrupt is asserted on receive FIFO overflow This interrupt is cleared by reading the RXOICR register

bull RXU interrupt is asserted when reading from an empty receive FIFO This interrupt is cleared by reading the RXUICR register

bull TXO interrupt is asserted when writing to a full transmit FIFO This interrupt is cleared by reading the TXOICR register

bull TXE interrupt is asserted when the fill level of the transmit FIFO (available in TXFLR) is below the programmable level set in TXFTLR This interrupt is non-sticky it is deasserted when fill level is increased above the programmable level

The raw (unmasked) status of these interrupts is available in the RISR register Each of the interrupts can be individually masked by the IMR register All interrupts are enabled by default The currently active interrupts are shown in the ISR register

If the RXO RXU and TXO interrupts occur during normal use of the SI master controller it is an indication of software problems

Interrupt is asserted towards the VCore-Ie interrupt controller when any enabled interrupt is asserted and the SI master controller is enabled

4825 SIMC Programming ExampleThis example shows how to use the SI master controller to interface with the SI slave of another device The slave device will be initialized for big endianmost significant bit first mode and then the DEVCPU_GCBGPR register is written with the value 0x01234567 It is assumed that the other devicersquos SI slave is connected on SI_nCS1 (and that appropriate GPIO alternate function has been enabled)

The SI slave is using a 24-bit address field and a 32-bit data field This example uses 4 x 16-bit data frames to transfer the write-access This means that 8 bits too much will be transferred this is not a problem for the SI slave interface it ignores data above and beyond the 56 bit required for a write-access

For information about initialization and how to calculate the 24-bit SI address field see Serial Interface in Slave Mode page 170 The address-field when writing DEVCPU_GCBGPR is 0x804001 (including write-indication)

The following steps are required to bring up the SI master controller and write twice to the SI slave device

Important The following procedure disconnects the SI boot master from the SI interface Booting must be done before attempting to overtake the boot-interface

1 Write GENERAL_CTRLIF_SI_OWNER = 2 to make SI master controller the owner of the SI interface

2 Write BAUDR = 250 to get 1 MHz baud rate3 Write SER = 2 to use SI_nCS1

SI_nCS0

SI_CLK

5 3 2 3 2 1 0

First frame

5 3 2 3 2 1 04

1 0 5 4

Second frame

4 Write CTRLR0 = 0x10F for 16-bit data frame and transmit only5 Write SIMCEN = 1 to enable the SI master controller6 Write DR[0] = 0x8000 0x0081 0x8181 0x8100 to configure SI slave for big endian most significant

bit first mode7 Wait for SRTFE = 1 and SRBUSY = 0 for chip select to deassert between accesses to the SI slave8 Write DR[0] = 0x8040 0x0101 0x2345 0x6700 to write DEVCPU_GCBGPR in slave device9 Wait for SRTFE = 1 and SRBUSY = 0 then disable the SI master controller by writing SIMCEN = 0When reading from the SI slave CTRLR0TMOD must be configured for transmit and receive One-byte padding is appropriate for a 1 MHz baud rate

483 TimersThis section provides information about the timers The following table lists the registers associated with timers

There are three decrementing 32-bit timers in the VCore-Ie system that run from a common divider The common divider is driven by a fixed 250 MHz clock and can generate timer ticks from 01 micros (10 MHz) to 1 ms (1 kHz) configurable through TIMER_TICK_DIV The default timer tick is 100 micros (10 kHz)

Software can access each timer value through the TIMER_VALUE[n] registers These can be read or written at any time even when the timers are active

When a timer is enabled through TIMER_CTRL[n]TIMER_ENA it decrements from the current value until it reaches zero An attempt to decrement a TIMER_VALUE[n] of zero generates interrupt and assigns TIMER_VALUE[n] to the contents of TIMER_RELOAD_VALUE[n] Interrupts generated by the timers are sent to the VCore-Ie interrupt controller From here interrupts can be forwarded to the VCore-Ie CPU or to an external CPU For more information see Interrupt Controller

By setting TIMER_CTRL[n]ONE_SHOT_ENA the timer disables itself after generating one interrupt By default timers will decrement interrupt and reload indefinitely (or until disabled by clearing TIMER_CTRL[n]TIMER_ENA)

A timer can be reloaded from TIMER_RELOAD_VALUE[n] at the same time as it is enabled by setting TIMER_CTRL[n]FORCE_RELOAD and TIMER_CTRL[n]TIMER_ENA at the same time

Example Configure Timer0 to interrupt every 1 ms With the default timer tick of 100 micros ten timer ticks are needed for a timer that wraps every 1 ms Configure TIMER_RELOAD_VALUE[0] to 0x9 then enable the timer and force a reload by setting TIMER_CTRL[0]TIMER_ENA and TIMER_CTRL[0]FORCE_RELOAD at the same time

484 UARTsThis section provides information about the UART (Universal Asynchronous ReceiverTransmitter) controllers There are two independent UART controller instances in the VCore-Ie system UART and UART2 These instances are identical copies and anywhere in this description the word UART can be replaced by UART2

Table 154 bull Timer Registers

Register DescriptionICPU_CFGTIMER_CTRL Enabledisable timer

ICPU_CFGTIMER_VALUE Current timer value

ICPU_CFGTIMER_RELOAD_VALUE Value to load when wrapping

ICPU_CFGTIMER_TICK_DIV Common timer-tick divider

The following table lists the registers associated with the UART

The VCore-Ie system UART is functionally based on the industry-standard 16550 UART (RS232 protocol) This implementation features a 16-byte receive and a 16-byte transmit FIFO

Figure 77 bull UART Timing

The number of data bits parity parity-polarity and stop-bit lengths are all programmable using LCR

The UART pins on the device are overlaid functions on the GPIO interface Before enabling the UART the VCore-Ie CPU must enable overlaid modes for the appropriate GPIO pins For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The following table lists the pins of the UART interfaces

The baud rate of the UART is derived from the VCore-Ie system frequency The divider value is indirectly set through the RBR_THR and IER registers The baud rate is equal to the VCore-Ie system clock frequency divided by sixteen times the value of the baud rate divisor A divider of zero disables the baud rate generator and no serial communications occur The default value for the divisor register is zero

Example Configuring a baud rate of 9600 in a 250 MHz VCore-Ie system To generate a baud rate of 9600 the divisor register must be set to 0x65C (250 MHz(16 times 9600 Hz)) Set LCRDLAB and write 0x5C to RBR_THR and 0x06 to IER (this assumes that the UART is not in use) Finally clear LCRDLAB to change the RBR_THR and IER registers back to the normal mode

By default the FIFO mode of the UART is disabled Enabling the 16-byte receive and 16-byte transmit FIFOs (through IIR_FCR) is recommended

Table 155 bull UART Registers

Register DescriptionUARTRBR_THR Receive buffertransmit bufferDivisor (low)

UARTIER Interrupt enabledivisor (high)

UARTIIR_FCR Interrupt identificationFIFO control

UARTLCR Line control

UARTMCR Modem control

UARTLSR Line status

UARTMSR Modem status

UARTSCR Scratchpad

UARTUSR UART status

Table 156 bull UART Interface Pins

Pin Name IO DescriptionUART_RXDGPIO I UART receive data

UART_TXDGPIO O UART transmit data

UART2_RXDGPIO I UART2 receive data

UART2_TXDGPIO O UART2 transmit data

1 15 or 2 stop bit(s)1 start bit 5 to 8 data bits (LSB first) +

optional parity

One Character

Note Although the UART itself supports RTS and CTS these signals are not available on the pins of the device

4841 UART InterruptThe UART can generate interrupt whenever any of the following prioritized events are enabled (through IER)

bull Receiver errorbull Receiver data availablebull Character timeout (in FIFO mode only)bull Transmit FIFO empty or at or below threshold (in programmable THRE interrupt mode)When an interrupt occurs the IIR_FCR register can be accessed to determine the source of the interrupt Note that the IIR_FCR register has different purposes when reading or writing When reading the interrupt status is available in bits 0 through 3 For more information about interrupts and how to handle them see the IIR_FCR register description

Example Enabling interrupt when transmit fifo is below one-quarter full To get this type of interrupt the THRE interrupt must be used First configure TX FIFO interrupt level to one-quarter full by setting IIR_FCRTET to 10 at the same time ensure that the IIR_FCRFIFOE field is also set Set IERPTIME to enable the THRE interrupt in the UART In addition the VCore-Ie interrupt controller must be configured for the CPU to be interrupted For more information see Interrupt Controller

485 Two-Wire Serial InterfaceThis section provides information about the two-wire serial interface controller in the VCore-Ie system The following table lists the registers associated with the two-wire serial interface

Table 157 bull Two-Wire Serial Interface Registers

Register DescriptionTWICFG General configuration

TWITAR Target address

TWISAR Slave address

TWIDATA_CMD Receivetransmit buffer and command

TWISS_SCL_HCNT Standard speed high time clock divider

TWISS_SCL_LCNT Standard speed low time clock divider

TWIFS_SCL_HCNT Fast speed high time clock divider

TWIFS_SCL_LCNT Fast speed low time clock divider

TWIINTR_STAT Masked interrupt status

TWIINTR_MASK Interrupt mask register

TWIRAW_INTR_STAT Unmasked interrupt status

TWIRX_TL Receive FIFO threshold for RX_FULL interrupt

TWITX_TL Transmit FIFO threshold for TX_EMPTY interrupt

TWICLR_ Individual CLR_ registers are used for clearing specific interrupts See register descriptions for corresponding interrupts

TWICTRL Control register

TWISTAT Status register

TWITXFLR Current transmit FIFO level

TWIRXFLR Current receive FIFO level

TWITX_ABRT_SOURCE Arbitration sources

TWISDA_SETUP Data delay clock divider

The two-wire serial interface controller is compatible with the industry standard two-wire serial interface protocol The controller supports standard speed up to 100 kbps and fast speed up to 400 kbps Multiple bus masters as well as both 7-bit and 10-bit addressing are also supported

The two-wire serial interface controller operates as master only

The two-wire serial interface pins on the device are overlaid functions on the GPIO interface Before enabling the two-wire serial interface the VCore-Ie CPU must enable overlaid functions for the appropriate GPIO pins For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The following table lists the pins of the two-wire serial interface

Setting CTRLENABLE enables the controller The controller can be disabled by clearing the CTRLENABLE field there is a chance that disabling is not allowed (at the time when it is attempted) the ENABLE_STATUS register shows if the controller was successful disabled

Before enabling the controller the user must decide on either standard or fast mode (CFGSPEED) and configure clock dividers for generating the correct timing (SS_SCL_HCNT SS_SCL_LCNT FS_SCL_HCNT FS_SCL_LCNT and SDA_SETUP) The configuration of the divider registers depends on the VCore-Ie system clock frequency The register descriptions explain how to calculate the required values

Some two-wire serial devices require a hold time on TWI_SDA after TWI_SCL when transmitting from the two-wire serial interface controller The device supports a configurable hold delay through the TWI_CONFIG register

The two-wire serial interface controller has an 8-byte combined receive and transmit FIFO

During normal operation of the two-wire serial interface controller the STATUS register shows the activity and FIFO states

Figure 78 bull Two-Wire Serial Interface Timing for 7-bit Address Access

TWIACK_GEN_CALL Acknowledge of general call

TWIENABLE_STATUS General two-wire serial controller status

ICPU_CFGTWI_CONFIG Configuration of TWI_SDA hold-delay

ICPU_CFGTWI_SPIKE_FILTER_CFG Configuration of TWI_SDA spike filter

Table 158 bull Two-Wire Serial Interface Pins

Pin Name IO DescriptionTWI_SCLGPIO IO Two-wire serial interface clock open-collector output

TWI_SDAGPIO IO Two-wire serial interface data open-collector output

TWI_SCL_MnGPIO IO Two-wire serial interface multiplexed clocks (12 instances in total) open-collector outputs

TWI_SCL_Mn_ADGPIO IO Two-wire serial interface multiplexed clocks (4 instances in total) Same as TWI_SCL_MnGPIO but the pin is always driven meaning feedback from slave devices is not possible

Table 157 bull Two-Wire Serial Interface Registers (continued)

Address Command

TWI_SCL

TWI_SDA A6 A0 RW ACK D7 D1 D0 ACK

1 7 9 1 7 8 98

DataSTART STOP

4851 Two-Wire Serial Interface AddressingTo configure either 7-bit or 10 bit addressing use CFGMASTER_10BITADDR

The two-wire serial interface controller can generate both General Call and START Byte Initiate this through TARGC_OR_START_ENA or TARGC_OR_START The targetslave address is configured using the TAR register

4852 Two-Wire Serial Interface InterruptThe two-wire serial interface controller can generate a multitude of interrupts All of these are described in the RAW_INTR_STAT register The RAW_INTR_STAT register contains interrupt fields that are always set when their trigger conditions occur The INTR_MASK register is used for masking interrupts and allowing interrupts to propagate to the INTR_STAT register When set in the INTR_STAT register the two-wire serial interface controller asserts interrupt toward the VCore-Ie interrupt controller

The RAW_INTR_STAT register also specifies what is required to clear the specific interrupts When the source of the interrupt is removed reading the appropriate CLR_ register (for example CLR_RX_OVER) clears the interrupt

4853 Built-in Two-Wire Serial MultiplexerThe device has built-in support for connecting to multiple two-wire serial devices that use the same two-wire serial address This is done by using the multiplexed clock outputs (TWI_SCL_Mn) for the two-wire serial devices rather than TWI_SCL Depending on which device or devices it needs to talk to software can then enabledisable the various clocks

From the two-wire serial controllerrsquos point of view it does not know if it is using TWI_SCL or TWI_SCL_Mn clocks When using multiplexed mode software needs to enabledisable individual TWI_SCL_Mn connections before initiating the access operation using the two wire serial controller Feedback on the clock (from slow two-wire serial devices) is automatically done for the TWI_SCL_Mn lines that are enabled

To enable multiplexed clocks configure the TWI_SCL_Mn overlaid mode in the GPIO controller during initialization Individual TWI_SCL_Mn clocks are then enabled when needed by writing 1 to the corresponding GPIO output bit (in DEVCPU_GCBGPIO_OUT) To disable the clock write 0 to the GPIO output bit Disabled TWI_SCL_Mn clocks are not driven during access and the feedback is disabled

Note In multiprocessor systems the DEVCPU_GCBGPIO_OUT_SET and DEVCPU_GCBGPIO_OUT_CLR registers can be used to avoid race conditions

486 MII Management ControllerThis section provides information about the MII Management (MIIM) controllers The following table lists the registers associated with the MII Management controllers

Register DescriptionDEVCPU_GCBMII_STATUS Controller status

DEVCPU_GCBMII_CMD Command and write data

DEVCPU_GCBMII_DATA Read data

DEVCPU_GCBMII_CFG Clock frequency configuration

DEVCPU_GCBMII_SCAN_0 Auto-scan address range

DEVCPU_GCBMII_SCAN_1 Auto-scan mask and expects

DEVCPU_GCBMII_SCAN_LAST_RSLTS Auto-scan result

DEVCPU_GCBMII_SCAN_LAST_RSLTS_VLD Auto-scan result valid

DEVCPU_GCB MII_SCAN_RSLTS_STICKY Differences in expected versus read auto-scan

The device contains two MIIM controllers with equal functionality Data is transferred on the MIIM interface using the Management Frame Format protocol specified in IEEE 8023 Clause 22 or the MDIO Manageable Device protocol defined in IEEE 8023 Clause 45 The Clause 45 protocol differs from the Clause 22 protocol by using indirect register access to increase the address range The controller supports both Clause 22 and Clause 45 The first MIIM controller is connected to the internal PHYs of the device

The MIIM interface pins for the second controller are overlaid functions on the GPIO interface Before using this MIIM controller the overlaid functions for the appropriate GPIO pins must first be enabled For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The MDIO signal is changed or sampled on the falling edge of the MDC clock by the controller The MDIO pin is tri-stated in-between access and when expecting read data

Figure 79 bull MII Management Timing

4861 Clock ConfigurationThe frequency of the management interface clock generated by the MIIM controller is derived from the switch corersquos frequency The MIIM clock frequency is configurable and is selected with MII_CFGMIIM_CFG_PRESCALE The calculation of the resulting frequency is explained in the register description for MII_CFGMIIM_CFG_PRESCALE The maximum frequency of the MIIM clock is 25 MHz

4862 MII Management PHY AccessReads and writes across the MII management interface are performed through the MII_CMD register Details of the operation such as the PHY address the register address of the PHY to be accessed the operation to perform on the register (for example read or write) and write data (for write operations) are set in the MII_CMD register When the appropriate fields of MII_CMD are set the operation is initiated by writing 0x1 to MII_CMDMIIM_CMD_VLD The register is automatically cleared when the MIIM command is initiated When initiating single MIIM commands MII_CMDMIIM_CMD_SCAN must be set to 0x0

When an operation is initiated the current status of the operation can be read in MII_STATUS The fields MII_STATUSMIIM_STAT_PENDING_RD and MII_STATUSMIIM_STAT_PENDING_WR can be used to poll for completion of the operation For a read operation the read data is available in MII_DATAMIIM_DATA_RDDATA after completion of the operation The value of MII_DATAMIIM_DATA_RDDATA is only valid if MII_DATAMIIM_DATA_SUCCESS indicates no read errors

The MIIM controller contains a small command FIFO Additional MIIM commands can be queued as long as MII_STATUSMIIM_STAT_OPR_PEND is cleared Care must be taken with read operations because multiple queued read operations will overwrite MII_DATAMIIM_DATA_RDDATA

Note A typical software implementation will never queue read operations because the software needs read data before progressing the state of the software In this case MIIM_STATUSMIIM_STAT_OPR_PEND is checked before issuing MIIM read or write commands for read operations MII_STATUSMIIM_STAT_BUSY is checked before returning read result

Table 160 bull MIIM Management Controller Pins

Pin Name IO DescriptionMDC1GPIO O MIIM clock for controller 1

MDIO1GPIO IO MIIM data inputoutput for controller 1

preamble32 bit

ST2 bit

OP2 bit

PHYAD5 bit

REGAD5 bit

TA2 bit

Addressdata16 bit

By default the MIIM controller operates in Clause 22 mode To access Clause 45 compatible PHYs MII_CFGMIIM_ST_CFG_FIELD and MII_CMDMIIM_CMD_OPR_FIELD must be set according to Clause 45 mode of operation

4863 PHY ScanningThe MIIM controller can be configured to continuously read certain PHY registers and detect if the read value is different from an expected value If a difference is detected a special sticky bit register is set or a CPU interrupt is generated or both For example the controller can be programmed to read the status registers of one or more PHYs and detect if the Link Status changed since the sticky register was last read

The reading of the PHYs is performed sequentially with the low and high PHY numbers specified in MII_SCAN_0 as range bounds The accessed address within each of the PHYs is specified in MII_CMDMIIM_CMD_REGAD The scanning begins when a 0x1 is written to MII_CMDMIIM_CMD_SCAN and a read operation is specified in MII_CMDMIIM_CMD_OPR_FIELD Setting MII_CMDMIIM_CMD_SINGLE_SCAN stops the scanning after all PHYs have been scanned one time The remaining fields of MII_CMD register are not used when scanning is enabled

The expected value for the PHY register is set in MII_SCAN_1MIIM_SCAN_EXPECT The expected value is compared to the read value after applying the mask set in MII_SCAN_1MIIM_SCAN_MASK To donrsquot-care a bit-position write a 0 to the mask If the expected value for a bit position differs from the read value during scanning and the mask register has a 1 for the corresponding bit a mismatch for the PHY is registered

The scan results from the most recent scan can be read in MII_SCAN_LAST_RSLTS The register contains one bit for each of the possible 32 PHYs A mismatch during scanning is indicated by a 0 MII_SCAN_LAST_RSLTS_VLD will indicate for each PHY if the read operation performed during the scan was successful The sticky-bit register MII_SCAN_RSLTS_STICKY has the mismatch bit set for all PHYs that had a mismatch during scanning since the last read of the sticky-bit register When the register is read its value is reset to all-ones (no mismatches)

4864 MII Management InterruptThe MII management controllers can generate interrupts during PHY scanning Each MII management controller has a separate interrupt signal to the interrupt controller Interrupt is asserted when one or more PHYs have a mismatch during scan The interrupt is cleared by reading the MII_SCAN_RSLTS_STICKY register which resets all MII_SCAN_RSLTS_STICKY indications

487 GPIO ControllerThis section provides information about the use of GPIO pins

The following table lists the registers associated with GPIO

Table 161 bull GPIO Registers

Register DescriptionDEVCPU_GCBGPIO_OUT Value to drive on GPIO outputs

DEVCPU_GCBGPIO_OUT_SET Atomic set of bits in GPIO_OUT

DEVCPU_GCBGPIO_OUT_CLR Atomic clear of bits in GPIO_OUT

DEVCPU_GCBGPIO_IN Current value on the GPIO pins

DEVCPU_GCBGPIO_OE Enable of GPIO output mode (drive GPIOs)

DEVCPU_GCBGPIO_ALT Enable of overlaid GPIO functions

DEVCPU_GCBGPIO_INTR Interrupt on changed GPIO value

DEVCPU_GCBGPIO_INTR_ENA Enable interrupt on changed GPIO value

DEVCPU_GCBGPIO_INTR_IDENT Currently interrupting sources

DEVCPU_GCBGPIO_SD_MAP Mapping of parallel signal detects

The GPIO pins are individually programmable GPIOs are inputs by default and can be individually changed to outputs through GPIO_OE The value of the GPIO pins is reflected in the GPIO_IN register GPIOs that are in output mode are driven to the value specified in GPIO_OUT

In a system where multiple different CPU threads (or different CPUs) may work on the GPIOs at the same time the GPIO_OUT_SET and GPIO_OUT_CLR registers provide a way for each thread to safely control the output value of individual GPIOs without having to implement locked regions and semaphores

The GPIO_ALT registers are only reset by external reset to the device This means that software reset of the DEVCPU_GCB is possible without affecting the mapping of overlaid functions on the GPIOs

4871 GPIO Overlaid FunctionsMost of the GPIO pins have overlaid (alternative) functions that can be enabled through replicated GPIO_ALT registers

To enable a particular GPIO[n] pin with the alternate function set the G_ALT[n] register field in the replicated registers as follows

bull Overlaid mode 1 set GPIO_ALT[1][n] GPIO_ALT[0][n] = 1 bull Overlaid mode 2 set GPIO_ALT[1][n] GPIO_ALT[0][n] = 2 bull Normal GPIO mode set GPIO_ALT[1][n] GPIO_ALT[0][n] = 0When the MIIM slave mode is enabled through the VCore_CFG strapping pins specific GPIO pins are overtaken and used for the MIIM slave interface

During reset the VCore_CFG interface is sampled and used for VCore configuration After reset the device is released and the GPIOs can be used for output or inputs For more information see VCore-Ie Configurations page 159

The following table maps the GPIO pins and available overlaid functions

Table 162 bull GPIO Overlaid Functions

Name Overlaid Function 1 Overlaid Function 2 Overlaid Function 3Configuration or Interface

GPIO_0 SG0_CLK REFCLK0_CONF0

GPIO_1 SG0_DO REFCLK0_CONF1

GPIO_2 SG0_DI

GPIO_3 SG0_LD REFCLK0_CONF2

GPIO_4 IRQ0_IN IRQ0_OUT TWI_SCL_M13

GPIO_5 IRQ1_IN IRQ1_OUT PCI_Wake

GPIO_6 UART_RXD TWI_SCL_M0

GPIO_7 UART_TXD TWI_SCL_M1

GPIO_8 SI_nCS1 TWI_SCL_M2 IRQ0_OUT

GPIO_10 PTP_2 TWI_SCL_M4 SFP0_SD

GPIO_12 UART2_RxD TWI_SCL_M6 SFP2_SD

GPIO_13 UART2_TxD TWI_SCL_M7 SFP3_SD

GPIO_14 MIIM1_MDC TWI_SCL_M8 SFP4_SD MIIM_SLV_MDC

GPIO_15 MIIM1_MDIO TWI_SCL_M9 SFP5_SD MIIM_SLV_MDIO

GPIO_16 TWI_SDA SI_nCS3

GPIO_17 TWI_SCL TWI_SCL_M10 SI_nCS4

4872 GPIO InterruptThe GPIO controller continually monitors all inputs and set bits in the GPIO_INTR register whenever a GPIO changes its input value By enabling specific GPIO pins in the GPIO_INTR_ENA register a change indication from GPIO_INTR is allowed to propagate (as GPIO interrupt) from the GPIO controller to the VCore-Ie Interrupt Controller

The currently interrupting sources can be read from GPIO_INTR_IDENT this register is the result of a binary AND between the GPIO_INTR and GPIO_INTR_ENA registers

4873 Parallel Signal DetectThe GPIO controller has 6 programmable parallel signal detects SFP0_SD through SFP5_SD When parallel signal detect is enabled for a front port index it overrides the signal-detectloss-of-signal value provided by the serial GPIO controller

To enable parallel signal detect n first configure which port index from the serial GPIO controller that must be overwritten by setting GPIO_SD_MAP[n]G_SD_MAP then enable the SFPn_SD function on the GPIOs

The following table lists parallel signal detect pins which are overlaid on GPIOs For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

488 Serial GPIO ControllerThe device features one serial GPIO (SIO) controller By using a serial interface the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device The primary purpose of the SIO controller is to connect control signals from SFP modules and to act as an LED controller

Each SIO controller supports up to 128 serial GPIOs (SGPIOs) organized into 32 ports with four SGPIOs per port

GPIO_18 PTP_0 TWI_SCL_M11_AD VCORE_CFG0

GPIO_20 RECO_CLK0 TACHO TWI_SCL_M14_AD VCORE_CFG2

GPIO_21 RECO_CLK1 PWM TWI_SCL_M15_AD VCORE_CFG3

Table 163 bull Parallel Signal Detect Pins

Register IO DescriptionSFP0_SDGPIO I Parallel signal detect 0

SFP1_SDGPIO I Parallel signal detect 1

Table 162 bull GPIO Overlaid Functions (continued)

The following table lists the registers associated with the SIO controller

The following table lists the SIO controller pins which are overlaid functions on GPIO pins For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The SIO controller works by shifting SGPIO values out on SG0_DO though a chain of shift registers on the PCB After shifting a configurable number of SGPIO bits the SIO controller asserts SG0_LD which causes the shift registers to apply the values of the shifted bits to outputs The SIO controller can also read inputs while shifting out SGPIO values on SG0_DO by sampling the SG0_DI input The values sampled on SG0_DI are made available to software

If the SIO controller is only used for outputs the use of the load signal is optional If the load signal is omitted simpler shift registers (without load) can be used however the outputs of these registers will toggle during shifting

When driving LED outputs it is acceptable that the outputs will toggle when SGPIO values are updated (shifted through the chain) When the shift frequency is fast the human eye is not able to see the shifting though the LEDs

The number of shift registers in the chain is configurable The SIO controller allows enabling of individual ports through SIO_PORT_ENA only enabled ports are shifted out on SG0_DO Ports that are not enabled are skipped during shifting of GPIO values

Note SIO_PORT_ENA allows skipping of ports in the SGPIO output stream that are not in use The number of GPIOs per (enabled) port is configurable as well through SIO_CFGSIO_PORT_WIDTH this can be set

Table 164 bull SIO Registers

Register DescriptionDEVCPU_GCBSIO_INPUT_DATA Input data

DEVCPU_GCBSIO_CFG General configuration

DEVCPU_GCBSIO_CLOCK Clock configuration

DEVCPU_GCBSIO_PORT_CFG Output port configuration

DEVCPU_GCBSIO_PORT_ENA Port enable

DEVCPU_GCBSIO_PWM_CFG PWM configuration

DEVCPU_GCBSIO_INTR_POL Interrupt polarity

DEVCPU_GCBSIO_INTR_RAW Raw interrupt status

DEVCPU_GCBSIO_INTR_TRIGGER0 Interrupt trigger mode 0 configuration

DEVCPU_GCBSIO_INTR Currently interrupting SGPIOs

DEVCPU_GCBSIO_INTR_ENA Interrupt enable

DEVCPU_GCBSIO_INTR_IDENT Currently active interrupts

Table 165 bull SIO Controller Pins

Pin Name IO DescriptionSG0_CLKGPIO O SIO clock output frequency is configurable using

SIO_CLOCKSIO_CLK_FREQ

SG0_DOGPIO O SIO data output

SG0_DIGPIO I SIO data input

SG0_LDGPIO O SIO load data polarity is configurable using SIO_CFGSIO_LD_POLARITY

to 1 2 3 or 4 bits The number of bits per port is common for all enabled ports so the number of shift registers on the PCB must be equal to the number of enabled ports times the number of SGPIOs per port

Enabling of ports and configuration of SGPIOs per port applies to both output mode and input mode Unlike a regular GPIO port a single SGPIO position can be used both as output and input That is software can control the output of the shift register AND read the input value at the same time Using SGPIOs as inputs requires load-capable shift registers

Regular shift registers and load-capable shift-registers can be mixed which is useful when driving LED indications for integrated PHYs while supporting reading of link status from SFP modules for example

Figure 80 bull SIO Timing

The SGPIO values are output in bursts followed by assertion of the SG0_LD signal Values can be output as a single burst or as continuous bursts separated by a configurable burst gap The maximum length of a burst is 32 times 4 data cycles The burst gap is configurable in steps of approximately 1 ms from 0 ms to 33 ms through SIO_CFGSIO_BURST_GAP_DIS and SIO_CFGSIO_BURST_GAP

A single burst is issued by setting SIO_CFGSIO_SINGLE_SHOT The field is automatically cleared by hardware when the burst is finished To issue continuous bursts set SIO_CFGSIO_AUTO_REPEAT The SIO controller continues to issue bursts until SIO_CFGSIO_AUTO_REPEAT is cleared

SGPIO output values are configured in SIO_PORT_CFGBIT_SOURCE The input value is available in SIO_INPUT_DATA

The following illustration shows what happens when the number of SGPIOs per port is configured to two (through SIO_CFGSIO_PORT_WIDTH) Disabling ports (through SIO_PORT_ENA) is handled in the same way as disabling the SGPIO ports

Figure 81 bull SIO Timing with SGPIOs Disabled

The frequency of the SG0_CLK clock output is configured through SIO_CLOCKSIO_CLK_FREQ The SG0_LD output is asserted after each burst this output is asserted for a period of 25 ns to 30 ns The polarity of SG0_LD is configured in SIO_CFGSIO_LD_POLARITY

pN-1b2

pNb3SG0_DO

SG0_DI

SG0_CLK

SG0_LD

Serial to parallel shift registers output data on rising edge

Parallel to serial shift registers load data on logical 0

pN-1b3

Burst gap

pN-2b1

pNb3SG0_DO

SG0_CLK

SG0_LD

pN-1b3

pN-1b2

pN-1b1

pN-1b0

pN-2b3

pN-2b2

Disabled Disabled Disabled Disabled

The SG0_LD output can be used to ensure that outputs are stable when serial data is being shifted through the registers This can be done by using the SG0_LD output to shift the output values into serial-to-parallel registers after the burst is completed If serial-to-parallel registers are not used the outputs will toggle while the burst is being shifted through the chain of shift registers A universal serial-to-parallel shift register outputs the data on a positive-edge load signal and a universal parallel-to-serial shift register shifts data when the load pin is high so one common load signal can be used for both input and output serial parallel conversion

The assertion of SG0_LD happens after the burst to ensure that after power up the single burst will result in well-defined output registers Consequently to sample input values one time two consecutive bursts must be issued The first burst results in the input values being sampled by the serial-to-parallel registers and the second burst shifts the input values into the SIO controller

The port order required in the serial bitstream depends on the physical layout of the shift register chain Often the input and output port orders must be opposite in the serial streams The port order of the input and output bitstream is independently configurable in SIO_CFGSIO_REVERSE_INPUT and SIO_CFGSIO_REVERSE_OUTPUT

The following illustration shows the port order

Figure 82 bull SGPIO Output Order

4881 Output ModesThe output mode of each SGPIO can be individually configured in SIO_PORT_CFGBIT_SOURCE The SIO controller features three output modes

bull Staticbull Blinkbull Link activityThe output mode can additionally be modified with PWM (SIO_PORT_CFGPWM_SOURCE) and configurable polarity (SIO_PORT_CFGBIT_POLARITY)

Static Mode The static mode is used to assign a fixed value to the SGPIO for example fixed 0 or fixed 1

Blink Mode The blink mode makes the SGPIO blink at a fixed rate The SIO controller features two blink modes that can be set independently A SGPIO can then be configured to use either blink mode 0 or blink mode 1 The blink outputs are configured in SIO_CFGSIO_BMODE_0 and SIO_CFGSIO_BMODE_1 To synchronize the blink modes between different devices reset the blink counter using SIO_CFGSIO_BLINK_RESET All the SIO controllers on a device must be reset at same

SG0_CLK

pN-1b3

pN-2b3

pN-1b0

pN-1b1

pN-1b2

pN-1b3

pN-2b3

pN-1b0

pN-1b1

pN-1b2

SG0_DO

SG0_DI

Reverse order

Default order

SG0_DO

SG0_DI

time to maintain the synchronization The burst toggle mode of blink mode 1 toggles the output with every burst

Link Activity Mode The link activity mode makes the output blink when there is activity on the port module (Rx or Tx) The following table lists the mapping between the SIO port number and port modules

Table 166 bull Blink Modes

Register DescriptionBlink Mode 0 0 20 Hz blink frequency

1 10 Hz blink frequency2 5 Hz blink frequency3 25 Hz blink frequency

Blink Mode 1 0 20 Hz blink frequency1 10 Hz blink frequency2 5 Hz blink frequency3 Burst toggle

Table 167 bull SIO Controller Port Mapping

SIO Port SG0 Mapping0 Port module 0

1 Port module 1

2 Port module 2

3 Port module 3

4 Port module 4

5 Port module 5

6 Port module 6

7 Port module 7

8 Port module 8

9 Port module 9

10 Port module 10

11 Free

12 Free

13 Free

14 Free

15 Free

16 Free

17 Free

18 Free

19 Free

20 Free

21 Free

22 Free

23 Free

24 Free

The link activity mode uses an envelope signal to gate the selected blinking pattern (blink mode 0 or blink mode 1) When the envelope signal is asserted the output blinks and when the envelope pattern is de-asserted the output is turned off To ensure that even a single packet makes a visual blink an activity pulse from the port module is extended to minimum 100 ms If another packet is sent while the envelope signal is asserted the activity pulse is extended by another 100 ms The polarity of the link activity modes can be set in SIO_PORT_CFGBIT_SOURCE

The following illustration shows the link activity timing

Figure 83 bull Link Activity Timing

4882 SIO InterruptThe SIO controller can generate interrupts based on the value of the input value of the SGPIOs All interrupts are level sensitive

Interrupts are enabled using the two registers Interrupts can be individually enabled for each port in SIO_INTR_ENA (32 bits) and in SIO_CFGSIO_GPIO_INTR_ENA (4 bits) interrupts are enabled for the four inputs per port In other words SIO_CFGSIO_GPIO_INTR_ENA is common for all 32 ports

The SIO controller has four interrupt registers that each has one bit for each of the 128 GPIOs

bull SIO_INTR_RAW is high if the corresponding input bit is high (corrected for polarity as configured in SIO_INTR_POL) This register changes when the input changes

bull SIO_INTR is high if the condition of the configured trigger mode for the bit is met The trigger mode can be configured in SIO_INTR_TRIGGER0 and SIO_INTR_TRIGGER1 between level-triggered edge-triggered falling-edge-triggered and rising-edge-triggered interrupt This register is a sticky bit vector and can only be cleared by software A bit is cleared by writing a 1 to the bit position

bull SIO_INTR_IDENT is the result of SIO_INTR with the disabled interrupts (from SIO_INTR_ENA and SIO_GPIO_INTR_ENA) removed This register changes when SIO_INTR or the enable registers change

The SIO controller has one interrupt output connected to the main interrupt controller which is asserted when one or more interrupts in SIO_INTR_IDENT are active To determine which SGPIO is causing the interrupt the CPU must read this register The interrupt output remains high until all interrupts in SIO_INTR_IDENT are cleared (either by clearing SIO_INTR or disabling the interrupts in SIO_INTR_ENA and SIO_GPIO_INTR_ENA)

25 Free

26 Free

27 Free

28 Free

29 Free

30 Free

31 Free

Table 167 bull SIO Controller Port Mapping (continued)

SIO Port SG0 Mapping

100 ms pulse

MAC pulse

Envelope

Blink mode

Output

4883 Loss of Signal DetectionThe SIO controller can propagate loss of signal detection inputs directly to the signal detection input of the port modules This is useful when for example SFP modules are connected to the device The mapping between SIO ports and port modules is the same as for the link activity outputs port 0 is connected to port module 0 port 1 is connected to port module 1 and so on

The value of SGPIO bit 0 of each SIO port is forwarded directly to the loss of signal input on the corresponding port module The port module must enable the loss of signal input locally

Loss of signal can also be taken directly from overlaid functions on the regular GPIOs In that case the input from the SIO controller is ignored

The polarity of the loss of signal input is configured using SIO_INT_POL meaning the same polarity must be used for loss of signal detect and interrupt

489 Fan ControllerThe device includes a fan controller that can be used to control and monitor a system fan A pulse width modulation (PWM) output regulates the fan speed The fan speed is monitored using a TACHO input The fan controller is especially powerful when combined with the internal temperature sensor For more information see Temperature Sensor page 212

The following table lists the registers associated with the fan controller

The following table lists fan controller pins which are overlaid on GPIOs For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

The PWM output frequency depends on the value of DEVCPU_GCBPWM_FREQ and the switch core clock frequency If pwm_freq is the desired PWM frequency and core_freq is the switch core frequency then DEVCPU_GCBPWM_FREQ must be configured with value core_freqpwm_freq256 The DEVCPU_GCBPWM_FREQ configuration register is 16bit wide and it defaults to value 24 The supported PWM frequency range depends on the core clock frequency With 15625MHz core frequency the PWM can be configured in the range of 10Hz - 610kHz The default PWM frequency is ~25kHz

The low frequencies can be used for driving three-wire fans using a FETtransistor The 25 kHz frequency can be used for four-wire fans that use the PWM input internally to control the fan The duty cycle of the PWM output is programmable from 0 to 100 with 8-bit accuracy The polarity of the output can be controlled by FAN_CFGINV_POL so a duty-cycle of 100 for example can be either always low or always high

The PWM output pin can be configured to act as a normal output or as an open-collector output where the output value of the pin is kept low but the output enable is toggled The open-collector output mode is enabled by setting FAN_CFGPWM_OPEN_COL_ENA

Note By using open-collector mode it is possible to externally pull-up to a higher voltage than the maximum GPIO IO supply The GPIO pins are 33 V-tolerable

Table 168 bull Fan Controller

Register DescriptionDEVCPU_GCBFAN_CFG General configuration

DEVCPU_GCBPWM_FREQ Configuration of PWM frequency

DEVCPU_GCBFAN_CNT Fan revolutions counter

Table 169 bull Fan Controller Pins

Register IO DescriptionTACHOGPIO I TACHO input for counting revolutions

PWMGPIO O PWM fan output

The speed of the fan is measured using a 16-bit counter that counts the rising edges on the TACHO input A fan usually gives one to four pulses per revolution depending on the fan type The counter value is available in the FAN_CNT register Depending on the value of FAN_CFGFAN_STAT_CFG the FAN_CNT register is updated in two different ways

bull If FAN_CFGFAN_STAT_CFG is set the FAN_CNT register behaves as a 16-bit wrapping counter that shows the total number of ticks on the TACHO input

bull If FAN_CFGFAN_STAT_CFG is cleared the FAN_CNT register is updated one time per second with the number of TACHO ticks received during the last second

Optionally the TACHO input is gated by the polarity-corrected PWM output by setting FAN_CFGGATE_ENA so that only TACHO pulses received while the polarity corrected PWM output is high are counted Glitches on the TACHO input can occur right after the PWM output goes high As a result the gate signal is delayed by 10 micros when PWM goes high There is no delay when PWM goes low and the length of the delay is not configurable Software must read the counter value in FAN_CNT and calculate the RPM of the fan

An example of how to calculate the RPM of the fan is if the fan controller is configured to 100 Hz and a 20 duty cycle each PWM pulse is high in 2 ms and low in 8 ms If gating is enabled the gating of the TACHO input is open in 199 ms and closed in 801 ms If the fan is turning with 100 RPMs and gives two TACHO pulses per revolution it will ideally give 200 pulses per minute TACHO pulses are only counted in 1999 of the time so it will give 200 times 01999 = 3998 pulses per minute If the additional 10 micros gating time is ignored the counter value is multiplied by 25 to get the RPM value because there is a 20 duty cycle with two TACHO pulses per revolution By multiplying with 25 the RPM value is calculated to 9995 which is 005 off the correct value (due to the 10 micros gating time)

4810 Temperature SensorThis section provides information about the on-die temperature sensor When enabled the temperature sensor logic will continually monitor the temperature of the die and make this available for software

The following table lists the registers associated with the temperature monitor

The temperature sensor is enabled by setting TEMP_SENSOR_CTRLSAMPLE_ENA After this the temperature sensor will sample temperature every 500 micros and show current temperature through TEMP_SENSOR_STATETEMP The formula for converting TEMP field value to centigrade temperature is

Temp (degC) = 1774 ndash 08777 times TEMP_SENSOR_STATETEMP

It takes approximately 500 micros after setting SAMPLE_ENA until the first temperature sample is ready The TEMP_SENSOR_SATETEMP_VALID field is set when the temperature value is available

4811 Memory Integrity MonitorSoft errors happen in all integrated circuits these are a result of natural alpha decay cosmic radiation or electrical disturbances in the environment in which the device operates The chance of soft errors happening in a memory (RAM) is higher than for flip-flop based logic because the memory structures are physically small and changes require less outside force than in flip flops The device has built-in protection from soft errors by using error correcting code (ECC) on critical memories In addition the device allows monitoring and reporting of soft error events

Table 170 bull Temperature Sensor Registers

Register DescriptionHSIOTEMP_SENSOR_CTRL Enabling of sensor

HSIOTEMP_SENSOR_STAT Temperature value

The following table lists the registers associated with the memory integrity monitor

The memory integrity monitor looks for memory soft-error indications Correctable (single bit) and non-correctable (multibit or parity) indications are detected during memory read and can be reported to software by the ITGR software interrupt For information about how to enable this interrupt see Interrupt Controller page 215

The memory integrity monitor operates in three different states IDLE LISTEN and DETECT After a reset the monitor starts in the IDLE state

IDLE The monitor is deactivated and in quiet mode In IDLE mode the memories still correct detect and store indications locally but they are not able to report indications to the monitor

LISTEN In the LISTEN state the monitor looks for indications in the memories MEMITGR_STATINDICATION is set (and interrupt is asserted) when indications are detected

DETECT DETECT state is used when indications are read from the memories It means that a valid indication is available in MEMITGR_INFO and the corresponding memory index in MEMITGR_IDX

The current state of the monitor is reported in MEMITGR_STATMODE_IDLE MEMITGR_STATMODE_DETECT and MEMITGR_STATMODE_LISTEN Software initiates transitions between states by setting the one-shot MEMITGR_CTRLACTIVATE field It may take some time to transition from one state to the next The MEMITGR_CTRACTIVATE field is not cleared before the next state is reached (also the MEMITGR_STATMODE_BUSY field is set while transitioning between states)

Table 171 bull Integrity Monitor Registers

Register DescriptionDEVCPU_GCBMEMITGR_CTRL Trigger monitor state changes

DEVCPU_GCBMEMITGR_STAT Current state of the monitor and memory status

DEVCPU_GCBMEMITGR_INFO Shows indication when in DETECT state

DEVCPU_GCBMEMITGR_IDX Shows memory index when in DETECT state

DEVCPU_GCBMEMITGR_DIV Monitor speed

Figure 84 bull Monitor State Diagram

The first time after reset that MEMITGR_CTRLACTIVATE is set the monitor resets the detection logic in all the memories and transitions directly from IDLE to LISTEN state

Before setting MEMITGR_CTRlACTIVATE for the first time speed up the monitor by setting MEMITGR_DIVMEM_DIV to the value specified in the registers list The memories of the PCIe MAC are clock-gated and bypassed when PCIe interface is not enabled enable monitoring of PCIe MAC memories by setting ICPU_CFGPCIE_CFGMEM_RING_CORE_ENA This field must not be set when PCIe interface is not enabled

To read out indications first transition from LISTEN to IDLE then continue transitioning until the LISTEN state is reached Every time the monitor ends up in the DETECT state an indication is available in the MEMITGR_INFO and MEMITGR_IDX registers Each memory stores one indication Indications are cleared when they are read by way of the monitor Each indication contains four flags and one memory address

bull The MEM_ERR flag is set when a non-correctable upset is detected and the corresponding address is available in MEM_ADDR

bull The MEM_ERR_OVF flag is set when a non-correctable upset is detected for which address could not be stored

bull The MEM_COR flag is set when a correctable upset is detected and the corresponding address is available in MEM_ADDR

bull The MEM_COR_OVF flag is set when a correctable upset is detected for which address could not be stored

Information about non-correctable upsets is prioritized over correctable upsets Address can only be saved when the monitor is in LISTEN mode The following flowchart shows how the detection logic sets flags and address

LISTEN

DETECT

At least one valid indication in the memories

Transitions in this diagram are triggered by setting MEMITGR_CTRLACTIVATE (can only

be set when non-BUSY)

No more indications in the memories

At least one (more) valid indication in the memories

Figure 85 bull Memory Detection Logic

If the MEM_ERR_OVF or MEM_COR_OVF flag is set at least one event has occurred for which the address could not be stored

The following table shows ECC-enabled memories in the device their index and the recommended approach for handling indications If the controller reports an index that is not mentioned in the list the recommended approach is to reboot the device

Reading from uninitialized memory locations has a high plausibility of triggering non correctable or correctable indications This is useful when developing integrity monitor software driver For example powering up a system without initializing the VCAPs and reading actions and sticky bits will trigger monitor indications Note that the contents of memories are not changed by device reset so power cycle is needed to reset the memories

4812 Interrupt ControllerThis section provides information about the VCore-Ie interrupt controller

Table 172 bull Memories with Integrity Support

Index DescriptionOthers For unlisted indexes the recommended approach is to reboot the device

Upset is detected

Is upset correctable

Is MEM_ERR set

Save upset address to MEM_ADDR

Set MEM_ERR Set MEM_ERR_OVF

Is MEM_ERR set

Is MEM_COR set

Set MEM_COR Set MEM_COR_OVF

yes yes

yesyes

Is monitor in LISTEN state

Is upset correctableyes

Set MEM_ERR_OVF Set MEM_COR_OVF

The following table lists the registers associated with the interrupt controller

The interrupt controller maps interrupt sources from VCore-Ie and switch core blocks port modules and external interrupt inputs to four interrupt destinations Two interrupt destinations are mapped to the VCore-Ie CPU and two can be transmitted from the device using the overlaid functions on GPIOs or using PCIe inband interrupt signaling

The following table lists the available interrupt sources in the device

Table 173 bull Interrupt Controller Registers

Register DescriptionICPU_CFGINTR_RAW Current value of interrupt inputs

ICPU_CFGINTR_BYPASS Force non-sticky function

ICPU_CFGINTR_TRIGGER Configure edge or level sensitive events

ICPU_CFGINTR_FORCE Force events (for software debug)

ICPU_CFGINTR_STICKY Currently logged events

ICPU_CFGINTR_ENA Enable of interrupt sources

ICPU_CFGINTR_ENA_CLR Atomic clear of bits in INTR_ENA

ICPU_CFGINTR_ENA_SET Atomic set of bits in INTR_ENA

ICPU_CFGINTR_IDENT Currently enabled and interrupting sources

ICPU_CFGDST_INTR_MAP Mapping of interrupt sources to destinations

ICPU_CFGDST_INTR_IDENT Currently enabled mapped and interrupting sources per destination

ICPU_CFGDEV_INTR_POL Polarity of module interrupt inputs

ICPU_CFGDEV_INTR_RAW Current value of module interrupts

ICPU_CFGDEV_INTR_BYPASS Force non-sticky function for module interrupts

ICPU_CFGDEV_INTR_TRIGGER Configure edge or level sensitive events for module interrupts

ICPU_CFGDEV_INTR_STICKY Currently logged module interrupt events

ICPU_CFGDEV_INTR_ENA Enable of module interrupts

ICPU_CFGDEV_INTR_IDENT Currently interrupting and enabled module interrupts

ICPU_CFGEXT_SRC_INTR_POL Polarity of external interrupt inputs

ICPU_CFGEXT_DST_INTR_POL Polarity of external interrupt outputs

ICPU_CFGEXT_DST_INTR_DRV Drive mode for external interrupt outputs

Table 174 bull Interrupt Sources

Source Name DescriptionDEV Aggregated port module interrupt This interrupt is asserted if there is an active and

enabled interrupt from any of the devicersquos port modules See Port Module InterruptsThis interrupt has bit index 0 in INTR_ and DST_INTR_ registers

EXT_SRC0 External interrupt source 0 See External InterruptsThis interrupt has bit index 1 in INTR_ and DST_INTR_ registers

TIMER0 Timer 0 interrupt See TimersThis interrupt has bit index 3 in INTR_ and DST_INTR_ registers

UART UART interrupt See UART InterruptThis interrupt has bit index 6 in INTR_ and DST_INTR_ registers

UART2 UART2 interrupt See UART InterruptThis interrupt has bit index 7 in INTR_ and DST_INTR_ registers

TWI TWI interrupt See Two-Wire Serial Interface InterruptThis interrupt has bit index 8 in INTR_ and DST_INTR_ registers

SIMC Serial Master Controller interrupt See Serial Master Controller Interrupt This interrupt has bit index 9 in INTR_ and DST_INTR_ registers

SW0 Software interrupt 0 See Mailbox and SemaphoresThis interrupt has bit index 10 in INTR_ and DST_INTR_ registers

SGPIO0 Serial GPIO interrupt 0 See SIO InterruptThis interrupt has bit index 12 in INTR_ and DST_INTR_ registers

GPIO Parallel GPIO interrupt See GPIO InterruptThis interrupt has bit index 13 in INTR_ and DST_INTR_ registers

MIIM0 MIIM Controller 0 interrupt See MII Management InterruptThis interrupt has bit index 14 in INTR_ and DST_INTR_ registers

FDMA Frame DMA interrupt see FDMA Events and InterruptsThis interrupt has bit index 16 in INTR_ and DST_INTR_ registers

ANA Analyzer interrupt See Interrupt HandlingThis interrupt has bit index 17 in INTR_ and DST_INTR_ registers

PTP_RDY Time stamp ready interrupt See Hardware Time Stamping ModuleThis interrupt has bit index 18 in INTR_ and DST_INTR_ registers

PTP_SYNC PTP synchronization interrupt See Master TimerThis interrupt has bit index 19 in INTR_ and DST_INTR_ registers

ITGR Memory integrity interrupt See Memory Integrity Monitor page 212This interrupt has bit index 20 in INTR_ and DST_INTR_ registers

XTR_RDY Extraction data ready interrupt See Frame ExtractionThis interrupt has bit index 21 in INTR_ and DST_INTR_ registers

INJ_RDY Injection ready interrupt See Frame InjectionThis interrupt has bit index 22 in INTR_ and DST_INTR_ registers

PCIE PCIe interrupt See Power ManagementThis interrupt has bit index 23 in INTR_ and DST_INTR_ registers

Table 174 bull Interrupt Sources (continued)

Source Name Description

The following table lists the available interrupt destinations in the device

All interrupts events and indications inside in the interrupt controller are active high If an interrupt source supports polarity correction it is applied before going into the interrupt controller If an interrupt destination supports polarity correction it is applied after leaving the interrupt controller

48121 Interrupt Source ConfigurationInterrupt sources are handled identically inside the interrupt controller This section describes interrupt source n which refers to the bit index of that interrupt source in the INTR_ and DST_INTR_ registers The following illustration shows the logic associated with a single interrupt source

Figure 86 bull Interrupt Source Logic

The current value of an interrupt source is available in INTR_RAWINTR_RAW[n] INTR_STICKYINTR_STICKY[n] is set when the interrupt controller detects an interrupt There are two detection methods

bull When INTR_TRIGGERINTR_TRIGGER[n] is set to level-activated the interrupt controller continually sets INTR_STICKYINTR_STICKY[n] for as long as the interrupt source is active

bull When INTR_TRIGGERINTR_TRIGGER[n] is set to edge-triggered the interrupt controller only sets INTR_STICKYINTR_STICKY[n] when the interrupt source changes value

bull When INTR_TRIGGERINTR_TRIGGER[n] is set to falling-edge-triggered the interrupt controller only sets INTR_STICKYINTR_STICKY[n] when the interrupt source changes from active to inactive value

bull When INTR_TRIGGERINTR_TRIGGER[n] is set to rising-edge-triggered the interrupt controller only sets INTR_STICKYINTR_STICKY[n] when the interrupt source changes from inactive to active value

Software can clear INTR_STICKYINTR_STICKY[n] by writing 1 to bit n However the interrupt controller will immediately set this bit again if the source input is still active (when INTR_TRIGGER is 0) or if it sees a triggering event on the source input (when INTR_TRIGGER different from 0)

The interrupt source is enabled in INTR_ENAINTR_ENA[n] When INTR_STICKYINTR_STICKY[n] is set and the interrupt is enabled the interrupt is indicated towards the interrupt destinations For more

Table 175 bull Interrupt Destinations

Destination Name DescriptionCPU0 Interrupt 0 to VCore-Ie CPU This interrupt has replication index 0 in

DST_INTR_ registers

CPU1 Interrupt 1 to VCore-Ie CPU This interrupt has replication index 1 in DST_INTR_ registers

EXT_DST0 External interrupt destination 0 See External Interrupts This interrupt has replication index 2 in DST_INTR_ registers

Filter Logic00 Pass any01 Detect change10 Active to inactive11 Inactive to active

INTR_TRIGGERINTR_TRIGGER[n]

Interrupt Source n

StickyHold interrupt indication until cleared by SW

INTR_STICKYINTR_STICKY[n]

INTR_BYPASSINTR_BYPASS[n]

INTR_ENAINTR_ENA[n]

INTR_IDENTINTR_IDENT[n]

To destination logic

INTR_RAWINTR_RAW[n]

information see Interrupt Destination Configuration An active and enabled interrupt source sets INTR_IDENTINTR_IDENT[n]

On rare occasions it is desirable to bypass the stickiness of interrupt sources and use INTR_RAWINTR_RAW[n] directly instead of INTR_STICKYINTR_STICKY[n] Set INTR_BYPASSINTR_BYPASS[n] to enable bypass and ignore INTR_STICKY and INTR_TRIGGER configurations

Note The bypass function may be useful for some software interrupt handler architectures It should only be used for interrupt sources that are guaranteed to be sticky in the source block For example the GPIO interrupts that are generated from sticky bits in DEVCPU_GCBGPIO_INTR may be applicable for the bypass mode

48122 Interrupt Destination ConfigurationThe four interrupt destinations are handled identically in the interrupt controller This section describes destination d which refers to the replication index of that interrupt in the DST_INTR_ registers The following illustration shows the logic associated with a single interrupt destination

Figure 87 bull Interrupt Destination Logic

The interrupt destination can enable individual sources for interrupt by writing a mask to DST_INTR_MAP[d]DST_INTR_MAP When a source is enabled in DST_INTR_MAP then an interrupt from this source will be propagated to the interrupt destination

The currently active and enabled source interrupts for a destination can be seen by reading DST_INTR_IDENT[d]DST_INTR_IDENT

48123 Port Module InterruptsEach port module can generate an interrupt Because there are too many modules to handle the interrupts in parallel with the other source interrupts in the INTR_ registers the port module interrupts are aggregated in a separate source interrupt hierarchy before being presented to the interrupt controller source logic as the DEV source interrupt

Figure 88 bull Port Module Interrupt Logic

The module interrupt polarity is configurable in DEV_INTR_POLDEV_INTR_POL[m]

DEV_INTR_RAW DEV_INTR_TRIGGER DEV_INTR_STICKY DEV_INTR_BYPASS DEV_INTR_ENA and DEV_INTR_IDENT works in the same way as the INTR_ counterparts see Interrupt Source Configuration for more information

The final step when handling module interrupts is an aggregation of all individual module interrupts to the DEV source interrupt

From source logicInterrupt destination d

DST_INTR_MAP[d]DST_INTR_MAP

DST_INTR_IDENT[d]DST_INTR_IDENT

OR (n to 1)AND

D Q QD

DEV_POLDEV_POL[m]

DEV_INTR_ENADEV_INTR_ENA[m]

Module interrupt m

ldquoDEVrdquo Source Interrupt0

DEV_INTR_BYPASSDEV_INTR_BYPASS[m]

DEV_INTR_STICKYDEV_INTR_STICKY[m]

ANDXOR

DEV_INTR_RAWDEV_INTR_RAW[m]

DEV_INTR_TRIGGERDEV_INTR_TRIGGER[m]

DEV_INTR_IDENTDEV_INTR_IDENT[m]

OR (m to 1)

The last part ORrsquos all the m module interrupts together to form the

aggregated ldquoDEVrdquo source interrupt

48124 External InterruptsThe interrupt controller supports two external source interrupts (inputs to the device) and two external destination interrupts (outputs from the device) The external interrupts are mapped to GPIOs using overlaid functions For more information about overlaid functions on the GPIOs for these signals see GPIO Overlaid Functions page 204

Source and destination interrupts works independently from each other and can be used at the same time The polarity (active high or low) of source and destination interrupts is configured in EXT_SRC_INTR_POL and EXT_DST_INTR_POL respectively

For destination interrupts it is possible to drive the output pin permanently or emulate open-collector output

bull To drive permanently configure EXT_INTR_DRV[e] = 0bull To emulate open collector output configure EXT_INTR_DRV[e] = 1 and EXT_INTR_POL[e] = 0 To

safely enable open-collector output the EXT_INTR_DRV and EXT_INTR_POL registers must be configured before enabling the overlaid function in the GPIO controller

Note Open collector output mode is required when multiple interrupt sources are hooked up to the same interrupt wire on the PCB and the wire is be pulled high with a resistor Each interrupt source can then drive the wire low through open-collector output when they want to signal interrupt

Table 176 bull External Interrupt Pins

Register IO DescriptionIRQ0_INGPIO I External Source Interrupt 0 Polarity is configured in

EXT_SRC_INTR_POLEXT_INTR_POL[0]

IRQ1_INGPIO I External Source Interrupt 1 Polarity is configured in EXT_SRC_INTR_POLEXT_INTR_POL[1]

IRQ0_OUTGPIO O External Destination Interrupt 0 Polarity is configured in EXT_DST_INTR_POLEXT_INTR_POL[0] This interrupt can also be mapped to GPIO (replaces source interrupt)

Features

5 Features

This section provides information about specific features supported by individual blocks in the device and how these features are administrated by configurations across the entire device Examples of various standard features are included such as the support for different spanning tree versions and VLAN operations as well as more advanced features such as QoS and VCAP

51 Switch ControlThis section provides information about the minimum requirements for switch operation

511 Switch InitializationThe following initialization sequence is required to ensure proper operation of the switch

1 Soft-reset the switch coreDEVCPU_GCBSOFT_RSTSOFT_SWC_RST = 1

2 Wait for DEVCPU_GCBSOFT_RSTSOFT_SWC_RST to clearInitialize memoriesSYSRESET_CFGMEM_ENA = 1SYSRESET_CFGMEM_INIT = 1

3 Wait 100 micros for memories to initialize (SYSRESET_CFGMEM_INIT cleared)4 Enable the switch core

SYSRESET_CFGCORE_ENA = 15 Enable each port module through QSYSPORTSWITCH_PORT_MODEPORT_ENA = 1

52 Port Module ControlThis section provides information about the features and configurations for port reset and port counters

521 Port Reset ProcedureWhen changing a switch portrsquos mode of operation or restarting a switch port the following port reset procedure must be followed

1 Disable the MAC frame reception in the switch portDEVMAC_ENA_CFGRX_ENA = 0

2 Disable traffic being sent to or from the switch portQSYSPORTSWITCH_PORT_MODE_ENA = 0

3 Disable shaping to speed up flushing of framesQSYSPORT_MODEDEQUEUE_DIS = 1

4 Wait at least the time it takes to receive a frame of maximum length at the portWorst-case delays for 10 kilobyte jumbo frames arebull 8 ms on a 10M portbull 800 micros on a 100M portbull 80 micros on a 1G portbull 32 micros on a 25G port

5 Disable HDX backpressureSYSFRONT_PORT_MODEHDX_MODE = 0

6 Flush the queues associated with the portREWPORTPORT_CFGFLUSH_ENA = 1

7 Enable dequeuing from the egress queuesQSYSPORT_MODEDEQUEUE_DIS = 0

8 Wait until flushing is completeQSYSPORTSW_STATUSEQ_AVAIL must return 0

9 Reset the switch port by setting the following reset bits in CLOCK_CFG

Features

bull DEVCLOCK_CFGMAC_TX_RST = 1bull DEVCLOCK_CFGMAC_RX_RST = 1bull DEVCLOCK_CFGPORT_RST = 1

10 Clear flushing againREWPORTPORT_CFGFLUSH_ENA = 0

11 Set up the switch port to the new mode of operation Keep the reset bits in CLOCK_CFG set12 Release the switch port from reset by clearing the reset bits in CLOCK_CFG

Note It is not necessary to reset the SerDes macros

522 Port CountersThe statistics collected in each port module provide monitoring of various events This section describes how industry-standard Management Information Bases (MIBs) can be implemented using the counter set in the device The following MIBs are considered

bull RMON statistics group (RFC 2819)bull IEEE 8023-2005 Annex 30A countersbull SNMP interfaces group (RFC 2863)bull SNMP Ethernet-like group (RFC 3536)

5221 RMON Statistics Group (RFC 2819)The following table provides the mapping of RMON counters to port counters

Table 177 bull Mapping of RMON Counters to Port Counters

RMON Counter RXTX Switch Core ImplementationEtherStatsDropEvents RX C_RX_CAT_DROP + C_DR_TAIL +

sum of C_DR_YELLOW_PRIO_x +sum of C_DR_GREEN_PRIO_x where x is 0 through 7

EtherStatsOctets RX C_RX_OCT

EtherStatsPkts RX C_RX_SHORT + C_RX_FRAG + C_RX_JABBER + C_RX_LONG + C_RX_SZ_64 + C_RX_SZ_65_127 + C_RX_SZ_128_255 + C_RX_SZ_256_511 + C_RX_SZ_512_1023 + C_RX_SZ_1024_1526 + C_RX_SZ_JUMBO

EtherStatsBroadcastPkts RX C_RX_BC

EtherStatsMulticastPkts RX C_RX_MC

EtherStatsCRCAlignErrors RX C_RX_CRC

EtherStatsUndersizePkts RX C_RX_SHORT

EtherStatsOversizePkts RX C_RX_LONG

EtherStatsFragments RX C_RX_FRAG

EtherStatsJabbers RX C_RX_JABBER

EtherStatsPkts64Octets RX C_RX_SZ_64

EtherStatsPkts65to127Octets RX C_RX_SZ_65_127

EtherStatsDropEvents TX C_TX_DROP + C_TX_AGE

Features

5222 IEEE 8023-2005 Annex 30A CountersThis section provides the mapping of IEEE 8023-2005 Annex 30A counters to port counters Only counter groups with supported counters are listed

EtherStatsOctets TX C_TX_OCT

EtherStatsPkts TX C_TX_SZ_64 + C_TX_SZ_65_127 + C_TX_SZ_128_255 + C_TX_SZ_256_511 + C_TX_SZ_512_1023 + C_TX_SZ_1024_1526 + C_TX_SZ_JUMBO

EtherStatsBroadcastPkts TX C_TX_BC

EtherStatsMulticastPkts TX C_TX_MC

EtherStatsCollisions TX C_TX_COL

EtherStatsPkts64Octets TX C_TX_SZ_64

EtherStatsPkts65to127Octets TX C_TX_SZ_65_127

Table 178 bull Mandatory Counters

Counter RxTx Switch Core ImplementationaFramesTransmittedOK TX C_TX_SZ_64 + C_TX_SZ_65_127 +

C_TX_SZ_128_255 + C_TX_SZ_256_511 + C_TX_SZ_512_1023 + C_TX_SZ_1024_1526 + C_TX_SZ_JUMBO

aSingleCollisionFrames TX Not available

aMultipleCollisionFrames TX Not available

aFramesReceivedOK RX Sum of C_RX_GREEN_PRIO_x + C_RX_YELLOW_PRIO_x where x is 0 through 7

aFrameCheckSequenceErrors RX Not available C_RX_CRC is the sum of FCS and alignment errors

aAlignmentErrors RX Not available C_RX_CRC is the sum of FCS and alignment errors

Table 179 bull Optional Counters

Counter RXTX Switch Core ImplementationaMulticastFramesXmittedOK TX C_TX_MC

aBroadcastFramesXmittedOK TX C_TX_BC

aMulticastFramesReceivedOK RX C_RX_MC

aBroadcastFramesReceivedOK RX C_RX_BC

aInRangeLengthErrors RX Not available

aOutOfRangeLengthField RX Not available

Table 177 bull Mapping of RMON Counters to Port Counters (continued)

RMON Counter RXTX Switch Core Implementation

Features

5223 SNMP Interfaces Group (RFC 2863)The following table provides the mapping of SNMP interfaces group counters to port counters

aFrameTooLongErrors RX C_RX_LONG

Table 180 bull Recommended MAC Control Counters

Counter RXTX Switch Core ImplementationaMACControlFramesTransmitted TX Not available

aMACControlFramesReceived RX C_RX_CONTROL

aUnsupportedOpcodesReceived RX Not available

Table 181 bull Pause MAC Control Recommended Counters

Counter RXTX Switch Core ImplementationaPauseMACControlFramesTransmitted TX C_TX_PAUSE

aPauseMACControlFramesReceived RX C_RX_PAUSE

Table 182 bull Mapping of SNMP Interfaces Group Counters to Port Counters

Counter RXTX Switch Core ImplementationIfInOctets RX C_RX_OCT

IfInUcastPkts RX C_RX_UC

IfInNUcastPkts RX C_RX_BC + C_RX_MC

IfInBroadcast (RFC 1573) RX C_RX_BC

IfInMulticast (RFC 1573) RX C_RX_MC

IfInDiscards RX C_DR_TAIL + C_RX_CAT_DROP

IfInErrors RX C_RX_CRC + C_RX_SHORT + C_RX_FRAG + C_RX_JABBER + C_RX_LONG

IfInUnknownProtos RX Always zero

IfOutOctets TX C_TX_OCT

IfOutUcastPkts TX C_TX_UC

IfOutNUcastPkts TX C_TX_BC + C_TX_MC

ifOutMulticast (RFC 1573) TX C_TX_MC

ifOutBroadcast (RFC 1573) TX C_TX_BC

IfOutDiscards TX Always zero

IfOutErrors TX C_TX_DROP + C_TX_AGE

Table 179 bull Optional Counters (continued)

Counter RXTX Switch Core Implementation

Features

5224 SNMP Ethernet-Like Group (RFC 3536)The following table provides the mapping of SNMP Ethernet-like group counters to port counters

53 Layer-2 SwitchThis section describes the following Layer-2 switch features

bull Switchingbull VLAN and GVRPbull Rapid and Multiple Spanning Treebull Link aggregationbull Port-based access controlbull Mirroring bull SNMP support

531 Basic SwitchingBasic switching covers forwarding address learning and address aging

5311 ForwardingThe device contains a Layer-2 switch and frames are forwarded using Layer-2 information only Exceptions to this are possible using VCAP capabilities For example to provide source-specific IP multicast forwarding

The switch is designed to comply with the IEEE Bridging standard in Std 8021D and the IEEE VLAN standard in Std 8021Q

bull Unicast frames are forwarded to a single destination port that corresponds to the DMACbull Multicast frames are forwarded to multiple ports determined by the DMAC multicast group The CPU

configures multicast groups in the MAC table and the port group identifier (PGID) table A multicast group can span across any set of ports

Table 183 bull Mapping of SNMP Ethernet-Like Group Counters to Port Counters

Counter RXTX Switch Core Implementationdot3StatsAlignmentErrors RX Not available C_RX_CRC is the sum of FCS

and alignment errors

dot3StatsFCSErrors RX Not available C_RX_CRC is the sum of FCS and alignment errors

dot3StatsSingleCollisionFrames TX Not available

dot3StatsMultipleCollisionFrames TX Not available

dot3StatsSQETestErrors RX Not applicable

dot3StatsDeferredTransmissions TX Not available

dot3StatsLateCollisions TX Not available C_TX_DROP is the sum of Late collisions and Excessive collisions

dot3StatsExcessiveCollisions TX Not available C_TX_DROP is the sum of Late collisions and Excessive collisions

dot3StatsInternalMacTransmitErrors TX Not applicable Always 0

dot3StatsCarrierSenseErrors TX Not available

dot3StatsFrameTooLongs RX C_RX_LONG

dot3StatsInternalMacReceiveErrors RX Not applicable Always 0

dot3InPauseFrames RX C_RX_PAUSE

dot3OutPauseFrames TX C_TX_PAUSE

Features

bull Broadcast frames (DMAC = FF-FF-FF-FF-FF-FF) are by default flooded to all ports except the ingress port Also in compliance with the standard a unicast or multicast frame with unknown DMAC is flooded to all ports except the ingress port It is possible to configure flood masks to restrict the flooding of frames There are separate flood masks for the following frame typesbull Unicast (ANAFLOODINGFLD_UNICAST)bull Layer 2 multicast (ANAFLOODINGFLD_MULTICAST)bull Layer 2 broadcast (ANAFLOODINGFLD_BROADCAST)bull IPv4 multicast data (ANAFLOODING_IPMCFLD_MC4_DATA)bull IPv4 multicast control (ANAFLOODING_IPMCFLD_MC4_CTRL)bull IPv6 multicast data (ANAFLOODING_IPMCFLD_MC6_DATA)bull IPv6 multicast control (ANAFLOODING_IPMCFLD_MC6_CTRL)

For frames with a known destination MAC address the destination mask comes from an entry in the port group identifier table (ANAPGID) The PGID table contains 92 entries (entry 0 through 91) where entry 0 through 63 are used for destination masks The remaining PGID entries are used for other parts of the forwarding and are described below

The following table shows the PGID table organization

The unicast entries contains only the port number corresponding to the entry number

Destination masks for multicast groups must be manually entered through the CPU into the destination masks table IPv4 and IPv6 multicast entries can also be entered using direct encoding in the MAC table where the destination masks table is not used For information about forwarding and configuring destination masks see ltneed referencegt

The aggregation masks ensures that a frame is forwarded to exactly one member of an aggregation group

For all forwarding decisions a source mask prevents frames from being sent back to the ingress port The source mask removes the ingress port from the destination mask

All ports are enabled for receiving frames by default This can be disabled by clearing ANAPORTPORT_CFGRECV_ENA

5312 Address LearningThe learning process minimizes the flooding of frames A framersquos source MAC address is learned together with its VID Each entry in the MAC table is uniquely identified by a (MACVID) pair In the forwarding process a framersquos (DMACVID) pair is used as the key for the MAC table lookup

The learning of unknown SMAC addresses can be either hardware-based or CPU-based The following list shows the available learn schemes which can be configured per port

bull Hardware-based learning autonomously adds entries to the MAC table without interaction from the CPU Use the following configurationbull ANAPORTPORT_CFGLEARN_ENA = 1bull ANAPORTPORT_CFGLEARNCPU = 0bull ANAPORTPORT_CFGLEARNDROP = 0bull ANAPORTPORT_CFGLEARNAUTO = 1

bull CPU-based learning copies frames with unknown SMACs or when the SMAC appears on a different port to the CPU These frames are forwarded as usual Use the following configurationbull ANAPORTPORT_CFGLEARN_ENA = 1bull ANAPORTPORT_CFGLEARNCPU = 1

Table 184 bull Port Group Identifier Table Organization

Entry Type NumberUnicast entries 0 ndash 11 (including CPU)

Multicast entries 12 ndash 63

Aggregation Masks 64 ndash 79

Source Masks 80 ndash 91

Features

bull ANAPORTPORT_CFGLEARNDROP = 0bull ANAPORTPORT_CFGLEARNAUTO = 0

bull Secure CPU-based learning is similar to CPU-based learning except that it allows the CPU to verify the SMAC addresses before both learning and forwarding Secure CPU-based learning redirects frames with unknown SMACs or when the SMAC appears on a different port to the CPU These frames are not forwarded by hardware Use the following configurationbull ANAPORT_CFGLEARN_ENA = 1bull ANAPORT_CFGLEARNCPU = 1bull ANAPORT_CFGLEARNDROP = 1bull ANAPORT_CFGLEARNAUTO = 0

bull No learning where all learn frames are discarded Frames with known SMAC in the MAC table are forwarded by hardware Use the following configurationbull ANAPORTPORT_CFGLEARN_ENA = 1bull ANAPORTPORT_CFGLEARNCPU = 0bull ANAPORTPORT_CFGLEARNDROP = 1bull ANAPORTPORT_CFGLEARNAUTO = 0

Frames forwarded to the CPU for learning can be extracted from the CPU extraction queue configured in ANAPORTCPUQ_CFGCPUQ_LRN

During CPU-based learning the rate of frames subject to learning being copied or redirected to the CPU can be controlled with the learn storm policer (ANASTORMLIMIT_CFG[3]) This policer puts a limit on the number of frames per second that are subject to learning being copied or redirected to the CPU The learn frames storm policer can help prevent a CPU from being overloaded when performing CPU based learning

5313 MAC Table Address AgingTo keep the MAC table updated an aging scan is conducted to remove entries that were not recently accessed This ensures that stations that have moved to a new location are not permanently prevented from receiving frames in their new location It also frees up MAC table entries occupied by obsolete stations to give room for new stations

In IEEE 8021D the recommended period for aging-out entries in the MAC address table is 300 seconds per entry The device aging implementation checks for the aging-out of all the entries in the table The first age scan sets the age bit for every entry in the table The second age scan removes entries where the age bit has not been cleared since the first age scan An entryrsquos age bit is cleared when a received framersquos (SMAC VID) matches an entryrsquos (MAC VID) that is the station is active and transmits frames To ensure that 300 seconds is the longest an entry can reside inaccessible (and unchanged) in the table the maximum time between age scans is 150 seconds

The device can conduct age scans in two ways

bull Automatic age scansbull CPU initiated age scansWhen using automatic aging the time between age scans is set in the ANAAUTOAGE register in steps of 1 second in the range from 1 second to 12 days

When using CPU-initiated aging the CPU implements the timing between age scans A scan is initiated by sending an aging command to the MAC address table (ANAMACACCESSMAC_TABLE_CMD)

The CPU-controlled age scan process can conveniently be used to flush the entire MAC table by conducting two age scans one immediately after the other

Flushing selective MAC table entries is also possible Incidents that require MAC table flushing are

bull Reconfiguration of Spanning Tree protocol port states which may cause station moves to occurbull If there is a link failure notification (identified by a PHY layer device) flush the MAC table on the

specific port where the link failedTo deal with these incidents the age scan process is configurable to run only for entries learned on a specified port or for a specified VLAN (ANAANAGEFILVID_VAL) The filters can also be combined to do aging on entries that match both the specific port and the specific VLAN

Features

Single entries can be flushed from the MAC table by sending the FORGET command to the MAC address table

532 Standard VLAN OperationThis section provides information about configuring and operating the device as a standard VLAN-aware switch Subsequent sections discuss the switch as a Q-in-Q enabled provider bridge and the use of private VLANs and asymmetric VLANs

The following table lists the port module registers for standard VLAN operation

The following table lists the analyzer configurations and status bits for standard VLAN operation

Table 185 bull Port Module Registers for Standard VLAN Operation

RegisterRegister Field Description ReplicationMAC_TAGS_CFG Allows tagged frames to be 4 bytes longer than the

length configured in MAC_MAXLEN_CFGPer port

Table 186 bull Analyzer Registers for Standard VLAN Operation

RegisterRegister Field Description ReplicationDROP_CFGDROP_UNTAGGED_ENA Discard untagged frames Per port

DROP_CFGDROP_C_TAGGED_ENA Discard VLAN tagged frames Per port

DROP_CFGDROP_PRIO_C_TAGGED_ENA

Discard priority tagged frames Per port

VLAN_CFGVLAN_AWARE_ENA Use incoming VLAN tags in VLAN classification

Per port

VLAN_CFGVLAN_POP_CNT Remove VLAN tags from frames in the rewriter

Per port

VLAN_CFGVLAN_DEIVLAN_CFGVLAN_PCPVLAN_CFGVLAN_VID

Ingress port VLAN configuration Per port

VLANMASK Per-port VLAN ingress filtering enable None

ANEVENTSVLAN_DISCARD A sticky bit indicating that a frame was dropped due to lack of VLAN membership of source port

ADVLEARNVLAN_CHK Disable learning for frames discarded due to source port VLAN membership check

VLANACCESS VLAN table command For indirect access to configuration of the 4096 VLANs

VLANTIDX VLAN table index For indirect access to configuration of the 4096 VLANs

AGENCTRLFID_MASK Enable shared VLAN learning None

CPU_FWD_GARP_CFG Enable capture of frames with reserved GARP DMAC addresses including GVRP for VLAN registration Per-address configuration

Per port

CPUQ_8021_CFGCPUQ_GARP_VAL CPU queue for captured GARP frames Per GARP address

Features

The following table lists the rewriter registers for standard VLAN operation

In a VLAN-aware switch each port is a member of one or more virtual LANs Each incoming frame must be assigned a VLAN membership and forwarded according to the assigned VID The following information draws on the definitions and principles of operations in IEEE 8021Q Note that the switch supports more features than mentioned in the following section which only describes the basic requirements for a VLAN aware switch

Standard VLAN operation is configured individually per switch port using the following configuration

bull MAC_TAGS_CFGVLAN_AWR_ENA = 1MAC_TAGS_CFGVLAN_LEN_AWR_ENA = 1

bull VLAN_CFGVLAN_AWARE_ENA = 1 VLAN_CFGVLAN_POP_CNT = 1

Each switch port has an Acceptable Frame Type parameter which is set to Admit Only VLAN tagged frames or Admit All Frames

bull Admit Only VLAN-tagged framesbull DROP_CFGDROP_UNTAGGED_ENA = 1bull DROP_CFGDROP_PRIO_C_TAGGED_ENA = 1bull DROP_CFGDROP_C_TAGGED = 0

bull Admit All Framesbull DROP_CFGDROP_UNTAGGED_ENA = 0bull DROP_CFGDROP_PRIO_C_TAGGED_ENA = 0bull DROP_CFGDROP_C_TAGGED = 0

Frames that are not discarded are subject to the VLAN classification Untagged and priority-tagged frames are classified to a Port VLAN Identifier (PVID) The PVID is configured per port in VLAN_CFGVLAN_VID Tagged frames are classified to the VID given in the framersquos tag For more information about VLAN classification see VLAN Classification page 55

5321 ForwardingForwarding is always based on the combination of the classified VID and the destination MAC address By default all switch ports are members of all VLANs This can be changed in VLANACCESS and VLANTIDX where port masks per VLAN are set up

5322 Ingress FilteringVLAN ingress filtering can be enabled per switch port with the register VLANMASK

The filter checks for all incoming frames to determine if the ingress port is a member of the VLAN to which the frame is classified If the port is not a member the frame is discarded Whenever a frame is discarded due to lack of VLAN membership the ANEVENTSVLAN_DISCARD sticky bit is set To ensure that VLAN ingress filtered frames are not learned ADVLEARNVLAN_CHK must be set

5323 GVRPGARP VLAN Registration Protocol (GVRP) is used to propagate VLAN configurations between bridges On a GVRP-enabled switch all GVRP frames must be redirected to the CPU for further processing The GVRP frames use a reserved GARP MAC address (01-80-C2-00-00-21) and can be redirected to the CPU by setting bit 1 in the analyzer register CPU_FWD_GARP_CFG

5324 Shared VLAN LearningThe device can be configured for either Independent VLAN learning or Shared VLAN learning Independent VLAN learning is the default

Table 187 bull Rewriter Registers for Standard VLAN Operation

RegisterRegister Field Description ReplicationTAG_CFG Egress VLAN tagging configuration Per port

PORT_VLAN_CFG Egress port VLAN configuration Per port

Features

Shared VLAN learning where multiple VLANs map to the same filtering database is enabled through Filter Identifiers (FIDs) Basically this means that learning is unique for a (MAC FID) set and that a learned MAC address is learned for all VIDs that map to the FID Shared VLAN learning is configured in FID_MAP per VLAN The device supports 64 different FIDs Any number of VLANs can map to the same FID

5325 UntaggingAn untagged set can be configured for each egress port which defines the VIDs for which frames are transmitted untagged The untagged set can consist of zero one or all VIDs For all VIDs not in the untagged set frames are transmitted tagged The available configurations in the rewriter are

bull The untagged set is emptyREWPORTTAG_CFGTAG_CFG = 3

bull The untagged set consists of all VIDsREWPORTTAG_CFGTAG_CFG = 0

bull The untagged set consists of one VID ltVIDgtREWPORTTAG_CFGTAG_CFG = 1REWPORTPORT_VLAN_CFGPORT_VID = ltVIDgt

Optionally frames received as priority-tagged frames (VID = 0) can also be transmitted as untagged (REWPORTTAG_CFGTAG_CFG=2)

Port-Based VLAN Example

Situation

Ports 0 and 1 are isolated from ports 2 and 3 using port-based VLANs Ports 0 and 1 are assigned port VID 1 and ports 2 and 3 port VID 2 All frames in the network are untagged

Resolution

Port module configuration of ports 0 ndash 1 Configure the ports to always use the port VIDVLAN_CFGVLAN_AWARE_ENA = 0 Allow only untagged framesDROP_CFGDROP_UNTAGGED_ENA = 0DROP_CFGDROP_PRIO_C_TAGGED = 1DROP_CFGDROP_C_TAGGED = 1 Configure the port VID to 1VLAN_CFGVLAN_VID = 1

Port module configuration of ports 2 ndash 3 Same as for ports 0-1 except that the port VID is set to 2VLAN_CFGVLAN_VID = 2 Analyzer configuration Configure VLAN 1 to contain ports 0-1VLANTIDXINDEX = 1VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 1VLANACCESSVLAN_PORT_MASK = 0x03VLANACCESSVLAN_TBL_CMD = 2 Configure VLAN 2 to contain ports 2-3VLANTIDXINDEX = 2VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 1VLANACCESSVLAN_PORT_MASK = 0x0CVLANACCESSVLAN_TBL_CMD = 2

Features

533 Provider Bridges and Q-in-Q OperationThe following table lists the port module configurations for provider bridge VLAN operation

The following table lists the port module configurations for provider bridge VLAN operation

The following table lists the analyzer configurations for provider bridge VLAN operation

The device supports the standard provider bridge features in IEEE 8021ad (Provider Bridges) Features related to provider bridges are

bull Support for multiple tag headers (EtherTypes 0x8100 0x88A8 and a programmable value are recognized as tag header EtherTypes)

bull Pushing and popping of up to two VLAN tagsbull Selective VLAN classification using either inner or outer VLAN tagbull Translating VLAN tag headers at ingress andor at egress (using the IS1 and ES0 TCAMs)bull Enabling or disabling learning per VLAN

Table 188 bull Port Module Configurations for Provider Bridge VLAN Operation

RegisterRegister Field Description ReplicationMAC_TAGS_CFG Allow single tagged frames to be 4 bytes longer and

double-tagged frames to be 8 bytes longer than the length configured in MAC_MAXLEN_CFG

Per port

Table 189 bull System Configurations for Provider Bridge VLAN Operation

RegisterRegister Field Description ReplicationVLAN_ETYPE_CFGVLAN_S_TAG_ETYPE_VAL

TPID for S-tagged frames EtherType 0x88A8 and the configurable value VLAN_ETYPE_CFGVLAN_S_TAG_ETYPE_VAL are identified as the S-tag identifier

Per port

Table 190 bull Analyzer Configurations for Provider Bridge VLAN Operation

DROP_CFGDROP_S_TAGGED_ENA Discard VLAN S-tagged frames Per port

DROP_CFGDROP_PRIO_S_TAGGED_ENA Discard priority S-tagged frames Per port

Per port

VLAN_CFGVLAN_TAG_TYPE Tag type for untagged frames (Customer tag or service tag)

Per port

VLAN_CFGVLAN_INNER_TAG_ENA Use inner tag for VLAN classification instead of outer tag

Per port

Features

The following section discusses briefly how to configure these different features in the switch

The device supports multiple VLAN tags They can be used in MAN applications as a provider bridge aggregating traffic from numerous independent customer LANs into the MAN space One of the purposes of the provider bridge is to recognize and use VLAN tags so that the VLANs in the MAN space can be used independent of the customersrsquo VLANs This is accomplished by adding a VLAN tag with a MAN-related VID for frames entering the MAN When leaving the MAN the tag is stripped and the original VLAN tag with the customer-related VID is again available This provides a tunneling mechanism to connect remote customer VLANs through a common MAN space without interfering with the VLAN tags All tags use EtherType 0x8100 for customer tags and EtherType 0x88A8 or a programmable value for service provider tags

In cases where a given service VLAN only has two member ports on the switch the learning can be disabled for the particular VLAN (VLANTIDXVLAN_LEARN_DISABLE) and can rely on flooding as the forwarding mechanism between the two ports This way the MAC table requirements are reduced

53301 MAN Access Switch ExampleSituation

The following is an example of setting up the device as a MAN access switch with the following requirements

bull Customer ports are aggregated into a network port for tunneling through the MAN to access remote VLANs

bull Local switching between ports of the different customers must be eliminatedbull Frames must be label-switched from network port to correct customer port without need for MAC

address learning

Features

Figure 89 bull MAN Access Switch Setup

This example is typically accomplished by letting each customer port have a unique port VID (PVID) which is used in the outer VLAN tag (the service provider tag) In the MAN the VID directly indicates the customer port from which the frame is received or the customer port to which the frame is going

A customer port is VLAN-unaware and classifies to a port-based VLAN In the egress direction of the customer port frames are transmitted untagged which facilitates the stripping of the outer tag That is the provider tag is stripped but the customer tag is kept The port must allow frames with a maximum size of 1522 bytes

Resolution

Configuration of customer 1rsquos port (port 8) Allow for a single VLAN tag in the length check and set the maximum length without VLAN tag to 1518 bytesMAC_TAGS_CFGVLAN_LEN_AWR_ENA = 1MAC_TAGS_CFGVLAN_AWAR_ENA = 1MAC_MAXLEN_CFGMAX_LEN = 1518

Customer 2s LANCustomer 1s LAN

MANService-Provider Domain

MAN Port Network PortCustomer

Frames in This Segment

Customer Tag

EtherType VID Description0x8100 1 Frames in customer 2s VLAN 1

0x8100 4 Frames in customer 2s VLAN 4

NA NA Customer 2s untagged frames

Customer Tag

EtherType VID

0x8100 1

Description

Frames in customer 1s VLAN 1

0x8100 0 Customer 1s priority-tagged frames

EtherType VID

0x88A8

Service Provider Tag(Outer Tag)

Customer Tag(Inner Tag)EtherType VID

0x8100 1

Description

0x88A8 1 0x8100 118

0x88A8 1 0x8100 0

0x88A8 2 0x8100 1

0x88A8 2 0x8100 4

0x88A8 2 NA NA

Frames tofrom customer 1s VLAN 1

Priority-tagged frames tofrom customer 1

Untagged frames tofrom customer 2

Features

Configure the port to leave any incoming tags in the frame and to ignore any incoming VLAN tags in the VLAN classification The port VID is always used in the VLAN classificationVLAN_CFGVLAN_POP_CNT = 0VLAN_CFGVLAN_AWARE_ENA = 0 Allow both C-tagged and untagged frames coming in to the device to also support customer traffic not using VLANs to be carried across the MANDROP_CFGDROP_UNTAGGED_ENA = 0DROP_CFGDROP_C_TAGGED = 0DROP_CFGDROP_PRIO_C_TAGGED = 0DROP_CFGDROP_S_TAGGED = 1DROP_CFGDROP_PRIO_S_TAGGED = 1 Use service provider tagging when frames from this port exit the switch (EtherType 0x88A8)VLAN_CFGVLANTAG_TYPE = 1 Configure the port VID to 1VLAN_CFGVLAN_VID = 1 Configure the egress side of the port to not insert tags (The service provider tags are stripped in the ingress side of the MAN port)TAG_CFGTAG_CFG = 0 Configuration of customer 2s port (port 9) Same as for customer 1rsquos port (port 8) except that the port VID is set to 2VLAN_CFGVLAN_VID = 2 Configuration of the network port (port 16) MAN traffic in transit between network ports is supported by configuring all network ports as follows Allow for two VLAN tags in the length check and set the max length without VLAN tags to 1518 bytesMAC_TAGS_CFGVLAN_LEN_AWR_ENA = 1MAC_TAGS_CFGVLAN_AWAR_ENA = 1MAC_TAGS_CFGPB_ENA =1MAC_MAXLEN_CFGMAX_LEN = 1518 Configure the port to use incoming VLAN tags in the VLAN classification and to remove the first (outer) VLAN tag (the service tag) from incoming framesVLAN_CFGVLAN_POP_CNT = 1VLAN_CFGVLAN_AWARE_ENA = 1 Allow only S-tagged framesDROP_CFGDROP_UNTAGGED_ENA = 1DROP_CFGDROP_C_TAGGED = 1DROP_CFGDROP_PRIO_C_TAGGED = 1DROP_CFGDROP_S_TAGGED = 0DROP_CFGDROP_PRIO_S_TAGGED = 0 The tag type is unused on the network portVLAN_CFGVLANTAG_TYPE = 0 Configure the egress side of the port to insert tagsTAG_CFGTAG_CFG = 1 Common configuration in the analyzer Configure VLAN 1 to contain customer 1rsquos port (port 8) and the network port (port 16) Disable learning in VLAN 1 Ingress filtering is donrsquot care for port based VLANsVLANTIDXINDEX = 1VLANTIDXVLAN_PRIV_VLAN = 0 (donrsquot care for this example)VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 1VLANTIDXVLAN_SRC_CHK = 0 (donrsquot care for this example)

Features

VLANACCESSVLAN_PORT_MASK = 0x00010100VLANACCESSVLAN_TBL_CMD = 2 Configure VLAN 2 to contain customer 2s port (port 9) and the network port (port 16) Disable learning in VLAN 2 Ingress filtering is donrsquot-care for port based VLANsVLANTIDXINDEX = 2VLANTIDXVLAN_PRIV_VLAN = 0 (donrsquot care for this example)VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 1VLANTIDXVLAN_SRC_CHK = 0 (donrsquot care for this example)VLANACCESSVLAN_PORT_MASK = 0x00010200VLANACCESSVLAN_TBL_CMD = 2

534 Private VLANsThe following table lists the analyzer configuration registers for private VLAN support

When a VLAN is configured to be a private VLAN communication between ports within that VLAN can be prevented Two application examples are

bull Customers connected to an ISP can be members of the same VLAN but they are not allowed to communicate with each other within that VLAN

bull Servers in a farm of web servers in a Demilitarized Zone (DMZ) are allowed to communicate with the outside world and with database servers on the inside segment but are not allowed to communicate with each other

For private VLANs to be applied the switch must first be configured for standard VLAN operation For more information see Standard VLAN Operation page 228 When this is in place one or more of the configured VLANs can be configured as private VLANs Ports in a private VLAN fall into one of three groups

bull Promiscuous portsbull Ports from which traffic can be forwarded to all ports in the private VLANbull Ports that can receive traffic from all ports in the private VLAN

bull Community Portsbull Ports from which traffic can only be forwarded to community and promiscuous ports in the

private VLANbull Ports that can receive traffic from only community and promiscuous ports in the private VLAN

bull Isolated portsbull Ports from which traffic can only be forwarded to promiscuous ports in the private VLANbull Ports that can receive traffic from only promiscuous ports in the private VLAN

The configuration of promiscuous community and isolated ports applies to all private VLANs

The forwarding of frames classified to a private VLAN happens

bull When traffic comes in on a promiscuous port in a private VLAN the VLAN mask from the VLAN table is applied

Table 191 bull Private VLAN Configuration Registers

Register Description ReplicationVLANACCESS VLAN table command For indirect access to configuration of

the 4096 VLANsNone

ISOLATED_PORTS VLAN port mask indicating isolated ports in private VLANs None

COMMUNITY_PORTS VLAN port mask indicating community ports in private VLANs

Features

bull When traffic comes in on a community port the ISOLATED_PORT mask is applied in addition to the VLAN mask from the VLAN table

bull When traffic comes in on an isolated port the ISOLATED_PORT mask and the COMMUNITY_PORT mask are applied in addition to the VLAN mask from the VLAN table

5341 ISP ExampleSituation

Customers A B and C are connected to the same switch at the ISP Customers A and B are allowed to communicate with each other as well as the ISP Customer C can only communicate with the ISP VLAN 1 is the private VLAN that isolates Customers A B from C Traffic on VLAN 1 coming in from the ISP (port 8) uses the VLAN mask in the VLAN table Traffic on VLAN 1 from customer A or B has the ISOLATED_PORTS mask applied in addition to the mask from the VLAN table with the result that traffic from customer A and B is not forwarded to customers C Traffic on VLAN 1 from customer C has the ISOLATED_PORTS mask and the COMMUNITY_PORTS mask applied in addition to the mask from the VLAN table with the result that traffic from customer C is not forwarded to customers A and B

The following illustration shows the desired setup

Figure 90 bull ISP Example for Private VLAN

Resolution

It is assumed that Port VID and tag handling for VLAN 1 is already configured according to the description in Standard VLAN Operation Configure VLAN 1 as a private VLAN in the VLAN table by performing these steps - Point to VLAN 1

RouterA RouterC

8 Promiscuous Port

Community Ports

VLAN 1

VLAN TableVID Ports in Mask Private

0 1 2 8

COMMUNITY_PORTS (Community ports set to 0)

0Bit Value

PC_A PC_C1 PC_C2PC_B

VLAN 1 VLAN 1

RouterB

VLAN 1

Isolated Port

ISOLATED_PORTS(Isolated ports set to 0)

0Bit Value

Features

- Set it as private - Disable mirroring of the VLAN (not important for the example) - Enable learning within the VLAN (not important for the example) - Disable source check within the VLAN (not important for the example) - Include ports 0 1 2 and 8 in the VLAN mask Insert the entry into the VLAN tableVLANTIDXINDEX = 1VLANTIDXVLAN_PRIV_VLAN = 1VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0 (donrsquot care for this example)VLANTIDXVLAN_SRC_CHK = 0 (dont care for this example)VLANACCESSVLAN_PORT_MASK = 0x00000107VLANACCESSVLAN_TBL_CMD = 2 Configure the private VLAN mask so that port 8 is a promiscuous port ports 0 and 1 are community ports and port 2 is an isolated portISOLATED_PORTSISOL_PORTS = 0x00000103COMMUNITY_PORTSCOMM_PORTS = 0x00000104

5342 DMZ ExampleSituation

VLAN 17 is a private VLAN that isolates Server1 and Server2 Traffic on VLAN 17 coming from the internal or the external router (ports 8 and 9) uses the VLAN mask in the VLAN table Traffic on VLAN 17 from Server1 and Server2 (ports 14 and 15) has the ISOLATED_PORTS applied in addition to the mask from the VLAN table with the result that traffic from Server1 is not forwarded to Server2 and visa versa

Figure 91 bull DMZ Example for Private VLAN

Resolution

It is assumed that Port VID and tag handling for VLAN 17 is already configured according to the description in Standard VLAN Operation Configure VLAN 17 as a private VLAN in the VLAN table by performing these steps - Point to VLAN 17 - Set it as private - Disable mirroring of the VLAN (not important for the example) - Enable learning within the VLAN (not important for the example)

LAN WAN

Server1 Server2

Internal Router External Router

ServerDB

Promiscuous Ports

Isolated Ports

VLAN 17 VLAN 17

VLAN 17VLAN 1714

VLAN Table

VID Ports in Mask Private

8 9 14 15

ISOLATED_PORTS (Promiscuous Ports Set to 1)

Bit Value

Features

- Disable source check within the VLAN (not important for the example) - Include ports 8 9 14 and 15 in the VLAN mask - Insert the entry into the VLAN tableVLANTIDXINDEX = 17VLANTIDXVLAN_PRIV_VLAN = 1VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0 (donrsquot care for this example)VLANTIDXVLAN_SRC_CHK = 0 (donrsquot care for this example)VLANACCESSVLAN_PORT_MASK = 0x0000C300VLANACCESSVLAN_TBL_CMD = 2 Configure the private VLAN mask so that ports 8 and 9 are promiscuous portsISOLATED_PORTSISOL_PORTS = 0x00000300

535 Asymmetric VLANsAsymmetric VLANs use the same configuration registers as for standard VLAN operation For more information about standard VLAN operation see Standard VLAN Operation page 228

Asymmetric VLANs can be used to prevent communication between hosts in a network This behavior is similar to what can be obtained by using private VLANs For more information seePrivate VLANs page 235

Situation

A server and two hosts are connected to a switch Communication between the hosts and the server should be allowed but the hosts are not allowed to communicate directly All traffic between the server and the hosts is untagged Host 1 is connected to port 9 host 2 to port 10 and the server to port 8

The host-1 port gets port VID 1 and the host-2 port gets port VID 2 The server port is a member of both VLANs 1 and 2 The server port gets port VID 3 and the two host ports are members of VLAN 3 as shown in the following illustration

Figure 92 bull Asymmetric VLANs

Resolution

Analyzer configurations common for ports 8 9 and 10 Allow only untagged framesDROP_CFGDROP_UNTAGGED_ENA = 0

VLAN Table

VID Ports in Mask

Host 2Host 1

Server8 PVID = 3

PVID = 1 9 10 PVID = 2

3 9 10

Features

DROP_CFGDROP_C_TAGGED_ENA = 1DROP_CFGDROP_PRIO_C_TAGGED_ENA = 1 As tagged frames are dropped all frames are classified to the port VIDVLAN_CFGVLAN_AWARE_ENA = 0 (donrsquot care for this example) Configure the egress side of the port to not insert tagsTAG_CFGTAG_CFG = 0 Analyzer configuration specific for port 8 Set the port VID to 3VLAN_CFGVLAN_VID = 3VLAN_CFGVLAN_DEI = 0 (donrsquot care for this example) Analyzer configuration specific for port 9 Set the port VID to 1VLAN_CFGVLAN_VID = 1VLAN_CFGVLAN_DEI = 0 (donrsquot care for this example)

Analyzer configuration specific for port 10 Set the port VID to 2VLAN_CFGVLAN_VID = 2VLAN_CFGVLAN_DEI = 0 (donrsquot care for this example) Analyzer configuration common to all ports Configure VLAN 1 to contain port 8VLANTIDXINDEX = 1VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 0VLANACCESSVLAN_PORT_MASK = 0x00000100VLANACCESSVLAN_TBL_CMD = 2 Configure VLAN 2 to contain port 8VLANTIDXINDEX = 2VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 0VLANACCESSVLAN_PORT_MASK = 0x00000100VLANACCESSVLAN_TBL_CMD = 2 Configure VLAN 3 to contain ports 9 and 10VLANTIDXINDEX = 3VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 0VLANACCESSVLAN_PORT_MASK = 0x00000600VLANACCESSVLAN_TBL_CMD = 2

536 Spanning Tree ProtocolsThis section provides information about Rapid Spanning Tree Protocol (RSTP) support and Multiple Spanning Tree Protocol (MSTP) support The device also supports legacy Spanning Tree Protocol (STP) STP was obsoleted by RSTP in IEEE 8021D and is not described in this document

It is assumed that only LAN ports connected to the switch core participate in the spanning tree protocol This implies that BPDUs are terminated by the switch core

Features

5361 Rapid Spanning Tree ProtocolThe following table lists the analyzer configuration registers for Rapid Spanning Tree Protocol (RSTP) operation

To eliminate potential loops in a network the Rapid Spanning Tree Protocol in IEEE 8021D creates a single path between any two bridges in a network adding stability and predictability to the network The protocol is implemented by assigning states to all ports Each state controls a portrsquos functionality limiting its ability to receive and transmit frames and learn addresses

Establishing a spanning tree is done through the exchange of BPDUs between bridge entities BPDUs are frequently exchanged between neighboring bridges These frames are identified by the Bridge protocol address range (DMAC = 01-80-C2-00-00-0x)

When there is a change in the network topology the protocol reconfigures the port states

Figure 93 bull Spanning Tree Example

The following table lists the Rapid Spanning Tree port state properties

The legacy STP states disabled blocking and listening correspond to the discarding state of RSTP

Table 192 bull Analyzer Configurations for RSTP Support

RegisterRegister Field Description ReplicationPGID[80-91] Source masks used for ingress filtering Per port

PGID[64-79] Aggregation masks that can be used for egress filtering for RSTP

PORT_CFGLEARN_ENA Enable learning per port Per port

CPU_FWD_BPDU_CFG Enable redirection of frames with reserved BPDU DMAC addresses

Per port per address

CPUQ_8021_CFGCPUQ_BPDU_VAL CPU extraction queue for redirected BPDU frames Per address

Table 193 bull RSTP Port State Properties

StateBPDU Reception

BPDU Generation

Frame Forwarding

SMAC Learning

Discarding Yes Yes No No

Learning Yes Yes No Yes

Forwarding Yes Yes Yes Yes

Spanning Tree Path Spanning Tree Path

Ports in discarding state

Features

All frames with a Bridge protocol address must be redirected to the CPU This is configured in CPU_FWD_BPDU_CFG BPDUs are forwarded to the CPU irrespective of the portrsquos RSTP state CPUQ_8021_CFGCPUQ_BPDU_VAL can be used to configure in which CPU extraction queue the BPDUs are placed BPDU generation is done through frame injection from the CPU

Frame forwarding is controlled through ingress filtering and egress filtering Ingress filtering can be done by using the source masks (PGID[80-91]) and egress filtering can be done by using the aggregation masks (PGID[64-79]) Forwarding can be disabled for ports not in the Forwarding state by clearing their source masks and excluding them from all aggregation masks The use of the aggregation masks for egress filtering does not preclude the combination of link aggregation and RSTP support All ports in a link aggregation group that are not in the Forwarding state must be disabled in all aggregation masks For link aggregated ports in the Forwarding state the aggregation masks must be configured for link aggregation (such as when RSTP is not supported)

Learning can be enabled per port with the PORT_CFGLEARN_ENA

The following table provides an overview of the port state configurations for port p

53611 RSTP ExampleSituation

Port 0 is in the RSTP Discarding state Port 2 is in the RSTP Learning state Port 3 is in the RSTP Forwarding state All other ports on the switch are unused

Resolution

Get Spanning Tree Protocol BDPUs to CPU extraction queue 0 for port 0 2 and 3CPU_FWD_BPDU_CFG[0]BPDU_REDIR_ENA[0] = 1CPU_FWD_BPDU_CFG[2]BPDU_REDIR_ENA[0] = 1CPU_FWD_BPDU_CFG[3]BPDU_REDIR_ENA[0] = 1CPUQ_8021_CFGCPUQ_BPDU_VAL[0] = 0 Configure the source mask for port 0 (Discarding state)PGID[80] = 0x00 Configure the source mask for port 2 (Learning state)PGID[82] = 0x00 Configure the source mask for port 3 (Forwarding state)PGID[83] = 0x77 Configure the aggregation masks to only allow forwarding to port 3 (Forwarding state)PGID[64-79] = 0x08 Configure the learn mask to only allow learning on ports 2 (Learning state) and 3 (Forwarding state)PORT_CFG[0]LEARN_ENA = 0PORT_CFG[2]LEARN_ENA = 1PORT_CFG[3]LEARN_ENA = 1

Table 194 bull RSTP Port State Configuration for Port p

CPU_FWD_BPDU_CFG[p]BPDU_REDIR_ENA[0] PGID[80+p]

PGID[64-79] All 16 Masks Bit p

PORT_CFG[p]LEARN_ENA

Discarding 1 0 0 0

Learning 1 0 0 1

Forwarding 1 1 except for bit p 1 1

Features

5362 Multiple Spanning Tree ProtocolThe following table lists the analyzer configuration registers for Multiple Spanning Tree Protocol (MSTP) operation

The Multiple Spanning Tree Protocol (MSTP) in IEEE 8021Q increases network use relative to RSTP by creating multiple spanning trees that VLANs can map to independently rather than having only one path between bridges common for all VLANs The multiple spanning trees are created by assigning different bridge identifiers for each spanning tree Mapping the VLANs to spanning trees is done arbitrarily

Figure 94 bull Multiple Spanning Tree Example

The Learning state is not supported for MSTP However this has limited impact because when the port is taken to the Forwarding state learning is done at wire-speed and as a result the SMAC learn delay is less important MSTP is supported for all VLANs

Table 195 bull Analyzer Configurations for MSTP Support

RegisterRegister Field Description ReplicationVLANACCESSVLAN_SRC_CHK Per-VLAN ingress filtering enable Part of

VLAN table command for indirect access to configuration of the 4095 VLANs

ADVLEARNVLAN_CHK Disable learning for frames discarded due to VLAN membership source port filtering

CPUQ_8021_CFGCPUQ_BPDU_VAL CPU extraction queue for redirected BPDU frames

Per address

MSTP 1

MSTP 2

Ports in discarding state for MSTP 1

MSTP 1

Features

The following table lists the multiple spanning tree port state properties

To enable the MSTP port states

bull Ensure that the switch is VLAN-aware For more information see Standard VLAN Operation page 228

bull Set the ADVLEARNVLAN_CHK bit to prevent learning of frames discarded due to VLAN ingress filtering

bull Configure all ports as defined for the forwarding state of the RSTP port For more information see Table 194 page 241

Port states per VLAN are hereafter solely configured through the VLAN masks as listed in the following table for port p and VLAN v

As an alternative to setting the VLANACCESSVLAN_SRC_CHK bit in all VLAN entries in the VLAN table VLAN ingress filtering can be enabled globally for all VLANs on a per port basis through VLANMASK

For all multiple spanning tree instances BPDUs are forwarded to the CPU irrespective of the port states

53621 MSTP ExampleSituation

Ports 10 and 11 are both members of VLANs 20 and 21 Two spanning trees are used

bull Spanning tree for VLAN 20 where both ports 10 and 11 are in the Forwarding statebull Spanning tree for VLAN 21 where port 10 is in the Discarding state and port 11 is in the Forwarding

stateAll other ports on the switch are unused

Resolution

Get all BDPUs to CPU queue 0CPU_FWD_BPDU_CFG[]BPDU_REDIR_ENA[0] = 1CPUQ_8021_CFGCPUQ_BPDU_VAL[0] = 0 Enable learning on all ports The VLAN table controls forwarding and learningDEVPORT_CFGLEARN_ENA = 1 Disable learning of VLAN membership source port filtered framesADVLEARNVLAN_CHK = 1 Configure VLAN 20 for ports 10 and 11 in Forwarding stateVLANTIDXINDEX = 20VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)

Table 196 bull MSTP Port State Properties

State per VLANBPDU Reception

BPDU Generation

Frame Forwarding

SMAC Learning

Learning (not supported) Yes Yes No Yes

Table 197 bull MSTP Port State Configuration for Port p and VLAN v

StateVLAN_ACCESSVLAN_SRC_CHKVLAN v

VLAN_ACCESSVLAN_PORT_MASK Bit p VLAN v

Discarding 1 0

Learning Not supported Not supported

Forwarding 1 1

Features

VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 1VLANACCESSVLAN_PORT_MASK = 0x00000C00VLANACCESSVLAN_TBL_CMD = 2 Configure VLAN 21 for port 10 in Discarding state and port 11 in Forwarding stateVLANTIDXINDEX = 21VLANTIDXVLAN_PRIV_VLAN = 0VLANTIDXVLAN_MIRROR = 0 (donrsquot care for this example)VLANTIDXVLAN_LEARN_DISABLE = 0VLANTIDXVLAN_SRC_CHK = 1VLANACCESSVLAN_PORT_MASK = 0x00000800VLANACCESSVLAN_TBL_CMD = 2

537 IEEE 8021X Network Access ControlIEEE 8021X Port-Based Network Access Control provides a standard for authenticating and authorizing devices attached to a LAN port

Generally IEEE 8021X is port-based however the device also supports MAC-based network access control

This section provides information about the configuration settings for port-based and MAC-based network access control

5371 Port-Based Network Access ControlThe following table lists the configuration settings required for port-based network access control

The configuration settings required for port-based network access control enable the following functionality

bull Redirects frames with DMAC 01-80-C2-00-00-03 to CPU even if the port is not yet authenticatedbull Stops forwarding of frames to ports that are not yet authenticated This is configured in

ANAPGID[64-79]bull Stops forwarding of frames received on ports that are not yet authenticated This is configured in

ANAPGID[80-91]

Table 198 bull Configurations for Port-Based Network Access Control

RegisterRegister Field Description Value ReplicationANACPU_FWD_BPDU_CFGBPDU_REDIR_ENA[3]

Must be set to 1 to redirect frames with destination MAC addresses 01-80-C2-00-00-03 to the CPU Port ModuleIEEE 8021X uses MAC address 01-80-C2-00-00-03

Per port

ANACPUQ_8021_CFGCPUQ_BPDU_VAL[3]

Queue to which authentication BPDUs are redirected None

ANAPGID[64-79] When a port is not yet authenticated any forwarding of frames to the port can be disabled by clearing the portrsquos bit in all 16 aggregation masks After authenticated these bits must be set

ANAPGID[80-91] Source masksWhen a port is not yet authenticated any forwarding of frames received on the port must be disabled This can be done by setting the ANAPGID[80+port] to all-zerosAfter authentication the portrsquos source mask must be set back to its normal value

Per port

Features

5372 MAC-Based Authentication with Secure CPU-Based LearningThe following table lists the configuration settings required for MAC-based network access control with secure CPU-based learning

The MAC-based network access control with secure CPU-based learning enables the following functionality

bull Redirects frames with DMAC 01-80-C2-00-00-03 to CPUbull Only frames from known authenticated MAC addresses are forwarded to other portsbull Frames from unknown MAC addresses are redirected to CPU for authentication After the address is

authenticated the CPU must insert an entry in the MAC table The authentication process may be initiated from the CPU when receiving learn frames

5373 MAC-Based Authentication with No LearningThe following table lists the configuration settings required for MAC-based network access control with no learning

The MAC-based network access control with no learning enables the following functionality

bull Frames with DMAC 01-80-C2-00-00-03 are redirected to CPU Unauthenticated and unauthorized devices must initiate an 8021X session by sending 8021X BPDUs (MAC address

Table 199 bull Configurations for MAC-Based Network Access Control with Secure CPU-Based Learning

RegisterRegister Field Description Value ReplicationANAPORTCPU_FWD_BPDU_CFGBPDU_REDIR_ENA[3] Must be set to 1 to redirect frames with

destination MAC addresses 01-80-C2-00-00-03 to the CPU Port ModuleIEEE 8021X uses MAC address 01-80-C2-00-00-03

Per port

ANACPUQ_8021_CFGCPUQ_BPDU_VAL[3] Queue to which authentication BPDUs are redirected

ANAPORTPORT_CFGLEARN_ENAANAPORTPORT_CFGLEARNCPUANAPORTPORT_CFGLEARNDROPANAPORTPORT_CFGLEARNAUTO

Must be set to support secure CPU-based learning See Address Learning page 226PORT_CFGLEARN_ENA = 1PORT_CFGLEARNCPU = 1PORT_CFGLEARNDROP = 1PORT_CFGLEARNAUTO = 0

Per port

Table 200 bull Configurations for MAC-Based Network Access Control with No Learning

destination MAC addresses 01-80-C2-00-00-03 to the CPU Port Module IEEE 8021X uses MAC address01-80-C2-00-00-03

Per port

Must be set to support no learning See Address Learning page 226PORT_CFGLEARN_ENA = 1PORT_CFGLEARNCPU = 0PORT_CFGLEARNDROP = 1PORT_CFGLEARNAUTO = 0

Features

01-80-C2-00-00-03) After the address is authenticated the CPU must insert an entry in the MAC table

bull Only frames from known authenticated MAC addresses are forwarded to other portsbull Frames from unknown MAC addresses are discarded and the CPU can therefore not initiate the

authentication process

538 Link AggregationLink aggregation bundles multiple ports (member ports) together into a single logical link It is primarily used to increase available bandwidth without introducing loops in the network and to improve resilience against faults A link aggregation group (LAG) can be established with individual links being dynamically added or removed This enables bandwidth to be incrementally scaled based on changing requirements A link aggregation group can be quickly reconfigured if faults are identified

Frames destined for a LAG are sent on only one of the LAGrsquos member ports The member port on which a frame is forwarded is determined by a 4-bit aggregation code (AC) that is calculated for the frame

The aggregation code ensures that frames belonging to the same frame flow (for example a TCP connection) are always forwarded on the same LAG member port For that reason reordering of frames within a flow is not possible The aggregation code is based on the following information

bull SMACbull DMACbull Source and destination IPv4 addressbull Source and destination TCPUDP ports for IPv4 packetsbull Source and destination TCPUDP ports for IPv6 packetsbull IPv6 Flow LabelFor best traffic distribution among the LAG member ports enable all contributions to the aggregation code

Each LAG can consist of up to 16 member ports Any quantity of LAGs may be configured for the device (only limited by the quantity of ports on the device) To configure a proper traffic distribution the ports within a LAG must use the same link speed

A port cannot be a member of multiple LAGs

5381 Link Aggregation ConfigurationThe following table lists the registers associated with link aggregation groups

Table 201 bull Link Aggregation Group Configuration Registers

RegisterRegister Field Description Value ReplicationANAPGID[0 ndash 63] Destination mask 64

ANAPGID[80 ndash 91] Source mask Per port

ANAPGID[64 ndash 79] Aggregation mask 16

ANAPORT_CFGPORTID_VAL Logical port number Must be set to the same value for all ports that are part of a given LAG for example the lowest port number that is a member of the LAG

Per port

ANAAGGR_CFG AC_IP6_FLOW_LBL_ENA Use IPv6 flow label when calculating AC Configure identically for all portsRecommended value is 1

ANAAGGR_CFG AC_IP4_SIPDIP_ENA Use IPv4 source and destination IP address when calculating aggregation code Configure identically for all portsRecommended value is 1

Features

To set up a link aggregation group the following destination masks source masks and aggregation masks must be configured

bull Destination Masks ANAPGID[0-63] For each of the member ports the corresponding destination mask must be configured to include all member ports of the LAG

bull Source Masks ANAPGID[80-91] The source masks must be configured to avoid flooding frames that are received at one member port back to another member port of the LAG As a result the source masks for each of the member ports must be configured to exclude all of the LAGrsquos member ports

bull Aggregation Masks ANAPGID[64-79] The aggregation masks must be configured to ensure that when a frame is destined for the LAG it gets forwarded to exactly one of the LAGrsquos member ports Also the distribution of traffic between member ports is determined by this configuration

The following illustration shows an example of a LAG configuration

ANAAGGR_CFGAC_IP4_TCPUDP_PORT_ENA Use IPv4 TCPUDP port when calculating aggregation code Configure identically for all ports Recommended value is 1

ANA AGGR_CFG AC_DMAC_ENA Use destination MAC address when calculating aggregation code Configure identically for all ports Recommended value is 1

ANA AGGR_CFG AC_SMAC_ENA Use source MAC address when calculating aggregation code Configure identically for all ports Recommended value is 1

ANA AGGR_CFG AC_RND_ENA Use random aggregation code Recommended value is 0

Table 201 bull Link Aggregation Group Configuration Registers (continued)

RegisterRegister Field Description Value Replication

Features

Figure 95 bull Link Aggregation Example

In this example ports 0 1 4 and 5 of switch A are configured as a LAG These ports are connected to 4 ports (4 5 6 7) of switch B providing an aggregated bandwidth of 4 Gbps between the two switches

The aggregation masks for switch A are configured such that frames (destined for the LAG) are distributed on the member ports as follows

bull Port 0 if framersquos aggregation code (AC) is 0x0 0x4 0x8 0xCbull Port 1 if framersquos aggregation code (AC) is 0x1 0x5 0x9 0xDbull Port 4 if framersquos aggregation code (AC) is 0x2 0x6 0xA 0xEbull Port 5 if framersquos aggregation code (AC) is 0x3 0x7 0xB 0xF

5382 Link Aggregation Control Protocol (LACP)LACP allows switches connected to each other to automatically discover if any ports are member of the same LAG

To implement LACP any LACP frames must be redirected to the CPU Such frames are identified by the DMAC being equal to 01-80-C2-00-00-02 (Slow Protocols Multicast address)

AC Port mask0x0 0b111110011010x1 0b111110011100x2 0b111110111000x3 0b111111011000x4 0b111110011010x5 0b111110011100x6 0b111110111000x7 0b111111011000x8 0b111110011010x9 0b111110011100xA 0b111110111000xB 0b111111011000xC 0b111110011010xD 0b111110011100xE 0b111110111000xF 0b11111101100

Aggregation MasksDESTINDX Port mask 0 0b000001100111 0b00000110011 4 0b00000110011 5 0b00000110011

Destination Masks

Configuration Switch A

Switch B

Switch A

0 1 4 5

4 5 6 7

Port Port mask0 0b111110011001 0b111110011004 0b111110011005 0b11111001100

Source Masks

Aggregation Masks

Configuration Switch B

Source Masks

PORT_CFG[0]PORTID_VAL = 0PORT_CFG[1]PORTID_VAL = 0PORT_CFG[4]PORTID_VAL = 0PORT_CFG[5]PORTID_VAL = 0

DESTINDX Port mask 4 0b000111100005 0b000111100006 0b000111100007 0b00011110000

Destination Masks

Features

The following table lists the registers associated with configuring the redirection of LACP frames to the CPU

539 Simple Network Management Protocol (SNMP)This section provides information about the port module registers and the analyzer registers for SNMP operation

The following table lists the system registers for SNMP operation

The following table lists the analyzer registers for SNMP support

For SNMP support according to IETF RFC 1157 use the following features

bull RMON countersbull MAC table GET_NEXT functionFor more information about the supported RMON counters see Port Counters page 222

For more information about the MAC table GET_NEXT function see Table 75 page 104

5310 MirroringTo debug network problems selected traffic can be copied or mirrored to a mirror port where a frame analyzer can be attached to analyze the frame flow

The traffic to be copied to the mirror port can be selected as follows

bull All frames received on a given port (also known as ingress mirroring)bull All frames transmitted on a given port (also known as egress mirroringbull Frames selected through configured VCAP entriesbull All frames classified to specific VIDsbull All frames sent to the CPU (may be useful for software debugging)bull Frames where the source MAC address is to be learned (also known as learn frame) which may be

useful for software debuggingThe mirror port may be any port on the device including the CPU

Table 202 bull Configuration Registers for LACP Frame Redirection to the CPU

RegisterRegister Field Description Value ReplicationANACPU_FWD_BPDU_CFGBPDU_REDIR_ENA[2] Must be set to 1 Per port

Table 203 bull System Registers for SNMP Support

Register Description ReplicationCNT The value of the counter For more information about how

to read counters see Statistics page 44None

Table 204 bull Analyzer Registers for SNMP Support

Register Description ReplicationMACACCESS Command register for indirect MAC table access Supports

GET_NEXT commandNone

MACHDATA High part of data word when accessing MAC table None

MACLDATA Low part of data word when accessing MAC table None

MACTINDX Index for direct-mode access to MAC table None

Features

53101 Mirroring ConfigurationThe following table lists configuration registers associated with mirroring

The following illustration shows a port mirroring example

Figure 96 bull Port Mirroring Example

All traffic to and from the server on port 3 (the probe port) is mirrored to port 2 (the mirror port) Note that the mirror port may become congested because both the Rx frames and Tx frames on the probe port become Tx frames on the mirror port The following mirror configuration is required

ANAPORT_CFG[3]SRC_MIRROR_ENA = 1ANAEMIRRORMASK[3] = 1ANAMIRRORPORTS = 0x0000004In addition to the mirror configuration settings the egress configuration of the mirror port (port 2) must be configured identically to the egress configuration of the probe port (port 3) This is to ensure that VLAN tagging and DSCP remarking at the mirror port is performed consistently with that of the probe port such that the frame copies at the mirror port are identical to the original frames on the probe port

Table 205 bull Configuration Registers for Mirroring

RegisterRegister Field Description Value ReplicationANAPORT_CFGSRC_MIRROR_ENA If set all frames received on this port are

mirrored to the port set configured in MIRRORPORTS that is ingress mirroring

Per port

ANA EMIRRORMASK Frames forwarded to ports in this mask are mirrored to the port set configured in MIRRORPORTS that is egress mirroring

Per port

ANAVLANTIDXVLAN_MIRROR If set all frames classified to this VLAN are mirrored to the port set configured in MIRRORPORTS

One per VID

ANAAGENCTRLMIRROR_CPU Frames destined for the CPU extraction queues are also forwarded to the port set configured in MIRRORPORTS

ANAMIRRORPORTS The mirror ports Usually only one mirror port is configured that is only one bit is set in this mask

ANACPUQ_CFGCPUQ_MIRROR CPU extraction queue used if CPU is included in MIRRORPORTS

ANAADVLEARNLEARN_MIRROR Learn frames are also forwarded to ports marked in MIRRORPORTS

VCAP Registers Configuration of VCAP entries for example to trigger copy to mirror port For more information see VCAP IS2 Port Configuration page 63

Per VCAP entry

SwitchProbe PortMirror Port

NetworkAnalyzer Server

Features

Multiple mirror conditions such as mirror multiple probe ports VLANs and so on can be enabled concurrently to the same mirror port However in such configurations it may not be possible to configure the egress part of the mirror port to perform tagging and DSCP remarking consistent with that of the original frame

54 IGMP and MLD SnoopingThis section provides information about the features and configurations related to Internet Group Management Protocol (IGMP) and Multicast Listener Discovery (MLD) snooping

By default Layer-3 multicast data traffic is flooded in a Layer-2 network in the broadcast domain spanned by the VLAN This causes unnecessary traffic in the network and extra processing of unsolicited frames in hosts not listening to the multicast traffic IGMP and MLD snooping enables a Layer-2 switch to listen to IGMP and MLD conversations between host and routers The switch can then prune multicast traffic from ports that do not have a multicast listener and as a result do not need a copy of the multicast frame This is done by managing the multicast group addresses and the associated port masks

IGMP is used to manage IPv4 multicast memberships and MLD is used to manage IPv6 multicast memberships

The device supports IGMPv2v3 and MLDv1v2 IGPMv2 and MLDv1 use any-source multicasting (ASM) where the multicast listener joins a group and can receive the multicast traffic from any source IGMPv3 and MLDv2 introduce source-specific multicasting (SSM) where both source and group are specified by the multicast listener when joining a group

The support in the device is two-fold

bull Control plane IGMP and MLD frames are redirected to the CPU This enables the CPU to listen to the queries and reports

bull Data plane By monitoring the multicast group registrations and de-registrations signaled through the IGMP and MLD frames the CPU can setup multicast group addresses and associated ports

541 IGMP and MLD Snooping ConfigurationTo implement IGMP and MLD snooping any IGMP or MLD frames must be redirected to the CPU For information about by the conditions by which such frames are identified see CPU Forwarding Determination page 58 IGMP and MLD frames can be independently snooped and assigned individual CPU extraction queues

The following table lists the registers associated with configuring the redirection of IGMP and MLD frames to the CPU

Table 206 bull Configuration Registers for IGMP and MLD Frame Redirection to CPU

RegisterRegister Field Description Value ReplicationANACPU_FWD_CFGIGMP_REDIR_ENA Must be set to 1 to redirect IGMP

frames to the CPUPer port

ANACPU_FWD_CFGMLD_REDIR_ENA Must be set to 1 to redirect MLD frames to the CPU

Per port

ANACPUQ_CFGCPUQ_IGMP CPU extraction queue for IGMP frames

ANACPUQ_CFGCPUQ_MLD CPU extraction queue for MLD frames None

Features

542 IP Multicast Forwarding ConfigurationThe following table lists the registers associated with configuring the multicast group addresses and the associated ports

IPv4 and IPv6 multicast group addresses are programmed in the MAC table as IPv4 and IPv6 multicast entries For more information see MAC Table page 101 The entry in the MAC table also holds the set of egress ports associated with the group address

By default programming an IPv4 or IPv6 multicast entry in the MAC table makes it an any-source multicast because the actual source IP address is insignificant with respect to forwarding

To create source-specific IPv4 or IPv6 multicast entries the Filter Identifier (FID) action in VCAP IS1 can be used which enables creation of specific FIDs per source IP address Entries in IS1 can contain the full IPv4 or IPv6 source address Multiple MAC table entries holding the same IPv4 or IPv6 multicast group address but different FIDs can then be created This effectively enables source-specific multicasting

The switch provides full control of flooding of unknown IP multicast frames For more information see DMAC Analysis page 110 Generally an IGMP and MLD snooping switch disables flooding of unknown multicast frames except to ports connecting to multicast routers Note that unknown IPv4 multicast control frames should be flooded to all ports because IPv4 is not as strict as IPv6 in terms of registration for IP multicast groups

55 Quality of Service (QoS)This section discusses features and configurations related to QoS

The device includes a number of features related to providing low-latency guaranteed services to critical network traffic such as voice and video in contrast to best-effort traffic such as web traffic and file transfers

All incoming frames are classified to a QoS class which is used in the queue system when assigning resources in the arbitration from ingress to egress queues and in the egress scheduler when selecting the next frame for transmission The device provides two methods for classifying to a QoS class and for remarking priority information in the frame Basic and Advanced classification

Basic QoS classification enables predefined schemes for handling Priority Code Points (PCP) Drop Eligible Indicator (DEI) and Differentiated Service Code Points (DSCP)

bull QoS classification based on PCP and DEI for tagged frames The mapping table from PCP and DEI to QoS class is programmable per port

Table 207 bull IP Multicast Configuration Registers

RegisterRegister Field Description Value ReplicationMACHDATA MAC address and VID when accessing the MAC table None

MACTINDX Direct address into the MAC table for direct read and write

FLOODING_IPMC Index into the PGID table used for flooding of IPv46 multicast control and data frames

IS1_ACTIONFID_SEL Specifies the use of IS1_ACTIONFID_VAL for the DMAC lookup the SMAC lookup or for both lookups

Per IS1 entry

IS1_ACTIONFID_VAL FID value Per IS1 entry

Features

bull QoS classification based on DSCP values Can optionally use only trusted DSCP values The mapping table from DSCP value to QoS class is common between all ports

bull The device has the option to work as a DS boundary node connecting two DS domains together by translating incomingoutgoing DSCP values for selected ports

bull The DSCP values can optionally be remarked based on the framersquos classified QoS classbull For untagged or non-IP frames a default per-port QoS class is programmableAdvanced QoS classification uses the VCAP IS1 which provides a flexible classification

bull A large range of higher layer protocol fields (Layer 2 through Layer 4) are available for rule matching

bull The IS1 action vector returns a QoS class and translations of PCP DEI and DSCP values are also possible

bull Through programming of entries in IS1 QoS rules can be made as specific as neededFor example per source MAC address per TCPUDP destination port number or combination of both

For more information about advanced QoS classification using the VCAP IS1 see Ingress Control Lists page 257

551 Basic QoS ConfigurationThe following table lists the registers associated with configuring basic QoS

Situation

Assume a configuration with the following requirements

bull All frames with DSCP=7 must get QoS class 7bull All frames with DSCP=8 must get QoS class 5bull DSCP = 9 is untrusted and all frames with DSCP=9 should be treated as a non-IP framebull VLAN-tagged frames with PCP=7 must get QoS class 7bull All other IP frames must get QoS class 1bull All other non-IP frames must get QoS class 0Solution

Program overall QoS configurationQOS_CFGQOS_DSCP_ENA = 1QOS_CFGQOS_PCP_ENA = 1

Program DSCP trust configuration (ldquordquo = 0 through 63)DSCP_CFG[]DSCP_TRUST_ENA = 1DSCP_CFG[9]DSCP_TRUST_ENA = 0

Program DSCP QoS configuration (ldquordquo = 0 through 63)DSCP_CFG[]QOS_DSCP_VAL = 1DSCP_CFG[7]QOS_DSCP_VAL = 7DSCP_CFG[8]QOS_DSCP_VAL = 5

Program PCP QoS configuration (ldquordquo = 0 through 15) Note both 7 and 15 are programmed in order to donrsquot care DEIQOS_PCP_DEI_MAP_CFG[] = 0QOS_PCP_DEI_MAP_CFG[7] = 7

Table 208 bull Basic QoS Configuration Registers

Register Description ReplicationANAPORTQOS_CFG QoS and DSCP configuration Per port

ANAPORTQOS_PCP_DEI_MAP_CFG Mapping of DEI and PCP to QoS class and drop precedence level

Per port

ANADSCP_CFG DSCP configuration Per DSCP

Features

QOS_PCP_DEI_MAP_CFG[15] = 7

Program default QoS class for non-IP non-tagged framesQOS_CFGQOS_DEFAULT_VAL = 0

552 IPv4 and IPv6 DSCP RemarkingIPv4 and IPv6 packets include a 6-bit Differentiated Services Code Point (DSCP) which switches and routers can use to determine the QoS class of a frame With a proper value in the DSCP field packets can be prioritized consistently throughout the network Compared to QoS classification based on user priority classification based on DSCP provides two main advantages

bull DSCP field is already present in all packets (assuming all traffic is IPv4IPv6)bull DSCP value is preserved during routing and is therefore better suited for end-to-end QoS signalingSome hosts may be able to send packets with an appropriate value in the DSCP field whereas other hosts may not provide an appropriate value in the DSCP field

For packets without an appropriate value in the DSCP field the device can be configured to write a new DSCP value into the frame based on the QoS class of the frame For example the device may have determined the QoS class based on the VLAN tag priority information (PCP and DEI) After the packet is transmitted by the egress port the DSCP field can be rewritten with a value based on the QoS class of the frame Any subsequent routers or switches can then be easily prioritize the frame based on the rewritten DSCP value

The DSCP rewriting functionality available in the device provides flexible per-ingress port and per-DSCP-value configuration of whether frames should be subject to DSCP rewrite If it is determined at the ingress port that the DSCP value should be rewritten and to which value this is then signaled to the egress ports where the actual change of the DSCP field is done

In addition the IS1 can be programmed to return a DSCP value as part of the action vector This value overrules the potential DSCP value coming out of the DSCP rewrite functionality described previously A DSCP value from either the basic classification or the advanced IS1 classification obey the same egress rules for the actual DSCP remarking

5521 DSCP Remarking ConfigurationThe following table lists the configuration registers associated with DSCP remarking

Table 209 bull Configuration Registers for DSCP Remarking

RegisterRegister Field Description Value ReplicationANAPORTDSCP_REWR_CFG Two-bit DSCP rewrite mode per ingress

port0x0 No DSCP rewrite0x1 Rewrite only if the framersquos current DSCP value is zero0x2 Rewrite only if the framersquos current DSCP value is enabled for remarking in ANADSCP_CFGDSCP_REWR_ENA0x3 Rewrite DSCP of all frames regardless of current DSCP value

Per ingress port

ANADSCP_CFGDSCP_REWR_ENA Enables specific DSCP values for rewrite for ports with DSCP rewrite mode set to 0x2

Per DSCP

ANADSCP_REWR_CFGDSCP_QOS_REWR_VAL

Maps the framersquos DP level and QoS class to a DSCP value

Per DP level and per QoS class

REWDSCP_CFGDSCP_REWR_CFG Enables DSCP rewrite for egress port Per egress port

REWDSCP_REMAP_CFG Remap table of DSCP values for drop precedence 0

Features

The configuration related to the ingress port controls whether a frame is to be remarked For each ingress port a DSCP rewrite mode is configured in ANAPORTDSCP_REWR_CFG This register defines the four different modes as follows

bull 0x0 No DSCP rewrite that is never change the received DSCP valuebull 0x1 Rewrite if DSCP is zero This may be useful if a DSCP value of zero indicates that the host has

not written any value to the DSCP fieldbull 0x2 Rewrite selected DSCP values In ANADSCP_CFGDSCP_REWR_ENA specific DSCP

values can be selected for rewrite for example if only certain DSCP values are allowed in the network

bull 0x3 Rewrite all DSCP valuesAfter a frame is selected for DSCP rewrite based on the configuration for the ingress port the new DSCP value is determined by mapping the QoS class and DP level to a new DSCP value (ANADSCP_REWR_CFGDSCP_QOS_REWR_VAL)

This DSCP value is overruled by IS1 if a hit in IS1 returns an action vector with DSCP_ENA set

The resulting DSCP value is forwarded to the Rewriter at the egress port which determines whether to actually write the new DSCP value into the frame (REWDSCP_CFGDSCP_REWR_CFG) Optionally the DSCP value may be translated before written into the frame (REWDSCP_REMAP_CFG REWDSCP_REMAP_DP1_CFG) for applications where the switch acts as an DS boundary node

When an IPv4 DSCP is rewritten the IP header checksum is updated accordingly

553 Voice over IP (VoIP)This section provides information about QoS in applications with Voice over IP (VoIP)

In a typical workgroup switch application with VoIP phones both workstations and VoIP phones are connected to the switch A workstation can be connected through a VoIP phone Traffic from the workstation is usually untagged whereas traffic from the VoIP phone may or may not be tagged The QoS classification mechanism applied on the access port depends on the capabilities of the VoIP phone these capabilities vary from phone to phone With different VoIP phone models in the network different access ports require different QoS classification mechanisms The access switch can perform QoS classification depending on the VoIP phone model to achieve consistent VoIP QoS across the network

Voice traffic can be identified in the following ways

bull Source MAC address (OUI) Most vendors use a dedicated OUI for VoIP phonesbull EtherType Legacy phones may use a special EtherType for VoIPbull VID A special VID used for voice trafficbull UDP Port Range Voice traffic often uses a well-known port range for the Real-time Transport

Protocol (RTP)bull DSCP or ToS Precedence Many phones can set the DSCP value or the ToS precedence bitsbull Priority Code Point Many phones send VLAN tagged frames and can set the priority code pointAll of these identification methods are supported by QoS classification through IS1 They can be used to determine the VoIP trafficrsquos QoS class when entering the switch For more information about the IS1 see VCAP IS1 Port Configuration page 63

To ensure consistent QoS across the network frames can be remarked on the uplink port Priority Code Points and DSCP values can be remarked based on the QoS class determined by the QCLs For more information about Priority Code Point and DSCP remarking see VLAN Editing page 133 and IPv4 and IPv6 DSCP Remarking page 254

Traffic received on the uplink port can usually rely on simple DSCP or PCP QoS classification

REWDSCP_REMAP_DP_1_CFG Remap table of DSCP values for drop precedence 1

Table 209 bull Configuration Registers for DSCP Remarking (continued)

Features

56 VCAP ApplicationsThis section provides information about Versatile Content Aware Processor (VCAP) applications for QoS classification source IP guarding and access control

The following table shows the different control lists that the VCAP can be used to build

561 Notation for Control Lists EntriesSetting up a control list typically requires a large amount of register configurations To maintain the overview of the VCAP functionality the following control list notations are used The register configurations are not listed For more information about the VCAP configurations see VCAP page 60

The notation used is

entry_number vcap entry_type entry_field=valuerarr action_field=valueEach control entry in the notation consists of

bull The entry number specifying the TCAM address for the specific TCAMbull The VCAP used (IS1 IS2 ES0)bull The entry type (for instance NORMAL or MAC_ETYPE)bull Zero one or more entry fields with specified values If no value is supplied it is assumed that the

value is 1bull The action (indicated with rarr)bull Zero one or more action fields with specified values If no value is supplied it is assumed that the

value is 1All entry fields not listed in the entry part of the control entry are set to donrsquot care

All action fields not listed in the action part of the control entry are set to zero

Default actions are special because they do not have an entry type and a pattern to match

default vcap (first|second) port=valuerarr action_field=valueThe notation is illustrated by the following examples

Example 1

An example of an ACL entry

255 is2 ipv4_other first igr_port_mask=(1ltlt7) sip=101012134rarr This ACL entry is located in entry number 255 It is matched for the first lookup and it is part of the port ACL for port 7 The type is ipv4_other and the action is not to change the normal flow for frames with SIP = 101012134

Example 2

Table 210 bull Control Lists and Application

Control List DescriptionIngress control lists (ICLs) QoS classification

VLAN classification and translationpolicy association group classification

IPv4 source guarding control lists (S4CLs) IPv4 source guarding

Access control lists (ACLs) Access control

Egress control lists (ECLs) Tagging and egress translations

Features

Policy ACL A can include a monitoring rule that disables forwarding and learning of all incoming IPv4 traffic but redirects a copy to CPU extraction queue number 3 using the hit-me-once filter The hit-me-once filter enables the CPU to control when it ready to accept a new frame The rule would look like this

254 is2 ipv4_other first pag=Ararr hit_me_once cpu_qu_num = 3Example 3

This example shows an ACE that allows forwarding and learning of ARP requests from port 7 if the source IP address is 101012134 The ACL entry also performs ARP sanity checks that frames must pass to match The checks include checking that it is a Layer-2 broadcast that the hardware address space is Ethernet that the protocol address space is IP that the MAC address and IP address lengths are correct and that the sender hardware address (SMAC) matches the SMAC of the frame

253 is2 arp first igr_port_mask=(1ltlt7) l2_bc opcode=arp_requestsip=101012134arp_addr_space_ok arp_proto_space_ok arp_len_okarp_sender_matchrarrExample 4

If the default action from first lookup for port 7 is to discard all traffic the following notation is used

default is2 first port=7rarr mask_mode=1 port_mask=0x0

562 Ingress Control ListsThe following table lists the registers associated with advanced QoS configuration through Ingress Control Lists

Situation

bull All frames with DSCP = 7 must get QoS class 2bull All frames with TCPUDP port numbers in the range 0 ndash 1023 must get QoS class 3 except frames

with TCPUDP port 25 which must get QoS class 1bull All other frames must get QoS class 0Solution

The resulting QoS Control List looks like this

255 is1 normal first etype_len ip_snap dscp = 7rarr qos_ena=1 qos_val = 2254 is1 normal first etype_len ip_snap l4_sport = 25rarr qos_ena=1 qos_val = 1253 is1 normal first etype_len ip_snap etype = 25rarr qos_ena=1 qos_val = 1252 is1 normal first etype_len ip_snap l4_sport=(key0 mask 0x3FF)rarr qos_ena=1 qos_val = 3251 is1 normal first etype_len ip_snap etype = (key 0 mask 0x3FF)rarr qos_ena=1 qos_val = 3ANAPORTQOS_CFGQOS_DEFAULT_VAL = 0

Table 211 bull Advanced QoS Configuration Register Overview

Register Description ReplicationANAPORTQOS_CFG QoS configuration Per port

Features

563 Access Control ListsThe examples operate with three levels of ACLs

bull Port ACLsbull Policy ACLsbull Switch ACLsThe port ACLs are specific to a single port or a group of ports that form a link aggregation group For example a port ACL can be used for source IP filtering locking a specific source IP address to a port For more information about this example see Restrictive SIP Filter Using IS2 page 259

The policy ACLs are shared for a group of ports that must have the same policy applied For example there could be one policy for ports through which workstations access the network and another policy for ports to which servers are connected

The switch ACLs apply to all ports of the switch They specify some general rules that apply to all traffic passing through the switch The rules can still be rather specific for example covering a specific VLAN or a specific IP address

In the examples the resulting ACL can include one port ACL one policy ACL and the switch ACL This is determined by the way the ingress port mask (IGR_PORT_MASK) and the policy association group (PAG) are used For information about IGR_PORT_MASK and PAG see VCAP IS2 page 78 There are several ways to use the 8-bit PAG but in this section all eight bits are used to point out a policy ACL The IGR_PORT_MASK points out the port ACL This permits one port ACL per port and a total of 256 policy ACLs Note that ports may share the same port ACL and a port by donrsquot caring bits in the port ACLrsquos IGR_PORT_MASK

Each port has a default PAG assigned to it The IS1 VCAP can be used to change the value of the PAG based on specific protocol fields matched in the IS1 lookup The resulting PAG is used in the IS2 VCAP lookup and is matched against the PAG field of the ACL entries

For an ACL entry in the IS2 VCAP the PAG and IGR_PORT_MASK use this notation

PAG = PolicyACL_IDIGR_PORT_MASK = 1ltltPortACL_ID

Note The ldquoltltrdquo operator is the bitwise left shift operator It shifts the left operand bit-wise to the left the number of positions specified by the right operand

The IGR_PORT_MASK is a mask so the port number is left-shifted to create the maskFor an ACL entry that is part of a port ACL for port 8 the PAG would be () and IGR_PORT_MASK would be (1ltlt8) = 0x100 The asterisk is a wildcard which means that the PolicyACL_ID is a donrsquot-care For an ACL entry that is part of policy ACL A the PAG would be (A) and the IGR_PORT_MASK would be () In this case the PortACL_ID is a donrsquot-care

If for example port 8 must have policy A applied the PAG assigned to port 8 is (A) Using this PAG value the following ACLs match the lookup

bull Port ACL for port 8 with PAG = () and IGR_PORT_MASK = (1ltlt8)bull Policy ACL A with PAG = (A) and IGR_PORT_MASK = ()bull Switch ACL with PAG = () and IGR_PORT_MASK = ()The ordering of the port ACL the policy ACL and switch ACL in the resulting ACL follows the ordering in the TCAM In the following illustration the switch ACL has the highest priority followed by the policy ACL A and finally the port ACL for port 8

The resulting ingress ACL in the example is made up of the ingress ACL entries in the switch ACL the policy ACL A the port ACL for port 8 and the default action for port 8 The VCAP also does a second lookup for which the resulting ACL has a common default action as the last rule

Features

Figure 97 bull Resulting ACL for Lookup with PAG = (A) and IGR_PORT_MASK = (1ltlt8)

564 Source IP Filter (SIP Filter)The VCAP enables filtering of source IP (SIP) addresses on a port also known as source IP guarding This can be used to only allow IP traffic from a specific SIP to enter the switch on a given port Doing this can prevent the following denial of service (DoS) attacks LAND attack SMURF attack SYN flood attack Martian attack and Ping attack

5641 Restrictive SIP Filter Using IS2A restrictive SIP filter can be applied per port in networks where only IP traffic is allowed The filter locks a specific SIP to the port and only permits ARP frames and IPv4 frames with the specified SIP to enter the switch on the given port

For monitoring purposes it is possible to permit IPv4 frames with other SIPs than the SIP locked to the port The action is to redirect to the CPU and the amount of traffic can be reduced by using the hit-me-once feature The ACL entry for this can be part of a policy ACL for all ports on which the SIP filter is applied

The port ACL has the following options

bull Permit IPv4 with trusted SIPbull Permit ARP with trusted SIP passing ARP sanity checksbull Permit all IPv4 mdash CPU redirect with hit-me-once filter (for monitoring)bull Default port action mdash discard all trafficSituation

Apply the restrictive SIP filter on port 7 with SIP 101012134

Resolution

IS2 VCAP RAM

TCAM Entries

Default Actions (First lookup)

Default Action (Second lookup)

Switch ACL

Policy ACL A

Port ACL for Port 8

Action

() Port ACL for Port 9

Policy ACL B

Port 8 default (first lookup)

Default (second lookup)

Contributing to resulting ACL (first lookup)

Contributing to resulting ACL (second lookup)

IGR_PORT_MASK

(1ltlt8)

(1ltlt9)

Features

The resulting ACL for port 7 looks like this

255 is2 ipv4_tcp_udp first igr_port_mask=(1ltlt7) sip=101012134rarr 254 is2 ipv4_other first igr_port_mask=(1ltlt7) sip=101012134rarr 253 is2 arp first igr_port_mask=(1ltlt7) l2_bc opcode=arp_requestsip=101012134arp_addr_space_ok arp_proto_space_ok arp_len_okarp_sender_matchrarr 252 is2 ipv4_tcp_upd first pag=Ararr hit_me_once cpu_queue=3251 is2 ipv4_other first pag=Ararr hit_me_once cpu_queue=3default is2 first port=11rarr mask_mode=1 port_mask=0x0 Applying this SIP filter requires to two entries per port plus three common entries

5642 Restrictive SIP Filter Using IS1 and IS2The same filter as listed above can be achieved using the host_match actions from IS1

Situation

Resolution

255 is1 smac_sip4 igr_port=7 sip=101012134rarr host_matchIS2

255 is2 ip4_tcp_upd first host_match=1rarr254 is2 ip4_other first host_match=1rarr253 is2 arp first igr_port_mask=(1ltlt7) l2_bc opcode=arp_requestsip=101012134arp_addr_space_ok arp_proto_space_ok arp_len_okarp_sender_matchrarr252 is2 ipv4_tcp_udp first pag=Ararr hit_me_once cpu_queue=3251 is2 ipv4_other first pag=Ararr hit_me_once cpu_queue=3default is2 first port=7rarr mask_mode=1 port_mask=0x0Applying this SIP filter requires to one entry in IS1 per port and five common entries in IS2

5643 Less Restrictive SIP Filter Using IS2For networks in which non-IP protocols are allowed for example IPX and ARP a less restrictive SIP filter can be applied with the following port ACL

bull Permit IPv4 with trusted SIPbull Discard all IPv4bull Default port action Permit all traffic (non-IPv4 because all IPv4 traffic is covered by the ACL entries

from other two items)

Features

For monitoring purposes the ldquoDiscard all IPv4rdquo ACL can be changed to perform CPU redirect This allows the CPU to monitor all incoming IPv4 frames with source IP addresses different from the trusted SIP but without allowing these frames to be forwarded to other ports

Situation

Apply the less restrictive SIP filter on port 8 with source IP address 101012134 and monitor any IPv4 traffic with unauthorized source IP addresses with hit-me-once filtering to CPU extraction queue number 2 The monitoring rule is part of policy ACL A that is applied to all user ports

Resolution

The resulting ingress ACL for port 8 looks like this

255 is2 ipv4_tcp_udp first igr_port_mask=(1ltlt8) sip=101012134rarr254 is2 ipv4_other first igr_port_mask=(1ltlt8) sip=101012134rarr63 is2 ipv4_tcp_udp first pag=Ararr hit_me_once cpu_queue=262 is2 ipv4_other first pag=Ararr hit_me_once cpu_queue=2default is2 first port=10rarrApplying this SIP filter requires two entries per port plus two common entries

565 DHCP ApplicationA DHCP application can be supported using one policy ACL for the user ports and another policy ACL for the DHCP server ports

On the user ports the DHCP requests must be snooped to be able to automatically reset the SIP filters that are applied per port DHCP replies should be prevented from being forwarded from user ports For monitoring purposes such illegal replies are redirected to the CPU

On the DHCP server ports DHCP replies are snooped to be able to automatically update the SIP filter for the user port where the reply goes

In addition an egress rule is needed to prevent forwarding of all DHCP requests to user ports

Situation

Policy ACL A is used for the user port DHCP policy and policy ACL B is used for the DHCP server policy The server ports are ports 8 and 9

Snoop DHCP requests from user ports in CPU extraction queue 1 using policer 0 to protect the CPU DHCP replies from the servers are snooped in queue 2 and are also subject to policing with policer 0 The illegal DHCP replies from user ports are redirected to queue 3 using the hit-me-once filter

Resolution

The PAG assigned to the user ports is (A) The PAG assigned to the DHCP server ports (8 and 9) is (B)

The following shows the ACL entries for the DHCP application

255 is2 ipv4_tcp_udp protocol=udpsport=bootp_client dport=bootp_serverrarr mask_mode=1 port_mask=0x000030063 is2 ipv4_tcp_udp first pag=A protocol=udpsport=bootp_client dport=bootp_serverrarr cpu_copy_ena cpu_queue=1 police_ena police_idx=062 is2 ipv4_tcp_udp first pag=A protocol=udpsport=bootp_server dport=bootp_clientrarr hit_me_once cpu_queue=331 is2 ipv4_tcp_udp first pag=B protocol=udpsport=bootp_server dport=bootp_client

Features

rarr cpu_copy_ena cpu_queue=2 police_ena police_idx=0default is2 firstrarr mask_mode=1 port_mask=0x0default is2 secondrarr Regardless of the number of ports covered four ACL entries are used one in the switch ACL two in policy ACL A and one in policy ACL B

566 ARP FilteringThe VCAP support two useful ARP filters

bull Policing ARP requests to the switchrsquos IP address to mitigate DoS attacks by ARP floodingbull Performing general ARP sanity checksBecause these are general rules it is sensible to make them part of the switch ACL

Situation

Discard all ARP frames that do not pass the ARP sanity checks Police ARP requests to the switchrsquos IP address 1010121 using ACL policer 2 ACL policer 2 is configured to allow 16 frames per second and the frames are copied to CPU extraction queue 0

RARP is not allowed in the network

Resolution

To do ARP filtering in the switch ACL perform the filtering for the switchrsquos IP address first then allow all ARP frames passing the sanity checks and finally discard all remaining ARP frames This is illustrated by the following

255 is2 arp first l2_bc opcode=arp_requestdip=1010121arp_addr_space_ok arp_proto_space_ok arp_len_okarp_sender_matchrarr cpu_copy_ena cpu_queue=0 police_ena police_idx=255254 is2 arp first l2_bc opcode=(arp_request or arp_reply)arp_addr_space_ok arp_proto_space_ok arp_len_okarp_sender_matchrarr 253 is2 arprarr mask_mode=1 port_mask=0x0The ACL policer configuration for policer 255 is done as follows

Set the base unit to 1 frame per second enable the policer and set the rate to 16 frames per second and a burst of 1 frameANAPOL[255]POL_MODE_CFGFRM_MODE = 1ANAPOL[255]POL_PIR_CFGPIR_RATE = 16ANAPOL[255]POL_PIR_CFGPIR_BURST = 3

Three ACL entries are used irrespective of the number of ports covered

567 Ping PolicingThe network can easily be protected against ping attacks using a switch ACL rule that applies an ACL policer to all ping packets

Situation

Allow no more than 128 ping packets per second to be forwarded through the switch by means of ACL policer 15 Ping packets in excess of 128 frames per second are discarded

Resolution

Features

Ping packets are ICMP frames with ICMP Type = Echo Request Echo Request is specified by the first byte of the ICMP frame being 0x08 The rest of the ICMP frame is donrsquot-care ICMP frames are carried in IPv4 frames with the protocol value 0x01

The resulting switch ACL entry is as follows

127 is2 ipv4_other first protocol=icmp ip4_payload_high=0x8rarr police_ena police_idx=15ACL policer 15 in the policer pool is configured to 128 frames per second like this

bull ANAPOL[15]POL_MODE_CFGFRM_MODE = 1bull ANAPOL[15]POL_PIR_CFGPIR_RATE = 128bull ANAPOL[15]POL_PIR_CFGPIR_BURST = 1One ACE is used regardless of the number of ports covered

568 TCP SYN PolicingA server in the network can be protected against TCP SYN DoS attacks by policing TCP connection requests to the serverrsquos IP address

Situation

Allow no more than 128 new TCP connections per second to the server with IP address 10101299 Use ACL policer 5

Resolution

TCP connection requests are TCP frames with the SYN flag set The resulting switch ACL entry is as follows

127 is2 ipv4_tcp_udp first protocol=tcpdip=10101299synrarr police_ena police_idx=5ACL policer 5 in the policer pool is configured to 128 frames per second by the following

57 CPU Extraction and InjectionThis section provides information about how the CPU extracts and injects frames to and from the switch core

The following illustration shows the CPU port module used for injection and extraction

Features

Figure 98 bull CPU Extraction and Injection

The switch core forwards CPU extracted frames to eight CPU extraction queues Each of these queue is then mapped to one of two CPU Extraction Groups For each extraction group there is a scheduler (strict or round robin) which selects between the CPU extraction queues mapped to the same group

When injecting frames there are two CPU Injection Groups available where for instance one can be used for the Frame DMA and one can be used for manually injected frames Both CPU injection groups have access to the switch core However within the switch-core CPU injected frames are all seen as coming from port 11 in terms of queue system and analyzer configuration

571 Forwarding to CPUSeveral mechanisms can be used to trigger redirection or copying of frames to the CPU They are listed in the following table

Table 212 bull Configurations for Redirecting or Copying Frames to the CPU

Frame TypeConfiguration (Including Selection of Extraction Queue)

Copy or Redirect

IEEE 8021D Reserved RangeDMAC = 01-80-C2-00-00-0x

ANAPORTCPU_FWD_BPDU_CFGANACPUQ_8021_CFGCPUQ_BPDU_VAL

Copy or redirect

IEEE 8021D AllbridgeDMAC = 01-80-C2-00-00-10

ANAPORTCPU_FWD_CFGCPU_ALLBRIDGE_REDIR_ENA ANACPUQ_CFGCPUQ_ALLBRIDGE

Copy or redirect

IEEE 8021D GARP RangeDMAC = 01-80-C2-00-00-2x

ANAPORTCPU_FWD_GARP_CFGANACPUQ_8021_CFGCPUQ_GARP_VAL

Copy or redirect

IEEE 8021D CCMLink Trace RangeDMAC = 01-80-C2-00-00-3x

ANAPORTCPU_FWD_CCM_CFGANACPUQ_8021_CFGCPUQ_CCM_VAL

Copy or redirect

IGMP (IPv4) ANAPORTCPU_FWD_CFGCPU_IGMP_REDIR_ENAANACPUQ_CFGCPUQ_IGMP

Redirect

Strict R

RStrict R

Extraction Group 0

Extraction Group 1

Queue to Port M

SchedulerSelector

CPU Port ModuleExtraction

CPU port 11 Injection Group 0

Injection Group 1

Injection

itch Core

CPU port 12

Features

572 Frame ExtractionThe CPU receives frames through the eight CPU extraction queues in the CPU port module The eight queues are using resources (memory and frame descriptor pointers) from the shared queue system and are subject to the thresholds and congestion rules programmed for the CPU port (port 11) and the shared queue system in general

The CPU can read frames from the CPU extraction queues in two ways

bull Reading registers in the CPU port module For more information see Frame Extraction page 142bull FDMA from CPU port module to RAM For more information see Frame DMA page 183

IP Multicast Control (IPv4) ANAPORTCPU_FWD_CFGCPU_IPMC_CTRL_COPY_ENAANACPUQ_CFGCPUQ_IPMC_CTRL

MLD (IPv6) ANAPORTCPU_FWD_CFGCPU_MLD_REDIR_ENAANACPUQ_CFGCPUQ_MLD

Redirect

Versatile Register Access Protocol (VRAP)

ANAPORTCPU_FWD_CFGCPU_VRAP_REDIR_ENAANACPUQ_CFG2CPUQ_VRAP

Redirect

CPU-based learning ANAPORTPORT_CFGLEARNCPUANACPUQ_CFGCPUQ_LRN

CPU-based learning of locked MAC table entries seen on a new port

ANAPORTPORT_CFGLOCKED_PORTMOVE_CPUANACPUQ_CFGCPUQ_LOCKED_PORTMOVE

CPU-based learning of frames exceeding learn limit in MAC table

ANAPORTPORT_CFGLIMIT_CPUANACPUQ_CFGCPUQ_LRN

MAC table match using MAC table ANAMACACCESSMAC_CPU_COPYANACPUQ_CFGCPUQ_MAC_COPY

MAC table match using PGID table ANAMACACCESSDEST_IDXANAPGIDPGID (bit 11)ANAPGIDCPUQ_DST_PGID

Redirect or copy

Flooded frames ANAMACACCESSDEST_IDXANAPGIDPGID (bit 11)ANAPGIDCPUQ_DST_PGID

Redirect or copy

Any frame received on selected ports ANAPORTCPU_SRC_COPY_ENAANACPUQ_CFGCPUQ_SRC_COPY

Mirroring ANAMIRRORPORTS (bit 11)ANACPUQ_CFGCPUQ_MIRRORFor more information about mirroring see Mirroring page 249

VCAP IS2 rules For more information about IS2 see VCAP IS2 page 78

Redirect or copy

SFlow ANACPUQ_CFGCPUQ_SFLOWFor more information about SFlow see sFlow Sampling page 117

Table 212 bull Configurations for Redirecting or Copying Frames to the CPU (continued)

Copy or Redirect

Features

In addition the VRAP engine may attach to one of the CPU extraction groups and use this to receive and process all extracted VRAP requests

The switch core may place the 20-byte long CPU extraction header before the DMAC or after the SMAC (SYSPORT_MODEINCL_XTR_HDR) The CPU extraction header contains relevant side band information about the frame such as the framersquos classification result (VLAN tag information DSCP QoS class Rx time stamp) and the reason for sending the frame to the CPU For more information about the contents of the CPU extraction header see Table 114 page 142

573 Frame InjectionThe CPU can inject frames through the two CPU injection groups The injection queues use resources (memory and frame descriptor pointers) from the shared queue system and are subject to the thresholds and congestion rules programmed for the CPU port (port 11) and the shared queue system in general

The CPU can write frames to the CPU injection groups in two ways

bull Registers access to the CPU port module For more information see CPU Extraction and Injection page 263

bull FDMA to CPU port module For more information see Frame DMA page 183In addition the VRAP engine may attach to one of the CPU injection groups and transmit and use this for transmitting VRAP replies

The first 20 bytes of a frame written into a CPU group is an injection header containing relevant side band information about how the frame must be processed by the switch core (SYSPORT_MODEINCL_INJ_HDR) For more information see Table 95 page 118

574 Frame Extraction and Injection Using An External CPUThe following table lists the configuration registers associated with using an external CPU

An external CPU can connect up to any front port module and use the Ethernet interface for extracting and injecting frames into the switch core

Note If an external CPU is connected by means of the serial interface or PCIe interface the frame extraction and injection is performed For more information see Frame Extraction page 265 and Frame Injection page 266

When injecting or extracting frames the CPU injection or extraction header is placed before the DMAC with an optional prefix For more information about the prefixing see Node Processor Interface (NPI) page 146 When injecting frames the CPU injection header controls whether a frame is processed by the analyzer or forwarded directly to the destination set specified in the injection header

An internal and external CPU may coexist in a dual CPU system where the two CPUs handles different run-time protocols When extracting CPU frames it is selectable which CPU extraction queues are connected to the external CPU and which remain connected to the internal CPU (SYSEXT_CPU_CFGEXT_CPUQ_MSK) If a frame is forwarded to the CPU for more than one reason (for example a BPDU which is also a learn frame) the frame can be forwarded to both the internal CPU extraction queues and to the external CPU

Table 213 bull Configuration Registers When Using An External CPU

RegisterRegister Field Description Value ReplicationQSYSEXT_CPU_CFGEXT_CPU_PORT Port number where external CPU is

connectedNone

QSYSEXT_CPU_CFGEXT_CPUQ_MSK Configures which CPU extraction queues are sent to the external CPU

SYSPORT_MODEINCL_XTR_HDR Enables the insertion of the CPU extraction header in egress frames

Per port

SYSPORT_MODEINCL_INJ_HDR Enables ingress port to look for CPU injection header in incoming frames

Per port

Registers

6 Registers

Information about the registers for this product is available in the attached file To view or print the information double-click the attachment icon

VSC7511 Registers 4-Port Layer-2 Gigabit Ethernet Switch

Attachment to VMDS-10488 42 319

Attachment to VMDS-10488 VSC7511 Registers Revision 42 1

Contents

1 Revision History 111 Revision 42 112 Revision 41 113 Revision 40 114 Revision 20 1

2 Registers 221 ANA 3

211 ANAANA 3212 ANAPGID 13213 ANAANA_TABLES 14214 ANAPORT 20215 ANAPFC 31216 ANACOMMON 32217 ANAPOL 38218 ANAPOL_MISC 40

22 DEV 41221 DEVPORT_MODE 41222 DEVMAC_CFG_STATUS 45223 DEVPCS1G_CFG_STATUS 51224 DEVPCS1G_TSTPAT_CFG_STATUS 59225 DEVPCS_FX100_CONFIGURATION 60226 DEVPCS_FX100_STATUS 62

23 DEVCPU_GCB 63231 DEVCPU_GCBCHIP_REGS 63232 DEVCPU_GCBVCORE_ACCESS 65233 DEVCPU_GCBGPIO 69234 DEVCPU_GCBMIIM 73235 DEVCPU_GCBMIIM_READ_SCAN 77236 DEVCPU_GCBMIIM_SLAVE 78237 DEVCPU_GCBPHY 78238 DEVCPU_GCBSIO_CTRL 79239 DEVCPU_GCBFAN_CTRL 872310 DEVCPU_GCBMEMITGR 882311 DEVCPU_GCBVRAP 92

24 DEVCPU_ORG 93241 DEVCPU_ORGDEVCPU_ORG 93

25 DEVCPU_PTP 99251 DEVCPU_PTPPTP_CFG 99252 DEVCPU_PTPPTP_STATUS 102253 DEVCPU_PTPPTP_PINS 103

26 DEVCPU_QS 106261 DEVCPU_QSXTR 106262 DEVCPU_QSINJ 109

27 HSIO 112271 HSIOPLL5G_CFG 113272 HSIOPLL5G_STATUS 114273 HSIORCOMP_STATUS 115274 HSIOSYNC_ETH_CFG 116275 HSIOSERDES1G_ANA_CFG 117276 HSIOSERDES1G_DIG_CFG 122

277 HSIOSERDES1G_DIG_STATUS 123278 HSIOMCB_SERDES1G_CFG 124279 HSIOSERDES6G_DIG_CFG 1252710 HSIOSERDES6G_ANA_CFG 1262711 HSIOSERDES6G_ANA_STATUS 1392712 HSIOMCB_SERDES6G_CFG 1422713 HSIOHW_CFGSTAT 1422714 HSIOTEMP_SENSOR 144

28 ICPU_CFG 145281 ICPU_CFGCPU_SYSTEM_CTRL 146282 ICPU_CFGSPI_MST 149283 ICPU_CFGMPU8051 151284 ICPU_CFGINTR 154285 ICPU_CFGTIMERS 164286 ICPU_CFGTWI_DELAY 167287 ICPU_CFGTWI_SPIKE_FILTER 167288 ICPU_CFGFDMA 168289 ICPU_CFGPCIE 1802810 ICPU_CFGMANUAL_XTRINJ 185

29 VCAP_CORE 188291 VCAP_COREVCAP_CORE_CFG 188292 VCAP_COREVCAP_CORE_CACHE 191293 VCAP_COREVCAP_CORE_MAP 193294 VCAP_CORETCAM_BIST 194

210 PCIE 1952101 PCIEPCIE_TYPE0_HDR 1952102 PCIEPCIE_PM_CAP 2002103 PCIEPCIE_MSI_CAP 2022104 PCIEPCIE_CAP 2032105 PCIEPCIE_AER_CAP 2082106 PCIEPCIE_PORT_LOGIC 212

211 QSYS 2162111 QSYSSYSTEM 2162112 QSYSTIMED_FRAME_CFG 2212113 QSYSRES_QOS_ADV 2242114 QSYSRES_CTRL 2252115 QSYSDROP_CFG 2272116 QSYSMMGT 2272117 QSYSHSCH 2282118 QSYSHSCH_MISC 233

212 REW 2342121 REWPORT 2342122 REWCOMMON 238

213 SBA 2392131 SBASBA 239

214 SFR 2422141 SFRSFR 242

215 SIMC 2552151 SIMCSIMC 255

216 SYS 2632161 SYSSYSTEM 2632162 SYSPAUSE_CFG 2682163 SYSMMGT 2702164 SYSSTAT 2712165 SYSPTP 271

217 TWI 2742171 TWITWI 274

218 UART 2932181 UARTUART 293

219 PHY 3022191 PHYPHY_STD 3022192 PHYPHY_EXT1 3252193 PHYPHY_EXT2 3312194 PHYPHY_GP 3362195 PHYPHY_EEE 341

Revision History

1 Revision History

This section describes the changes that were implemented in the document The changes are listed by revision starting with the most current publication

11 Revision 42Revision 42 of this datasheet was published in March 2019 The following is a summary of the changes in revision 42 of this document

12 Revision 41In revision 41 of this document the register list was updated For more information see Registers page 2

13 Revision 40In revision 40 of this document the REV_ID was updated For more information see Table 121 page 64

Registers

2 Registers

This section provides information about the programming interface register maps register descriptions and register tables of the device

In writing to registers with reserved bits use a read-modify-write technique where the entire register is read but with only the user bits to be chance are modified Do not change the values of the register and bits marked as reserved Their read state should not be considered static or unchanging Unspecified registers and bits must be written to 0 and can be ignored when read

The first-level table lists all register targets and associated base addresses The second level table lists registers groups and offsets within targets and the third-level tables list registers within the register groups

Both register groups and registers may be replicated (repeated) a number of times The repeat-count and the distance between two repetitions are listed in the Instances and Address Spacing column Spacing is omitted if there is only one instance The Offset within Target and the Offset within Register Group columns hold the offset of the first instance of the register group or register

Use the following steps to calculate the absolute address of a given register

1 Multiply the register groups replication number by the register groups address spacing2 Add the result to the register groups offset within the target3 Multiply the registers replication number with the registers address spacing4 Add the result to the registers offset within the register group5 Add these two numbers to the absolute address of the target in question

Table 1 bull List of Targets and Base Addresses

Target Name Base Address Description DetailsANA 0x71880000 Analyzer Configuration Page 3

DEV[0] 0x711E0000 Port Configuration Page 41

DEV[1] 0x711F0000 Port Configuration Page 41

DEV[2] 0x71200000 Port Configuration Page 41

DEVCPU_GCB 0x71070000 General configuration block Page 63

DEVCPU_ORG 0x71000000 CPU Device Origin Page 93

DEVCPU_PTP 0x710E0000 DEVCPU Precision Timing Protocol Originator Page 99

DEVCPU_QS 0x71080000 CPU Device Queue System Page 106

ES0 0x71040000 Versatile Content Aware Processor Page 188

HSIO 0x710D0000 Macro Control Register Collection Page 112

ICPU_CFG 0x70000000 AMBA Top Level Settings Page 145

S1 0x71050000 Versatile Content Aware Processor Page 188

Registers

21 ANA

211 ANAANAParent ANA

Instances 1

PCIE_EP 0x70111000 PCIe Endpoint Configuration Space Page 195

QSYS 0x71800000 Queue System Configuration Page 216

REW 0x71030000 Rewriter Configuration Page 234

SBA 0x70110000 Shared Bus Arbiter Page 239

SFR SFR VCore CPU SFR Page 242

SIMC 0x70101000 SI Master Controller Page 255

SYS 0x71010000 Switching Engine Configuration Page 263

TWI 0x70100400 Two-Wire Interface Controller Page 274

UART 0x70100000 UART Controller Page 293

UART2 0x70100800 UART Controller Page 293

PHY 0x71000000 PHY Configuration Page 302

Table 2 bull Register Groups in ANA

Register Group NameOffset within Target

Instances and Address Spacing Description Details

ANA 0x00009000 1 Common analyzer registers Page 3

PGID 0x00008C00 1 Port Group Identifier table Page 13

ANA_TABLES 0x00008B00 1 Analyzer tables Page 14

PORT 0x00007000 120x00000100

Classifier configuration per port

PFC 0x00008800 110x00000040

Priority-based flow control configuration

COMMON 0x000090B4 1 Common configurations for classifier

POL 0x00004000 3840x00000020

Policer configuration Page 38

POL_MISC 0x00008B80 1 Policer flow control configuration

Table 1 bull List of Targets and Base Addresses (continued)

Target Name Base Address Description Details

Registers

2111 ANAANAADVLEARNParent ANAANA

Instances 1

Table 3 bull Registers in ANA

Register NameOffset within Register Group

ADVLEARN 0x00000000 1 Advanced learning setup Page 4

VLANMASK 0x00000004 1 VLAN source port mask Page 5

ANAGEFIL 0x0000000C 1 Aging filter Page 5

ANEVENTS 0x00000010 1 Event sticky bits Page 6

STORMLIMIT_BURST 0x00000014 1 Storm policer burst Page 7

STORMLIMIT_CFG 0x00000018 40x00000004

Storm policer configuration per storm policer

ISOLATED_PORTS 0x00000028 1 Private VLAN mask for isolated ports

COMMUNITY_PORTS 0x0000002C 1 Private VLAN mask for community ports

AUTOAGE 0x00000030 1 Auto-age timer Page 9

MACTOPTIONS 0x00000034 1 MAC table options Page 9

LEARNDISC 0x00000038 1 Learn discard counter Page 9

AGENCTRL 0x0000003C 1 Analyzer configuration Page 10

MIRRORPORTS 0x00000040 1 Mirror target ports Page 11

EMIRRORPORTS 0x00000044 1 Egress mirror mask Page 11

FLOODING 0x00000048 1 Standard flooding configuration

FLOODING_IPMC 0x0000004C 1 Flooding configuration for IP multicasts

SFLOW_CFG 0x00000050 120x00000004

sFlow sampling configuration per switch port

PORT_MODE 0x00000080 130x00000004

Port configuration per device port

Table 4 bull Fields in ADVLEARN

Field Name Bit Access Description DefaultVLAN_CHK 11 RW If this bit is set a frame discarded because of

VLAN ingress filtering is not subject to learning VLAN ingress filtering is controlled by the VLAN_SRC_CHK flag in the VLAN table (see VLANACCESS register) or the VLANMASK register

Registers

2112 ANAANAVLANMASKParent ANAANA

Instances 1

2113 ANAANAANAGEFILParent ANAANA

Instances 1

This register sets up which entries are touched by an aging operation (manual as well as automatic aging)

In this way it is possible to have different aging periods in each VLAN and to have quick removal of entries on specific ports

The register also affects the GET_NEXT MAC table command When using the register to control the behavior of GET_NEXT it is recommended to disable automatic aging while executing the GET_NEXT command

LEARN_MIRROR 100 RW Learn frames are also forwarded to ports marked in this mask

Table 5 bull Fields in VLANMASK

Field Name Bit Access Description DefaultVLANMASK 110 RW Mask for requiring VLAN ingress filtering If

the bit for the frames physical ingress port is set in this mask then the port must be member of ingress frames VLAN (VLANACCESSVLAN_PORT_MASK) otherwise the frame is discarded

Table 6 bull Fields in ANAGEFIL

Field Name Bit Access Description DefaultAGE_LOCKED 20 RW Select entries to age If cleared unlocked

entries are aged and potentially removed If set locked entries are aged but not removed

PID_EN 19 RW If set only MAC table entries with a destination index matching PID_VAL are aged or searched with GET_NEXT

PID_VAL 1814 RW Destination index used in selective aging or MAC table searching

VID_EN 13 RW If set only MAC table entries with a VID matching VID_VAL are aged or searched with GET_NEXT

VID_VAL 120 RW VID used in selective aging or MAC table searching

0x0000

Table 4 bull Fields in ADVLEARN (continued)

Field Name Bit Access Description Default

Registers

2114 ANAANAANEVENTSParent ANAANA

Instances 1

Table 7 bull Fields in ANEVENTS

Field Name Bit Access Description DefaultMSTI_DROP 27 Sticky A frame was discarded due to blocking MSTI 0x0

AUTOAGE 24 Sticky An AUTOAGE run was performed 0x0

STORM_DROP 22 Sticky A frame was discarded because it exceeded the flooding storm limitations configured in STORMLIMIT

LEARN_DROP 21 Sticky A frame was discarded because it was subject to learning and the DropMode flag was set in ADVLEARN

AGED_ENTRY 20 Sticky An entry was removed at CPU Learn or CPU requested an aging process

CPU_LEARN_FAILED 19 Sticky A learn operation failed due to hash table depletion CPU-based learning only

AUTO_LEARN_FAILED 18 Sticky A learn operation of incoming source MAC address failed due to hash table depletion Hardware-based learning only

LEARN_REMOVE 17 Sticky An entry was removed when learning a new source MAC address

AUTO_LEARNED 16 Sticky An entry was learned from an incoming frame Hardware-based learning only

AUTO_MOVED 15 Sticky A station was moved to another port 0x0

CLASSIFIED_DROP 13 Sticky A frame was not forwarded due to classification (such as BPDUs)

CLASSIFIED_COPY 12 Sticky A frame was copied to the CPU due to classification

VLAN_DISCARD 11 Sticky A frame was discarded due to lack of VLAN membership on source port

FWD_DISCARD 10 Sticky A frame was discarded due to missing forwarding state on source port

MULTICAST_FLOOD 9 Sticky A frame was flooded with multicast flooding mask

UNICAST_FLOOD 8 Sticky A frame was flooded with unicast flooding mask

DEST_KNOWN 7 Sticky A frame was forwarded with known destination MAC address

BUCKET3_MATCH 6 Sticky A destination was found in hash table bucket 3

Registers

2115 ANAANASTORMLIMIT_BURSTParent ANAANA

Instances 1

2116 ANAANASTORMLIMIT_CFGParent ANAANA

Instances 4

0 UC storm policer

1 BC storm policer

2 MC policer

3 Learn policer

CPU_OPERATION 2 Sticky A CPU-initiated operation on the MAC or VLAN table was processed Default is 1 due to auto-initialization of the MAC and VLAN table

DMAC_LOOKUP 1 Sticky A destination address was looked up in the MAC table

SMAC_LOOKUP 0 Sticky A source address was looked up in the MAC table

Table 8 bull Fields in STORMLIMIT_BURST

Field Name Bit Access Description DefaultSTORM_BURST 30 RW Allowed number of frames in a burst is

2STORM_BURST The maximum allowed burst is 4096 frames which corresponds to STORM_BURST = 12 The STORM_BURST is common for all storm policers

Table 9 bull Fields in STORMLIMIT_CFG

Field Name Bit Access Description DefaultSTORM_RATE 63 RW Allowed rate of storm policer is

2STORM_UNIT framessec or kiloframessec (see STORM_UNIT) The maximum allowed rate is 1024 kiloframessec which corresponds to STORM_RATE = 10 with STORM_UNIT set to 0

STORM_UNIT 2 RW If set the base unit for the storm policer is 1 frame per second If cleared the base unit is 1 kiloframes per second

Table 7 bull Fields in ANEVENTS (continued)

Registers

2117 ANAANAISOLATED_PORTSParent ANAANA

Instances 1

2118 ANAANACOMMUNITY_PORTSParent ANAANA

Instances 1

STORM_MODE 10 RW Mode of operation for storm policer0 Disabled1 Police CPU destination only2 Police front port destinations only3 Police both CPU and front port destinations

Table 10 bull Fields in ISOLATED_PORTS

Field Name Bit Access Description DefaultISOL_PORTS 110 RW This mask is used in private VLANs

applications Promiscuous and community ports must be set and isolated ports must be cleared

For frames classified to a private VLAN (see the VLAN_PRIV_VLAN field in VLAN table) the resulting VLAN mask is calculated as follows- Frames received on a promiscuous port use the VLAN mask directly- Frames received on a community port use the VLAN mask ANDed with the ISOL_PORTS- Frames received on a isolated port use the VLAN mask ANDed with the COMM_PORTS ANDed with the ISOL_PORTS

For frames classified to a non-private VLAN this mask is not used

Table 11 bull Fields in COMMUNITY_PORTS

Field Name Bit Access Description DefaultCOMM_PORTS 110 RW This mask is used in private VLANs

applications Promiscuous and isolated ports must be set and community ports must be cleared

See ISOLATED_PORTSISOL_PORTS for details

Table 9 bull Fields in STORMLIMIT_CFG (continued)

Registers

2119 ANAANAAUTOAGEParent ANAANA

Instances 1

21110 ANAANAMACTOPTIONSParent ANAANA

Instances 1

21111 ANAANALEARNDISCParent ANAANA

Instances 1

The total number of MAC table entries that have been or would have been learned but have been discarded due to a lack of storage space

Table 12 bull Fields in AUTOAGE

Field Name Bit Access Description DefaultAGE_FAST 21 RW Sets the unit of AGE_PERIOD to 131 us

AGE_PERIOD must be a minimum of 3 when using the FAST option

AGE_PERIOD 201 RW Time in seconds between automatic aging of a MAC table entry Setting AGE_PERIOD to zero effectively disables automatic aging An inactive unlocked MAC table entry is aged after 2AGE_PERIOD

0x00000

AUTOAGE_LOCKED 0 RW Enable setting of the AGED_FLAG for locked entries in the MAC table when doing an age scan Locked entries are never removed but the AGED_FLAG can be used to indicate activity for the MAC address

Table 13 bull Fields in MACTOPTIONS

Field Name Bit Access Description DefaultREDUCED_TABLE 1 RW When set the MAC table is reduced to 256

entries (64 rows of 4 entries)0x0

SHADOW 0 RW Enable MAC table shadow registers The SHADOW bit affects the behavior of the READ command in MACACCESSMAC_TABLE_CMD With the shadow bit set reading bucket 0 causes the remaining 3 buckets in the row to be stored in shadow registers Following read accesses to bucket 1-3 return the content of the shadow registers This is useful when reading a MAC table which can change while being read

Registers

21112 ANAANAAGENCTRLParent ANAANA

Instances 1

Table 14 bull Fields in LEARNDISC

Field Name Bit Access Description DefaultLEARNDISC 310 RW Number of discarded learn requests due to

MAC table overflow (collisions or MAC table entry limits)

0x00000000

Table 15 bull Fields in AGENCTRL

Field Name Bit Access Description DefaultFID_MASK 2312 RW Mask used to enable shared learning among

multiple VLANs The FID value used in learning and MAC table lookup is calculated as FID = VID and (not FID_MASK) By default FID_MASK is set to all-zeros corresponding to independent VLAN learning In this case FID becomes identical to VID

IGNORE_DMAC_FLAGS 11 RW Do not react to flags found in the DMAC entry or the corresponding flags for flooded frames (FLOOD_IGNORE_VLAN)

IGNORE_SMAC_FLAGS 10 RW Do not react to flags found in the SMAC entry Note the IGNORE_VLAN flag is not checked for SMAC entries

FLOOD_SPECIAL 9 RW Flood frames using the lowest 12 bits of DMAC as destination port mask This is only added for testing purposes

FLOOD_IGNORE_VLAN 8 RW VLAN mask is not applied to flooded frames 0x0

MIRROR_CPU 7 RW Frames destined for the CPU extraction queues are also forwarded to the port set configured in MIRRORPORTS

LEARN_CPU_COPY 6 RW If set auto-learned stations get the CPU_COPY flag set in the MAC table entry

LEARN_SRC_KILL 5 RW If set auto-learned stations get the SRC_KILL flag set in the MAC table entry

LEARN_IGNORE_VLAN 4 RW If set auto-learned stations get the IGNORE_VLAN flag set in the MAC table entry

CPU_CPU_KILL_ENA 3 RW If set CPU injected frames are never sent back to the CPU

GREEN_COUNT_MODE 2 RW Counter mode for the Rx priority counters for green frames (C_RX_GREEN_PRIO_x)0 Count octets1 Count frames

Registers

21113 ANAANAMIRRORPORTSParent ANAANA

Instances 1

21114 ANAANAEMIRRORPORTSParent ANAANA

Instances 1

21115 ANAANAFLOODINGParent ANAANA

Instances 1

YELLOW_COUNT_MODE 1 RW Counter mode for the Rx priority counters for yellow frames (C_RX_YELLOW_PRIO_x)0 Count octets1 Count frames

RED_COUNT_MODE 0 RW Counter mode for the Rx priority counters for red frames (C_RX_RED_PRIO_x)0 Count octets1 Count frames

Table 16 bull Fields in MIRRORPORTS

Field Name Bit Access Description DefaultMIRRORPORTS 110 RW Ports set in this mask receive a mirror copy If

CPU is included in mask (most significant bit set) then the frame is copied to CPU extraction queue CPUQ_CFGCPUQ_MIRROR

Table 17 bull Fields in EMIRRORPORTS

Field Name Bit Access Description DefaultEMIRRORPORTS 110 RW Frames forwarded to ports in this mask are

mirrored to the port set configured in MIRRORPORTS (ie egress port mirroring)

Table 18 bull Fields in FLOODING

Field Name Bit Access Description DefaultFLD_UNICAST 1712 RW Set the PGID mask to use when flooding

unknown unicast frames0x3F

FLD_BROADCAST 116 RW Set the PGID mask to use when flooding unknown broadcast frames

Table 15 bull Fields in AGENCTRL (continued)

Registers

21116 ANAANAFLOODING_IPMCParent ANAANA

Instances 1

21117 ANAANASFLOW_CFGParent ANAANA

Instances 12

21118 ANAANAPORT_MODEParent ANAANA

Instances 13

These configurations exists per front port and for two CPU ports

FLD_MULTICAST 50 RW Set the PGID mask to use when flooding unknown multicast frames (except IP multicasts)

Table 19 bull Fields in FLOODING_IPMC

Field Name Bit Access Description DefaultFLD_MC4_CTRL 2318 RW Set the PGID mask to use when flooding

unknown IPv4 Multicast Control frames0x3F

FLD_MC4_DATA 1712 RW Set the PGID mask to use when flooding unknown IPv4 Multicast Data frames

FLD_MC6_CTRL 116 RW Set the PGID mask to use when flooding unknown IPv6 Multicast Control frames

Table 20 bull Fields in SFLOW_CFG

Field Name Bit Access Description DefaultSF_RATE 132 RW Probability of a frame being SFLOW

sampled Unit is 14096 A value of 0 makes 14096 of the candidates being forwarded to the SFLOW CPU extraction queue A values of 4095 makes all candidates being forwarded

SF_SAMPLE_RX 1 RW Enable SFLOW sampling of frames received on this port

SF_SAMPLE_TX 0 RW Enable SFLOW sampling of frames transmitted on this port

Table 18 bull Fields in FLOODING (continued)

Registers

212 ANAPGIDParent ANA

Instances 1

2121 ANAPGIDPGIDParent ANAPGID

Instances 92

Three port masks are applied to all frames allowing transmission to a port if the corresponding bit is set in all masks

0-63 A mask is applied based on destination analysis

64-79 A mask is applied based on aggregation analysis

80-90 A mask is applied based on source port analysis

Destination analysis

There are 64 destination masks in total By default the first 11 port masks only have the bit corresponding to their port number set These masks should not be changed except for aggregation

The remaining destination masks are set to 0 by default and are available for use for Layer-2 multicasts and flooding (See FLOODING and FLOODING_IPMC)

Aggregation analysis

The aggregation port masks are used to select only one port within each aggregation group These 16 masks must be setup to select only one port in each aggregated port group

Table 21 bull Fields in PORT_MODE

Field Name Bit Access Description DefaultRESERVED 21 RW Must be set to its default 0x2

L3_PARSE_CFG 0 RW Enable frame analysis on Layer-3 and Layer-4 protocol information If cleared all frames are seen as non-IP and are handled accordingly This affects all blocks using IP information such as classification TCAM lookups IP flooding and forwarding and DSCP rewriting

Table 22 bull Registers in PGID

PGID 0x00000000 920x00000004

Port Group Identifiers Page 13

Registers

For ports which are not part of any aggregation group the corresponding bits in all 16 masks must be set

Ie if no aggregation is configured all masks must be set to all-ones

The aggregation mask used for the forwarding of a given frame is selected by the frames aggregation code (see AGGRCTRL)

Source port analysis

The source port masks are used to prevent frames from being looped back to the ports on which they were received and must be updated according to the

aggregation configuration A frame that is received on port n uses mask 80+n as a mask to filter out destination ports to avoid loopback or to facilitate port grouping (port-based VLANs) The default values are that all bits are set except for the index number

213 ANAANA_TABLESParent ANA

Instances 1

Table 23 bull Fields in PGID

Field Name Bit Access Description DefaultCPUQ_DST_PGID 2927 RW CPU extraction queue used when CPU port

is enabled in PGID Only applicable for the destination analysis

PGID 110 RW When a mask is chosen bit N must be set for the frame to be transmitted on port N

Table 24 bull Registers in ANA_TABLES

ANMOVED 0x00000030 1 Station move logger Page 15

MACHDATA 0x00000034 1 MAC address high Page 15

MACLDATA 0x00000038 1 MAC address low Page 15

MACACCESS 0x0000003C 1 MAC table command Page 15

MACTINDX 0x00000040 1 MAC table index Page 17

VLANACCESS 0x00000044 1 VLAN table command Page 18

VLANTIDX 0x00000048 1 VLAN table index Page 18

ENTRYLIM 0x00000000 120x00000004

MAC table entry limits per switch port

PTP_ID_HIGH 0x00000054 1 PTP identifiers 63-32 Page 19

PTP_ID_LOW 0x00000058 1 PTP identifiers 31-0 Page 20

Registers

2131 ANAANA_TABLESANMOVEDParent ANAANA_TABLES

Instances 1

2132 ANAANA_TABLESMACHDATAParent ANAANA_TABLES

Instances 1

2133 ANAANA_TABLESMACLDATAParent ANAANA_TABLES

Instances 1

2134 ANAANA_TABLESMACACCESSParent ANAANA_TABLES

Instances 1

This register is used for updating or reading the MAC table from the CPU

Table 25 bull Fields in ANMOVED

Field Name Bit Access Description DefaultANMOVED 110 RW This mask detects port moves in the MAC

table When a station is learned on a new port while already learned on another port the bit corresponding to the new port is set in this mask This mask can be used to detect topology problems in the network where stations are learned on multiple ports repeatedly If some bits in this register get asserted repeatedly the ports can be shut down or management warnings can be issued

Table 26 bull Fields in MACHDATA

Field Name Bit Access Description DefaultVID 2816 RW VID used in MAC table operations through

MACACCESS For read operations the VID value is returned in this field

0x0000

MACHDATA 150 RW Most significant 16 MAC address bits used in MAC table operations through MACACCESS

0x0000

Table 27 bull Fields in MACLDATA

Field Name Bit Access Description DefaultMACLDATA 310 RW Lower 32 MAC address bits used in MAC

table operations through MACACCESS0x00000000

Registers

The command (MAC_TABLE_CMD) selects between different operations and uses the following encoding

000 - IDLE

The previous operation has completed

001 - LEARN

Insertlearn new entry in MAC table Position given by (MAC VID) in MACHDATA and MACLDATA

010 - FORGET

Deleteunlearn entry given by (MAC VID) in MACHDATA and MACLDATA

Both locked and unlocked entries are deleted

011 - AGE

Start an age scan on the MAC table

100 - GET_NEXT

Get the smallest entry in the MAC table numerically larger than the (MAC VID) specified in MACHDATA and MACLDATA The VID and MAC are evaluated as a 60-bit number with the VID being most significant

101 - INIT

Table is initialized (completely cleared)

110 - READ

The READ command is divided into two modes Direct mode and indirect mode

Direct mode (read)

With MACACCESSVALID cleared the entry pointed to by MACTINDXM_INDEX (row) and MACTINDXBUCKET (column) is read

Indirect mode (lookup)

With MACACCESSVALID set the entry pointed to by (MAC VID) in the MACHDATA and MACLDATA is read

111 - WRITE

Write entry Address of the entry is specified in MACTINDXM_INDEX (row) and MACTINDXBUCKET (column)

An existing entry (locked or unlocked) is overwritten

The MAC_TABLE_CMD must be IDLE before a new command can be issued

The AGE and CLEAR commands run for approximately 50 us The other commands execute immediately

Registers

The flags IGNORE_VLAN and MAC_CPU_COPY are ignored for DMAC lookup if AGENCTRLIGNORE_DMAC_FLAGS is set

The flags SRC_KILL and MAC_CPU_COPY are ignored for SMAC lookup if AGENCTRLIGNORE_SMAC_FLAGS is set

2135 ANAANA_TABLESMACTINDXParent ANAANA_TABLES

Instances 1

Table 28 bull Fields in MACACCESS

Field Name Bit Access Description DefaultMAC_CPU_COPY 15 RW Frames matching this entry are copied to the

CPU extraction queue CPUQ_CFGCPUQ_MAC_COPY Applies to both SMAC and DMAC lookup

SRC_KILL 14 RW Frames matching this entry are discarded Applies only to the SMAC lookup For discarding frames based on the DMAC lookup a NULL PGID mask can be used

IGNORE_VLAN 13 RW The VLAN mask is ignored for this destination Applies only to DMAC lookup

AGED_FLAG 12 RW This flag is set on every aging run Entry is removed if flag is already set The flag is cleared when the entry is target for a SMAC lookup Locked entries will not be removed Bit is for IPv6 Multicast used for port 25

VALID 11 RW Entry is valid 0x0

ENTRY_TYPE 109 RW Type of entry0 Normal entry eligible for aging1 Locked entry Entry is not removed by aging2 IPv4 Multicast entry Entry is not removed by aging3 IPv6 Multicast entry Entry is not removed by aging

DEST_IDX 83 RW Index for the destination masks table (PGID) For unicasts this is a number from 0-EXB_PORT_CNT_MINUS_ONE

MAC_TABLE_CMD 20 RW MAC Table Command See below 0x0

Table 29 bull Fields in MACTINDX

Field Name Bit Access Description DefaultBUCKET 1110 RW Selects one of the four MAC table entries in a

row The row is addressed with the INDEX field

Registers

2136 ANAANA_TABLESVLANACCESSParent ANAANA_TABLES

Instances 1

The VLAN_TBL_CMD field of this register is used for updating and reading the VLAN table The command (VLAN_TBL_CMD) selects between different operations and uses the following encoding

00 - IDLE

01 - READ

The VLAN table entry set in VLANTIDXV_INDEX is returned in VLANACCESSVLAN_PORT_MASK and the VLAN flags in VLANTIDX

10 - WRITE

The VLAN table entry pointed to by VLANTIDXV_INDEX is updated with VLANACCESSVLAN_PORT_MASK and the VLAN flags in VLANTIDX

11 - INIT

The VLAN table is initialized to default values (all ports are members of all VLANs)

The VLAN_TBL_CMD must be IDLE before a new command can be issued The INIT command run for approximately 50 us whereas the other commands execute immediately When an operation has completed VLAN_TBL_CMD changes to IDLE

2137 ANAANA_TABLESVLANTIDXParent ANAANA_TABLES

Instances 1

M_INDEX 90 RW The index selects one of the 1024 MAC table rows Within a row the entry is addressed by the BUCKET field

Table 30 bull Fields in VLANACCESS

Field Name Bit Access Description DefaultVLAN_PORT_MASK 132 RW Frames classified to this VLAN can only be

sent to ports in this mask Note that the CPU port module is always member of all VLANs and its VLAN membership can therefore not be configured through this mask

VLAN_TBL_CMD 10 RW VLAN Table Command 0x0

Table 29 bull Fields in MACTINDX (continued)

Registers

2138 ANAANA_TABLESENTRYLIMParent ANAANA_TABLES

Instances 12

2139 ANAANA_TABLESPTP_ID_HIGHParent ANAANA_TABLES

Instances 1

Table 31 bull Fields in VLANTIDX

Field Name Bit Access Description DefaultVLAN_PRIV_VLAN 15 RW If set a VLAN is a private VLAN See

ISOLATED_PORTSISOL_PORTS for details

VLAN_LEARN_DISABLED 14 RW Disable learning for this VLAN 0x0

VLAN_MIRROR 13 RW If set all frames classified to this VLAN are mirrored to the port set configured in MIRRORPORTS

VLAN_SRC_CHK 12 RW If set VLAN ingress filtering is enabled for this VLAN If set a frames ingress port must be member of the frames VLAN otherwise the frame is discarded

V_INDEX 110 RW Index used to select VLAN table entry for readwrite operations (see VLANACCESS) This value equals the VID

Table 32 bull Fields in ENTRYLIM

Field Name Bit Access Description DefaultENTRYLIM 1714 RW Maximum number of unlocked entries in the

MAC table learned on this portLocked entries and IPMC entries do not obey this limitBoth auto-learned and unlocked CPU-learned entries obey this limit0 1 entry1 2 entriesn 2n entriesgt12 8192 entries

ENTRYSTAT 130 RW Current number of unlocked MAC table entries learned on this port

0x0000

Registers

21310 ANAANA_TABLESPTP_ID_LOWParent ANAANA_TABLES

Instances 1

214 ANAPORTParent ANA

Instances 12

Table 33 bull Fields in PTP_ID_HIGH

Field Name Bit Access Description DefaultPTP_ID_HIGH 310 RW Bit vector with current use of PTP timestamp

identifiers 32 through 63 Timestamp identifier is 63 is reserved for signaling that no identifiers are available A timestamp identifier is released by setting the corresponding bitBit 0 Timestamp identifier 32Bit 31 Timestamp identifier 63

0x00000000

Table 34 bull Fields in PTP_ID_LOW

Field Name Bit Access Description DefaultPTP_ID_LOW 310 RW Bit vector with current use of PTP timestamp

identifiers 0 through 31 A timestamp identifier is released by setting the corresponding bitBit 0 Timestamp identifier 0Bit 31 Timestamp identifier 31

0x0000000F

Table 35 bull Registers in PORT

VLAN_CFG 0x00000000 1 Port VLAN configuration Page 21

DROP_CFG 0x00000004 1 VLAN acceptance filtering Page 22

QOS_CFG 0x00000008 1 QoS and DSCP configuration Page 22

VCAP_CFG 0x0000000C 1 VCAP configuration Page 23

VCAP_S1_KEY_CFG 0x00000010 30x00000004

VCAP S1 key configuration per S1 lookup

VCAP_S2_CFG 0x0000001C 1 VCAP S2 configuration Page 24

QOS_PCP_DEI_MAP_CFG 0x00000020 160x00000004

Mapping of DEI and PCP to QoS class and drop precedence level

Registers

2141 ANAPORTVLAN_CFGParent ANAPORT

Instances 1

CPU_FWD_CFG 0x00000060 1 CPU forwarding of special protocols

CPU_FWD_BPDU_CFG 0x00000064 1 CPU forwarding of BPDU frames

CPU_FWD_GARP_CFG 0x00000068 1 CPU forwarding of GARP frames

CPU_FWD_CCM_CFG 0x0000006C 1 CPU forwarding of CCMLink trace frames

PORT_CFG 0x00000070 1 Special port configuration Page 28

POL_CFG 0x00000074 1 Policer selection Page 29

PTP_CFG 0x00000078 1 Timing protocol configuration Page 30

PTP_DLY1_CFG 0x0000007C 1 PTP ingress delay 1 configuration

PTP_DLY2_CFG 0x00000080 1 PTP ingress delay 2 configuration

Table 36 bull Fields in VLAN_CFG

Field Name Bit Access Description DefaultVLAN_AWARE_ENA 20 RW Enable VLAN awareness If set Q-tag

headers are processed during the basic VLAN classification If cleared Q-tag headers are ignored during the basic VLAN classification

VLAN_POP_CNT 1918 RW Number of tag headers to remove from ingress frame0 Keep all tags1 Pop up to 1 tag (outer tag if available)2 Pop up to 2 tags (outer and inner tag if available)3 Disable rewriting of VLAN tags and DSCP value The rewriter can still update the FCS

VLAN_INNER_TAG_ENA 17 RW Set if the inner Q-tag must be used instead of the outer Q-tag If the received frame is single tagged the outer tag is used This bit influences the VLAN acceptance filter (DROP_CFG) the basic VLAN classification (VLAN_CFG) and the basic QoS classification (QOS_CFG)

Table 35 bull Registers in PORT (continued)

Registers

2142 ANAPORTDROP_CFGParent ANAPORT

Instances 1

2143 ANAPORTQOS_CFGParent ANAPORT

Instances 1

VLAN_TAG_TYPE 16 RW Tag Protocol Identifier type for port-based VLAN0 C-tag (EtherType = 0x8100)1 S-tag (EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG))

VLAN_DEI 15 RW DEI value for port-based VLAN 0x0

VLAN_PCP 1412 RW PCP value for port-based VLAN 0x0

VLAN_VID 110 RW VID value for port-based VLAN 0x000

Table 37 bull Fields in DROP_CFG

Field Name Bit Access Description DefaultDROP_UNTAGGED_ENA 6 RW Drop untagged frames 0x0

DROP_S_TAGGED_ENA 5 RW Drop S-tagged frames (VID different from 0 and EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG))

DROP_C_TAGGED_ENA 4 RW Drop C-tagged frames (VID different from 0 and EtherType = 0x8100)

DROP_PRIO_S_TAGGED_ENA 3 RW Drop S-tagged frames (VID=0 and EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG))

DROP_PRIO_C_TAGGED_ENA 2 RW Drop priority C-tagged frames (VID=0 and EtherType = 0x8100)

DROP_NULL_MAC_ENA 1 RW Drop frames with source or destination MAC address equal to 0x000000000000

DROP_MC_SMAC_ENA 0 RW Drop frames with multicast source MAC address

Table 38 bull Fields in QOS_CFG

Field Name Bit Access Description DefaultDP_DEFAULT_VAL 8 RW Default drop precedence level 0x0

QOS_DEFAULT_VAL 75 RW Default QoS class 0x0

QOS_DSCP_ENA 4 RW If set the DP level and QoS class can be based on DSCP values

Table 36 bull Fields in VLAN_CFG (continued)

Registers

2144 ANAPORTVCAP_CFGParent ANAPORT

Instances 1

2145 ANAPORTVCAP_S1_KEY_CFGParent ANAPORT

Instances 3

QOS_PCP_ENA 3 RW If set DP level and QoS class can be based on the PCP and DEI bits for tagged frames

DSCP_TRANSLATE_ENA 2 RW Set if the DSCP value must be translated before using the DSCP value If set the translated DSCP value is given from DSCP_CFG[DSCP]DSCP_TRANSLATE_VAL

DSCP_REWR_CFG 10 RW Configure which DSCP values to rewrite based on DP level and QoS class If the DSCP value is to be rewritten then the new DSCP = DSCP_REWR_CFG[8DP level + QoS class]DSCP_QOS_REWR_VAL0 Rewrite none1 Rewrite if DSCP=02 Rewrite for selected values configured in DSCP_CFG[DSCP]DSCP_REWR_ENA3 Rewrite all

Table 39 bull Fields in VCAP_CFG

Field Name Bit Access Description DefaultS1_ENA 14 RW If S1 is enabled each frame received on this

port is processed and matched against the entries in the S1 TCAM Each frame results in three lookups

S1_DMAC_DIP_ENA 1311 RW Set if the destination MAC address and the destination IP address must be used in S1 key instead of the source MAC address and the source IP address One bit per lookup Only applicable to S1 keys S1_NORMAL and S1_NORMAL_IP6

S1_VLAN_INNER_TAG_ENA 108 RW Set if the inner Q-tag must be passed on to the S1 TCAM instead of the outer Q-tag For single tagged frames the outer tag is used For untagged frames the port VLAN is used This bit influences the TPID VID PCP and DEI input to the S1 key generation One bit per lookup Only applicable to S1_NORMAL

PAG_VAL 70 RW Default PAG value used as input to S2 The PAG value can be changed by S1 actions

Table 38 bull Fields in QOS_CFG (continued)

Registers

2146 ANAPORTVCAP_S2_CFGParent ANAPORT

Instances 1

Table 40 bull Fields in VCAP_S1_KEY_CFG

Field Name Bit Access Description DefaultS1_KEY_IP6_CFG 64 RW Selects key per lookup in S1 for IPv6 frames

0 Use key S1_NORMAL1 Use key S1_7TUPLE2 Use key S1_5TUPLE_IP43 Use key S1_NORMAL_IP64 Use key S1_5TUPLE_IP65 Use key S1_DBL_VID

S1_KEY_IP4_CFG 32 RW Selects key per lookup in S1 for IPv4 frames0 Use key S1_NORMAL1 Use key S1_7TUPLE2 Use key S1_5TUPLE_IP43 Use key S1_DBL_VID

S1_KEY_OTHER_CFG 10 RW Selects key per lookup in S1 for non-IP frames0 Use key S1_NORMAL1 Use key S1_7TUPLE2 Use key S1_DBL_VID

Table 41 bull Fields in VCAP_S2_CFG

port is processed and matched against the entries in the S2 TCAM Each frame results in two lookups to determine both an ingress and an egress action

S2_SNAP_DIS 1312 RW If set MAC_SNAP frames received on this port are treated as MAC_LLC frames when matching in S2Bit 0 controls the first lookup and bit 1 controls the second lookup

S2_ARP_DIS 1110 RW If set MAC_ARP frames received on this port are treated as MAC_ETYPE frames when matching in S2Bit 0 controls the first lookup and bit 1 controls the second lookup

S2_IP_TCPUDP_DIS 98 RW If set IP_TCPUDP frames received on this port are treated as MAC_ETYPE frames when matching in S2Bit 0 controls the first lookup and bit 1 controls the second lookup

Registers

2147 ANAPORTQOS_PCP_DEI_MAP_CFGParent ANAPORT

Instances 16

2148 ANAPORTCPU_FWD_CFGParent ANAPORT

Instances 1

S2_IP_OTHER_DIS 76 RW If set IP_OTHER frames received on this port are treated as MAC_ETYPE frames when matching in S2Bit 0 controls the first lookup and bit 1 controls the second lookup

S2_IP6_CFG 52 RW S2_IP6_CFG controls the key generation for IPv6 frames Bits 10 control the first lookup and bits 32 control the second lookup0 IPv6 frames are matched against IP6_TCP_UDP or IP6_OTHER entries1 IPv6 frames are matched against IP6_STD entries2 IPv6 frames are matched against IP4_TCP_UDP or IP4_OTHER entries3 IPv6 frames are matched against MAC_ETYPE entries

S2_OAM_DIS 10 RW If set OAM frames received on this port are treated as MAC_ETYPE frames when matching in S2Bit 0 controls the first lookup and bit 1 controls the second lookup

Table 42 bull Fields in QOS_PCP_DEI_MAP_CFG

Field Name Bit Access Description DefaultDP_PCP_DEI_VAL 3 RW Map the frames PCP and DEI values to a

drop precedence level DP level = QOS_PCP_DEI_MAP_CFG[index]DP_PCP_DEI_VAL where index = 8DEI + PCP Only applicable to tagged frames The use of Inner or outer tag can be selected using VLAN_CFGVLAN_INNER_TAG_ENA

QOS_PCP_DEI_VAL 20 RW Map the frames PCP and DEI values to a QoS class QoS class = QOS_PCP_DEI_MAP_CFG[index]QOS_PCP_DEI_VAL where index = 8DEI + PCP Only applicable to tagged frames The use of inner or outer tag can be selected using VLAN_CFGVLAN_INNER_TAG_ENA

Table 41 bull Fields in VCAP_S2_CFG (continued)

Registers

2149 ANAPORTCPU_FWD_BPDU_CFGParent ANAPORT

Instances 1

Table 43 bull Fields in CPU_FWD_CFG

Field Name Bit Access Description DefaultCPU_VRAP_REDIR_ENA 7 RW If set VRAP frames are redirected to the

CPU extraction queue given by CPUQ_CFG2CPUQ_VRAP

CPU_MLD_REDIR_ENA 6 RW If set MLD frames are redirected to the CPU 0x0

CPU_IGMP_REDIR_ENA 5 RW If set IGMP frames are redirected to the CPU

CPU_IPMC_CTRL_COPY_ENA 4 RW If set IPv4 multicast control frames (destination IP address in the range 22400x) are copied to the CPU

CPU_SRC_COPY_ENA 3 RW If set all frames received on this port are copied to the CPU extraction queue given by CPUQ_CFGCPUQ_SRC_COPY

CPU_ALLBRIDGE_DROP_ENA 2 RW If set All LANs Bridge Management Group Address frames (DMAC = 01-80-C2-00-00-10) are not forwarded to any front ports Together with CPU_ALLBRIDGE_REDIR_ENA CPU_ALLBRIDGE_DROP_ENA controls the forwardingCPU_ALLBRIDGE_DROP_ENA=0 CPU_ALLBRIDGE_REDIR_ENA=0 No actionCPU_ALLBRIDGE_DROP_ENA=0 CPU_ALLBRIDGE_REDIR_ENA=1 Redirect to CPUCPU_ALLBRIDGE_DROP_ENA=1 CPU_ALLBRIDGE_REDIR_ENA=0 DiscardCPU_ALLBRIDGE_DROP_ENA=1 CPU_ALLBRIDGE_REDIR_ENA=1 Copy to CPU

CPU_ALLBRIDGE_REDIR_ENA 1 RW If set All LANs Bridge Management Group Address frames (DMAC = 01-80-C2-00-00-10) are redirected to the CPU See also CPU_ALLBRIDGE_DROP_ENA

Registers

21410 ANAPORTCPU_FWD_GARP_CFGParent ANAPORT

Instances 1

21411 ANAPORTCPU_FWD_CCM_CFGParent ANAPORT

Table 44 bull Fields in CPU_FWD_BPDU_CFG

Field Name Bit Access Description DefaultBPDU_DROP_ENA 3116 RW If bit x is set BPDU frame (DMAC = 01-80-

C2-00-00-0x) is not forwarded to any front portsTogether with BPDU_REDIR_ENA BPDU_DROP_ENA controls the forwarding of BPDU frames

BPDU_DROP_ENA=0 BPDU_REDIR_ENA=0 No actionBPDU_DROP_ENA=0 BPDU_REDIR_ENA=1 Redirect to CPUBPDU_DROP_ENA=1 BPDU_REDIR_ENA=0 DiscardBPDU_DROP_ENA=1 BPDU_REDIR_ENA=1 Copy to CPU

0x0000

BPDU_REDIR_ENA 150 RW If bit x is set BPDU frame (DMAC = 01-80-C2-00-00-0x) is redirected to the CPU See also BPDU_DROP_ENA

0x0000

Table 45 bull Fields in CPU_FWD_GARP_CFG

Field Name Bit Access Description DefaultGARP_DROP_ENA 3116 RW If bit x is set GARP frame (DMAC = 01-80-

C2-00-00-2x) is not forwarded to any front portTogether with GARP_REDIR_ENA GARP_DROP_ENA controls the forwarding of GARP framesGARP_DROP_ENA=0 GARP_REDIR_ENA=0 No actionGARP_DROP_ENA=0 GARP_REDIR_ENA=1 Redirect to CPUGARP_DROP_ENA=1 GARP_REDIR_ENA=0 DiscardGARP_DROP_ENA=1 GARP_REDIR_ENA=1 Copy to CPU

0x0000

GARP_REDIR_ENA 150 RW If bit x is set GARP frame (DMAC = 01-80-C2-00-00-2x) is redirected to the CPU See also GARP_DROP_ENA

0x0000

Registers

Instances 1

21412 ANAPORTPORT_CFGParent ANAPORT

Instances 1

Table 46 bull Fields in CPU_FWD_CCM_CFG

Field Name Bit Access Description DefaultCCM_DROP_ENA 3116 RW If bit x is set CCMLink trace frame (DMAC =

01-80-C2-00-00-3x) is not forwarded to any front portTogether with CCM_REDIR_ENA CCM_DROP_ENA controls the forwarding of CCMLink trace framesCCM_DROP_ENA=0 CCM_REDIR_ENA=0 No actionCCM_DROP_ENA=0 CCM_REDIR_ENA=1 Redirect to CPUCCM_DROP_ENA=1 CCM_REDIR_ENA=0 DiscardCCM_DROP_ENA=1 CCM_REDIR_ENA=1 Copy to CPU

0x0000

CCM_REDIR_ENA 150 RW If bit x is set CCMLink trace frame (DMAC = 01-80-C2-00-00-3x) is redirected to the CPU See also CCM_DROP_ENA

0x0000

Table 47 bull Fields in PORT_CFG

Field Name Bit Access Description DefaultSRC_MIRROR_ENA 15 RW If set all frames received on this port are

mirrored to the port set configured in MIRRORPORTS (ie ingress mirroring) For egress mirroring see EMIRRORMASK

LIMIT_DROP 14 RW If set learn frames on an ingress port which has exceeded the maximum number of MAC table entries are discarded Forwarding to CPU is still allowed Note that if LEARN_ENA is cleared then the LIMIT_DROP is ignored

LIMIT_CPU 13 RW If set learn frames on an ingress port which has exceeded the maximum number of MAC table entries are copied to the CPU extraction queue specified in CPUQ_CFGCPUQ_LRN Note that if LEARN_ENA is cleared then the LIMIT_CPU is ignored

LOCKED_PORTMOVE_DROP 12 RW If set incoming frames triggering a port move for a locked entry in the MAC table received on this port are discarded Forwarding to CPU is still allowed Note that if LEARN_ENA is cleared then the LOCKED_PORTMOVE_DROP is ignored

Registers

21413 ANAPORTPOL_CFGParent ANAPORT

Instances 1

LOCKED_PORTMOVE_CPU 11 RW If set incoming frames triggering a port move for a locked MAC table entry received on this port are copied to the CPU extraction queue specified in CPUQ_CFGCPUQ_LOCKED_PORTMOVE Note that if LEARN_ENA is cleared then the LOCKED_PORTMOVE_CPU is ignored

LEARNDROP 10 RW If set incoming learn frames received on this port are discarded Forwarding to CPU is still allowed Note that if LEARN_ENA is cleared then the LEARNDROP is ignored

LEARNCPU 9 RW If set incoming learn frames received on this port are copied to the CPU extraction queue specified in CPUQ_CFGCPUQ_LRN Note that if LEARN_ENA is cleared then the LEARNCPU is ignored

LEARNAUTO 8 RW If set incoming learn frames received on this port are auto learned Note that if LEARN_ENA is cleared then the LEARNAUTO is ignored

LEARN_ENA 7 RW Enable learning for frames received on this port If cleared learning is skipped and any configuration settings in LEARNAUTO LEARNCPU LEARNDROP is ignored

RECV_ENA 6 RW Enable forwarding from this port based on VLAN and destination MAC address If cleared the VLAN and MAC tables are not looked up and result is set to 0 Learning and CPU forwarding are still possible

PORTID_VAL 52 RW Logical port number for front port If port is not a member of a LLAG then PORTID must be set to the physical port numberIf port is a member of a LLAG then PORTID must be set to the common PORTID_VAL used for all member ports of the LLAGThe value must not exceed the number of physical ports on the device

Table 47 bull Fields in PORT_CFG (continued)

Registers

21414 ANAPORTPTP_CFGParent ANAPORT

Instances 1

Table 48 bull Fields in POL_CFG

Field Name Bit Access Description DefaultPOL_CPU_REDIR_8021 19 RW If set frames with a DMAC = IEEE reserved

addresses (BPDU GARP CCM ALLBRIGDE) which are copied to the CPU are not policed by any policers

POL_CPU_REDIR_IP 18 RW If set IGMP and MLD frames which are redirected to the CPU are not policed by any policers The frames are still counted in the policers buckets

PORT_POL_ENA 17 RW Enable port policing for frames on received on this port Port policing on physical port P uses policer P

QUEUE_POL_ENA 169 RW Bit mask where bitltngt enables policing of frames classified to QoS class n on this port Policing of QoS class Q on physical port P uses policer 32+P8+Q

POL_ORDER 80 RW Each frame is checked against three policers 1) port 2) QoS and 3) VCAP In this register a bit set makes updating of a policer dependant on the result from another

Bitltn+3mgt set means Policer state ltngt is checked before policer ltmgt is updated

Bit0 Port policer must be open in order to update port policer with frameBit1 QoS policer must be open in order to update port policer with frameBit2 VCAP policer must be open in order to update port policer with frame

Bit3 Port policer must be open in order to update QoS policer with frameBit4 QoS policer must be open in order to update QoS policer with frameBit5 VCAP policer must be open in order to update QoS policer with frame

Bit6 Port policer must be open in order to update VCAP policer with frameBit7 QoS policer must be open in order to update VCAP policer with frameBit8 VCAP policer must be open in order to update VCAP policer with frame

Registers

21415 ANAPORTPTP_DLY1_CFGParent ANAPORT

Instances 1

215 ANAPFCParent ANA

Instances 11

Table 49 bull Fields in PTP_CFG

Field Name Bit Access Description DefaultPTP_BACKPLANE_MODE 0 RW Backplane mode for PTP If set the receive

timestamp is read from the PTP header (4 reserved bytes at offset 16) instead of from the ingress timer Ingress delays PTP_DLY1_CFG and PTP_DLY2_CFG are not applied in backplane mode

Table 50 bull Fields in PTP_DLY1_CFG

Field Name Bit Access Description DefaultPTP_DLY1_VAL 310 RW Delay optionally subtracted from the frames

receive timestamp This can for instance be a peer-to-peer link delay or a delay due to asymmetry The subtraction is enabled through IS2 action REW_OP for one-step PTP Unit is ns Value is signed

0x00000000

receive timestamp This can for instance be a peer-to-peer link delay or a delay due to asymmetry The subtraction is enabled through IS2 action REW_OP for one-step PTP This is not applicable if the ingress port is in backplane mode Unit is ns Value is signed

0x00000000

Registers

2151 ANAPFCPFC_CFGParent ANAPFC

Instances 1

216 ANACOMMONParent ANA

Instances 1

Table 52 bull Registers in PFC

PFC_CFG 0x00000000 1 Priority-based flow control configuration

Table 53 bull Fields in PFC_CFG

Field Name Bit Access Description DefaultRX_PFC_ENA 92 RW Enable PFC per priority Bit n enables PFC

on priority n0x00

FC_LINK_SPEED 10 RW Configures the link speed This is used to evaluate the time specifications in incoming pause frames 0 2500 Mbps1 1000 Mbps2 100 Mbps3 10 Mbps

Table 54 bull Registers in COMMON

AGGR_CFG 0x00000000 1 Aggregation code generation Page 33

CPUQ_CFG 0x00000004 1 CPU extraction queue configuration

CPUQ_CFG2 0x00000008 1 CPU extraction queue configuration 2

CPUQ_8021_CFG 0x0000000C 160x00000004

CPU extraction queue per address of BPDU GARP and CCM frames

DSCP_CFG 0x0000004C 640x00000004

DSCP configuration per DSCP value

DSCP_REWR_CFG 0x0000014C 160x00000004

DSCP rewrite values per DP level and QoS class

Registers

2161 ANACOMMONAGGR_CFGParent ANACOMMON

Instances 1

2162 ANACOMMONCPUQ_CFGParent ANACOMMON

Instances 1

VCAP_RNG_TYPE_CFG 0x0000018C 80x00000004

VCAP range checkers Page 35

VCAP_RNG_VAL_CFG 0x000001AC 80x00000004

Range configuration per range checker

VRAP_CFG 0x000001CC 1 VRAP classifier configuration Page 36

VRAP_HDR_DATA 0x000001D0 1 VRAP data Page 36

VRAP_HDR_MASK 0x000001D4 1 VRAP mask Page 37

DISCARD_CFG 0x000001D8 1 Various options for discard filters

FID_CFG 0x000001DC 1 FID selector configuration Page 37

Table 55 bull Fields in AGGR_CFG

Field Name Bit Access Description DefaultAC_RND_ENA 7 RW Use pseudo random number for aggregation

code Overrule other contributions0x0

AC_DMAC_ENA 6 RW Use the lower 12 bits of the destination MAC address for aggregation code

AC_SMAC_ENA 5 RW Use the lower 12 bits of the source MAC address for aggregation code

AC_IP6_FLOW_LBL_ENA 4 RW Use the 20-bit IPv6 flow label for aggregation code

AC_IP6_TCPUDP_ENA 3 RW Use least significant 8 bits of both source port and destination port of IPv6 frames for aggregation code

AC_IP4_SIPDIP_ENA 2 RW Use least significant 8 bits of both source IP address and destination IP address of IPv4 frames for aggregation code

Table 54 bull Registers in COMMON (continued)

Registers

2163 ANACOMMONCPUQ_CFG2Parent ANACOMMON

Instances 1

2164 ANACOMMONCPUQ_8021_CFGParent ANACOMMON

Instances 16

The register instance number corresponds to the address of the extracted frame For instance CPUQ_8021_CFG[4]CPUQ_BPDU_VAL is the CPU extraction queue used for BPDU frames with address 01-80-C2-00-00-04

Table 56 bull Fields in CPUQ_CFG

Field Name Bit Access Description DefaultCPUQ_MLD 2927 RW CPU extraction queue used for MLD frames 0x0

CPUQ_IGMP 2624 RW CPU extraction queue used for IGMP frames 0x0

CPUQ_IPMC_CTRL 2321 RW CPU extraction queue used for IPv4 multicast control frames

CPUQ_ALLBRIDGE 2018 RW CPU extraction queue used for All LANs Bridge Management Group Address frames (DMAC = 01-80-C2-00-00-10)

CPUQ_LOCKED_PORTMOVE 1715 RW CPU extraction queue for frames triggering a port move for a locked MAC table entry

CPUQ_SRC_COPY 1412 RW CPU extraction queue for frames copied due to CPU_SRC_COPY_ENA

CPUQ_MAC_COPY 119 RW CPU extraction queue for frames copied due to CPU_COPY return by MAC table lookup

CPUQ_LRN 86 RW CPU extraction queue for frames copied due to learned or moved stations

CPUQ_MIRROR 53 RW CPU extraction queue for frames copied due to mirroring to the CPU

CPUQ_SFLOW 20 RW CPU extraction queue for frames copied due to SFLOW sampling

Table 57 bull Fields in CPUQ_CFG2

Field Name Bit Access Description DefaultCPUQ_VRAP 20 RW CPU extraction queue used for VRAP

frames0x0

Table 58 bull Fields in CPUQ_8021_CFG

Field Name Bit Access Description DefaultCPUQ_BPDU_VAL 86 RW CPU extraction queue used for BPDU

frames0x0

Registers

2165 ANACOMMONDSCP_CFGParent ANACOMMON

Instances 64

2166 ANACOMMONDSCP_REWR_CFGParent ANACOMMON

Instances 16

2167 ANACOMMONVCAP_RNG_TYPE_CFGParent ANACOMMON

Instances 8

CPUQ_GARP_VAL 53 RW CPU extraction queue used for GARP frames

CPUQ_CCM_VAL 20 RW CPU extraction queue used for CCMLink trace frames

Table 59 bull Fields in DSCP_CFG

Field Name Bit Access Description DefaultDP_DSCP_VAL 11 RW Maps the frames DSCP value to a drop

precedence level This is enabled in QOS_CFGQOS_DSCP_ENA

QOS_DSCP_VAL 108 RW Maps the frames DSCP value to a QoS class This is enabled in QOS_CFGQOS_DSCP_ENA

DSCP_TRANSLATE_VAL 72 RW Translated DSCP value triggered if DSCP translation is set for port (QOS_CFG[port]DSCP_TRANSLATE_ENA)

DSCP_TRUST_ENA 1 RW Must be set for a DSCP value if the DSCP value is to be used for QoS classification

DSCP_REWR_ENA 0 RW Set if the DSCP value is selected to be rewritten This is controlled in QOS_CFGDSCP_REWR_CFG

Table 60 bull Fields in DSCP_REWR_CFG

Field Name Bit Access Description DefaultDSCP_QOS_REWR_VAL 50 RW Map the frames DP level and QoS class to a

DSCP value DSCP = DSCP_REWR_CFG[8DP level + QoS class]DSCP_QOS_REWR_VAL This is controlled in QOS_CFGDSCP_REWR_CFG and DSCP_CFGDSCP_REWR_ENA

Table 58 bull Fields in CPUQ_8021_CFG (continued)

Registers

2168 ANACOMMONVCAP_RNG_VAL_CFGParent ANACOMMON

Instances 8

2169 ANACOMMONVRAP_CFGParent ANACOMMON

Instances 1

21610 ANACOMMONVRAP_HDR_DATAParent ANACOMMON

Instances 1

Table 61 bull Fields in VCAP_RNG_TYPE_CFG

Field Name Bit Access Description DefaultVCAP_RNG_CFG 20 RW

0 Idle1 TCPUDP destination port is matched against range2 TCPUDP source port is matched against range3 TCPUDP source and destination ports are matched against range Match if either source or destination port is within range4 VID is matched against range (S1 VID in frame S2 classified VID)5 DSCP value is matched against range6 Reserved7 Reserved

Table 62 bull Fields in VCAP_RNG_VAL_CFG

Field Name Bit Access Description DefaultVCAP_RNG_MIN_VAL 3116 RW Lower value Value is included in range 0x0000

VCAP_RNG_MAX_VAL 150 RW Upper value Value is included in range 0x0000

Table 63 bull Fields in VRAP_CFG

Field Name Bit Access Description DefaultVRAP_VLAN_AWARE_ENA 12 RW If set VRAP frames must be single VLAN

tagged and the frames VID must match ANAVRAP_CFGVRAP_VID If cleared VRAP frames must be untagged

VRAP_VID 110 RW VID value for VRAP frames 0x000

Registers

21611 ANACOMMONVRAP_HDR_MASKParent ANACOMMON

Instances 1

21612 ANACOMMONDISCARD_CFGParent ANACOMMON

Instances 1

21613 ANACOMMONFID_CFGParent ANACOMMON

Instances 1

Table 64 bull Fields in VRAP_HDR_DATA

Field Name Bit Access Description DefaultVRAP_HDR_DATA 310 RW The frames VRAP header (4 bytes after

EPID) is matched against VRAP_HDR_DATA except for bits dont cared by VRAP_HDR_MASK

0x10000000

Table 65 bull Fields in VRAP_HDR_MASK

Field Name Bit Access Description DefaultVRAP_HDR_MASK 310 RW Bits set in VRAP_HDR_MASK dont care the

equivalent bits in VRAP_HDR_DATA0x07FFFFFF

Table 66 bull Fields in DISCARD_CFG

RESERVED 2 RW Must be set to its default 0x1

DROP_TAGGING_S2_ENA 1 RW Frames discarded due to wrong tagging will still allow S2 lookup

DROP_CTRLPROT_S2_ENA 0 RW Frames discarded with L2L3 protocol filter will still allow S2 lookup

Registers

217 ANAPOLParent ANA

Instances 384

General purpose policers selected by port configuration and ACL actions

2171 ANAPOLPOL_PIR_CFGParent ANAPOL

Instances 1

2172 ANAPOLPOL_CIR_CFGParent ANAPOL

Instances 1

Table 67 bull Fields in FID_CFG

Field Name Bit Access Description DefaultVID_MC_ENA 0 RW If set the frames classified VID is used

instead of the FID for multicast frames when hashing into the MAC table for the DMAC lookup The IS1 action FID_SEL can still overrule this setting The SMAC lookup is unchanged by this configuration

Table 68 bull Registers in POL

POL_PIR_CFG 0x00000000 1 Excess configuration Page 38

POL_CIR_CFG 0x00000004 1 Committed configuration Page 38

POL_MODE_CFG 0x00000008 1 Common configuration for this policer

POL_PIR_STATE 0x0000000C 1 Excess state of the policer Page 39

POL_CIR_STATE 0x00000010 1 Committed state of the policer Page 40

Table 69 bull Fields in POL_PIR_CFG

Field Name Bit Access Description DefaultPIR_RATE 206 RW Excess information rate (EIR) Unit is 33 13

kbps0x0000

PIR_BURST 50 RW Excess burst size (EBS) Maximum allowed value is 60 Unit is 4 kilobytes

Registers

2173 ANAPOLPOL_MODE_CFGParent ANAPOL

Instances 1

2174 ANAPOLPOL_PIR_STATEParent ANAPOL

Instances 1

Table 70 bull Fields in POL_CIR_CFG

Field Name Bit Access Description DefaultCIR_RATE 206 RW Committed information rate (CIR) Unit is 33

13 kbps0x0000

CIR_BURST 50 RW Committed burst size (CBS) Maximum allowed value is 60 Unit is 4 kilobytes

Table 71 bull Fields in POL_MODE_CFG

Field Name Bit Access Description DefaultIPG_SIZE 95 RW Size of interframe gap to add to each frame if

line rate policing is chosen in FRM_MODE0x14

FRM_MODE 43 RW Accounting mode of the policer0 Line rate Measure bytes in frames including IPG_SIZE1 Data rate Measure bytes in frames excluding IPG2 Frame rate Measure frames with rate unit = 33 13 frames per second and burst unit = 328 frames3 Frame rate Measure frames with rate unit = 13 frame per second burst unit = 03 frames

DLB_COUPLED 2 RW Coupling flag If enabled yellow frames are allowed to use CIR as well as EIR If disabled yellow frames are only allowed to use CIR0 Coupling is disabled1 Coupling is enabled

CIR_ENA 1 RW Enable dual leaky bucket mode If disabled the policer operates as a single leaky bucket policer governed by POL_PIR_CFG If enabled the policer operates as a dual leaky bucket policer governed by POL_PIR_CFG and POL_CIR_CFG

Registers

2175 ANAPOLPOL_CIR_STATEParent ANAPOL

Instances 1

218 ANAPOL_MISCParent ANA

Instances 1

2181 ANAPOL_MISCPOL_FLOWCParent ANAPOL_MISC

Instances 27

Table 72 bull Fields in POL_PIR_STATE

Field Name Bit Access Description DefaultPIR_LVL 210 RW Current fill level of the excess bucket Unit is

05 bits0x000000

Table 73 bull Fields in POL_CIR_STATE

Field Name Bit Access Description DefaultCIR_LVL 210 RW Current fill level of the committed bucket Unit

is 05 bits0x000000

Table 74 bull Registers in POL_MISC

POL_FLOWC 0x00000000 270x00000004

Flow control configuration per front port

POL_HYST 0x0000006C 1 Set flow control hysteresis Page 41

Table 75 bull Fields in POL_FLOWC

Field Name Bit Access Description DefaultPOL_FLOWC 0 RW Use MAC flow control for lowering ingress

rate0 Standard policing Frames are discarded when the rate is exceeded1 Flow control policing Policer instructs the MAC to issue pause frames when the rate is exceeded

Registers

2182 ANAPOL_MISCPOL_HYSTParent ANAPOL_MISC

Instances 1

22 DEV

221 DEVPORT_MODEParent DEV

Instances 1

Table 76 bull Fields in POL_HYST

Field Name Bit Access Description DefaultPOL_FC_HYST 94 RW Set hysteresis for when to re-open a bucket

after the burst capacity has been used Unit is 1 kilobytes This applies to policer in flow control mode (POL_FLOWC=1)

POL_DROP_HYST 30 RW Set hysteresis for when to re-open a bucket after the burst capacity has been used Unit is 2 kilobytes This applies to policer in drop mode (POL_FLOWC=0)

Table 77 bull Register Groups in DEV

PORT_MODE 0x00000000 1 Port configuration Page 41

MAC_CFG_STATUS 0x0000001C 1 MAC configuration and status Page 45

PCS1G_CFG_STATUS 0x00000048 1 PCS 1G Configuration Status Registers

PCS1G_TSTPAT_CFG_STATUS 0x0000008C 1 PCS1G Testpattern Configuration and Status Registers

PCS_FX100_CONFIGURATION 0x00000094 1 PCS FX100 Configuration Registers

PCS_FX100_STATUS 0x00000098 1 PCS FX100 Status Registers Page 62

Table 78 bull Registers in PORT_MODE

CLOCK_CFG 0x00000000 1 Clock and reset configuration Page 42

PORT_MISC 0x00000004 1 Forwarding configuration of special frame types

Registers

2211 DEVPORT_MODECLOCK_CFGParent DEVPORT_MODE

Instances 1

2212 DEVPORT_MODEPORT_MISCParent DEVPORT_MODE

Instances 1

EEE_CFG 0x0000000C 1 Control Energy Efficient Ethernet operation

RX_PATH_DELAY 0x00000010 1 Local path delay compensation per front port

TX_PATH_DELAY 0x00000014 1 Local path delay compensation per front port

PTP_PREDICT_CFG 0x00000018 1 PTP Predictor Configuration per port

Table 79 bull Fields in CLOCK_CFG

Field Name Bit Access Description DefaultMAC_TX_RST 7 RW Reset the MAC Tx clock domain 0x1

MAC_RX_RST 6 RW Reset the MAC Rx clock domain 0x1

PCS_TX_RST 5 RW Reset the PCS Tx clock domain 0x1

PCS_RX_RST 4 RW Reset the PCS Rx clock domain 0x1

PORT_RST 3 RW 0x1

LINK_SPEED 10 RW Selects the link speed0 No link1 10002500 Mbps2 100 Mbps3 10 Mbps

Table 80 bull Fields in PORT_MISC

Field Name Bit Access Description DefaultFWD_ERROR_ENA 4 RW Forward frames with errors signaled by the

MAC0x0

FWD_PAUSE_ENA 3 RW Forward pause frames (EtherType = 0x8808 opcode = 0x0001) The reaction to incoming pause frames is controlled independently of FWD_PAUSE_ENA

Table 78 bull Registers in PORT_MODE (continued)

Registers

2213 DEVPORT_MODEEEE_CFGParent DEVPORT_MODE

Instances 1

FWD_CTRL_ENA 2 RW Forward MAC control frames excluding pause frames (EtherType = 0x8808 opcode different from 0x0001)

Table 81 bull Fields in EEE_CFG

Field Name Bit Access Description DefaultEEE_ENA 22 RW Enable EEE operation on the port

A port enters the low power mode when no egress queues have data ready

The port is activated when one of the following conditions is true- A queue has been non-empty for EEE_TIMER_AGE- A queue has more than EEE_HIGH_FRAMES frames pending- A queue has more than EEE_HIGH_BYTES bytes pending- A queue is marked as a fast queue and has data pending

EEE_TIMER_AGE 2115 RW Maximum time frames in any queue must wait before the port is activated The default value corresponds to 48 us

Time = 4(EEE_TIMER_AGE16) (EEE_TIMER_AGE mod 16) microseconds

EEE_TIMER_WAKEUP 148 RW Time from the egress port is activated until frame transmission is restarted Default value corresponds to 16 usTime = 4(EEE_TIMER_WAKEUP16) (EEE_TIMER_WAKEUP mod 16) microseconds

EEE_TIMER_HOLDOFF 71 RW When all queues are empty the port is kept active until this time has passed Default value corresponds to 5 usTime = 4(EEE_TIMER_HOLDOFF16) (EEE_TIMER_HOLDOFF mod 16) microseconds

PORT_LPI 0 RO Status bit indicating whether port is in low-power-idle due to the LPI algorithm (EEE_CFG) If set transmissions are held back

Table 80 bull Fields in PORT_MISC (continued)

Registers

2214 DEVPORT_MODERX_PATH_DELAYParent DEVPORT_MODE

Instances 1

2215 DEVPORT_MODETX_PATH_DELAYParent DEVPORT_MODE

Instances 1

2216 DEVPORT_MODEPTP_PREDICT_CFGParent DEVPORT_MODE

Instances 1

Table 82 bull Fields in RX_PATH_DELAY

Field Name Bit Access Description DefaultRX_PATH_DELAY 230 RW Delay through the local system receive path

which is added to the frames receive timestamp The value is signedUnit Nanoseconds

0xFFFFD8

Table 83 bull Fields in TX_PATH_DELAY

Field Name Bit Access Description DefaultTX_PATH_DELAY 230 RW Delay through the local system transmit path

which is added to the frames transmit timestamp The value is signedUnit Nanoseconds

0x000028

Table 84 bull Fields in PTP_PREDICT_CFG

Field Name Bit Access Description DefaultPTP_PHY_PREDICT_CFG 114 RW Enables various informations from internal

phy when finding the right ingress delayTime in ns to add to timestamper in the egress direction to compensate for static delay through the physical encoding layers ffe1000 ffe100 rx_pkt nibbl40 nibb400 add_delay200xxxxxxx1 FFE1000 value will be addedxxxxxx1x FFE100 value will be added xxxxx1xx Rx_Pkt delay x8 will be addedxxxx1xxx 40 ns will be added if nibble_inserted is setxxx1xxxx 400 ns will be added if nibble inserted is setxx1xxxxx 200 ns will be added if add_delay200 is setx1xxxxxx Nibble inserted will be inverted1xxxxxxx RxPkt delay will be negated

Registers

222 DEVMAC_CFG_STATUSParent DEV

Instances 1

The 1G25G MAC module contains configuration and status registers related to the MAC module of the 1G and 25G ports

2221 DEVMAC_CFG_STATUSMAC_ENA_CFGParent DEVMAC_CFG_STATUS

Instances 1

PTP_PHASE_PREDICT_CFG 30 RW Enables increased accuracy in the time stamping logic by finding the dynamic phase between port and 1588 clocks This setting is used for both directions0001 125 MHz port clock0010 25 MHz port clock0011 25 MHz port clock0100 16113 MHz port clock0101 15625 MHz port clockothers Disabled

Table 85 bull Registers in MAC_CFG_STATUS

MAC_ENA_CFG 0x00000000 1 Mode Configuration Register Page 45

MAC_MODE_CFG 0x00000004 1 Mode Configuration Register Page 46

MAC_MAXLEN_CFG 0x00000008 1 Max Length Configuration Register

MAC_TAGS_CFG 0x0000000C 1 VLAN Service tag configuration register

MAC_ADV_CHK_CFG 0x00000010 1 Advanced Check Feature Configuration Register

MAC_IFG_CFG 0x00000014 1 Inter Frame Gap Configuration Register

MAC_HDX_CFG 0x00000018 1 Half-duplex Configuration Register

MAC_FC_MAC_LOW_CFG 0x00000020 1 MAC Flow Control Configuration Register

MAC_FC_MAC_HIGH_CFG 0x00000024 1 MAC Flow Control Configuration Register

MAC_STICKY 0x00000028 1 Sticky Bit Register Page 50

Table 84 bull Fields in PTP_PREDICT_CFG (continued)

Registers

2222 DEVMAC_CFG_STATUSMAC_MODE_CFGParent DEVMAC_CFG_STATUS

Instances 1

2223 DEVMAC_CFG_STATUSMAC_MAXLEN_CFGParent DEVMAC_CFG_STATUS

Instances 1

2224 DEVMAC_CFG_STATUSMAC_TAGS_CFGParent DEVMAC_CFG_STATUS

Instances 1

The MAC can be configured to accept 0 1 and 2 tags and the TAG value can be user-defined

Table 86 bull Fields in MAC_ENA_CFG

Field Name Bit Access Description DefaultRX_ENA 4 RW Receiver Module Enable

0 Receiver Module Disabled1 Receiver Module Enabled

TX_ENA 0 RW Transmitter Module Enable0 Transmitter Module Disabled1 Transmitter Module Enabled

Table 87 bull Fields in MAC_MODE_CFG

Field Name Bit Access Description DefaultGIGA_MODE_ENA 4 RW Enables 1 Gbps mode

0 10100 Mbps mode1 1 Gbps mode Note FDX_ENA must also be set

FDX_ENA 0 RW Enables full-duplex0 Half-duplex1 Full-duplex

Note Full-duplex MUST be selected if GIGA_MODE is enabled

Table 88 bull Fields in MAC_MAXLEN_CFG

Field Name Bit Access Description DefaultMAX_LEN 150 RW Maximum frame length in bytes accepted by

the MAC Frames that are longer than the maximum length are discarded

0x05EE

Registers

2225 DEVMAC_CFG_STATUSMAC_ADV_CHK_CFGParent DEVMAC_CFG_STATUS

Instances 1

Table 89 bull Fields in MAC_TAGS_CFG

Field Name Bit Access Description DefaultTAG_ID 3116 RW This field defines which EtherTypes are

recognized as a VLAN TPID - besides 0x8100 The value is used for all tag positions Ie a double tagged frame can have the following tag values(TAG1TAG2)( 0x8100 0x8100 )( 0x8100 TAG_ID )( TAG_ID 0x8100 ) or( TAG_ID TAG_ID )

Single tagged frame can have the following TPID values 0x8100 or TAG_ID

0x8100

VLAN_LEN_AWR_ENA 2 RW When set single tagged frames are allowed to be 4 bytes longer than the MAC_MAXLEN_CFG configuration and double tagged frames are allowed to be 8 bytes longer Single tagged frames are adjusted if VLAN_AWR_ENA is also set Double tagged frames are adjusted if both VLAN_AWR_ENA and VLAN_DBL_AWR_ENA are set

VLAN_DBL_AWR_ENA 1 RW If set double tagged frames are subject to length adjustments (VLAN_LEN_AWR_ENA) VLAN_AWR_ENA must be set when VLAN_DBL_AWR_ENA is set0 The MAC does not look for inner tags1 The MAC accepts inner tags with TPID=0x8100 or TAG_ID

VLAN_AWR_ENA 0 RW If set single tagged frames are subject to length adjustments (VLAN_LEN_AWR_ENA)0 The MAC does not look for any tags1 The MAC accepts outer tags with TPID=0x8100 or TAG_ID

Registers

2226 DEVMAC_CFG_STATUSMAC_IFG_CFGParent DEVMAC_CFG_STATUS

Instances 1

2227 DEVMAC_CFG_STATUSMAC_HDX_CFGParent DEVMAC_CFG_STATUS

Instances 1

Table 90 bull Fields in MAC_ADV_CHK_CFG

Field Name Bit Access Description DefaultLEN_DROP_ENA 0 RW Length Drop Enable

Configures the Receive Module to drop frames in reference to in-range and out-of-range errors0 Length Drop Disabled1 Length Drop Enabled

Table 91 bull Fields in MAC_IFG_CFG

Field Name Bit Access Description DefaultTX_IFG 128 RW Used to adjust the duration of the inter-frame

gap in the Tx direction and must be set according to the speed and duplex settings10100 Mbps HDX FDX 0x19 0x131000 Mbps 0x07

RX_IFG2 74 RW Used to adjust the duration of the second part of the inter-frame gap in the Rx direction and must be set according to the speed and duplex settings10100 Mbps HDX FDX 0x8 0xB1000 Mbps 0x1

RX_IFG1 30 RW Used to adjust the duration of the first part of the inter-frame gap in the Rx direction and must be set according to the speed settings10100 Mbps 0x71000 Mbps 0x5

Table 92 bull Fields in MAC_HDX_CFG

Field Name Bit Access Description DefaultWEXC_DIS 24 RW Determines whether the MAC backs off after

an excessive collision has occurred If set back off is disabled after excessive collisions0 Back off after excessive collisions1 Dont back off after excessive collisions

Registers

2228 DEVMAC_CFG_STATUSMAC_FC_MAC_LOW_CFGParent DEVMAC_CFG_STATUS

Instances 1

2229 DEVMAC_CFG_STATUSMAC_FC_MAC_HIGH_CFGParent DEVMAC_CFG_STATUS

Instances 1

SEED 2316 RW Seed value loaded into the PRBS of the MACUsed to prevent excessive collision events

SEED_LOAD 12 RW Load SEED value into PRNG register A SEED value is loaded into the PRNG register of the MAC when SEED_LOAD is asserted After a load the SEED_LOAD must be deasserted0 Do not load SEED value1 Load SEED value

RETRY_AFTER_EXC_COL_ENA 8 RW This bit is used to setup the MAC to retransmit a frame after an early collision even though 16 (or more) early collisions have occurred0 A frame is discarded and counted as an excessive collision if 16 collisions occur for this frame1 The MAC retransmits a frame after an early collision regardless of the number of previous early collisions The backoff sequence is reset after every 16 collisions

LATE_COL_POS 60 RW Adjustment of earlylate collision boundaryThis bitgroup is used to adjust the MAC so that a collision on a shared transmission medium before bit 512 is handled as an early collision whereas a collision after bit 512 is handled as a late collision ie no retransmission is performed

Table 93 bull Fields in MAC_FC_MAC_LOW_CFG

Field Name Bit Access Description DefaultMAC_LOW 230 RW Lower three bytes in the SMAC in generated

flow control frames

0xNNN Lower three DMAC bytes

0x000000

Table 92 bull Fields in MAC_HDX_CFG (continued)

Registers

22210 DEVMAC_CFG_STATUSMAC_STICKYParent DEVMAC_CFG_STATUS

Instances 1

Clear the sticky bits by writing a 0 in the relevant bitgroups (writing a 1 sets the bit)

Table 94 bull Fields in MAC_FC_MAC_HIGH_CFG

Field Name Bit Access Description DefaultMAC_HIGH 230 RW Higher three bytes in the SMAC in generated

flow control frames0xNNN Higher three DMAC bytes

0x000000

Table 95 bull Fields in MAC_STICKY

Field Name Bit Access Description DefaultRX_IPG_SHRINK_STICKY 9 Sticky Sticky bit indicating that an inter packet gap

shrink was detected (IPG lt 12 bytes)0x0

RX_PREAM_SHRINK_STICKY 8 Sticky Sticky bit indicating that a preamble shrink was detected (preamble lt 8 bytes)0 no preamble shrink was detected1 a preamble shrink was detected one or more timesBit is cleared by writing a 1 to this position

RX_CARRIER_EXT_STICKY 7 Sticky Sticky bit indicating that a carrier extend was detected0 no carrier extend was detected1 one or more carrier extends were detectedBit is cleared by writing a 1 to this position

RX_CARRIER_EXT_ERR_STICKY

6 Sticky Sticky bit indicating that a carrier extend error was detected0 no carrier extend error was detected1 one or more carrier extend errors were detectedBit is cleared by writing a 1 to this position

RX_JUNK_STICKY 5 Sticky Sticky bit indicating that junk was received (bytes not recognized as a frame)0 no junk was received1 junk was received one or more timesBit is cleared by writing a 1 to this position

TX_RETRANSMIT_STICKY 4 Sticky Sticky bit indicating that the transmit MAC asked the host for a frame retransmission0 no tx retransmission was initiated1 one or more tx retransmissions were initiatedBit is cleared by writing a 1 to this position

Registers

223 DEVPCS1G_CFG_STATUSParent DEV

Instances 1

Configuration and status register set for PCS1G

TX_JAM_STICKY 3 Sticky Sticky bit indicating that the transmit host issued a jamming signal0 the transmit host issued no jamming signal1 the transmit host issued one or more jamming signalsBit is cleared by writing a 1 to this position

TX_FIFO_OFLW_STICKY 2 Sticky Sticky bit indicating that the MAC transmit FIFO has overrun

TX_FRM_LEN_OVR_STICKY 1 Sticky Sticky bit indicating that the transmit frame length has overrun Ie a frame longer than 64K occurred0 no tx frame length error occurred1 one or more tx frames length errors occurredBit is cleared by writing a 1 to this position

TX_ABORT_STICKY 0 Sticky Sticky bit indicating that the transmit host initiated abort was executed

Table 96 bull Registers in PCS1G_CFG_STATUS

PCS1G_CFG 0x00000000 1 PCS1G Configuration Page 52

PCS1G_MODE_CFG 0x00000004 1 PCS1G Mode Configuration Page 52

PCS1G_SD_CFG 0x00000008 1 PCS1G Signal Detect Configuration

PCS1G_ANEG_CFG 0x0000000C 1 PCS1G Aneg Configuration Page 53

PCS1G_ANEG_NP_CFG 0x00000010 1 PCS1G Aneg Next Page Configuration

PCS1G_LB_CFG 0x00000014 1 PCS1G Loopback Configuration

PCS1G_ANEG_STATUS 0x00000020 1 PCS1G ANEG Status Register Page 54

PCS1G_ANEG_NP_STATUS 0x00000024 1 PCS1G Aneg Next Page Status Register

PCS1G_LINK_STATUS 0x00000028 1 PCS1G link status Page 55

PCS1G_LINK_DOWN_CNT 0x0000002C 1 PCS1G link down counter Page 56

PCS1G_STICKY 0x00000030 1 PCS1G sticky register Page 56

PCS1G_DEBUG_STATUS 0x00000034 1 PCS1G debug status Page 57

Table 95 bull Fields in MAC_STICKY (continued)

Registers

2231 DEVPCS1G_CFG_STATUSPCS1G_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G main configuration register

2232 DEVPCS1G_CFG_STATUSPCS1G_MODE_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G mode configuration

PCS1G_LPI_CFG 0x00000038 1 PCS1G Low Power Idle Configuration

PCS1G_LPI_WAKE_ERROR_CNT

0x0000003C 1 PCS1G wake error counter Page 58

PCS1G_LPI_STATUS 0x00000040 1 PCS1G Low Power Idle Status Page 58

Table 97 bull Fields in PCS1G_CFG

Field Name Bit Access Description DefaultLINK_STATUS_TYPE 4 RW Set type of link_status indication at CPU-

System0 Sync_status (from PCS synchronization state machine)1 Bit 15 of PCS1G_ANEG_STATUSlp_adv_ability (Link updown)

PCS_ENA 0 RW PCS enable0 Disable PCS1 Enable PCS

Table 98 bull Fields in PCS1G_MODE_CFG

Field Name Bit Access Description DefaultUNIDIR_MODE_ENA 4 RW Unidirectional mode enable Implementation

of 8023 Clause 66 When asserted this enables MAC to transmit data independent of the state of the receive link0 Unidirectional mode disabled1 Unidirectional mode enabled

SGMII_MODE_ENA 0 RW Selection of PCS operation0 PCS is used in SERDES mode1 PCS is used in SGMII mode

Table 96 bull Registers in PCS1G_CFG_STATUS (continued)

Registers

2233 DEVPCS1G_CFG_STATUSPCS1G_SD_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G signal_detect configuration

2234 DEVPCS1G_CFG_STATUSPCS1G_ANEG_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G Auto-negotiation configuration register

Table 99 bull Fields in PCS1G_SD_CFG

Field Name Bit Access Description DefaultSD_SEL 8 RW Signal detect selection (select input for

internal signal_detect line)0 Select signal_detect line from hardmacro1 Select external signal_detect line

SD_POL 4 RW Signal detect polarity The signal level on signal_detect input pin must be equal to SD_POL to indicate signal detection (SD_ENA must be set)0 Signal Detect input pin must be 0 to indicate a signal detection1 Signal Detect input pin must be 1 to indicate a signal detection

SD_ENA 0 RW Signal Detect Enable0 The Signal Detect input pin is ignored The PCS assumes an active Signal Detect at all times1 The Signal Detect input pin is used to determine if a signal is detected

Table 100 bull Fields in PCS1G_ANEG_CFG

Field Name Bit Access Description DefaultADV_ABILITY 3116 RW Advertised Ability Register Holds the

capabilities of the device as described IEEE 8023 Clause 37

0x0000

SW_RESOLVE_ENA 8 RW Software Resolve Abilities0 If Auto Negotiation fails (no matching HD or FD capabilities) the link is disabled1 The result of an Auto Negotiation is ignored - the link can be setup through software This bit must be set in SGMII mode

ANEG_RESTART_ONE_SHOT 1 One-shot Auto Negotiation Restart0 No action1 Restart Auto Negotiation

Registers

2235 DEVPCS1G_CFG_STATUSPCS1G_ANEG_NP_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G Auto-negotiation configuration register for next-page function

2236 DEVPCS1G_CFG_STATUSPCS1G_LB_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G loopback configuration register

2237 DEVPCS1G_CFG_STATUSPCS1G_ANEG_STATUSParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G Auto-negotiation status register

ANEG_ENA 0 RW Auto Negotiation Enable0 Auto Negotiation Disabled1 Auto Negotiation Enabled

Table 101 bull Fields in PCS1G_ANEG_NP_CFG

Field Name Bit Access Description DefaultNP_TX 3116 RW Next page register Holds the next-page

information as described in IEEE 8023 Clause 37

0x0000

NP_LOADED_ONE_SHOT 0 One-shot Next page loaded0 next page is free and can be loaded1 next page register has been filled (to be set after np_tx has been filled)

Table 102 bull Fields in PCS1G_LB_CFG

Field Name Bit Access Description DefaultTBI_HOST_LB_ENA 0 RW Loops data in PCS (TBI side) from egress

direction to ingress direction The Rx clock is automatically set equal to the Tx clock0 TBI Loopback Disabled1TBI Loopback Enabled

Table 103 bull Fields in PCS1G_ANEG_STATUS

Field Name Bit Access Description DefaultLP_ADV_ABILITY 3116 RO Advertised abilities from link partner as

described in IEEE 8023 Clause 370x0000

Table 100 bull Fields in PCS1G_ANEG_CFG (continued)

Registers

2238 DEVPCS1G_CFG_STATUSPCS1G_ANEG_NP_STATUSParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G Auto-negotiation next page status register

2239 DEVPCS1G_CFG_STATUSPCS1G_LINK_STATUSParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G link status register

PR 4 RO Resolve priority0 ANEG is in progress1 ANEG nearly finished - priority can be resolved (through software)

PAGE_RX_STICKY 3 Sticky Status indicating whether a new page has been received0 No new page received1 New page receivedBit is cleared by writing a 1 to this position

ANEG_COMPLETE 0 RO Auto Negotiation Complete0 No Auto Negotiation has been completed1 Indicates that an Auto Negotiation has completed successfully

Table 104 bull Fields in PCS1G_ANEG_NP_STATUS

Field Name Bit Access Description DefaultLP_NP_RX 3116 RO Next page ability register from link partner as

Table 105 bull Fields in PCS1G_LINK_STATUS

Field Name Bit Access Description DefaultDELAY_VAR 1512 RO Additional delay in rx-path multiply the value

of this field by the line-rate bit-period (800ps for 101001000 320ps for 2G5 mode) This field is valid when the link is up it remains constant for as long as the link is up value may change on link-down eventThis field shows the number of data bits that is stored in the rx comma-alignment block values of 0-9 is possible

Table 103 bull Fields in PCS1G_ANEG_STATUS (continued)

Registers

22310 DEVPCS1G_CFG_STATUSPCS1G_LINK_DOWN_CNTParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G link down counter register

22311 DEVPCS1G_CFG_STATUSPCS1G_STICKYParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G status register for sticky bits

SIGNAL_DETECT 8 RO Indicates whether or not the selected Signal Detect input line is asserted does not consider the Polarity0 No signal detected1 Signal detected

LINK_STATUS 4 RO Indicates whether the link is up or down A link is up when ANEG state machine is in state LINK_OK or AN_DISABLE_LINK_OK0 Link down1 Link up

SYNC_STATUS 0 RO Indicates if PCS has successfully synchronized0 PCS is out of sync1 PCS has synchronized

Table 106 bull Fields in PCS1G_LINK_DOWN_CNT

Field Name Bit Access Description DefaultLINK_DOWN_CNT 70 RW Link Down Counter A counter that counts the

number of times a link has been down The counter does not saturate at 255 and is only cleared when writing 0 to the register

Table 105 bull Fields in PCS1G_LINK_STATUS (continued)

Registers

22312 DEVPCS1G_CFG_STATUSPCS1G_DEBUG_STATUSParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G debug status register

22313 DEVPCS1G_CFG_STATUSPCS1G_LPI_CFGParent DEVPCS1G_CFG_STATUS

Instances 1

Configuration register for Low Power Idle (Energy Efficient Ethernet)

Table 107 bull Fields in PCS1G_STICKY

Field Name Bit Access Description DefaultLINK_DOWN_STICKY 4 Sticky The sticky bit is set when the link has been

down - ie if the ANEG state machine has not been in the AN_DISABLE_LINK_OK or LINK_OK state for one or more clock cycles This occurs if eg ANEG is restarted or for example if signal-detect or synchronization has been lost for more than 10 ms (16 ms in SGMII mode) By setting the UDLT bit the required down time can be reduced to 977 us (156 us)0 Link is up1 Link has been downBit is cleared by writing a 1 to this position

OUT_OF_SYNC_STICKY 0 Sticky Sticky bit indicating if PCS synchronization has been lost0 Synchronization has not been lost at any time1 Synchronization has been lost for one or more clock cyclesBit is cleared by writing a 1 to this position

Table 108 bull Fields in PCS1G_DEBUG_STATUS

Field Name Bit Access Description DefaultXMIT_MODE 1312 RO Indicates the mode of the TBI

00 Idle mode01 Configuration mode10 Reserved11 Data mode

Registers

22314 DEVPCS1G_CFG_STATUSPCS1G_LPI_WAKE_ERROR_CNTParent DEVPCS1G_CFG_STATUS

Instances 1

PCS1G Low Power Idle wake error counter (Energy Efficient Ethernet)

22315 DEVPCS1G_CFG_STATUSPCS1G_LPI_STATUSParent DEVPCS1G_CFG_STATUS

Instances 1

Status register for Low Power Idle (Energy Efficient Ethernet)

Table 109 bull Fields in PCS1G_LPI_CFG

Field Name Bit Access Description DefaultQSGMII_MS_SEL 20 RW QSGMII masterslave selection (only one

master allowed per QSGMII) The master drives LPI timing on serdes0 Slave1 Master

LPI_RX_WTIM 54 RW Max wake-up time before link_fail00 10 us01 13 us10 17 us11 20 us

TX_ASSERT_LPIDLE 0 RW Assert Low-Power Idle (LPI) in transmit mode0 Disable LPI transmission1 Enable LPI transmission

Table 110 bull Fields in PCS1G_LPI_WAKE_ERROR_CNT

Field Name Bit Access Description DefaultWAKE_ERROR_CNT 150 RW Wake Error Counter A counter that is

incremented when the link partner does not send wake-up burst in due time The counter saturates at 65535 and is cleared when writing 0 to the register

0x0000

Table 111 bull Fields in PCS1G_LPI_STATUS

Field Name Bit Access Description DefaultRX_LPI_FAIL 16 RO Receiver has failed to recover from Low-

Power Idle mode0 No failure1 Failed to recover from LPI mode

RX_LPI_EVENT_STICKY 12 Sticky Receiver Low-Power idle occurrence0 No LPI symbols received1 Receiver has received LPI symbolsBit is cleared by writing a 1 to this position

Registers

224 DEVPCS1G_TSTPAT_CFG_STATUSParent DEV

Instances 1

PCS1G testpattern configuration and status register set

2241 DEVPCS1G_TSTPAT_CFG_STATUSPCS1G_TSTPAT_MODE_CFGParent DEVPCS1G_TSTPAT_CFG_STATUS

Instances 1

PCS1G testpattern mode configuration register (Frame based pattern 4 and 5 might be not available depending on chip type)

RX_QUIET 9 RO Receiver Low-Power Quiet mode0 Receiver not in quiet mode1 Receiver is in quiet mode

RX_LPI_MODE 8 RO Receiver Low-Power Idle mode0 Receiver not in low power idle mode1 Receiver is in low power idle mode

TX_LPI_EVENT_STICKY 4 Sticky Transmitter Low-Power idle occurrence0 No LPI symbols transmitted1 Transmitter has transmitted LPI symbolsBit is cleared by writing a 1 to this position

TX_QUIET 1 RO Transmitter Low-Power Quiet mode0 Transmitter not in quiet mode1 Transmitter is in quiet mode

TX_LPI_MODE 0 RO Transmitter Low-Power Idle mode0 Transmitter not in low power idle mode1 Transmitter is in low power idle mode

Table 112 bull Registers in PCS1G_TSTPAT_CFG_STATUS

PCS1G_TSTPAT_MODE_CFG 0x00000000 1 PCS1G TSTPAT MODE CFG Page 59

PCS1G_TSTPAT_STATUS 0x00000004 1 PCS1G TSTPAT STATUS Page 60

Table 111 bull Fields in PCS1G_LPI_STATUS (continued)

Registers

2242 DEVPCS1G_TSTPAT_CFG_STATUSPCS1G_TSTPAT_STATUSParent DEVPCS1G_TSTPAT_CFG_STATUS

Instances 1

PCS1G testpattern status register

225 DEVPCS_FX100_CONFIGURATIONParent DEV

Instances 1

Configuration register set for PCS 100Base-FX logic

Table 113 bull Fields in PCS1G_TSTPAT_MODE_CFG

Field Name Bit Access Description DefaultJTP_SEL 20 RW Jitter Test Pattern Select Enables and

selects the jitter test pattern to be transmitted The jitter test patterns are according to the IEEE 8023 Annex 36A0 Disable transmission of test patterns1 High frequency test pattern - repeated transmission of D215 code group2 Low frequency test pattern - repeated transmission of K287 code group3 Mixed frequency test pattern - repeated transmission of K285 code group4 Long continuous random test pattern (packet length is 1524 bytes)5 Short continuous random test pattern (packet length is 360 bytes)

Table 114 bull Fields in PCS1G_TSTPAT_STATUS

Field Name Bit Access Description DefaultJTP_ERR_CNT 158 RW Jitter Test Pattern Error Counter Due to re-

sync measures it might happen that single errors are not counted (applies for 25gpbs mode) The counter saturates at 255 and is only cleared when writing 0 to the register

JTP_ERR 4 RO Jitter Test Pattern Error0 Jitter pattern checker has found no error1 Jitter pattern checker has found an error

JTP_LOCK 0 RO Jitter Test Pattern Lock0 Jitter pattern checker has not locked1 Jitter pattern checker has locked

Registers

2251 DEVPCS_FX100_CONFIGURATIONPCS_FX100_CFGParent DEVPCS_FX100_CONFIGURATION

Instances 1

Configuration bit groups for 100Base-FX PCS

Table 115 bull Registers in PCS_FX100_CONFIGURATION

PCS_FX100_CFG 0x00000000 1 PCS 100Base FX Configuration

Table 116 bull Fields in PCS_FX100_CFG

SD_POL 25 RW Signal detect polarity The signal level on signal_detect input pin must be equal to SD_POL to indicate signal detection (SD_ENA must be set) Use 1 when SD_SEL is set to hardmacro0 Signal Detect input pin must be 0 to indicate a signal detection1 Signal Detect input pin must be 1 to indicate a signal detection

LINKHYSTTIMER 74 RW Link hysteresis timer configuration The hysteresis time lasts [linkhysttimer] 65536 ns + 2320 ns If linkhysttime is set to 5 the hysteresis lasts the minimum time of 330 us as specified in IEEE 8023 - 24334

UNIDIR_MODE_ENA 3 RW Unidirectional mode enable Implementation 0f 8023 clause 66 When asserted this enables MAC to transmit data independent of the state of the receive link0 Unidirectional mode disabled1 Unidirectional mode enabled

FEFCHK_ENA 2 RW Far-End Fault (FEF) detection enable0 Disable FEF detection1 Enable FEF detection

Registers

226 DEVPCS_FX100_STATUSParent DEV

Instances 1

Status register set for PCS 100Base-FX logic

2261 DEVPCS_FX100_STATUSPCS_FX100_STATUSParent DEVPCS_FX100_STATUS

Instances 1

Status bit groups for 100Base-FX PCS Note If sigdet_cfg = 00 is selected status signal signal_detect shows the internal signal_detect value is gated with the status of rx toggle-rate control circuitry

FEFGEN_ENA 1 RW Far-End Fault (FEF) generation enable0 Disable FEF generation1 Enable FEF generation

Table 117 bull Registers in PCS_FX100_STATUS

PCS_FX100_STATUS 0x00000000 1 PCS 100Base FX Status Page 62

Table 118 bull Fields in PCS_FX100_STATUS

Field Name Bit Access Description DefaultEDGE_POS_PTP 118 RO Data change position in the 10bit words

received Must be used for adjusting PTP ingress delays

PCS_ERROR_STICKY 7 Sticky PCS error has occurred1 RX_ER was high while RX_DV active0 No RX_ER indication found while RX_DV activeBit is cleared by writing a 1 to this position

FEF_FOUND_STICKY 6 Sticky Far-end Fault state has occurred1 A Far-End Fault has been detected0 No Far-End Fault occurredBit is cleared by writing a 1 to this position

SSD_ERROR_STICKY 5 Sticky Stream Start Delimiter error occurred1 A Start-of-Stream Delimiter error has been detected0 No SSD error occurredBit is cleared by writing a 1 to this position

Table 116 bull Fields in PCS_FX100_CFG (continued)

Registers

23 DEVCPU_GCB

231 DEVCPU_GCBCHIP_REGSParent DEVCPU_GCB

Instances 1

SYNC_LOST_STICKY 4 Sticky Synchronization lost1 Synchronization lost0 No sync lost occurredBit is cleared by writing a 1 to this position

FEF_STATUS 2 RO Current status of Far-end Fault detection state1 Link currently in fault state0 Link is in normal state

SIGNAL_DETECT 1 RO Current status of selected signal_detect input line1 Proper signal detected0 No proper signal found

SYNC_STATUS 0 RO Status of synchronization1 Link established0 No link found

Table 119 bull Register Groups in DEVCPU_GCB

CHIP_REGS 0x00000000 1 Page 63

VCORE_ACCESS 0x00000020 1 Registers for accessing the VCore

GPIO 0x00000034 1 Page 69

MIIM 0x0000009C 20x00000024

MIIM_READ_SCAN 0x000000E4 1 Page 77

MIIM_SLAVE 0x000000EC 1 Page 78

PHY 0x000000F0 1 PHY configuration and status registers

SIO_CTRL 0x000000F8 1 Serial IO control configuration Page 79

FAN_CTRL 0x00000204 1 Fan controller configuration and status

MEMITGR 0x00000210 1 Memory integrity monitor Page 88

VRAP 0x00000228 1 VRAP controller Page 92

Table 118 bull Fields in PCS_FX100_STATUS (continued)

Registers

2311 DEVCPU_GCBCHIP_REGSCHIP_IDParent DEVCPU_GCBCHIP_REGS

Instances 1

2312 DEVCPU_GCBCHIP_REGSGPRParent DEVCPU_GCBCHIP_REGS

Instances 1

2313 DEVCPU_GCBCHIP_REGSSOFT_RSTParent DEVCPU_GCBCHIP_REGS

Instances 1

Table 120 bull Registers in CHIP_REGS

CHIP_ID 0x00000000 1 Chip ID register Page 64

GPR 0x00000004 1 General purpose register Page 64

SOFT_RST 0x00000008 1 Reset control register Page 64

HW_STAT 0x00000010 1 Various status indications Page 65

Table 121 bull Fields in CHIP_ID

Field Name Bit Access Description DefaultREV_ID 3128 RO Revision ID Chip revision starting from 0 0x0

PART_ID 2712 RO Part ID Part ID for identification of Microsemi Chips contents of this field is updated when reset is released

0x7511

MFG_ID 111 RO Manufacturer ID 0x074

ONE 0 RO Always 1 0x1

Table 122 bull Fields in GPR

Field Name Bit Access Description DefaultGPR 310 RW General purpose register for software

development0x00000000

Registers

2314 DEVCPU_GCBCHIP_REGSHW_STATParent DEVCPU_GCBCHIP_REGS

Instances 1

232 DEVCPU_GCBVCORE_ACCESSParent DEVCPU_GCB

Instances 1

Table 123 bull Fields in SOFT_RST

Field Name Bit Access Description DefaultSOFT_SWC_RST 1 RW Set this field to reset the switch core

(everything except the SERDES IO and PLL blocks) This field is automatically cleared by the resetNote It is possible for the VCore to protect itself from this soft-reset for more info see ICPU_CFGRESETCORE_RST_PROTECT inside the VCore register space

SOFT_CHIP_RST 0 RW Set this field to reset the whole chip This field is automatically cleared by the resetNote It is possible for the VCore to protect itself from this soft-reset for more info see ICPU_CFGRESETCORE_RST_PROTECT inside the VCore register space

Table 124 bull Fields in HW_STAT

Field Name Bit Access Description DefaultPLL0_CONF 31 RO PLL_CONF strapping value from GPIOs

sampled after reset release0x0

MEM_FAIL 0 RO This field is set if a hardware fail has been detected in any of the memories during startup-initialization of the chip This field is valid after release of reset

Table 125 bull Registers in VCORE_ACCESS

VA_CTRL 0x00000000 1 Control register for VCore accesses

VA_ADDR 0x00000004 1 Address register for VCore accesses

VA_DATA 0x00000008 1 Data register for VCore accesses

Registers

2321 DEVCPU_GCBVCORE_ACCESSVA_CTRLParent DEVCPU_GCBVCORE_ACCESS

Instances 1

2322 DEVCPU_GCBVCORE_ACCESSVA_ADDRParent DEVCPU_GCBVCORE_ACCESS

Instances 1

VA_DATA_INCR 0x0000000C 1 Data register for VCore accesses (w auto increment of address)

VA_DATA_INERT 0x00000010 1 Data register for VCore accesses (will not initiate access)

Table 126 bull Fields in VA_CTRL

Field Name Bit Access Description DefaultVA_ERR 32 RO If the VCore access logic detects an error this

field is set based on the nature of the error This is a read-only field which is cleared by the VCore access logic when a new access is (sucessfully) accepted0 No errors detected1 SBA not ready when accessed2 SBA reported error3 DATA or ADDR written during active access

VA_BUSY_RD 1 RO This field is set to the value of VA_CTRLVA_BUSY whenever one of the data registers VA_DATA VA_DATA_INCR or VA_DATA_INERT is read By examining this field it is possible to determine if VA_BUSY was set at the time a read from one of these registers was performed

VA_BUSY 0 RO This field is set by hardware when an access into VCore domain is started and cleared when the access is done

Table 125 bull Registers in VCORE_ACCESS (continued)

Registers

2323 DEVCPU_GCBVCORE_ACCESSVA_DATAParent DEVCPU_GCBVCORE_ACCESS

Instances 1

The VA_DATA VA_DATA_INCR and VA_DATA_INERT registers are used for indirect access into the VCore domain The functionality of the VA_DATA_INCR and VA_DATA_INERT registers are similar to this register - but with minor exceptions These exceptions are fleshed out in the description of the respective registers

Table 127 bull Fields in VA_ADDR

Field Name Bit Access Description DefaultVA_ADDR 310 RW The address to access in the VCore domain

all addresses must be 32-bit alligned (ie the two least significant bit must always be 0)When accesses are initiated using the VA_DATA_INCR register then this field is autoincremented by 4 at the end of the transferThe memory region of the VCore that maps to switch-core registers may not be accessed by using these registers

0x00000000

Registers

2324 DEVCPU_GCBVCORE_ACCESSVA_DATA_INCRParent DEVCPU_GCBVCORE_ACCESS

Instances 1

2325 DEVCPU_GCBVCORE_ACCESSVA_DATA_INERTParent DEVCPU_GCBVCORE_ACCESS

Table 128 bull Fields in VA_DATA

Field Name Bit Access Description DefaultVA_DATA 310 RW Reading or writing fromto this field initiates

accesses into the VCore domain While an access is ongoing (VA_CTRLVA_BUSY is set) this field may not be written It is possible to read this field while an access is ongoing but the data returned will be 0x80000000When writing to this field a write into the VCore domain is initiated to the address specified in the VA_ADDR register with the data that was written to this field Only 32-bit writes are supported This field may not be written to until the VA_CTRLVA_BUSY indicates that no accesses is ongoingWhen reading from this field a read from the VCore domain is initiated from the address specified in the VA_ADDR register Important The data that is returned from reading this field (and stating an access) is not the result of the newly initiated read instead the data from the last access is returned The result of the newly initiated read access will be ready once the VA_CTRLVA_BUSY field shows that the access is doneNote When the result of a read-access is read from this field (the second read) a new access will automatically be intiated This is desirable when reading a series of addresses from VCore domain If a new access is not desirable then the result should be read from the VA_DATA_INERT register instead of this field

0x00000000

Table 129 bull Fields in VA_DATA_INCR

Field Name Bit Access Description DefaultVA_DATA_INCR 310 RW This field behaves in the same way as

VA_DATA Except when an access is initiated by using this field (either read or write) the address register (VA_ADDR) is automatically incremented by 4 at the end of the access ie when VA_CTRLVA_BUSY is deasserted

0x00000000

Registers

Instances 1

233 DEVCPU_GCBGPIOParent DEVCPU_GCB

Instances 1

General Purpose IO Control configuration and status registers

Each register in this group contains one field with one bit per GPIO pin Bit 0 in each field correponds to GPIO0 bit 1 to GPIO1 and so on

2331 DEVCPU_GCBGPIOGPIO_OUT_SETParent DEVCPU_GCBGPIO

Instances 1

Table 130 bull Fields in VA_DATA_INERT

Field Name Bit Access Description DefaultVA_DATA_INERT 310 RW This field behaves in the same way as

VA_DATA Except accesses (read or write) does not initiate VCore accesses Writing to this register just overwrites the value currently held by all of the data registers (VA_DATA VA_DATA_INCR and VA_DATA_INERT)

0x00000000

Table 131 bull Registers in GPIO

GPIO_OUT_SET 0x00000000 1 GPIO output set Page 69

GPIO_OUT_CLR 0x00000004 1 GPIO output clear Page 70

GPIO_OUT 0x00000008 1 GPIO output Page 70

GPIO_IN 0x0000000C 1 GPIO input Page 70

GPIO_OE 0x00000010 1 GPIO pin direction Page 71

GPIO_INTR 0x00000014 1 GPIO interrupt Page 71

GPIO_INTR_ENA 0x00000018 1 GPIO interrupt enable Page 71

GPIO_INTR_IDENT 0x0000001C 1 GPIO interrupt identity Page 71

GPIO_ALT 0x00000020 20x00000004

GPIO alternate functions Page 72

GPIO_SD_MAP 0x00000028 160x00000004

GPIO Signal Detect Mapping Page 72

Registers

2332 DEVCPU_GCBGPIOGPIO_OUT_CLRParent DEVCPU_GCBGPIO

Instances 1

2333 DEVCPU_GCBGPIOGPIO_OUTParent DEVCPU_GCBGPIO

Instances 1

In a multi-threaded software environment using the registers GPIO_OUT_SET and GPIO_OUT_CLR for modifying GPIO values removes the need for software-locked access

2334 DEVCPU_GCBGPIOGPIO_INParent DEVCPU_GCBGPIO

Instances 1

Table 132 bull Fields in GPIO_OUT_SET

Field Name Bit Access Description DefaultG_OUT_SET 210 One-shot Setting a bit in this field will immediately set

the corresponding bit in GPIO_OUTG_OUT Reading this register always return 00 No change1 Corresponding bit in GPIO_OUTG_OUT is set

0x000000

Table 133 bull Fields in GPIO_OUT_CLR

Field Name Bit Access Description DefaultG_OUT_CLR 210 One-shot Setting a bit in this field will immediately clear

the corresponding bit in GPIO_OUTG_OUT Reading this register always return 00 No change1 Corresponding bit in GPIO_OUTG_OUT is cleared

0x000000

Table 134 bull Fields in GPIO_OUT

Field Name Bit Access Description DefaultG_OUT 210 RW Controls the value on the GPIO pins enabled

for output (via the GPIO_OE register) This field can be modified directly or by using the GPIO_O_SET and GPIO_O_CLR registers

0x000000

Registers

2335 DEVCPU_GCBGPIOGPIO_OEParent DEVCPU_GCBGPIO

Instances 1

2336 DEVCPU_GCBGPIOGPIO_INTRParent DEVCPU_GCBGPIO

Instances 1

2337 DEVCPU_GCBGPIOGPIO_INTR_ENAParent DEVCPU_GCBGPIO

Instances 1

2338 DEVCPU_GCBGPIOGPIO_INTR_IDENTParent DEVCPU_GCBGPIO

Instances 1

Table 135 bull Fields in GPIO_IN

Field Name Bit Access Description DefaultG_IN 210 RO GPIO input register Reflects the current state

of the corresponding GPIO pins0x000000

Table 136 bull Fields in GPIO_OE

Field Name Bit Access Description DefaultG_OE 210 RW Configures the direction of the GPIO pins

0 Input1 Output

0x000000

Table 137 bull Fields in GPIO_INTR

Field Name Bit Access Description DefaultG_INTR 210 Sticky Indicates whether a GPIO input has changed

since last clear0 No change1 GPIO has changed

0x000000

Table 138 bull Fields in GPIO_INTR_ENA

Field Name Bit Access Description DefaultG_INTR_ENA 210 RW Enables individual GPIO pins for interrupt 0x000000

Registers

2339 DEVCPU_GCBGPIOGPIO_ALTParent DEVCPU_GCBGPIO

Instances 2

23310 DEVCPU_GCBGPIOGPIO_SD_MAPParent DEVCPU_GCBGPIO

Instances 16

Table 139 bull Fields in GPIO_INTR_IDENT

Field Name Bit Access Description DefaultG_INTR_IDENT 210 RO Shows which GPIO sources that are

currently interrupting This field is the result of an AND-operation between the GPIO_INTR and the GPIO_INTR_ENA registers

0x000000

Table 140 bull Fields in GPIO_ALT

Field Name Bit Access Description DefaultG_ALT 210 RW Configures alternate functions for individual

GPIOs See datasheet for information on possible alternate functionsThe LSB of the GPIO encoding is placed in replication 0 MSB is placed in replication 1 For example to encode Alternate mode 2 for GPIO[n] write DEVCPU_GCBGPIO_ALT[0][n] = 0 and DEVCPU_GCBGPIO_ALT[1][n] = 1Note This register is only reset by the devices reset input ie it is not affected by soft reset00 GPIO mode01 Alternate mode 110 Alternate mode 211 Alternate mode 3

0x000000

Registers

234 DEVCPU_GCBMIIMParent DEVCPU_GCB

Instances 2

2341 DEVCPU_GCBMIIMMII_STATUSParent DEVCPU_GCBMIIM

Instances 1

Table 141 bull Fields in GPIO_SD_MAP

Field Name Bit Access Description DefaultG_SD_MAP 50 RW Set to map a specific GPIO mapped signal

detect input to specific front-port index There is one replication for each GPIO mapped signal detect input If multiple signal detects are enabled and map to same front-port index then the higher replication index will take priority For example to map 3rd signal detect input asif it was provided by 2nd SERDES set DEVCPU_GCBGPIO_SD_MAP[2]G_SD_MAP = 1 and enable SD2 via DEVCPU_GCBGPIO_ALT registers

Table 142 bull Registers in MIIM

MII_STATUS 0x00000000 1 MIIM Status Page 73

MII_CMD 0x00000008 1 MIIM Command Page 74

MII_DATA 0x0000000C 1 MIIM Reply Data Page 75

MII_CFG 0x00000010 1 MIIM Configuration Page 75

MII_SCAN_0 0x00000014 1 MIIM Scan 0 Page 76

MII_SCAN_LAST_RSLTS 0x0000001C 1 MIIM Results Page 76

MII_SCAN_LAST_RSLTS_VLD 0x00000020 1 MIIM Results Page 77

Table 143 bull Fields in MII_STATUS

Field Name Bit Access Description DefaultMIIM_SCAN_COMPLETE 4 RO Signals if all PHYs have been scanned ( with

auto scan ) at least once0 Auto scan has not scanned all PHYs1 Auto scan has scanned all PHY at least once

Registers

2342 DEVCPU_GCBMIIMMII_CMDParent DEVCPU_GCBMIIM

Instances 1

MIIM_STAT_BUSY 3 RO Indicates the current state of the MIIM controller When read operations are done (no longer busy) then read data is available via the DEVCPU_GCBMII_DATA register0 MIIM controller is in idle state1 MIIM controller is busy performing MIIM cmd (Either read or read cmd)

MIIM_STAT_OPR_PEND 2 RO The MIIM controller has a CMD fifo of depth one When this field is 0 then it is safe to write another MIIM command to the MIIM controller0 Read or write not pending1 Read or write pending

MIIM_STAT_PENDING_RD 1 RO Indicates whether a read operation via the MIIM interface is in progress or not0 Read not in progress1 Read in progress

MIIM_STAT_PENDING_WR 0 RO Indicates whether a write operation via the MIIM interface is in progress or not0 Write not in progress1 Write in progress

Table 144 bull Fields in MII_CMD

Field Name Bit Access Description DefaultMIIM_CMD_VLD 31 One-shot Must be set for starting a new PHY access

This bit is automatically cleared0 Write to this register is ignored1 Write to this register is processed

MIIM_CMD_PHYAD 2925 RW Indicates the addressed PHY number 0x00

MIIM_CMD_REGAD 2420 RW Indicates the addressed of the register within the PHY that shall be accessed

MIIM_CMD_WRDATA 194 RW Data to be written in the PHY register 0x0000

MIIM_CMD_SINGLE_SCAN 3 RW Select if scanning of the PHY shall be done once or scanning should be done continuously0 Do continuously PHY scanning 1 Stop once all PHY have been scanned

Table 143 bull Fields in MII_STATUS (continued)

Registers

2343 DEVCPU_GCBMIIMMII_DATAParent DEVCPU_GCBMIIM

Instances 1

2344 DEVCPU_GCBMIIMMII_CFGParent DEVCPU_GCBMIIM

Instances 1

MIIM_CMD_OPR_FIELD 21 RW Indicates type of operationClause 22

01 Write10 Read

Clause 45

00 Address01 Write10 Read inc11 Read

MIIM_CMD_SCAN 0 RW Indicates whether automatic scanning of PHY registers is enabled When enabled the PHY-number for each automatic read is continuously round-robined from PHY_ADDR_LOW through PHY_ADDR_HIGH This function is started upon a read operation (ACCESS_TYPE)Scan MUST be disabled when doing any configuration of the MIIM controller0 Disabled1 Enabled

Table 145 bull Fields in MII_DATA

Field Name Bit Access Description DefaultMIIM_DATA_SUCCESS 1716 RO Indicates whether a read operation failed or

succeeded00 OK11 Error

MIIM_DATA_RDDATA 150 RO Data read from PHY register 0x0000

Table 144 bull Fields in MII_CMD (continued)

Registers

2345 DEVCPU_GCBMIIMMII_SCAN_0Parent DEVCPU_GCBMIIM

Instances 1

2347 DEVCPU_GCBMIIMMII_SCAN_LAST_RSLTSParent DEVCPU_GCBMIIM

Instances 1

Table 146 bull Fields in MII_CFG

Field Name Bit Access Description DefaultMIIM_ST_CFG_FIELD 109 RW The ST (start-of-frame) field of the MIIM

frame format adopts the value of this field This must be configured for either clause 22 or 45 MIIM operation01 Clause 2200 Clause 45Other values are reserved

MIIM_CFG_PRESCALE 70 RW Configures the MIIM clock frequency This is computed as system_clk(2(1+X)) where X is the value written to this registerNote Setting X to 0 is invalid and will result in the same frequency as setting X to 1Values less than 4 are reserved and must not be used

Table 147 bull Fields in MII_SCAN_0

Field Name Bit Access Description DefaultMIIM_SCAN_PHYADHI 95 RW Indicates the high PHY number to scan

during automatic scanning0x00

MIIM_SCAN_PHYADLO 40 RW Indicates the low PHY number to scan during automatic scanning

Field Name Bit Access Description DefaultMIIM_SCAN_MASK 3116 RW Indicates the mask for comparing the PHY

registers during automatic scan0x0000

MIIM_SCAN_EXPECT 150 RW Indicates the expected value for comparing the PHY registers during automatic scan

0x0000

Registers

2348 DEVCPU_GCBMIIMMII_SCAN_LAST_RSLTS_VLDParent DEVCPU_GCBMIIM

Instances 1

235 DEVCPU_GCBMIIM_READ_SCANParent DEVCPU_GCB

Instances 1

2351 DEVCPU_GCBMIIM_READ_SCANMII_SCAN_RSLTS_STICKYParent DEVCPU_GCBMIIM_READ_SCAN

Instances 2

Table 149 bull Fields in MII_SCAN_LAST_RSLTS

Field Name Bit Access Description DefaultMIIM_LAST_RSLT 310 RO Indicates for each PHY if a PHY register has

matched the expected value (with mask)This register reflects the value of the last reading of the phy register0 Mismatch1 Match

0xFFFFFFFF

Table 150 bull Fields in MII_SCAN_LAST_RSLTS_VLD

Field Name Bit Access Description DefaultMIIM_LAST_RSLT_VLD 310 RO Indicates for each PHY if a PHY register

matched are valid or not0 Scan result not valid 1 Scan result valid

0x00000000

Table 151 bull Registers in MIIM_READ_SCAN

MII_SCAN_RSLTS_STICKY 0x00000000 20x00000004

MIIM Results Page 77

Registers

236 DEVCPU_GCBMIIM_SLAVEParent DEVCPU_GCB

Instances 1

2361 DEVCPU_GCBMIIM_SLAVEMIIM_SLAVE_CFGParent DEVCPU_GCBMIIM_SLAVE

Instances 1

237 DEVCPU_GCBPHYParent DEVCPU_GCB

Instances 1

Table 152 bull Fields in MII_SCAN_RSLTS_STICKY

Field Name Bit Access Description DefaultMIIM_SCAN_RSLTS_STICKY 310 RO Indicates for each PHY if a PHY register has

had a mismatch of the expected value (with mask) since last reading of MIIM_SCAN_RSLTS_STICKY

Result is sticky and result will indicate if there has been a mismatch since the last reading of this register

Upon reading this register all bits are reset to 10 Mismatch1 Match

0xFFFFFFFF

Table 153 bull Registers in MIIM_SLAVE

MIIM_SLAVE_CFG 0x00000000 1 MIIM Configuration Page 78

Table 154 bull Fields in MIIM_SLAVE_CFG

Field Name Bit Access Description DefaultSPIKE_FILTER_CFG 51 RW Configuration of the spike filter width on the

MDC and MDIO inputsFilters spikes with a width of (SPIKE_FILTER_CFG+1)SYSTEM_CLK or less

SPIKE_FILTER_ENA 0 RW Set this field to enable the spike filter on the MDC and MDIO inputs When enabled the MIIM_SLAVE_CFGSPIKE_FILTER_CFG field determines the width of the spike filter

Registers

2371 DEVCPU_GCBPHYPHY_CFGParent DEVCPU_GCBPHY

Instances 1

2372 DEVCPU_GCBPHYPHY_STATParent DEVCPU_GCBPHY

Instances 1

238 DEVCPU_GCBSIO_CTRLParent DEVCPU_GCB

Instances 1

Table 155 bull Registers in PHY

PHY_CFG 0x00000000 1 PHY configuration register Page 79

PHY_STAT 0x00000004 1 PHY status register Page 79

Table 156 bull Fields in PHY_CFG

Field Name Bit Access Description DefaultPHY_RESET 85 RW

Set to 1 to release reset0x0

PHY_COMMON_RESET 4 RWSet to 1 to release reset

PHY_ENA 30 RW Enable PHY interface for Device 0 to 3 0x0

Table 157 bull Fields in PHY_STAT

Field Name Bit Access Description DefaultFAST_LINK_STATUS 2017 RO 0x0

LINK_STAT_DUPLEX 1613 RO 0x0

LINK_STAT_SPEED_1000 129 RO 0x0

SUPERVISOR_COMPLETE 0 RO 0x0

Registers

2381 DEVCPU_GCBSIO_CTRLSIO_INPUT_DATAParent DEVCPU_GCBSIO_CTRL

Instances 4

2382 DEVCPU_GCBSIO_CTRLSIO_CFGParent DEVCPU_GCBSIO_CTRL

Instances 1

Table 158 bull Registers in SIO_CTRL

SIO_INPUT_DATA 0x00000000 40x00000004

Last value at SGPIO pins Page 80

SIO_CFG 0x00000010 1 General configurations Page 80

SIO_CLOCK 0x00000014 1 SGPIO shift clock frequency Page 82

SIO_PORT_CFG 0x00000018 320x00000004

Output configuration Page 83

SIO_PORT_ENA 0x00000098 1 Port enable Page 84

SIO_PWM_CFG 0x0000009C 30x00000004

Pulse-width modulation configuration

SIO_INTR_POL 0x000000A8 40x00000004

SGPIO interrupt polarity Page 84

SIO_INTR_RAW 0x000000B8 40x00000004

Interrupt raw status Page 84

SIO_INTR_TRIGGER0 0x000000C8 40x00000004

Interrupt trigger mode 0 Page 85

SIO_INTR_TRIGGER1 0x000000D8 40x00000004

SIO_INTR 0x000000E8 40x00000004

Currently interrupting SGPIOs Page 86

SIO_INTR_ENA 0x000000F8 1 SGPIO interrupt enable per port

SIO_INTR_IDENT 0x000000FC 40x00000004

Currently active interrupts Page 86

Table 159 bull Fields in SIO_INPUT_DATA

Field Name Bit Access Description DefaultSIO_INPUT_DATA 310 RO Serial input data Each replication N holds

bit N from all ports - bit N from port M is mapped to replication N bit M Values of disabled gpios are undefined

0x00000000

Registers

Table 160 bull Fields in SIO_CFG

Field Name Bit Access Description DefaultSIO_PWM_WINDOW 3124 RW Configure the size of the PWM window

0 255 cycles1-254 2-255 cycles255 Reserved

SIO_REDUCED_GAP 23 RW When set the SIO_BURST_GAP is divided by 32

SIO_BMODE_1 2221 RW Configuration for blink mode 1Supports three different blink modes and a burst toggle mode in which blink mode 1 will alternate for each burst0 Blink freq appr 20Hz1 Blink freq appr 10Hz2 Blink freq appr 5Hz3 Burst toggle

SIO_BMODE_0 2019 RW Configuration of blink mode 0 Supports four different blink modes0 Blink freq appr 5Hz1 Blink freq appr 25Hz2 Blink freq appr 125Hz3 Blink freq appr 0625Hz

SIO_BLINK_RESET 18 RW Reset the blink counters Used to synchronize the blink modes between different chips0 Blink counter is running1 Blink counter is reset until sio_blink_reset is unset again

SIO_BURST_GAP_DIS 17 RW Set to disable burst gap 0x0

SIO_BURST_GAP 1612 RW Configures the length of burst gap in steps of approx 168 ms Burst gap can be disabled by setting DEVCPU_GCBSIO_CFGSIO_BURST_GAP_DIS For smaller burst gap set DEVCPU_GCBSIO_CFGSIO_REDUCED_GAP The gap is calculated by (Value+1) (2^18) (system clock period)0 168 ms burst gap1 336 ms burst gap31 5369 ms burst gap

SIO_SINGLE_SHOT 11 One-shot Use this to output a single burst Will be cleared by hardware when the burst has finished

SIO_AUTO_REPEAT 10 RW Use this to output repeated bursts interleaved with burst gaps Must be manually reset again to stop output of bursts

SIO_LD_POLARITY 9 RW Polarity of the Ld signal0 load signal is active low1 load signal is active high

Registers

2383 DEVCPU_GCBSIO_CTRLSIO_CLOCKParent DEVCPU_GCBSIO_CTRL

Instances 1

SIO_PORT_WIDTH 87 RW Number of SGPIOs pr port0 1 gpio pr port1 2 gpios pr port2 3 gpios pr port3 4 gpios pr port

SIO_REVERSE_OUTPUT 6 RW Reverse the output bitstreamThe default order of the output bit stream is (displayed in transmitted order)(portN bit3 portN bit2 port0 bit1 port0 bit0)The reverse order of the output bit stream is (displayed in transmitted order)(port0 bit0 port0 bit1 portN bit2 portN bit3)0 Do not reverse1 Reverse

SIO_REVERSE_INPUT 5 RW Reverse the input bitstreamThe default order of the input bit stream is (displayed in received order)(port0 bit0 port0 bit1 portN bit2 portN bit3)The reverse order of the input bit stream is (displayed in received order)(portN bit3 portN bit2 port0 bit1 port0 bit0)0 Do not reverse1 Reverse

SIO_GPIO_INTR_ENA 41 RW Bit interrupt enable Enables interrupts for the four gpios in a port Is applied to all ports0 Interrupt is disabled for bit n for all ports1 Interrupt is enabled for bit n for all ports

SIO_MASTER_INTR_ENA 0 RW Master interrupt enable Enables interrupts Is applied to all gpios on all ports This field only has effect on the interrupt output signal of the sio_ctrl block It has no effect on the interrupt registers0 Interrupt is disabled for all bits for all ports1 Interrupt is enabled for all bits for all ports

Table 160 bull Fields in SIO_CFG (continued)

Registers

2384 DEVCPU_GCBSIO_CTRLSIO_PORT_CFGParent DEVCPU_GCBSIO_CTRL

Instances 32

Table 161 bull Fields in SIO_CLOCK

Field Name Bit Access Description DefaultSIO_CLK_FREQ 198 RW SIO controller clock frequency Divides the

250 MHz system clk with the value of this field Eg field is set to 10 the output frequency will be 25 MHz0 Disable clock1 Reserved do not useOthers Clock divider value

SYS_CLK_PERIOD 70 RW The system clock period given in the clock period in PS divided by 100

Table 162 bull Fields in SIO_PORT_CFG

Field Name Bit Access Description DefaultBIT_SOURCE 2312 RW Output source select for the four outputs from

each portThe source select is encoded using three bits for each output bit Output bit0 is defined by (2 down to 0) output bit1 is defined by (5 down to 3) output bit2 is defined by (8 down to 6) and output bit3 is defined by (11 down to 9)0 Forced 01 Forced 12 Blink mode 03 Blink mode 14 Link activity blink mode 05 Link activity blink mode 16 Reserved7 Reserved

PWM_SOURCE 114 RW PWM source select for the four outputs from each portThe PWM source select is encoded using two bits for each output bit Output bit0 is defined by (1 down to 0) output bit1 is defined by (3 down to 2) output bit2 is defined by (5 down to 4) and output bit3 is defined by (7 down to 6)0 PWM disabled1 PWM 0 used2 PWM 1 used3 PWM 2 used

BIT_POLARITY 30 RW Output polarity select for the four outputs from each portThe polarity select is encoded using one bit for each output bit0 Normal polarity1 Inversed polarity

Registers

2385 DEVCPU_GCBSIO_CTRLSIO_PORT_ENAParent DEVCPU_GCBSIO_CTRL

Instances 1

2386 DEVCPU_GCBSIO_CTRLSIO_PWM_CFGParent DEVCPU_GCBSIO_CTRL

Instances 3

2387 DEVCPU_GCBSIO_CTRLSIO_INTR_POLParent DEVCPU_GCBSIO_CTRL

Instances 4

2388 DEVCPU_GCBSIO_CTRLSIO_INTR_RAWParent DEVCPU_GCBSIO_CTRL

Instances 4

Table 163 bull Fields in SIO_PORT_ENA

Field Name Bit Access Description DefaultSIO_PORT_ENA 310 RW Port enable vector with one enable bit for

each portPort order (portN down to port0)0 Port is disabled1 Port is enabled

0x00000000

Table 164 bull Fields in SIO_PWM_CFG

Field Name Bit Access Description DefaultPWM_DUTY_CYCLE 70 RW Define the duty cycle for the PWMs

0x00 Always off0xFF Always on

Table 165 bull Fields in SIO_INTR_POL

Field Name Bit Access Description DefaultSIO_INTR_POL 310 RW Interrupt polarity This register defines at

which logic value an interrupt is generated For bit0 this register is also used to define the polarity of the loss of signal output0 interrupt and loss of signal is active high1 interrupt and loss of signal is active low

0x00000000

Registers

2389 DEVCPU_GCBSIO_CTRLSIO_INTR_TRIGGER0Parent DEVCPU_GCBSIO_CTRL

Instances 4

Table 166 bull Fields in SIO_INTR_RAW

Field Name Bit Access Description DefaultSIO_INTR_RAW 310 RO Shows the current value of individual

interrupts All interrupts are active high (but has been corrected for polarity as configured in SIO_INTR_POL)

0x00000000

Table 167 bull Fields in SIO_INTR_TRIGGER0

Field Name Bit Access Description DefaultSIO_INTR_TRIGGER0 310 RW Configure trigger mode of individual

interrupts The trigger mode determines how the value of the SIO_INTR_RAW register is transfered to the SIO_INTR register

This register is the LSB of the encoding Register SIO_INTR_TRIGGER1 is the MSB of the encoding

For level-triggered interrupts SIO_INTR is set when an input is received that results in a high corresponding bit in SIO_INTR_RAWFor edge-triggered interrupts SIO_INTR is set when an input is received that results in a change of the corresponding bit in SIO_INTR_RAWFor falling-edge-triggered interrupts SIO_INTR is set when an input is received that results in a change from 1 to 0 of the corresponding bit in SIO_INTR_RAWFor rising-edge-triggered interrupts SIO_INTR is set when an input is received that results in a change from 0 to 1 of the corresponding bit in SIO_INTR_RAW00 Interrupt is level-activated01 Interrupt is edge-triggered10 Interrupt is falling-edge-triggered11 Interrupt is rising-edge-triggered

0x00000000

Registers

23811 DEVCPU_GCBSIO_CTRLSIO_INTRParent DEVCPU_GCBSIO_CTRL

Instances 4

23812 DEVCPU_GCBSIO_CTRLSIO_INTR_ENAParent DEVCPU_GCBSIO_CTRL

Instances 1

23813 DEVCPU_GCBSIO_CTRLSIO_INTR_IDENTParent DEVCPU_GCBSIO_CTRL

Instances 4

Field Name Bit Access Description DefaultSIO_INTR_TRIGGER1 310 RW See description of SIO_INTR_TRIGGER0 0x00000000

Table 169 bull Fields in SIO_INTR

Field Name Bit Access Description DefaultSIO_INTR 310 Sticky Interrupt register These sticky bits are set

when an input is received that are triggered by the corresponding SIO_INTR_TRIGGER configuration0 No interrupt for given gpio1 Interrupt for given gpio

0x00000000

Table 170 bull Fields in SIO_INTR_ENA

Field Name Bit Access Description DefaultSIO_INTR_ENA 310 RW Interrupt enable vector with one enable bit for

each portPort order (portN down to port0)

0 Interrupt is disabled for the port1 Interrupt is enabled for the port

0x00000000

Table 171 bull Fields in SIO_INTR_IDENT

Field Name Bit Access Description DefaultSIO_INTR_IDENT 310 RO Shows the currently active interrupts This

register is the result of the SIO_INTR interrupts with the disabled interrupts (from SIO_INTR_ENA and SIO_GPIO_INTR_ENA) removed0 No active interrupt for given gpio1 Active interrupt for given gpio

0x00000000

Registers

239 DEVCPU_GCBFAN_CTRLParent DEVCPU_GCB

Instances 1

2391 DEVCPU_GCBFAN_CTRLFAN_CFGParent DEVCPU_GCBFAN_CTRL

Instances 1

2392 DEVCPU_GCBFAN_CTRLPWM_FREQParent DEVCPU_GCBFAN_CTRL

Instances 1

Table 172 bull Registers in FAN_CTRL

FAN_CFG 0x00000000 1 Fan controller configuration Page 87

PWM_FREQ 0x00000004 1 Configuration of the PWM frequency

FAN_CNT 0x00000008 1 TACH counter Page 88

Table 173 bull Fields in FAN_CFG

Field Name Bit Access Description DefaultDUTY_CYCLE 2316 RW Define the duty cycle

CLK_CYCLES_10US 154 RW The number of system clock cycles that fit in 10 us

INV_POL 3 RW Define the polarity of the PWM output0 PWM is logic 1 when on1 PWM is logic 0 when on

GATE_ENA 2 RW Enable gating of the TACH input by the PWM output so that only TACH pulses received when PWM is on are counted0 Disabled1 Enabled

PWM_OPEN_COL_ENA 1 RW Configure the PWM output to be open collector

FAN_STAT_CFG 0 RW Configure behavior of TACH input tick counter see DEVCPU_GCBFAN_CNT for more infromation

Registers

2393 DEVCPU_GCBFAN_CTRLFAN_CNTParent DEVCPU_GCBFAN_CTRL

Instances 1

2310 DEVCPU_GCBMEMITGRParent DEVCPU_GCB

Instances 1

23101 DEVCPU_GCBMEMITGRMEMITGR_CTRLParent DEVCPU_GCBMEMITGR

Instances 1

Table 174 bull Fields in PWM_FREQ

Field Name Bit Access Description DefaultPWM_FREQ 160 RW Set the frequency of the PWM output The

value of this field must be (System clock frequency)(PWM frequency)256

0x00018

Table 175 bull Fields in FAN_CNT

Field Name Bit Access Description DefaultFAN_CNT 150 RO Counts the number of TACH input ticks If

DEVCPU_GCBFAN_CFGFAN_STAT_CFG is set then this is a wrapping counter that shows the total number of registered TACH ticks If DEVCPU_GCBFAN_CFGFAN_STAT_CFG is cleared then this counter is updated once every second with the number of TACH ticks registered during the last second

0x0000

Table 176 bull Registers in MEMITGR

MEMITGR_CTRL 0x00000000 1 Monitor control Page 88

MEMITGR_STAT 0x00000004 1 Monitor status Page 89

MEMITGR_INFO 0x00000008 1 Memory indication Page 90

MEMITGR_IDX 0x0000000C 1 Memory index Page 91

MEMITGR_DIV 0x00000010 1 Monitor speed Page 91

Registers

23102 DEVCPU_GCBMEMITGRMEMITGR_STATParent DEVCPU_GCBMEMITGR

Instances 1

Table 177 bull Fields in MEMITGR_CTRL

Field Name Bit Access Description DefaultACTIVATE 0 One-shot Setting this field transitions the integrity

monitor between operating modes Transitioning between modes takes time this field remains set until the new mode is reached During this time the monitor also reports busy DEVCPU_GCBMEMITGR_STATMODE_BUSY is set)From IDLE (DEVCPU_GCBMEMITGR_STATMODE_IDLE is set) the monitor can transition into either DETECT or LISTEN mode the DETECT mode is entered if a memory reports an indication - the LISTEN mode is entered if no indications are reported The first time after reset the monitor will not detect indications that is it will transition directly from IDLE to LISTEN modeFrom DETECT (DEVCPU_GCBMEMITGR_STATMODE_DETECT is set) the monitor can transition into either DETECT or LISTEN mode the DETECT mode is entered if more indications are reported - the LISTEN mode is entered if no more indications are reportedFrom LISTEN (DEVCPU_GCBMEMITGR_STATMODE_LISTEN is set) the monitor can transition into IDLE modeSoftware shall not set this field when the monitor is BUSY (when DEVCPU_GCBMEMITGR_STATMODE_BUSY is set)

Table 178 bull Fields in MEMITGR_STAT

Field Name Bit Access Description DefaultINDICATION 4 RO If this field is set then there is an indication

from one of the memories that needs to be analyzed An indication is either a parity detection or an error correctionThis field is only set when the monitor is in LISTEN mode (DEVCPU_GCBMEMITGR_STATMODE_LISTEN is set) in all other states (including BUSY) this field returns 0

Registers

23103 DEVCPU_GCBMEMITGRMEMITGR_INFOParent DEVCPU_GCBMEMITGR

Instances 1

This field is only valid when the monitor is in the DETECT (DEVCPU_GCBMEMITGR_STATMODE_DETECT is set) mode

MODE_LISTEN 3 RO This field is set when the monitor is in LISTEN mode during listen mode the monitor continually check for paritycorrection indications from the memories

MODE_DETECT 2 RO This field is set when the monitor is in DETECT mode during detect mode the DEVCPU_GCBMEMITGR_INFO and DEVCPU_GCBMEMITGR_IDX registers contains valid information about one indication

MODE_IDLE 1 RO This field is set when the monitor is in IDLE mode

MODE_BUSY 0 RO The busy signal is a copy of the DEVCPU_GCBMEMITGR_CTRLACTIVATE field see description of that field for more information about the different statesmodes of the monitor

Table 179 bull Fields in MEMITGR_INFO

Field Name Bit Access Description DefaultMEM_ERR 31 RO This field is set if the monitor has detected a

parity indication (or an unrecoverable correction)

MEM_COR 30 RO This field is set if the monitor has detected a correction

MEM_ERR_OVF 29 RO This field is set if the monitor has detected a parity indication (or an unrecoverable correction) for which the address has not been recordedIf DEVCPU_GCBMEMITGR_INFOMEM_ERR is set then there has been more than one indication then only the address of the newest indication has been kept If DEVCPU_GCBMEMITGR_INFOMEM_ERR is cleared then an indication has occurred for which the address could not be stored this is a very rare situation that can only happen if an indication is detected just as the memory is talking to the monitor

Table 178 bull Fields in MEMITGR_STAT (continued)

Registers

23104 DEVCPU_GCBMEMITGRMEMITGR_IDXParent DEVCPU_GCBMEMITGR

Instances 1

23105 DEVCPU_GCBMEMITGRMEMITGR_DIVParent DEVCPU_GCBMEMITGR

Instances 1

MEM_COR_OVF 28 RO This field is set if the monitor has correction indication for which the address has not been recordedIf DEVCPU_GCBMEMITGR_INFOMEM_ERR is set then there has also been a parity indication (or an unrecoverable correction) which takes priority over correction indicationsIf DEVCPU_GCBMEMITGR_INFOMEM_ERR is cleared and DEVCPU_GCBMEMITGR_INFOMEM_COR is set then there has been more than one correction indication then only the address of the newest correction indication has been keptIf DEVCPU_GCBMEMITGR_INFOMEM_ERR and DEVCPU_GCBMEMITGR_INFOMEM_COR is both cleared then a correction indication has occurred for which the address could not be stored this is a very rare situation that can only happen if an indication is detected just as the memory is talking to the monitor

MEM_ADDR 270 RO This field is valid only when DEVCPU_GCBMEMITGR_INFOMEM_ERR or DEVCPU_GCBMEMITGR_INFOMEM_COR is set

0x0000000

Table 180 bull Fields in MEMITGR_IDX

Field Name Bit Access Description DefaultMEM_IDX 150 RO This field contains a unique index for the

memory for which info is currently provided in DEVCPU_GCBMEMITGR_INFO Indexes are counted from 1 (not 0)

0x0000

Table 179 bull Fields in MEMITGR_INFO (continued)

Registers

2311 DEVCPU_GCBVRAPParent DEVCPU_GCB

Instances 1

23111 DEVCPU_GCBVRAPVRAP_ACCESS_STATParent DEVCPU_GCBVRAP

Instances 1

Table 181 bull Fields in MEMITGR_DIV

Field Name Bit Access Description DefaultMEM_DIV 150 RW Configure divider for generating the sync-

pulse to memories (controls the speed at which the monitor talks to the memories) The lower this is set the faster indications can be read out of the memoriesSee datasheet for appropriate value

0x00FF

Table 182 bull Registers in VRAP

VRAP_ACCESS_STAT 0x00000000 1 VRAP events Page 92

Table 183 bull Fields in VRAP_ACCESS_STAT

Field Name Bit Access Description DefaultFRM_RECV_STICKY 3 Sticky This field is set if a valid VRAP frame has

been received0x0

CMD_INVALID_STICKY 2 Sticky This field is set if an invalid command inside a valid VRAP frame has been received The VRAP engine has ignored the command

FRM_INVALID_STICKY 1 Sticky This field is set if an invalid VRAP frame has been received and discarded by the VRAP-engine Frames with a VRAP header different from V1 are considered invalid

REPLY_ABORT_STICKY 0 Sticky This field is set if a VRAP reply frame has been aborted This my happen if a protocol violation is detected during VRAP request frame processing

Registers

24 DEVCPU_ORG

241 DEVCPU_ORGDEVCPU_ORGParent DEVCPU_ORG

Instances 1

2411 DEVCPU_ORGDEVCPU_ORGIF_CTRLParent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 184 bull Register Groups in DEVCPU_ORG

DEVCPU_ORG 0x00000000 1 Origin registers Page 93

Table 185 bull Registers in DEVCPU_ORG

IF_CTRL 0x00000000 1 Physical interface control Page 93

IF_CFGSTAT 0x00000004 1 Physical interface configuration and status

ORG_CFG 0x00000008 1 Origin configuration Page 95

ERR_CNTS 0x0000000C 1 Error counters Page 95

TIMEOUT_CFG 0x00000010 1 Timeout configuration Page 95

MAILBOX_SET 0x00000018 1 Atomic set of mailbox Page 96

MAILBOX_CLR 0x0000001C 1 Atomic clear of mailbox Page 96

MAILBOX 0x00000020 1 Mailbox Page 97

SEMA_CFG 0x00000024 1 Semaphore configuration Page 97

SEMA0 0x00000028 1 Semaphore 0 Page 97

SEMA0_OWNER 0x0000002C 1 Semaphore 0 owner Page 98

SEMA1_OWNER 0x00000034 1 Semaphore 1 owner Page 99

Registers

2412 DEVCPU_ORGDEVCPU_ORGIF_CFGSTATParent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 186 bull Fields in IF_CTRL

Field Name Bit Access Description DefaultIF_CTRL 30 RW This register configures critical interface

parameters it is constructed so that it can always be written correctly no matter the current state of the interface When initializing a physical interface then this is the first register that must be written the state of the interface at that point may be unknown and therefore the following scheme is required to bring the interface to a known stateWhen writing a 4-bit value to this field construct a 32-bit data-word as follows a) copy the 4-bit value into bits 30 118 1916 and 2724 b) reverse the 4-bit value and copy into bits 74 1512 2320 and 3128 Example To write the value 2 to this field the 32-bit data-word to write is 0x42424242Bit 0 configures endianness (when applicable) 0Little-Endian 1Big-EndianBit 1 configures bit-order (when applicable) 0MSB-first 1LSB-firstBit 23 are reserved and should be kept 0For the SI interface the default value of this field is 0x1 For all other interfaces the default value is 0x0

Table 187 bull Fields in IF_CFGSTAT

Field Name Bit Access Description DefaultIF_NUM 3124 RO Interface number software can use this field

to determine which interface that is currently used for accessing the device0 VCore System1 VRAP2 SI3 MIIM

IF_STAT 16 Sticky SI interface This field is set if the SI interface has read data from device before it was ready (this can happen if the SI frequency is too high or when too few padding bytes has been specified)

IF_CFG 30 RW SI interface This is the number of padding bytes to insert before read-data is shifted out of the deviceThis is needed when using high serial interface frequencies

Registers

2413 DEVCPU_ORGDEVCPU_ORGORG_CFGParent DEVCPU_ORGDEVCPU_ORG

Instances 1

2414 DEVCPU_ORGDEVCPU_ORGERR_CNTSParent DEVCPU_ORGDEVCPU_ORG

Instances 1

2415 DEVCPU_ORGDEVCPU_ORGTIMEOUT_CFGParent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 188 bull Fields in ORG_CFG

Field Name Bit Access Description DefaultFAST_WR 0 RW Clear this field to make write accesses return

status By default write operations return status OK because they are finished before status of the access is known All non-OK responses will be logged in DEVCPU_ORGERR_CNTS no matter the value of this field

Table 189 bull Fields in ERR_CNTS

Field Name Bit Access Description DefaultERR_TGT_BUSY 1916 RW The Target Busy indication is triggered

when an interface tries to access a target which is currently reset or if another interface is using the target

ERR_WD_DROP_ORG 1512 RW The Watch Dog Drop Origin indication is triggered when the origin does not receive reply from the CSR ring within a given amount of time This cannot happen during normal operation

ERR_WD_DROP 118 RW The Watch Dog Drop indication is triggered when a target is too long about processing a request Usually requests are processed immediately but some accesses requires interaction with the core-logic when this logic is in reset or during very heavy traffic load there is a chance of timing out in the target

ERR_NO_ACTION 74 RW The No Action indication is triggered when a target is accessed with a non-existing address In other words the target did not contain a register at the requested address

ERR_UTM 30 RW The Unknown Target Module indication is triggered when a non-existing target is requested In other words there was no target with the requested target-id

Registers

This register is shared between all interfaces on the Origin

2416 DEVCPU_ORGDEVCPU_ORGGPRParent DEVCPU_ORGDEVCPU_ORG

Instances 1

2417 DEVCPU_ORGDEVCPU_ORGMAILBOX_SETParent DEVCPU_ORGDEVCPU_ORG

Instances 1

2418 DEVCPU_ORGDEVCPU_ORGMAILBOX_CLRParent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 190 bull Fields in TIMEOUT_CFG

Field Name Bit Access Description DefaultTIMEOUT_CFG 110 RW The contents of this field controls the timeout

delay for the CSR system Setting this field to 0 disables timeout Timeout is handled as follows A counter that decrements continually when reaching 0 it will wrap to the value specified by this field When a target has been processing a request for three wraps the target time-out and generate a WD_DROP indication In the origin an Interface that has been processing a request for four wraps will time out and generate a WD_DROP_ORG indication

Field Name Bit Access Description DefaultGPR 310 RW General purpose 32-bit registers for debug

and software development The contents of this register can always (safely) be read However write operations from different masters (to this register) which occur at (exactly) the same time will fail

0x00000000

Table 192 bull Fields in MAILBOX_SET

Field Name Bit Access Description DefaultMAILBOX_SET 310 One-shot Set bits in this register to atomically set

corresponding bits in the DEVCPU_ORGMAILBOX register This register return 0 on read

0x00000000

Registers

2419 DEVCPU_ORGDEVCPU_ORGMAILBOXParent DEVCPU_ORGDEVCPU_ORG

Instances 1

24110 DEVCPU_ORGDEVCPU_ORGSEMA_CFGParent DEVCPU_ORGDEVCPU_ORG

Instances 1

24111 DEVCPU_ORGDEVCPU_ORGSEMA0Parent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 193 bull Fields in MAILBOX_CLR

Field Name Bit Access Description DefaultMAILBOX_CLR 310 One-shot Set bits in this register to atomically clear

0x00000000

Table 194 bull Fields in MAILBOX

Field Name Bit Access Description DefaultMAILBOX 310 RW Mailbox register which is shared between all

interfaces on the Origin Atomic (safe) modifications to the contents of this register can be performed by using the DEVCPU_ORGMAILBOX_CLR and DEVCPU_ORGMAILBOX_SET registers

0x00000000

Table 195 bull Fields in SEMA_CFG

Field Name Bit Access Description DefaultSEMA_INTR_POL 10 RW By default semaphore-interrupt is generated

when a semaphore is free By setting this field interrupt is generated when semaphore is taken bit 0 corresponds to semaphore 0 bit 1 to semaphore 10 Interrupt on taken semaphore1 Interrupt on free semaphore

Registers

24112 DEVCPU_ORGDEVCPU_ORGSEMA0_OWNERParent DEVCPU_ORGDEVCPU_ORG

Instances 1

Table 196 bull Fields in SEMA0

Field Name Bit Access Description DefaultSEMA0 0 RW General SemaphoreThe first interface to

read this field will be granted the semaphore (reading this field returns 0x1) Once the semaphore has been granted all reads return 0 from this field (until the semaphore has been released) Any interface can release the semaphore by writing (any value) to this field0 Semaphore ownership denied1 Semaphore has been granted

Table 197 bull Fields in SEMA0_OWNER

Field Name Bit Access Description DefaultSEMA0_OWNER 310 RO Current owner of the semaphore This field is

a one-hot encoded vector each bit in this vector correspond to an interface on the origin If this field return 0 then the semaphore was free at the time of reading the register0 Semaphore is free1 VCore System owns semaphore2 VRAP owns semaphore4 SI owns smaphore8 MIIM owns semaphore

0x00000000

Registers

Instances 1

25 DEVCPU_PTP

251 DEVCPU_PTPPTP_CFGParent DEVCPU_PTP

Instances 1

0x00000000

Table 200 bull Register Groups in DEVCPU_PTP

PTP_CFG 0x000000A0 1 PTP controller configuration and status

PTP_STATUS 0x000000BC 1 Status of PTP timers Page 102

PTP_PINS 0x00000000 50x00000020

Timing synchronization Page 103

Table 201 bull Registers in PTP_CFG

PTP_MISC_CFG 0x00000000 1 Misc PTP configurations Page 100

CLK_ADJ_CFG 0x00000004 1 Generated clock adjustment configuration

CLK_ADJ_FRQ 0x00000008 1 Generated clock frequency adjustment

PTP_PIN_INTR 0x0000000C 1 Pending interrupt mask Page 101

Registers

2511 DEVCPU_PTPPTP_CFGPTP_MISC_CFGParent DEVCPU_PTPPTP_CFG

Instances 1

2512 DEVCPU_PTPPTP_CFGCLK_ADJ_CFGParent DEVCPU_PTPPTP_CFG

Instances 1

One replication exsists per time domain

2513 DEVCPU_PTPPTP_CFGCLK_ADJ_FRQParent DEVCPU_PTPPTP_CFG

PTP_PIN_INTR_ENA 0x00000010 1 Enable interrupts per pin Page 101

PTP_INTR_IDENT 0x00000014 1 Current interrupt status Page 101

PTP_SYS_CLK_CFG 0x00000018 1 System clock configuration Page 102

Table 202 bull Fields in PTP_MISC_CFG

Field Name Bit Access Description DefaultPTP_ENA 2 RW Enable master counter

0 Master counter disabled and reset1 Master counter enabled

PTP_HOLD 1 RW Hold master counter0 Master counter counts if enabled1 Master counter will stay at the reached value

PTP_TOD_FREEZE 0 RW The PTP_CUR timers will be frozen when this field is set for a domain in order to return concurrent values

Table 203 bull Fields in CLK_ADJ_CFG

Field Name Bit Access Description DefaultCLK_ADJ_DIR 1 RW Clock frequency adjustment direction

0 Positive adjustment Every adjustment adds 1ns to the counter =gt clock period is decreased clock frequency is increased1 Negative adjustment Every adjustment subtracts 1ns from the counter =gt clock period is increased clock frequency is decreased

CLK_ADJ_ENA 0 RW Clock frequency adjust enable0 Adjustment Disabled1 Adjustment Enabled

Table 201 bull Registers in PTP_CFG (continued)

Registers

Instances 1

Adjust master timer acording to detected PPB error Ex 1PBB Adjust every 1ns 50006PBB Adjust every 19997600ps

2514 DEVCPU_PTPPTP_CFGPTP_PIN_INTRParent DEVCPU_PTPPTP_CFG

Instances 1

2515 DEVCPU_PTPPTP_CFGPTP_PIN_INTR_ENAParent DEVCPU_PTPPTP_CFG

Instances 1

2516 DEVCPU_PTPPTP_CFGPTP_INTR_IDENTParent DEVCPU_PTPPTP_CFG

Instances 1

Table 204 bull Fields in CLK_ADJ_FRQ

Field Name Bit Access Description DefaultCLK_ADJ_UNIT 30 RW Clock frequency adjust unit

0 Adjustment made every CLK_ADJ picoseconds1 Adjustment made every CLK_ADJ nanoseconds

CLK_ADJ 290 RW Clock frequency adjustN Number of unadjusted CLK_ADJ_UNIT after which the counter for the clock must be adjusted

0x00000000

Table 205 bull Fields in PTP_PIN_INTR

Field Name Bit Access Description DefaultINTR_PTP 40 Sticky One bit per pin set when an active edge is

seen0x00

Table 206 bull Fields in PTP_PIN_INTR_ENA

Field Name Bit Access Description DefaultINTR_PTP_ENA 40 RW Enable interrupt per ptp pin 0x00

Table 207 bull Fields in PTP_INTR_IDENT

Field Name Bit Access Description DefaultINTR_PTP_IDENT 40 RO Bit n will be high if an interrupt is currently

pending for pin ltngt0x00

Registers

2517 DEVCPU_PTPPTP_CFGPTP_SYS_CLK_CFGParent DEVCPU_PTPPTP_CFG

Instances 1

252 DEVCPU_PTPPTP_STATUSParent DEVCPU_PTP

Instances 1

2521 DEVCPU_PTPPTP_STATUSPTP_CUR_NSFParent DEVCPU_PTPPTP_STATUS

Instances 1

2522 DEVCPU_PTPPTP_STATUSPTP_CUR_NSECParent DEVCPU_PTPPTP_STATUS

Instances 1

Current time of day nanoseconds part

Table 208 bull Fields in PTP_SYS_CLK_CFG

Field Name Bit Access Description DefaultPTP_SYS_CLK_PER_NS 84 RW Must be configured to running system clock

period rounded down to closest interger nanoseconds value

PTP_SYS_CLK_PER_PS100 30 RW Must be configured to number of 100ps to add on top of the PTP_SYS_CLK_PER_NS value to get to the correct clock period

Table 209 bull Registers in PTP_STATUS

PTP_CUR_NSF 0x00000000 1 Current timestamping value Page 102

PTP_CUR_NSEC 0x00000004 1 Current time of day Page 102

PTP_CUR_SEC_LSB 0x00000008 1 Current time of day Page 103

PTP_CUR_SEC_MSB 0x0000000C 1 Current time of day Page 103

Table 210 bull Fields in PTP_CUR_NSF

Field Name Bit Access Description DefaultPTP_CUR_NSF 310 RO Returns the current value of the

timestamping clock The time of day registers will be latched when this register is read

0x00000000

Registers

2523 DEVCPU_PTPPTP_STATUSPTP_CUR_SEC_LSBParent DEVCPU_PTPPTP_STATUS

Instances 1

2524 DEVCPU_PTPPTP_STATUSPTP_CUR_SEC_MSBParent DEVCPU_PTPPTP_STATUS

Instances 1

253 DEVCPU_PTPPTP_PINSParent DEVCPU_PTP

Instances 5

Table 211 bull Fields in PTP_CUR_NSEC

Field Name Bit Access Description DefaultPTP_CUR_NSEC 290 RO Time of day naoseconds latched when NSF

was read0x00000000

Table 212 bull Fields in PTP_CUR_SEC_LSB

Field Name Bit Access Description DefaultPTP_CUR_SEC_LSB 310 RO Value of current tod secs latched when NSF

was read0x00000000

Table 213 bull Fields in PTP_CUR_SEC_MSB

Field Name Bit Access Description DefaultPTP_CUR_SEC_MSB 150 RO Current time of day seconds part latched

when NSF was read0x0000

Table 214 bull Registers in PTP_PINS

PTP_PIN_CFG 0x00000000 1 Configuration of use of the register group

PTP_TOD_SEC_MSB 0x00000004 1 Time Of Day MSB Page 104

PTP_TOD_SEC_LSB 0x00000008 1 Time Of Day LSB Page 105

PTP_TOD_NSEC 0x0000000C 1 Time Of Day nanosecs part Page 105

PTP_NSF 0x00000010 1 Stamper clock Page 105

PIN_WF_HIGH_PERIOD 0x00000014 1 Waveform programming Page 105

PIN_WF_LOW_PERIOD 0x00000018 1 Waveform programming Page 106

Registers

2531 DEVCPU_PTPPTP_PINSPTP_PIN_CFGParent DEVCPU_PTPPTP_PINS

Instances 1

Select use of the ptp io pin Ptp pin 4 is not attached to any physical IO

2532 DEVCPU_PTPPTP_PINSPTP_TOD_SEC_MSBParent DEVCPU_PTPPTP_PINS

Instances 1

Table 215 bull Fields in PTP_PIN_CFG

Field Name Bit Access Description DefaultPTP_PIN_ACTION 53 RW Defined actions are

IDLE No operation LOAD Load TimeOfDay with configured values STORE Store TimeOfDay and NSF of selected time domain CLOCK Generate a clock output DELTA Add PTP_TOD_NSEC field as a signed integer to TimeOfDay

When the sync option is set the action will be done when the pin sees an active edgeThe action will automatically return to IDLE when complete

0 IDLE1 LOAD2 STORE3 CLOCK4 DELTA5-7 reserved

PTP_PIN_SYNC 2 RW For LOADSTOREDELTA actions setting this option will suspend the action until an active edge is seen on the pin Otherwise it will be done immediatelyFor the CLOCK action the sync option makes the pin generate a single pulse ltWAFEFORM_LOWgt nanoseconds after the time of day has increased the seconds The pulse will get a width of ltWAVEFORM_HIGHgt nanoseconds

PTP_PIN_INV_POL 1 RW Polarity of the PTP pin 0 Active high1 Active low

PTP_PIN_DOM 0 RW Configures the time domain the pin is connected to

Registers

2533 DEVCPU_PTPPTP_PINSPTP_TOD_SEC_LSBParent DEVCPU_PTPPTP_PINS

Instances 1

2534 DEVCPU_PTPPTP_PINSPTP_TOD_NSECParent DEVCPU_PTPPTP_PINS

Instances 1

2535 DEVCPU_PTPPTP_PINSPTP_NSFParent DEVCPU_PTPPTP_PINS

Instances 1

2536 DEVCPU_PTPPTP_PINSPIN_WF_HIGH_PERIODParent DEVCPU_PTPPTP_PINS

Instances 1

Table 216 bull Fields in PTP_TOD_SEC_MSB

Field Name Bit Access Description DefaultPTP_TOD_SEC_MSB 150 RW Bits 4732 of the time-of-day seconds 0x0000

Table 217 bull Fields in PTP_TOD_SEC_LSB

Field Name Bit Access Description DefaultPTP_TOD_SEC_LSB 310 RW Bits 310 of the time-of-day seconds 0x00000000

Table 218 bull Fields in PTP_TOD_NSEC

Field Name Bit Access Description DefaultPTP_TOD_NSEC 290 RW Time Of Day nanoseconds loaded or stored

into TimeOfDay A synced store operation may return a value between -2 and 999999999 in this field To normalize the complete TOD in case field is read 0x3ffffffef software must subtract one from the SEC part and add 1000000000 to the NSEC part

0x00000000

Table 219 bull Fields in PTP_NSF

Field Name Bit Access Description DefaultPTP_NSF 310 RO Value of NSF counter when loadsave action

was executed This value will not be loaded into the timers upon a LOAD operation

0x00000000

Registers

2537 DEVCPU_PTPPTP_PINSPIN_WF_LOW_PERIODParent DEVCPU_PTPPTP_PINS

Instances 1

26 DEVCPU_QS

261 DEVCPU_QSXTRParent DEVCPU_QS

Instances 1

The DEVCPU_QSXTR_GRP_CFG DEVCPU_QSXTR_RD and DEVCPU_QSXTR_FRM_PRUNING registers are replicated once per extraction group Replication index n corresponds to extraction group number n

Table 220 bull Fields in PIN_WF_HIGH_PERIOD

Field Name Bit Access Description DefaultPIN_WFH 290 RW Configure waveform Unit is nanoseconds

EX 25MHz 6040 clock PIN_ACTION=CLOCK PIN_SYNC=0 PIN_WFH=24 PIN_WFL=16EX 1 us pulse after 150 ns PIN_ACTION=CLOCK PIN_SYNC=1 PIN_WFH=1000 PIN_WFL=150

0x00000000

Table 221 bull Fields in PIN_WF_LOW_PERIOD

Field Name Bit Access Description DefaultPIN_WFL 290 RW Configure waveform 0x00000000

Table 222 bull Register Groups in DEVCPU_QS

XTR 0x00000000 1 Frame extraction Page 106

INJ 0x00000024 1 Frame injection Page 109

Table 223 bull Registers in XTR

XTR_GRP_CFG 0x00000000 20x00000004

Extraction group configuration Page 107

Registers

2611 DEVCPU_QSXTRXTR_GRP_CFGParent DEVCPU_QSXTR

Instances 2

XTR_RD 0x00000008 20x00000004

Manual extraction data Page 108

XTR_FRM_PRUNING 0x00000010 20x00000004

Extraction frame pruning Page 108

XTR_FLUSH 0x00000018 1 Extraction group flush Page 108

XTR_DATA_PRESENT 0x0000001C 1 Extraction status Page 109

Table 224 bull Fields in XTR_GRP_CFG

Field Name Bit Access Description DefaultMODE 32 RW Configures mode of the extraction group

Each extraction group can be assigned to one of three ownersNote The VRAP block support only one context if more than one extraction group is assigned the lowest group-number will be used0 VRAP block1 Manual extraction (via DEVCPU_QS registers)2 FDMA extraction and manual extraction via SBA registers

STATUS_WORD_POS 1 RW Select order of last data and status wordsThis field only applies to manual extraction mode (see DEVCPU_QSXTR_GRP_CFGMODE)0 Status just before last data1 Status just after last data

BYTE_SWAP 0 RW This field allows swapping the endianness of DEVCPU_QSXTR_RD Most software will want to read extraction data in network order (big-endian mode) ie the first byte of the destiantion MAC address to be placed on byte-address 0 of DEVCPU_QSXTR_RD In order to do this a little endian CPU must set this field a big endian CPU must clear this fieldThis field only applies to manual extraction mode (see DEVCPU_QSXTR_GRP_CFGMODE)0 Same endianness1 Swap endianness

Table 223 bull Registers in XTR (continued)

Registers

2612 DEVCPU_QSXTRXTR_RDParent DEVCPU_QSXTR

Instances 2

2613 DEVCPU_QSXTRXTR_FRM_PRUNINGParent DEVCPU_QSXTR

Instances 2

2614 DEVCPU_QSXTRXTR_FLUSHParent DEVCPU_QSXTR

Instances 1

Table 225 bull Fields in XTR_RD

Field Name Bit Access Description DefaultDATA 310 RO Frame Data Read from this register to obtain

the next 32 bits of the frame data currently stored in the CPU queue system Each read must check for the special values 0x8000000n 0lt=nlt=7 as described by the encodingNote The encoding is presented in little endian format if swapping is used (see DEVCPU_QSXTR_GRP_CFGBYTE_SWAP) then the special values are swapped as well Ie a little endian CPU using BYTE_SWAP=1 has to look for 0x0n000080 instead of 0x8000000nThe position of the unusedvalid bytes follows the endianness encoding and swappingn=0-3 EOF Unused bytes in end-of-frame word is nn=4 EOF but truncatedn=5 EOF Aborted Frame invalidn=6 Escape Next read is packet datan=7 Data not ready for reading out

0x07000080

Table 226 bull Fields in XTR_FRM_PRUNING

Field Name Bit Access Description DefaultPRUNE_SIZE 70 RW Extracted frames for the corresponding

queue are pruned to (PRUNE_SIZE+1) 32-bit wordsNote PRUNE_SIZE includes the IFH when this present in the frame0 No pruning1 Frames extracted are pruned to 8 bytes2 Frames extracted are pruned to 12 bytes255 Frames extracted are pruned to 1024 bytes

Registers

2615 DEVCPU_QSXTRXTR_DATA_PRESENTParent DEVCPU_QSXTR

Instances 1

262 DEVCPU_QSINJParent DEVCPU_QS

Instances 1

The DEVCPU_QSINJ_GRP_CFG DEVCPU_QSINJ_WR DEVCPU_QSINJ_CTRL and DEVCPU_QSINJ_ERR registers are replicated once per injection group Replication index n corresponds to injection group number n

Table 227 bull Fields in XTR_FLUSH

Field Name Bit Access Description DefaultFLUSH 10 RW Enable software flushing of a CPU queue

Note the queue will continue to be flushed until this field is cleared by SW The flushing will automatically stop on frame boundary so OQS is allowed to transmit to the CPU queue during flushing0 No action1 Do CPU queue flushing

Table 228 bull Fields in XTR_DATA_PRESENT

Field Name Bit Access Description DefaultDATA_PRESENT 10 RO Shows if data is available for a specific

group It remains set until all frame data have been extracted This field is only set if the mode of the group is set to manual extraction via DEVCPU_QS registers0 No frames available for this CPU queue group1 At least one frame is available for this CPU queue group

Table 229 bull Registers in INJ

INJ_GRP_CFG 0x00000000 20x00000004

Injection group configuration Page 110

INJ_WR 0x00000008 20x00000004

Manual injection data Page 110

INJ_CTRL 0x00000010 20x00000004

Injection control Page 111

INJ_STATUS 0x00000018 1 Injection status Page 111

Registers

2621 DEVCPU_QSINJINJ_GRP_CFGParent DEVCPU_QSINJ

Instances 2

2622 DEVCPU_QSINJINJ_WRParent DEVCPU_QSINJ

Instances 2

INJ_ERR 0x0000001C 20x00000004

Injection errors Page 112

Table 230 bull Fields in INJ_GRP_CFG

Field Name Bit Access Description DefaultMODE 32 RW Configures mode of the injection group Each

injection group can be assigned to one of three ownersNote The VRAP block support only one context if more than one injection group is assigned the lowest group-number will be used0 VRAP block1 Manual injection (via DEVCPU_QS registers)2 FDMA injection and manual injection via SBA registers

BYTE_SWAP 0 RW This field allows swapping the endianness of the DEVCPU_QSINJ_WR register Most software will want to write injection data in network order (big-endian mode) ie the first byte of the destiantion MAC address to be placed on byte-address 0 of DEVCPU_QSINJ_WR In order to do this a little endian CPU must set this field a big endian CPU must clear this fieldThis field only applies to manual extraction mode (see DEVCPU_QSINJ_GRP_CFGMODE)0 Same endianness as CPU1 Swap endianness

Table 229 bull Registers in INJ (continued)

Registers

2623 DEVCPU_QSINJINJ_CTRLParent DEVCPU_QSINJ

Instances 2

2624 DEVCPU_QSINJINJ_STATUSParent DEVCPU_QSINJ

Instances 1

Table 231 bull Fields in INJ_WR

Field Name Bit Access Description DefaultDATA 310 RW Frame Write Write to this register inject the

next 32 bits of the frame data currently injected into the chipReading from this register returns 0

0x00000000

Table 232 bull Fields in INJ_CTRL

Field Name Bit Access Description DefaultGAP_SIZE 2421 RW Controls the min-spacing from EOF to SOF

on injected frames the default value emulates the delay of standard preambleIFG setting on a front-port Set this field to zero when injecting with IFH

ABORT 20 One-shot Set to abort the current frame 0x0

EOF 19 One-shot Set to indicate that the next data written to DEVCPU_QsINJ_WR is end-of-frame At the same time as setting this field also set DEVCPU_QSINJ_CTRLVLD_BYTES to indicate the number of valid data bytes in the end-of-frame word

SOF 18 One-shot Set to indicate that the next data written to DEVCPU_QSINJ_WR is start-of-frame

VLD_BYTES 1716 RW Set to indicate how many bytes of the next data written to DEVCPU_QSINJ_WR which are valid This field is only used during end-of-frame words (see DEVCPU_QSINJ_CTRLEOF for more information) The position of the valid bytes follows the endianness encoding and swapping0 All bytes are validn n byte are valid

Registers

2625 DEVCPU_QSINJINJ_ERRParent DEVCPU_QSINJ

Instances 2

27 HSIORegister Collection for Control of Macros (SERDES1G SERDES6G LCPLL)

Table 233 bull Fields in INJ_STATUS

Field Name Bit Access Description DefaultWMARK_REACHED 54 RO Before the CPU injects a frame software

may check if the input queue has reached high watermark If wathermark in the IQS has been reached this bit will be set0 Input queue has not reached high watermark1 Input queue has reached high watermark and frames injected may be dropped due to buffer overflow

FIFO_RDY 32 RO When 1 the injector groups FIFO is ready for additional data written through the DEVCPU_QSINJ_WR register0 The injector group cannot accept additional data1 The injector group is able to accept additional data

INJ_IN_PROGRESS 10 RO When 1 the injector group is in the process of receiving a frame and at least one write to INJ_WR remains before the frame is forwarded to the front ports When 0 the injector group is waiting for an initiation of a frame injection0 A frame injection is not in progress1 A frame injection is in progress

Table 234 bull Fields in INJ_ERR

Field Name Bit Access Description DefaultABORT_ERR_STICKY 1 Sticky Set if a frame has been aborted because of

double-SOF injection (missing EOF)0x0

WR_ERR_STICKY 0 Sticky Set in case of overflow as a result of not obeying FIFO-ready

Registers

271 HSIOPLL5G_CFGParent HSIO

Instances 1

Configuration register set for PLL5G

Table 235 bull Register Groups in HSIO

PLL5G_CFG 0x00000000 1 PLL5G Configuration Registers

PLL5G_STATUS 0x0000001C 1 PLL5G Status Registers Page 114

RCOMP_STATUS 0x0000003C 1 RCOMP Status Registers Page 115

SYNC_ETH_CFG 0x00000040 1 SYNC_ETH Configuration Registers

SERDES1G_ANA_CFG 0x0000004C 1 SERDES1G Analog Configuration Registers

SERDES1G_DIG_CFG 0x00000068 1 SERDES1G Digital Configuration Register

SERDES1G_DIG_STATUS 0x00000080 1 SERDES1G Digital Status Register

MCB_SERDES1G_CFG 0x00000088 1 MCB SERDES1G Configuration Register

SERDES6G_DIG_CFG 0x0000008C 1 SERDES6G Digital Configuration Registers

SERDES6G_ANA_CFG 0x000000BC 1 SERDES6G Analog ConfigStatus Registers

SERDES6G_ANA_STATUS 0x000000F4 1 SERDES6G Analog Status Registers

HW_CFGSTAT 0x0000010C 1 General high-speed IO configuration and status

TEMP_SENSOR 0x0000011C 1 Temperature sensor control Page 144

Table 236 bull Registers in PLL5G_CFG

PLL5G_CFG4 0x00000010 1 PLL5G Configuration 4 Page 114

Registers

2711 HSIOPLL5G_CFGPLL5G_CFG4Parent HSIOPLL5G_CFG

Instances 1

Configuration register 4 for PLL5G

Instances 1

272 HSIOPLL5G_STATUSParent HSIO

Table 237 bull Fields in PLL5G_CFG4

IB_CTRL 150 RW settings for reference clock input buffer[10] sel_vref490m[9] ena_cmv_term[10] ena_ib (not supported in ES6512)[1512] r_adjall other bits reserved

0x7600

Field Name Bit Access Description DefaultREFCLK_SEL_SRC 23 RW Set to enable refclk_sel from

PLL5G_CFG6REFCLK_SEL instead of using external input By default external pins are used for configuring reference clock frequency

REFCLK_SEL 2220 RW select refclk frequency 0 125MHz 1 15625MHz 2 250MHz 3 3125MHz 4 25MHz

REFCLK_SRC 19 RW select internal refclk input buffer or external input

POR_DEL_SEL 1716 RW select POR delay0 500us1 1ms2 4ms3 64ms

RESERVED 50 RW Must be set to its default 0x0E

Registers

Instances 1

Status register set for PLL5G

2721 HSIOPLL5G_STATUSPLL5G_STATUS0Parent HSIOPLL5G_STATUS

Instances 1

Status register 0 for the PLL5G

273 HSIORCOMP_STATUSParent HSIO

Instances 1

Status register set for RCOMP

2731 HSIORCOMP_STATUSRCOMP_STATUSParent HSIORCOMP_STATUS

Instances 1

Status register bits for the RCOMP

Table 239 bull Registers in PLL5G_STATUS

PLL5G_STATUS0 0x00000000 1 PLL5G Status 0 Page 115

Table 240 bull Fields in PLL5G_STATUS0

Field Name Bit Access Description DefaultRANGE_LIM 12 RO RCPLL Flag range limiter signaling 0x0

OUT_OF_RANGE_ERR 11 RO RCPLL Flag that indicates a out of range condition while NOT in calibration mode

CALIBRATION_ERR 10 RO RCPLL Flag that indicates errors that may occur during the calibration procedure

CALIBRATION_DONE 9 RO RCPLL Flag that indicates that the calibration procedure has finished

READBACK_DATA 81 RO RCPLL Interface to read back internal data of the FSM

LOCK_STATUS 0 RO PLL lock status 0 not locked 1 locked 0x0

Table 241 bull Registers in RCOMP_STATUS

RCOMP_STATUS 0x00000000 1 RCOMP Status Page 115

Registers

274 HSIOSYNC_ETH_CFGParent HSIO

Instances 1

2741 HSIOSYNC_ETH_CFGSYNC_ETH_CFGParent HSIOSYNC_ETH_CFG

Instances 2

This register is replicated once per GPIO mapped recovered clock destination

Table 242 bull Fields in RCOMP_STATUS

Field Name Bit Access Description DefaultBUSY 12 RO Resistor comparison activity

0 resistor measurement finished or inactive1 resistor measurement in progress

DELTA_ALERT 7 RO Alarm signal if rcomp isnt best choice anymore0 inactive1 active

RCOMP 30 RO Measured resistor value0 maximum resistance value15 minimum resistance value

Table 243 bull Registers in SYNC_ETH_CFG

SYNC_ETH_CFG 0x00000000 20x00000004

Recovered Clock Configuration

SYNC_ETH_PLL_CFG 0x00000008 1 PLL Recovered Clock Configuration

Table 244 bull Fields in SYNC_ETH_CFG

Field Name Bit Access Description DefaultSEL_RCVRD_CLK_SRC 74 RW Select recovered clock source

0-1 Select recovered CuPHY clock 0 through 12-7 Select SD1G 0 through 58-10 Select SD6G 0 through 211 Select PLL0 referenceOther values are reserved

Registers

2742 HSIOSYNC_ETH_CFGSYNC_ETH_PLL_CFGParent HSIOSYNC_ETH_CFG

Instances 1

275 HSIOSERDES1G_ANA_CFGParent HSIO

Instances 1

Configuration register set for SERDES1G (analog parts)

SEL_RCVRD_CLK_DIV 31 RW Select recovered clock divider0 Divide clock by 21 Divide clock by 42 Divide clock by 83 Divide clock by 164 Divide clock by 55 Divide clock by 256 No clock dividing7 Reserved

RCVRD_CLK_ENA 0 RW Set to enable recovered clock output This field only applies to GPIO mapped clock outputs0 Disable (high-impedance)1 Enable (output recovered clock)

Table 245 bull Fields in SYNC_ETH_PLL_CFG

Field Name Bit Access Description DefaultPLL_AUTO_SQUELCH_ENA 0 RW Enable auto-squelching for sync ethernet

clock output when set the clock output will stop toggling (keep its last value constantly) when PLL is out of lock

Table 246 bull Registers in SERDES1G_ANA_CFG

SERDES1G_DES_CFG 0x00000000 1 SERDES1G Deserializer Cfg Page 118

SERDES1G_IB_CFG 0x00000004 1 SERDES1G Input Buffer Cfg Page 119

SERDES1G_OB_CFG 0x00000008 1 SERDES1G Output Buffer Cfg Page 120

SERDES1G_SER_CFG 0x0000000C 1 SERDES1G Serializer Cfg Page 121

SERDES1G_COMMON_CFG 0x00000010 1 SERDES1G Common Cfg Page 121

SERDES1G_PLL_CFG 0x00000014 1 SERDES1G Pll Cfg Page 122

Table 244 bull Fields in SYNC_ETH_CFG (continued)

Registers

2751 HSIOSERDES1G_ANA_CFGSERDES1G_DES_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for SERDES1G deserializer

Table 247 bull Fields in SERDES1G_DES_CFG

Field Name Bit Access Description DefaultDES_PHS_CTRL 1613 RW Control of phase regulator logic Bit 3 must

be set to 00 Disabled1 Enabled with 99 ppm limit2 Enabled with 202 ppm limit3 Enabled with 485 ppm limit4 Enabled if corresponding PCS is in sync with 50 ppm limit5 Enabled if corresponding PCS is in sync with 99 ppm limit6 Enabled if corresponding PCS is in sync with 202 ppm limit7 Enabled if corresponding PCS is in sync with 485 ppm limit

DES_CPMD_SEL 1211 RW Deserializer phase control main CPMD select0 Directly from DES1 Through hysteresis stage from DES2 From core3 Disabled

DES_MBTR_CTRL 108 RW Des phase control for 180 degrees deadlock block mode of operation0 Depending on density of input pattern1 Active until PCS has synchronized2 Depending on density of input pattern until PCS has synchronized3 Never4 Always5-7 Reserved

DES_BW_ANA 75 RW Bandwidth selection for proportional path of CDR loop0 No division1 Divide by 22 Divide by 43 Divide by 84 Divide by 165 Divide by 326 Divide by 647 Divide by 128

Registers

2752 HSIOSERDES1G_ANA_CFGSERDES1G_IB_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for SERDES1G input buffer

DES_BW_HYST 31 RW Selection of time constant for integrative path of CDR loop0 Divide by 21 Divide by 42 Divide by 83 Divide by 164 Divide by 325 Divide by 646 Divide by 1287 Divide by 256

Table 248 bull Fields in SERDES1G_IB_CFG

Field Name Bit Access Description DefaultIB_FX100_ENA 27 RW Switches signal detect circuit into low

frequency mode must be used in FX100 mode

IB_DET_LEV 2119 RW Detect thresholds0 159-189mVppd1 138-164mVppd2 109-124mVppd3 74-89mVppd

IB_HYST_LEV 14 RW Input buffer hysteresis levels0 59-79mV1 81-124mV

IB_ENA_CMV_TERM 13 RW Enable common mode voltage termination0 Low termination (VDD_A x 07)1 High termination (VDD_A)

IB_ENA_DC_COUPLING 12 RW Enable dc-coupling of input signal0 Disable1 Enable

IB_ENA_DETLEV 11 RW Enable detect level circuit0 Disable1 Enable

IB_ENA_HYST 10 RW Enable hysteresis for input signal Hysteresis can only be enabled if DC offset compensation is disabled0 Disable1 Enable

Table 247 bull Fields in SERDES1G_DES_CFG (continued)

Registers

2753 HSIOSERDES1G_ANA_CFGSERDES1G_OB_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for SERDES1G output buffer

IB_ENA_OFFSET_COMP 9 RW Enable offset compensation of input stage This bit must be disabled to enable hysteresis (IB_ENA_HYST)0 Disable1 Enable

IB_EQ_GAIN 86 RW Selects weighting between AC and DC input path0 Reserved1 Reserved2 0dB (recommended value)3 15dB4 3dB5 6dB6 9dB125dB

IB_SEL_CORNER_FREQ 54 RW Corner frequencies of AC path0 13GHz1 15GHz2 16GHz3 18GHz

RESERVED 30 RW Must be set to its default 0xB

Table 249 bull Fields in SERDES1G_OB_CFG

Field Name Bit Access Description DefaultOB_SLP 1817 RW Slope slew rate control

0 45ps1 85ps2 105ps3 115ps

OB_AMP_CTRL 1613 RW Amplitude control in steps of 50mVppd0 04Vppd15 11Vppd

OB_VCM_CTRL 74 RW Common mode voltage control0 Reserved1 440mV2 480mV3 460mV4 530mV5 500mV6 570mV7 550mV

Table 248 bull Fields in SERDES1G_IB_CFG (continued)

Registers

2754 HSIOSERDES1G_ANA_CFGSERDES1G_SER_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for SERDES1G serializer

2755 HSIOSERDES1G_ANA_CFGSERDES1G_COMMON_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for common SERDES1G functions Note When enabling the facility loop (ena_floop) also the phase alignment in the serializer has to be enabled and configured adequate

Table 250 bull Fields in SERDES1G_SER_CFG

Field Name Bit Access Description DefaultSER_IDLE 9 RW Invert output D0b for idle-mode of OB

0 Non-inverting1 Inverting

SER_DEEMPH 8 RW Invert and delays (one clk cycle) output D1 for de-emphasis of OB0 Non-inverting and non-delaying1 Inverting and delaying

SER_ENHYS 3 RW Enable hysteresis for phase alignment0 Disable hysteresis1 Enable hysteresis

SER_BIG_WIN 2 RW Use wider window for phase alignment0 Use small window for low jitter (100 to 200ps)1 Use wide window for higher jitter (150 to 300 ps)

SER_EN_WIN 1 RW Enable window for phase alignment0 Disable window1 Enable window

SER_ENALI 0 RW Enable phase alignment0 Disable phase alignment1 Enable phase alignment

Table 251 bull Fields in SERDES1G_COMMON_CFG

Field Name Bit Access Description DefaultSYS_RST 31 RW System reset (low active)

0 Apply reset (not self-clearing)1 Reset released

Table 249 bull Fields in SERDES1G_OB_CFG (continued)

Registers

2756 HSIOSERDES1G_ANA_CFGSERDES1G_PLL_CFGParent HSIOSERDES1G_ANA_CFG

Instances 1

Configuration register for SERDES1G RCPLL

276 HSIOSERDES1G_DIG_CFGParent HSIO

Instances 1

Configuration register set for SERDES1G digital BIST and DFT functions

2761 HSIOSERDES1G_DIG_CFGSERDES1G_MISC_CFGParent HSIOSERDES1G_DIG_CFG

SE_AUTO_SQUELCH_ENA 21 RW Enable auto-squelching for sync ethernet clock output when set the clock output will stop toggling (keep its last value constantly) when PCS looses link synchrony0 Disable1 Enable

ENA_LANE 18 RW Enable lane0 Disable lane1 Enable line

ENA_ELOOP 11 RW Enable equipment loop0 Disable1 Enable

ENA_FLOOP 10 RW Enable facility loop0 Disable1 Enable

Table 252 bull Fields in SERDES1G_PLL_CFG

PLL_FSM_CTRL_DATA 158 RW Control data for FSM 0xC8

PLL_FSM_ENA 7 RW Enable FSM 0x0

Table 253 bull Registers in SERDES1G_DIG_CFG

SERDES1G_MISC_CFG 0x00000014 1 SERDES1G Misc Configuration

Table 251 bull Fields in SERDES1G_COMMON_CFG (continued)

Registers

Instances 1

Configuration register for miscellaneous functions

277 HSIOSERDES1G_DIG_STATUSParent HSIO

Instances 1

Status register set for SERDES1G digital BIST and DFT functions

2771 HSIOSERDES1G_DIG_STATUSSERDES1G_DFT_STATUSParent HSIOSERDES1G_DIG_STATUS

Instances 1

Status register of SERDES1G DFT functions

Table 254 bull Fields in SERDES1G_MISC_CFG

Field Name Bit Access Description DefaultDES_100FX_CPMD_ENA 8 RW Enable deserializer cpmd handling for 100fx

mode0 Disable1 Enable

RX_LPI_MODE_ENA 5 RW Enable RX-Low-Power feature (Power control by LPI-FSM in connected PCS)0 Disable1 Enable

TX_LPI_MODE_ENA 4 RW Enable TX-Low-Power feature (Power control by LPI-FSM in connected PCS)0 Disable1 Enable

RX_DATA_INV_ENA 3 RW Enable data inversion received from Deserializer0 Disable1 Enable

TX_DATA_INV_ENA 2 RW Enable data inversion sent to Serializer0 Disable1 Enable

LANE_RST 0 RW Lane Reset0 No reset1 Reset (not self-clearing)

Table 255 bull Registers in SERDES1G_DIG_STATUS

SERDES1G_DFT_STATUS 0x00000000 1 SERDES1G DFT Status Page 123

Registers

278 HSIOMCB_SERDES1G_CFGParent HSIO

Instances 1

All SERDES1G macros are accessed via the serial Macro Configuration Bus (MCB) Each macro is configured by one MCB slave All MCB slaves are connected in a daisy-chain loop

2781 HSIOMCB_SERDES1G_CFGMCB_SERDES1G_ADDR_CFGParent HSIOMCB_SERDES1G_CFG

Instances 1

Configuration of SERDES1G MCB slaves to be accessed

Table 256 bull Fields in SERDES1G_DFT_STATUS

Field Name Bit Access Description DefaultBIST_NOSYNC 2 RO BIST sync result

0 Synchronization successful1 Synchronization on BIST data failed

Table 257 bull Registers in MCB_SERDES1G_CFG

MCB_SERDES1G_ADDR_CFG 0x00000000 1 MCB SERDES1G Address Cfg

Table 258 bull Fields in MCB_SERDES1G_ADDR_CFG

Field Name Bit Access Description DefaultSERDES1G_WR_ONE_SHOT 31 One-shot Initiate a write access to marked SERDES1G

slaves0 No write operation pending1 Initiate write to slaves (kept 1 until write operation has finished)

SERDES1G_RD_ONE_SHOT 30 One-shot Initiate a read access to marked SERDES1G slaves0 No read operation pending (read op finished after bit has been set)1 Initiate a read access (kept 1 until read operation has finished)

SERDES1G_ADDR 80 RW Activation vector for SERDES1G-Slaves one-hot coded each bit is related to one macro eg bit 0 enablesdisables access to macro no 00 Disable macro access via MCB1 Enable macro access via MCB

Registers

Instances 1

2791 HSIOSERDES6G_DIG_CFGSERDES6G_DIG_CFGParent HSIOSERDES6G_DIG_CFG

Instances 1

Configuration register for SERDES6G digital functions

Instances 1

SERDES6G_DIG_CFG 0x00000000 1 SERDES6G Digital Configuration register

SERDES6G_MISC_CFG 0x0000001C 1 SERDES6G Misc Configuration

Table 260 bull Fields in SERDES6G_DIG_CFG

Field Name Bit Access Description DefaultSIGDET_AST 53 RW Signal detect assertion time

0 0 us1 35 us2 70 us3 105 us4 140 us57 reserved

SIGDET_DST 20 RW Signal detect deassertion time0 0 us1 250 us2 350 us3 450 us4 550 us57 reserved

Registers

Instances 1

Field Name Bit Access Description DefaultSEL_RECO_CLK 1413 RW Select recovered clock divider

0 No clock dividing1 Divide clock by 52 Divide clock by 43 Reserved

DES_100FX_CPMD_ENA 8 RW Enable deserializer cpmd handling for 100fx mode0 Disable1 Enable

RX_BUS_FLIP_ENA 7 RW Enable flipping rx databus (MSB - LSB) 0x0

TX_BUS_FLIP_ENA 6 RW Enable flipping tx databus (MSB - LSB) 0x0

SERDES6G_IB_CFG 0x00000004 1 SERDES6G IB Configuration register 0

SERDES6G_IB_CFG1 0x00000008 1 SERDES6G IB Configuration register 1

Registers

Instances 1

SERDES6G_IB_CFG2 0x0000000C 1 SERDES6G IB Configuration register 2

SERDES6G_OB_CFG 0x0000001C 1 SERDES6G Output Buffer Cfg 0

SERDES6G_OB_CFG1 0x00000020 1 SERDES6G Output Buffer Cfg1

SERDES6G_SER_CFG 0x00000024 1 SERDES6G Serializer Cfg Page 135

SERDES6G_PLL_CFG 0x0000002C 1 SERDES6G Pll Cfg Page 137

SERDES6G_ACJTAG_CFG 0x00000030 1 SERDES6G ACJTAG Cfg Page 138

Field Name Bit Access Description DefaultDES_PHS_CTRL 1613 RW Control of phase regulator logic (bit 3 selects

input to integrator block - 0 cpmd from DES 1 cpmd from core)0 Disabled1 Enabled with 99 ppm limit2 Enabled with 202 ppm limit3 Enabled with 485 ppm limit4 Enabled if corresponding PCS is in sync with 50 ppm limit5 Enabled if corresponding PCS is in sync with 99 ppm limit6 Enabled if corresponding PCS is in sync with 202 ppm limit7 Enabled if corresponding PCS is in sync with 485 ppm limit

Table 262 bull Registers in SERDES6G_ANA_CFG (continued)

Registers

Instances 1

Configuration settings 0

DES_MBTR_CTRL 1210 RW Des phase control for 180 degrees deadlock block mode of operation000 Depending on density of input pattern001 Active until PCS has synchronized010 Depending on density of input pattern until PCS has synchronized011 Never100 Always111 Debug feature Add cpmd of DES and cpmd from core

DES_CPMD_SEL 98 RW DES phase control main cpmd select00 Directly from DES01 Through hysteresis stage from DES10 From core11 Disabled

DES_BW_HYST 75 RW Bandwidth selection Selects dividing factor for hysteresis CPMD outputs0 Divide by 21 Divide by 42 Divide by 83 Divide by 164 Divide by 325 Divide by 646 Divide by 1287 Divide by 256

DES_BW_ANA 31 RW Bandwidth selection Selects dividing factor for non-hysteresis CPMD outputs0 No division1 Divide by 22 Divide by 43 Divide by 84 Divide by 165 Divide by 326 Divide by 647 Divide by 128

Field Name Bit Access Description DefaultIB_SOFSI 3029 RW Select location of offset correction inside

equalizer0 No offset correction1 First stage (preferred)2 Last stage3 First and last stage

Registers

IB_VBULK_SEL 28 RW Controls Bulk Voltage of High Speed Cells0 Reserved1 Low (mission mode)

IB_RTRM_ADJ 2724 RW Resistance adjustment for termination and CML cell regulationThis configuration defines an offset (2-complement) to the RCOMP valueThe effective value is limited between 0 to 157 RCOMP+71 RCOMP+10 RCOMP15 RCOMP-18 RCOMP -8

IB_ICML_ADJ 2320 RW Current adjustment for CML cells0 low current1 high current

IB_TERM_MODE_SEL 1918 RW Select common mode termination voltage

0 Open - recommended mission mode for DC-coupling1 VCM ref - recommended mission mode for AC-coupling2 VDD - used to increase amplitude in certain DC-coupled modes3 capacitance only - Reserved for debug test purpose

IB_SIG_DET_CLK_SEL 1715 RW Select signal detect clock Frequency = 125 MHz 2nSet to 0 for ATE testing (reduces test-time)Set to 7 for optimized performance in mission mode

IB_REG_PAT_SEL_HP 1413 RW Selects pattern detection for regulation of high-pass-gain0 Only regulation assessment if basic pattern is detected1 Regulation assessment if basic and simplified pattern are detected2 Regulation assessment if basic and critical pattern are detected3 Regulation assessment if simplified basic and critical pattern are detected

IB_REG_PAT_SEL_MID 1211 RW Selects pattern detection for regulation of mid-pass-gain0 Only regulation assessment if basic pattern is detected1 Regulation assessment if basic and simplified pattern are detected2 Regulation assessment if basic and critical pattern are detected3 Regulation assessment if simplified basic and critical pattern are detected

Registers

IB_REG_PAT_SEL_LP 109 RW Selects pattern detection for regulation of low-pass-gain0 Only regulation assessment if basic pattern is detected1 Regulation assessment if basic and simplified pattern are detected2 Regulation assessment if basic and critical pattern are detected3 Regulation assessment if simplified basic and critical pattern are detected

IB_REG_PAT_SEL_OFFSET 87 RW Selects pattern detection for regulation of offset0 Only regulation assessment if basic pattern is detected1 Regulation assessment if basic and simplified pattern are detected2 Regulation assessment if basic and critical pattern are detected3 Regulation assessment if simplified basic and critical pattern are detected

IB_ANA_TEST_ENA 6 RW Enable analog test output0 Disable1 Enable

IB_SIG_DET_ENA 5 RW Enable signal detection0 Disable1 Enable

IB_CONCUR 4 RW Selection between constant current and constant resistor mode for CML cells0 Constant resistor mode1 Constant current mode

IB_CAL_ENA 3 RW Enable calibrationIB calibration should be started after SERDES6G_COMMON_CFGENA_LANE was set to 1Calibration procedure takes up to 1sec depending on configuration of SERDES6G_IB_CFGIB_SIG_DET_CLK_SELMax- calibration time is for SERDES6G_IB_CFGIB_SIG_DET_CLK_SEL set to 70 Disable1 Enable (mission mode)

IB_SAM_ENA 2 RW Enable SAMpling stage0 Disable1 Enable (mission mode)

IB_EQZ_ENA 1 RW Enable EQualiZation-Stage0 Disable1 Enable (mission mode)

Registers

27103 HSIOSERDES6G_ANA_CFGSERDES6G_IB_CFG1Parent HSIOSERDES6G_ANA_CFG

Instances 1

IB_REG_ENA 0 RW Enable equalizer REGulation stage0 Disable1 Enable (mission mode)

Table 265 bull Fields in SERDES6G_IB_CFG1

Field Name Bit Access Description DefaultIB_TJTAG 2117 RW Selects threshold voltage for ac-jtag Voltage

= (n + 1) 20 mV0x08

IB_TSDET 1612 RW Selects threshold voltage for signal detect Voltage = (n + 1) 20 mV

IB_SCALY 118 RW Selects number of calibration cycles for equalizer sampling stage signal-detect and AC-JTAG comparator BIAS0 no calibration --gt neutral values are used

IB_FILT_HP 7 RW Selects doubled filtering of high-pass-gain regulation or set it to hold if ib_frc_hp = 1

IB_FILT_MID 6 RW Selects doubled filtering of mid-pass-gain regulation or set it to hold if ib_frc_mid = 1

IB_FILT_LP 5 RW Selects doubled filtering of low-pass-gain regulation or set it to hold if ib_frc_lp = 1

IB_FILT_OFFSET 4 RW Selects doubled filtering of offset regulation or set it to hold if ib_frc_offset = 1

IB_FRC_HP 3 RW Selects manual control for high-pass-gain regulation if enabled

IB_FRC_MID 2 RW Selects manual control for mid-pass-gain regulation if enabled

IB_FRC_LP 1 RW Selects manual control for low-pass-gain regulation if enabled

IB_FRC_OFFSET 0 RW Selects manual control for offset regulation if enabled

Registers

Instances 1

Field Name Bit Access Description DefaultIB_TINFV 2927 RW Selects maximum threshold influence for

threshold calibration of VScope samplers 0 40mV1 80mV

IB_OINFI 2622 RW Selects maximum offset influence for offset regulation0 10mV1 20mV

IB_OINFS 1816 RW Selects maximum offset influence for offset calibration of main samplers0 40mV1 80mV

IB_OCALS 1510 RW Selects offset voltage for main sampler calibration 0 -70mV 31 -0mV32 +0mV 63 70mV

IB_TCALV 95 RW Selects threshold voltage for VScope sampler calibration0 10mV1 20mV

IB_UMAX 43 RW Tunes common mode voltage to adapt to max voltage of input signal0 320mVppd1 480mVppd2 640mVppd (recommended for mission mode)3 800mVppd

IB_UREG 20 RW 0dB regulation voltage for high-speed-cells

0 160mV1 180mV2 200mV3 220mV4 240mV (recommended for mission mode)5 260mV6 280mV7 300mV

Registers

Instances 1

Configuration register 0 for SERDES6G output buffer

Field Name Bit Access Description DefaultIB_INI_HP 2318 RW Init force value for high-pass gain regulation 0x00

IB_INI_MID 1712 RW Init force value for mid-pass gain regulation 0x1F

IB_INI_LP 116 RW Init force value for low-pass gain regulation 0x01

IB_INI_OFFSET 50 RW Init force value for offset gain regulation 0x1F

Field Name Bit Access Description DefaultIB_MAX_HP 2318 RW Max value for high-pass gain regulation 0x3F

IB_MAX_MID 1712 RW Max value for mid-pass gain regulation 0x3F

IB_MAX_LP 116 RW Max value for low-pass gain regulation 0x02

IB_MAX_OFFSET 50 RW Max value for offset gain regulation 0x3F

Field Name Bit Access Description DefaultIB_MIN_HP 2318 RW Min value for high-pass gain regulation 0x00

IB_MIN_MID 1712 RW Min value for mid-pass gain regulation 0x00

IB_MIN_LP 116 RW Min value for low-pass gain regulation 0x00

IB_MIN_OFFSET 50 RW Min value for offset gain regulation 0x00

Registers

27109 HSIOSERDES6G_ANA_CFGSERDES6G_OB_CFG1Parent HSIOSERDES6G_ANA_CFG

Instances 1

Field Name Bit Access Description DefaultOB_IDLE 31 RW PCIe support

1 idle - force to 0V differential0 Normal mode

OB_ENA1V_MODE 30 RW Output buffer supply voltage1 Set to nominal 1V0 Set to higher voltage

OB_POL 29 RW Polarity of output signal0 Normal1 Inverted

OB_POST0 2823 RW Coefficients for 1st Post Cursor (MSB is sign) 0x00

OB_PREC 2218 RW Coefficients for Pre Cursor (MSB is sign) 0x00

OB_POST1 1511 RW Coefficients for 2nd Post Cursor (MSB is sign)

OB_SR_H 8 RW Half the predriver speed use for slew rate control0 Disable - slew rate lt 60 ps1 Enable - slew rate gt 60 ps

OB_SR 74 RW Driver speed fine adjustment of slew rate 30-60ps (if OB_SR_H = 0) 60-140ps (if OB_SR_H = 1)

LSB is not used

000x ~30ps60ps111x ~60ps140ps

OB_RESISTOR_CTRL 30 RW Resistance adjustment for termination and CML cell regulationThis configuration defines an offset (2-complement) to the RCOMP valueThe effective value is limited between 0 to 157 RCOMP+71 RCOMP+10 RCOMP15 RCOMP-18 RCOMP -8

Registers

Instances 1

Configuration register for common SERDES6G functions

Table 271 bull Fields in SERDES6G_OB_CFG1

Field Name Bit Access Description DefaultOB_ENA_CAS 86 RW Output skew used for skew adjustment in

SGMII mode - 1bit-hot-coded000 Non-SGMII1Gbps modes001 Lowest skew010 SGMII1Gbps mode100 Highest skewAll other settings Reserved

OB_LEV 50 RW Level of output amplitudefor 1V mode max ~48for 12V mode max 630 lowest level63 highest level

Field Name Bit Access Description DefaultSER_ALISEL 54 RW Select reference clock source for phase

alignment

00 RXCLKP (for facility loop mode)01 RefClk15MHz (for XAUIRXAUI)10 RXCLKN (debug)11 ext ALICLK (debug)

SER_ENALI 0 RW Enable phase alignment0 Disable phase alignment1 Enable phase alignment (required for MLD-modes - XAUIRXAUI - and facility loop mode)

Registers

Should be set after SERDES6G_COMMON_CFGENA_LANE was set to 10 Apply reset (not self-clearing)1 Reset released (mission mode)

SE_DIV2_ENA 16 RW Set to enable local divide-by-2 for sync ethernet clock output

ENA_FLOOP 6 RW Enable facility loop

SERDES6G_SER_CFGSER_ENALI must be set to 1SERDES6G_SER_CFGSER_ALISEL must be set to 00 Disable1 Enable

HRATE 3 RW Enable half rate

Baudrate configuration is controlled bySERDES6G_PLL_CFGPLL_DIV4SERDES6G_PLL_CFGPLL_ROT_FRQSERDES6G_PLL_CFGPLL_ROT_DIRSERDES6G_PLL_CFGPLL_ENA_ROTSERDES6G_COMMON_CFGIF_MODESERDES6G_COMMON_CFGHRATESERDES6G_COMMON_CFGQRATE

0 Disable1 Enable

Registers

Instances 1

QRATE 2 RW Enable quarter rate

0 Disable1 Enable

IF_MODE 10 RW Interface mode

0 8-bit mode1 10-bit mode2 16-bit mode3 20-bit mode

Field Name Bit Access Description DefaultPLL_ENA_OFFS 1716 RW Enable offset compensation B1 Feedback

path B0 VCO0x3

PLL_DIV4 15 RW Enable div4 mode

Registers

271013 HSIOSERDES6G_ANA_CFGSERDES6G_ACJTAG_CFGParent HSIOSERDES6G_ANA_CFG

PLL_ENA_ROT 14 RW Enable rotation

PLL_FSM_CTRL_DATA 136 RW Control data for PLL-FSM

Encoding below are only examples for some modes

60 SGMII1G-Modes48 XAUI25Gbps96 RXAUI120 QSGMII

PLL_ROT_DIR 1 RW Select rotation direction

PLL_ROT_FRQ 0 RW Select rotation frequency

Table 274 bull Fields in SERDES6G_PLL_CFG (continued)

Registers

Instances 1

Configuration register for (AC)JTAG debug capability

2711 HSIOSERDES6G_ANA_STATUSParent HSIO

Instances 1

Status register set for SERDES6G (analog parts)

27111 HSIOSERDES6G_ANA_STATUSSERDES6G_IB_STATUS0Parent HSIOSERDES6G_ANA_STATUS

Instances 1

Status register for Signal Detect

Table 275 bull Fields in SERDES6G_ACJTAG_CFG

Field Name Bit Access Description DefaultACJTAG_INIT_DATA_N 5 RW ACJTAG init data for n leg 0x0

ACJTAG_INIT_DATA_P 4 RW ACJTAG init data for p leg 0x0

ACJTAG_INIT_CLK 3 RW ACJTAG clock line 0x0

OB_DIRECT 2 RW JTAG direct output (directly driven) 0x0

ACJTAG_ENA 1 RW ACJTAG enable (ac_mode) 0x0

JTAG_CTRL_ENA 0 RW Enable JTAG control via CSR0 External controlled1 CSR controlled

Table 276 bull Registers in SERDES6G_ANA_STATUS

SERDES6G_IB_STATUS0 0x00000000 1 SERDES6G IB Status register 0

SERDES6G_ACJTAG_STATUS 0x00000008 1 SERDES6G ACJTAG Status Page 140

SERDES6G_PLL_STATUS 0x0000000C 1 SERDES6G Pll Status Page 141

SERDES6G_REVID 0x00000010 1 SERDES6G REVID Page 141

Table 277 bull Fields in SERDES6G_IB_STATUS0

Field Name Bit Access Description DefaultIB_CAL_DONE 8 RO Signals mission mode after calibration was

done0x0

Registers

Instances 1

Regulation stage status register

27113 HSIOSERDES6G_ANA_STATUSSERDES6G_ACJTAG_STATUSParent HSIOSERDES6G_ANA_STATUS

Instances 1

Status register of (AC)JTAG debug capability

IB_HP_GAIN_ACT 7 RO Flag high-pass-gain regulation activity Caution currently this signal is generated with a clock of datarate16 and NOT captured (sticky)

IB_MID_GAIN_ACT 6 RO Flag mid-pass-gain regulation activity Caution currently this signal is generated with a clock of datarate16 and NOT captured (sticky)

IB_LP_GAIN_ACT 5 RO Flag low-pass-gain regulation activity Caution currently this signal is generated with a clock of datarate16 and NOT captured (sticky)

IB_OFFSET_ACT 4 RO Flag offset regulation activity Caution currently this signal is generated with a clock of datarate16 and NOT captured (sticky)

IB_OFFSET_VLD 3 RO Valid average data of calibration process at ib_offset_stat available

IB_OFFSET_ERR 2 RO Overflow error during calibration process Value at ib_offset_stat not valid

IB_OFFSDIR 1 RO Detection of offset direction in selected (ib_offsx) sampling channels

IB_SIG_DET 0 RO Detection of toggling signal at PADP and PADN

Field Name Bit Access Description DefaultIB_HP_GAIN_STAT 2318 RO Current high-pass-gain regulation value 0x00

IB_MID_GAIN_STAT 1712 RO Current mid-pass-gain regulation value 0x00

IB_LP_GAIN_STAT 116 RO Current low-pass-gain regulation value 0x00

IB_OFFSET_STAT 50 RO Current offset regulation value 0x00

Table 277 bull Fields in SERDES6G_IB_STATUS0 (continued)

Registers

27114 HSIOSERDES6G_ANA_STATUSSERDES6G_PLL_STATUSParent HSIOSERDES6G_ANA_STATUS

Instances 1

Status register of SERDES6G RCPLL

27115 HSIOSERDES6G_ANA_STATUSSERDES6G_REVIDParent HSIOSERDES6G_ANA_STATUS

Instances 1

Revision ID register

Table 279 bull Fields in SERDES6G_ACJTAG_STATUS

Field Name Bit Access Description DefaultACJTAG_CAPT_DATA_N 2 RO ACJTAG captured data for n leg 0x0

ACJTAG_CAPT_DATA_P 1 RO ACJTAG captured data for p leg 0x0

IB_DIRECT 0 RO JTAG direct input (directly driven) 0x0

Table 280 bull Fields in SERDES6G_PLL_STATUS

Field Name Bit Access Description DefaultPLL_CAL_NOT_DONE 10 RO Calibration status

0 Calibration not started or ongoing1 Calibration finished

PLL_CAL_ERR 9 RO Calibration error0 No error during calibration1 Errors occurred during calibration

PLL_OUT_OF_RANGE_ERR 8 RO Out of range error0 No out of range condition detected1 Out of range condition since last calibration detected

PLL_RB_DATA 70 RO PLL read-back data depending on pll_rb_data_sel either the calibrated setting or the measured period

Table 281 bull Fields in SERDES6G_REVID

Field Name Bit Access Description DefaultSERDES_REV 3126 RO Serdes revision 0x00

RCPLL_REV 2521 RO RCPLL revision 0x00

SER_REV 2016 RO SER revision 0x00

DES_REV 1510 RO DES revision 0x00

OB_REV 95 RO OB revision 0x00

IB_REV 40 RO IB revision 0x00

Registers

Instances 1

All SERDES6G macros are accessed via the serial Macro Configuration Bus (MCB) Each macro is configured by one MCB Slave All MCB Slaves are connected in a daisy-chain loop

Instances 1

Configuration of SERDES6G MCB Slaves to be accessed

2713 HSIOHW_CFGSTATParent HSIO

Instances 1

Slaves0 No write operation pending1 Initiate write to slaves (kept 1 until write operation has finished)

SERDES6G_RD_ONE_SHOT 30 One-shot Initiate a read access to marked SERDES6G Slaves0 No read operation pending (read op finished after bit has been set)1 Initiate a read access (kept 1 until read operation has finished)

0x1FFFFFF

Registers

27131 HSIOHW_CFGSTATHW_CFGParent HSIOHW_CFGSTAT

Instances 1

27132 HSIOHW_CFGSTATHW_QSGMII_CFGParent HSIOHW_CFGSTAT

Instances 1

Table 284 bull Registers in HW_CFGSTAT

HW_CFG 0x00000000 1 Various configration Page 143

HW_QSGMII_CFG 0x00000004 1 Additional configuration for QSGMII channels

HW_QSGMII_STAT 0x00000008 1 Additional status from QSGMII channels

Table 285 bull Fields in HW_CFG

Field Name Bit Access Description DefaultPCIE_ENA 1 RW Set to enable PCIe mode for SerDes6G_2

0 Disable PCIE1 Enable PCIE

Table 286 bull Fields in HW_QSGMII_CFG

Field Name Bit Access Description DefaultSHYST_DIS 3 RW Set to disable hysteresis of receive

synchronization state machine This setting applies to all QSGMII channels

E_DET_ENA 2 RW Set to enable 8b10b receive error propagation 8b10b error code-groups are replaced by K707 error symbols This setting applies to all QSGMII channels

USE_I1_ENA 1 RW Set to transmit I1 during idle sequencing only This setting applies to all QSGMII channels

FLIP_LANES 0 RW Set to flip QSGMII lanes Lane 0 is interchanged with 3 and 1 is interchanged with 2 for both receie and transmit directions Each bit in this field correspond to a QSGMII channel bit 0 configures QSGMII0 bit 1 configures QSGMII1 etc

Registers

27133 HSIOHW_CFGSTATHW_QSGMII_STATParent HSIOHW_CFGSTAT

Instances 1

2714 HSIOTEMP_SENSORParent HSIO

Instances 1

Controls the temperature sensor readout

27141 HSIOTEMP_SENSORTEMP_SENSOR_CTRLParent HSIOTEMP_SENSOR

Instances 1

Table 287 bull Fields in HW_QSGMII_STAT

Field Name Bit Access Description DefaultDELAY_VAR_X200PS 61 RO Variable delay in QSGMII ingress path

provided in steps of 200ps values 0 though 39 is possible allowing a span from 0ns to 78ns Each replication of this register correspond to a QSGMII channel replication 0 is from QSGMII0 replication 1 is from QSGMII1 etcThe value for a QSGMII channel is valid when it has synchronized to an incoming QSGMII signal and will remain constant while the channel stays in sync

SYNC 0 RO Set when QSGMII channel has successfully synchronized on K281 code-group this field is only valid when HSIOHW_QSGMII_CFGSHYST_DIS is 0

Table 288 bull Registers in TEMP_SENSOR

TEMP_SENSOR_CTRL 0x00000000 1 Temperature Sensor Control Page 144

TEMP_SENSOR_STAT 0x00000008 1 Temperature Sensor Status Page 145

Registers

27142 HSIOTEMP_SENSORTEMP_SENSOR_STATParent HSIOTEMP_SENSOR

Instances 1

28 ICPU_CFG

Table 289 bull Fields in TEMP_SENSOR_CTRL

Field Name Bit Access Description DefaultSAMPLE_ENA 0 RW Set this field to enable sampling of

temperature Approximately 200us after setting this field HSIOTEMP_SENSOR_STATTEMP_VALID will be set together with a valid temperature value After this the temperature will be updated every 500us for as long as this field remains set Clear to disable temperature sensor

Table 290 bull Fields in TEMP_SENSOR_STAT

Field Name Bit Access Description DefaultTEMP_VALID 8 RO This fied is set when valid temperature data

is available in HSIOTEMP_SENSOR_STATTEMP

TEMP 70 RO Temperature data readout this field is valid when HSIOTEMP_SENSOR_STATTEMP_VALID is set This field is continually updated while the termperature sensor is enabled see HSIOTEMP_SENSOR_CTRLSAMPLE_ENA for more informationTemperature(C)=1774 - 08777DATA

Table 291 bull Register Groups in ICPU_CFG

CPU_SYSTEM_CTRL 0x00000000 1 Configurations for the CPU system

SPI_MST 0x0000003C 1 SPI boot master Page 149

MPU8051 0x00000054 1 Configurationstatus for the 8051

INTR 0x00000070 1 Interrupt controller Page 154

TIMERS 0x000000E4 1 Timers Page 164

TWI_DELAY 0x00000198 1 TWI hold time configuration Page 167

Registers

281 ICPU_CFGCPU_SYSTEM_CTRLParent ICPU_CFG

Instances 1

2811 ICPU_CFGCPU_SYSTEM_CTRLGPRParent ICPU_CFGCPU_SYSTEM_CTRL

Instances 8

2812 ICPU_CFGCPU_SYSTEM_CTRLRESETParent ICPU_CFGCPU_SYSTEM_CTRL

Instances 1

TWI_SPIKE_FILTER 0x0000019C 1 TWI spike filter configuration Page 167

FDMA 0x000001A0 1 Frame DMA Page 168

PCIE 0x00000364 1 PCIe endpoint Page 180

MANUAL_XTRINJ 0x00004000 1 Manual extraction and injection via FDMA

Table 292 bull Registers in CPU_SYSTEM_CTRL

GPR 0x00000000 80x00000004

General Purpose Register Page 146

RESET 0x00000020 1 Reset Settings Page 146

GENERAL_CTRL 0x00000024 1 General control Page 147

GENERAL_STAT 0x00000028 1 General status Page 148

Field Name Bit Access Description DefaultGPR 310 RW General purpose 8 times 32-bit registers for

software development and debugNote This register is only reset by the devices reset input ie it is not affected by soft reset

0x00000000

Table 291 bull Register Groups in ICPU_CFG (continued)

Registers

2813 ICPU_CFGCPU_SYSTEM_CTRLGENERAL_CTRLParent ICPU_CFGCPU_SYSTEM_CTRL

Instances 1

Table 294 bull Fields in RESET

Field Name Bit Access Description DefaultCORE_RST_CPU_ONLY 3 RW Set this field to enable VCore System reset

protection It is possible to protect the VCore System from soft-reset (issued via RESETCORE_RST_FORCE) and watchdog-timeout When this field is set the aforementioned resets only reset the VCore CPU not the VCore System0 Soft-reset and WDT-event and reset entire VCore1 Soft-reset and WDT-event only reset the VCore CPU

CORE_RST_PROTECT 2 RW Set this field to enable VCore reset protection It is possible to protect the entire VCore from chip-level soft-reset (issued via DEVCPU_GCBSOFT_RSTSOFT_CHIP_RST) Setting this field does not protect agains hard-reset of the chip (by asserting the reset pin)0 No reset protection1 VCore is protected from chip-level-soft-reset

CORE_RST_FORCE 1 One-shot Set this field to generate a soft reset for the VCore This field will be cleared when the reset has taken effectIt is possible to protect the VCore system (everything else than the VCore CPU) from reset via RESETCORE_RST_CPU_ONLY0 VCore is not reset1 Initiate soft reset of the VCore

Table 295 bull Fields in GENERAL_CTRL

Field Name Bit Access Description DefaultIF_MIIM_SLV_ADDR_SEL 10 RW MIIM slave address when MIIM slave

interface is enabled0 Address 01 Address 31

IF_MIIM_SLV_ENA 9 RW The default value of this field depends on strapping of the VCoreSet this field to enable the MIIM slave-interface on the GPIOs

Registers

2814 ICPU_CFGCPU_SYSTEM_CTRLGENERAL_STATParent ICPU_CFGCPU_SYSTEM_CTRL

Instances 1

IF_SI_OWNER 54 RW The default value of this field depends on strapping of the VCore Select the owner of the dedicated SI interface Note if the SI slave is not owner of this interface it is not possible for an external CPU to access registers in the chip via the dedicated SI interfaceIt is possible for VCore CPU to boot via SI and then change overship to either SI Slave or SI Master Controller00 SI Slave01 SI Boot Master10 SI Master Controller

SIMC_SSP_ENA 3 RW Hooked up to the master contention input (ss_in_n) of the SPI Master block

CPU_DIS 1 RW The default value of this field depends on strapping of the VCoreClear this field to allow booting of the VCore CPU while this field is set the VCore CPU is held in reset0 VCore CPU is allowed to boot1 VCore CPU is forced in reset

BOOT_MODE_ENA 0 RW Use this field to change from Boot mode to Normal mode In Boot mode the reset vector of the VCore CPU maps to CS0 on the FLASH interface When in Normal mode this address maps instead to the DRAM Controller The DRAM Controller must be operational before disabling Boot modeAfter setting Boot mode this register must be read back The change in Boot mode takes effect during read0 The VCore memory map is in Normal mode1 The VCore memory map is in Boot mode

Table 296 bull Fields in GENERAL_STAT

Field Name Bit Access Description DefaultVCORE_CFG 74 RO Shows the value of the VCore Cfg strapping

inputs0x0

Table 295 bull Fields in GENERAL_CTRL (continued)

Registers

282 ICPU_CFGSPI_MSTParent ICPU_CFG

Instances 1

2821 ICPU_CFGSPI_MSTSPI_MST_CFGParent ICPU_CFGSPI_MST

Instances 1

REG_IF_ERR 31 RO Debug information for checking register readwrite problems This is a read-only field which can only be cleared by reset of the VCore System0 No errors detected1 Non-32bit access to VCore or SwC registers access has been discarded read returns 0x8888 or 0x882 SwC registers not ready when accessed access has been discarded read returns 0x888888883 SwC registers reported error check DEVCPU_ORGERR_CNTS for error read returns 0x888888884 Unimplemented VCore register access has been discarded read returns 0x88888888

CPU_SLEEP 0 RO This field is set if the VCore CPU has entered sleep mode

Table 297 bull Registers in SPI_MST

SPI_MST_CFG 0x00000000 1 SPI boot master configuration Page 149

SW_MODE 0x00000014 1 Manual control of the SPI interface

Table 298 bull Fields in SPI_MST_CFG

Field Name Bit Access Description DefaultA32B_ENA 11 RW Set to enable 32bit address mode In 32bit

addressing mode only CS0 is used the SPI address region is limited to 256MByte reserved for the SI interface0 Use 24bit addressing with 4 different CS1 Use 32bit addressing on CS0 max 256MByte

Table 296 bull Fields in GENERAL_STAT (continued)

Registers

2822 ICPU_CFGSPI_MSTSW_MODEParent ICPU_CFGSPI_MST

Instances 1

Note There are 4 chip selects in total but only chip select 0 is mapped to IO-pin (SI_nEn) The rest of the SPI chip selects are available as alternate functions on GPIOs these must be enabled in the GPIO controller before they can be controlled via this register

FAST_READ_ENA 10 RW The type of read-instruction that the SPI Controller generates for reads0 READ (slow read - Instruction code - 0x03)1 FAST READ (fast read - Instruction code - 0x0B)

CS_DESELECT_TIME 95 RW The minimum number of SPI clock cycles for which the SPI chip select (SI_nEn) must be deasserted in between transfers Typical value of this is 100 ns Setting this field to 0 is illegal

CLK_DIV 40 RW Controls the clock frequency for the SPI interface (SI_Clk) The clock frequency is VCore system clock divided by the value of this field Setting this field to 0 or 1 value is illegalThe SPI interface frequency is 250MHzCLK_DIV

Table 299 bull Fields in SW_MODE

Field Name Bit Access Description DefaultSW_PIN_CTRL_MODE 13 RW Set to enable software pin control mode (Bit

banging) when set software has direct control of the SPI interfaceThis mode is used for writing into flash

SW_SPI_SCK 12 RW Value to drive on SI_Clk output This field is only used if SW_MODESW_PIN_CTRL_MODE is set

SW_SPI_SCK_OE 11 RW Set to enable drive of SI_Clk output This field is only used if SW_MODESW_PIN_CTRL_MODE is set

SW_SPI_SDO 10 RW Value to drive on SI_DO output This field is only used if SW_MODESW_PIN_CTRL_MODE is set

SW_SPI_SDO_OE 9 RW Set to enable drive of SI_DO output This field is only used if SW_MODESW_PIN_CTRL_MODE is set

Table 298 bull Fields in SPI_MST_CFG (continued)

Registers

283 ICPU_CFGMPU8051Parent ICPU_CFG

Instances 1

2831 ICPU_CFGMPU8051MPU8051_STATParent ICPU_CFGMPU8051

Instances 1

These read only fields can be used for debugging 8051 programs

SW_SPI_CS 85 RW Value to drive on SI_nEn outputs each bit in this field maps to a corresponding chip-select (0 though 3) This field is only used if SW_MODESW_PIN_CTRL_MODE is setNote Chip selects 1 though 3 are available as alternate GPIO functions

SW_SPI_CS_OE 41 RW Set to enable drive of SI_nEn outputs each bit in this field maps to a corresponding chip-select (0 though 3) This field is only used if SW_MODESW_PIN_CTRL_MODE is setNote Chip selects 1 though 3 are available as alternate GPIO functions

SW_SPI_SDI 0 RO Current value of the SI_DI input 0x0

Table 300 bull Registers in MPU8051

MPU8051_STAT 0x00000004 1 8051 status Page 151

MPU8051_MMAP 0x00000008 1 8051 memory mapping mechanism

MEMACC_CTRL 0x0000000C 1 8051 memory loadexamine configurationstatus

MEMACC 0x00000010 1 8051 memory offset configuration

MEMACC_SBA 0x00000014 1 SBA memory offset configuration

Table 301 bull Fields in MPU8051_STAT

Field Name Bit Access Description DefaultMPU8051_STOP 8 RO Set when the 8051 has stopped itself by

setting bit 2 in the PCON SFR register0x0

MPU8051_GPR 70 RO A read-only copy of the 8051 GPR register at SFR address 0xF0

Table 299 bull Fields in SW_MODE (continued)

Registers

2832 ICPU_CFGMPU8051MPU8051_MMAPParent ICPU_CFGMPU8051

Instances 1

The MAP_ and MSADDR_ fields in this register is similar to the corresponding 8051 SFR register for control mapping the on-chip memory into the 8051 memory space These fields must be used to configure 8051 memory mapping if the 8051 on-chip memory is loaded manually via an external processor If the 8051 program itself does loading of on-chip memory then it must instead use the SFR equivalents

2833 ICPU_CFGMPU8051MEMACC_CTRLParent ICPU_CFGMPU8051

Table 302 bull Fields in MPU8051_MMAP

Field Name Bit Access Description DefaultMSADDR_CODE_HIGH 7 RW Configure which half of the on-chip memory

an 8051 data-accesses in the low 32KByte memory range (when mapped to on-chip memory) actually use When set to 0 the low half of the on-chip 64KByte is accessed when set to 1 the high half is accessed

MSADDR_CODE_LOW 6 RW Configure which half of the on-chip memory an 8051 code-accesses in the low 32KByte memory range (when mapped to on-chip memory) actually use When set to 0 the low half of the on-chip 64KByte is accessed when set to 1 the high half is accessed

MSADDR_DATA_HIGH 5 RW Configure which half of the on-chip memory an 8051 data-accesses in the high 32KByte memory range (when mapped to on-chip memory) actually use When set to 0 the low half of the on-chip 64KByte is accessed when set to 1 the high half is accessed

MSADDR_DATA_LOW 4 RW Configure which half of the on-chip memory an 8051 data-accesses in the low 32KByte memory range (when mapped to on-chip memory) actually use When set to 0 the low half of the on-chip 64KByte is accessed when set to 1 the high half is accessed

MAP_CODE_HIGH 3 RW Set to map 8051 code-accesses in the high 32KByte memory range to on-chip memory instead of FLASH

MAP_CODE_LOW 2 RW Set to map 8051 code-accesses in the low 32KByte memory range to on-chip memory instead of FLASH

MAP_DATA_HIGH 1 RW Set to map 8051 data-accesses in the high 32KByte memory range to on-chip memory instead of FLASH

MAP_DATA_LOW 0 RW Set to map 8051 data-accesses in the low 32KByte memory range to on-chip memory instead of FLASH

Registers

Instances 1

2834 ICPU_CFGMPU8051MEMACCParent ICPU_CFGMPU8051

Instances 1

When loading (or examining) onchip 8051 memory then it is only possible to move 32-bit words This is why bits [1716] and [10] of this register is not implemented Setting START and STOP addresses determines how many words that are loaded (or examined) For example when loading programs of less than 64KBytes decreasing the stop address will speed up the load time

When manually loading or examining the onchip 8051 memory via an external CPU the data has to be put somewhere in SBA memory space on its way into or out-of the onchip 8051 memory for this the 8 x 32-bit general purpose registers starting at 0x70000000 is a good choice By using all (or some) of these registers it is possible to move up to 8 32-bit words tofrom the onchip memory per access

2835 ICPU_CFGMPU8051MEMACC_SBAParent ICPU_CFGMPU8051

Instances 1

There is no stop address in the SBA address space The number of 32-bit words which is moved per access is determined by the MEMACCMEMACC_START and MEMACCMEMACC_STOP

Table 303 bull Fields in MEMACC_CTRL

Field Name Bit Access Description DefaultMEMACC_EXAMINE 1 RW This field controls if the onchip 8051 memory

is either loaded (written) or examined (read)0 Load data from SBA to onchip memory1 Examine data from onchip memory to SBA

MEMACC_DO 0 One-shot Set this field to start an access with the parameters specified by MEMACC_CTRLMEMACC_EXAMINE MEMACCMEMACC_START MEMACCMEMACC_STOP and MEMACC_SBAMEMACC_SBA_START This field is cleared when the requested number of 32-bit words has been transfered

Table 304 bull Fields in MEMACC

Field Name Bit Access Description DefaultMEMACC_STOP 3118 RW Ending 32-bit word address when loading or

examining the onchip 8051 memory the value of this field must be equal to or higher than the MEMACCMEMACC_START field

0x3FFF

MEMACC_START 152 RW Starting 32-bit word address when loading or examining the onchip 8051 memory

0x0000

Registers

284 ICPU_CFGINTRParent ICPU_CFG

Instances 1

These are the VCore interrupt controller registers The controller has 25 interrupt sources (inputs) which can each be mapped to one of 4 interrupt destinations (outputs) The controller has a dedicated block for handling 15 device interrupts the handling of device interrupts can be considdered a small interrupt controller located before the interrupt controller

Table 305 bull Fields in MEMACC_SBA

Field Name Bit Access Description DefaultMEMACC_SBA_START 312 RW This field determines where in the SBA

memory space (32-bit alligned) the automatic loadexamine mechanims readswrites data tofrom the onchip 8051 memory

0x10000000

Table 306 bull Registers in INTR

INTR_RAW 0x00000000 1 Interrupt raw status Page 155

INTR_TRIGGER 0x00000004 20x00000004

Interrupt trigger mode Page 155

INTR_FORCE 0x0000000C 1 Interrupt force sticky event Page 156

INTR_STICKY 0x00000010 1 Interrupt sticky status Page 157

INTR_BYPASS 0x00000014 1 Interrupt bypass enable Page 157

INTR_ENA 0x00000018 1 Interrupt enable Page 157

INTR_ENA_CLR 0x0000001C 1 Atomic clear of interrupt enable

INTR_ENA_SET 0x00000020 1 Atomic set of interrupt Page 158

INTR_IDENT 0x00000024 1 Currently active interrupt sources

DST_INTR_MAP 0x00000028 40x00000004

Mapping of source to destination interrupts

DST_INTR_IDENT 0x00000038 40x00000004

Currently active interrupt sources per destination

EXT_SRC_INTR_POL 0x00000048 1 External source interrupt polarity

EXT_DST_INTR_POL 0x0000004C 1 External destination interrupt polarity

EXT_DST_INTR_DRV 0x00000050 1 External interrupt destination output drive mode

DEV_INTR_POL 0x00000054 1 Device interrupt polarity Page 160

DEV_INTR_RAW 0x00000058 1 Device interrupt raw status Page 161

Registers

2841 ICPU_CFGINTRINTR_RAWParent ICPU_CFGINTR

Instances 1

2842 ICPU_CFGINTRINTR_TRIGGERParent ICPU_CFGINTR

Instances 2

DEV_INTR_TRIGGER 0x0000005C 20x00000004

Device interrupt trigger mode Page 161

DEV_INTR_STICKY 0x00000064 1 Device interrupt sticky status Page 162

DEV_INTR_BYPASS 0x00000068 1 Device interrupt bypass enable

DEV_INTR_ENA 0x0000006C 1 Device interrupt enable Page 163

DEV_INTR_IDENT 0x00000070 1 Currently active device interrupts

Table 307 bull Fields in INTR_RAW

Field Name Bit Access Description DefaultINTR_RAW 240 RO Shows the current value of individual

interrupt sources All sources are active high (the external interrupts has been corrected for polarity as configured in ICPU_CFGEXT_SRC_INTR_POL)

0x0000000

Table 306 bull Registers in INTR (continued)

Registers

2843 ICPU_CFGINTRINTR_FORCEParent ICPU_CFGINTR

Instances 1

Table 308 bull Fields in INTR_TRIGGER

Field Name Bit Access Description DefaultINTR_TRIGGER 240 RW Configure trigger mode of individual interrupt

sources The trigger mode determines how the value of the ICPU_CFGINTR_RAW register is transfered to the ICPU_CFGINTR_STICKY register This register is replicated the first replication controls bit 0 in the encoding the second replication controls bit 1 in the encoding Ie to configure falling-edge-triggered interrupt for interrupt source 5 set ICPU_CFGINTR_TRIGGER[0][5]=0 and ICPU_CFGINTR_TRIGGER[1][5]=1For level-triggered interrupts ICPU_CFGINTR_STICKY is set for as long as the corresponding bit in ICPU_CFGINTR_RAW is high - ie is not possible to clear a bit in ICPU_CFGINTR_STICKY until the corresponding ICPU_CFGINTR_RAW is zeroFor edge-triggeded interrupts ICPU_CFGINTR_STICKY is set when the corresponding bit in ICPU_CFGINTR_RAW changes valueFor falling-edge-triggeded interrupts ICPU_CFGINTR_STICKY is set when the corresponding bit in ICPU_CFGINTR_RAW changes from 1 to 0For rising-edge-triggeded interrupts ICPU_CFGINTR_STICKY is set when the corresponding bit in ICPU_CFGINTR_RAW changes from 0 to 10 Interrupt is level-activated1 Interrupt is edge-triggered2 Interrupt is falling-edge-triggered3 Interrupt is rising-edge-triggered

0x0000000

Table 309 bull Fields in INTR_FORCE

Field Name Bit Access Description DefaultINTR_FORCE 240 One-shot Set to force corresponding

ICPU_CFGINTR_STICKY bitsThis field may be useful during development of software interrupt handler functions

0x0000000

Registers

2844 ICPU_CFGINTRINTR_STICKYParent ICPU_CFGINTR

Instances 1

2845 ICPU_CFGINTRINTR_BYPASSParent ICPU_CFGINTR

Instances 1

2846 ICPU_CFGINTRINTR_ENAParent ICPU_CFGINTR

Instances 1

Table 310 bull Fields in INTR_STICKY

Field Name Bit Access Description DefaultINTR_STICKY 240 Sticky This register is set based on source interrupt

events or by debug-force See ICPU_CFGINTR_TRIGGER and ICPU_CFGINTR_FORCE for more information Bits in this register remains set until cleared by software

0x0000000

Table 311 bull Fields in INTR_BYPASS

Field Name Bit Access Description DefaultINTR_BYPASS 240 RW This register allows bypass of

ICPU_CFGINTR_STICKY for individual interrupt sources When an interrupt source is in bypass mode then ICPU_CFGINTR_RAW is used instead of ICPU_CFGINTR_STICKYNote Enabling bypass does not make sense for all interrupt sources It should only be used when the corresponding interrupt is sticky at the source For example manual extraction data available interrupts can be configured to bypass because the interrupt will remain asserted until the available data has been extractedNote The device interrupt is bypassed per default stickyness is already implemented by ICPU_CFGDEV_INTR_STICKY

0x0000001

Registers

2847 ICPU_CFGINTRINTR_ENA_CLRParent ICPU_CFGINTR

Instances 1

2848 ICPU_CFGINTRINTR_ENA_SETParent ICPU_CFGINTR

Instances 1

2849 ICPU_CFGINTRINTR_IDENTParent ICPU_CFGINTR

Instances 1

Table 312 bull Fields in INTR_ENA

Field Name Bit Access Description DefaultINTR_ENA 240 RW Set to enable propagation of individual

interrupt sources to destinationsAtomic access to this register (needed in a multithreaded system) can be implemented by the ICPU_CFGINTR_ENA_CLR and ICPU_CFGINTR_ENA_SET registers

0x0000000

Table 313 bull Fields in INTR_ENA_CLR

Field Name Bit Access Description DefaultINTR_ENA_CLR 240 One-shot Set bit(s) in this register to clear the

corresponding bits in ICPU_CFGINTR_ENA This register can be used for atomic access to ICPU_CFGINTR_ENA register

0x0000000

Table 314 bull Fields in INTR_ENA_SET

Field Name Bit Access Description DefaultINTR_ENA_SET 240 One-shot Set bit(s) in this register to set the

0x0000000

Registers

28410 ICPU_CFGINTRDST_INTR_MAPParent ICPU_CFGINTR

Instances 4

Replicated per destination interrupt

28411 ICPU_CFGINTRDST_INTR_IDENTParent ICPU_CFGINTR

Instances 4

28412 ICPU_CFGINTREXT_SRC_INTR_POLParent ICPU_CFGINTR

Instances 1

Table 315 bull Fields in INTR_IDENT

Field Name Bit Access Description DefaultINTR_IDENT 240 RO Shows the currently active interrupt sources

For interrupt sources that are not bypassed this register is a result of ANDing ICPU_CFGINTR_STICKY with ICPU_CFGINTR_ENA

0x0000000

Table 316 bull Fields in DST_INTR_MAP

Field Name Bit Access Description DefaultDST_INTR_MAP 240 RW Set to enable mapping of individual interrupt

sources to interrupt destinations This register is replicated once for each destination interrupt

0x0000000

Table 317 bull Fields in DST_INTR_IDENT

Field Name Bit Access Description DefaultDST_INTR_IDENT 240 RO Shows the currently active interrupt sources

per destination interrupt The contents of this register is equal to ICPU_CFGINTR_IDENT ANDed with the corresponding ICPU_CFGDST_INTR_MAPIf any bit is set in this register the corresponding destination interrupt is asserted

0x0000000

Registers

28413 ICPU_CFGINTREXT_DST_INTR_POLParent ICPU_CFGINTR

Instances 1

28414 ICPU_CFGINTREXT_DST_INTR_DRVParent ICPU_CFGINTR

Instances 1

28415 ICPU_CFGINTRDEV_INTR_POLParent ICPU_CFGINTR

Instances 1

Table 318 bull Fields in EXT_SRC_INTR_POL

Field Name Bit Access Description DefaultEXT_SRC_INTR_POL 10 RW Set individual bits in this register to configure

polarity of the corresponding external source interrupt0 External interrupt input is active low1 External interrupt input is active high

Table 319 bull Fields in EXT_DST_INTR_POL

Field Name Bit Access Description DefaultEXT_DST_INTR_POL 10 RW Set individual bits in this register to configure

polarity of the corresponding external destination interrupt0 External interrupt output is active low1 External interrupt output is active high

Table 320 bull Fields in EXT_DST_INTR_DRV

Field Name Bit Access Description DefaultEXT_DST_INTR_DRV 10 RW This register configures drive mode of the

corresponding external destination interrupt0 Only drive external interrupt output when asserted (tristate when inactive)1 External interrupt output is always driven

Table 321 bull Fields in DEV_INTR_POL

Field Name Bit Access Description DefaultDEV_INTR_POL 140 RW Set individual bits in this register to configure

polarity of the corresponding device interrupt0 Device interrupt is active low1 Device interrupt is active high

0x7FFF

Registers

28416 ICPU_CFGINTRDEV_INTR_RAWParent ICPU_CFGINTR

Instances 1

28417 ICPU_CFGINTRDEV_INTR_TRIGGERParent ICPU_CFGINTR

Instances 2

Table 322 bull Fields in DEV_INTR_RAW

Field Name Bit Access Description DefaultDEV_INTR_RAW 140 RO Shows the current value of individual device

interrupt sources All sources are active high (sources have been corrected for polarity as configured in ICPU_CFGDEV_INTR_POL)

0x0000

Registers

28418 ICPU_CFGINTRDEV_INTR_STICKYParent ICPU_CFGINTR

Instances 1

Table 323 bull Fields in DEV_INTR_TRIGGER

Field Name Bit Access Description DefaultDEV_INTR_TRIGGER 140 RW Configure trigger mode of individual device

interrupt sources The trigger mode determines how the value of the ICPU_CFGDEV_INTR_RAW register is transfered to the ICPU_CFGDEV_INTR_STICKY register This register is replicated the first replication controls bit 0 in the encoding the second replication controls bit 1 in the encoding Ie to configure edge-triggered interrupt for device 3 set ICPU_CFGDEV_INTR_TRIGGER[0][3]=1 and ICPU_CFGDEV_INTR_TRIGGER[1][3]=0For level-triggered interrupts ICPU_CFGDEV_INTR_STICKY is set for as long as the corresponding bit in ICPU_CFGDEV_INTR_RAW is high - ie is not possible to clear a bit in ICPU_CFGDEV_INTR_STICKY until the corresponding ICPU_CFGDEV_INTR_RAW is zeroFor edge-triggeded interrupts ICPU_CFGDEV_INTR_STICKY is set when the corresponding bit in ICPU_CFGDEV_INTR_RAW changes valueFor falling-edge-triggeded interrupts ICPU_CFGDEV_INTR_STICKY is set when the corresponding bit in ICPU_CFGDEV_INTR_RAW changes from 1 to 0For rising-edge-triggeded interrupts ICPU_CFGDEV_INTR_STICKY is set when the corresponding bit in ICPU_CFGDEV_INTR_RAW changes from 0 to 10 Interrupt is level-activated1 Interrupt is edge-triggered2 Interrupt is falling-edge-triggered3 Interrupt is rising-edge-triggered

0x0000

Registers

28419 ICPU_CFGINTRDEV_INTR_BYPASSParent ICPU_CFGINTR

Instances 1

28420 ICPU_CFGINTRDEV_INTR_ENAParent ICPU_CFGINTR

Instances 1

28421 ICPU_CFGINTRDEV_INTR_IDENTParent ICPU_CFGINTR

Instances 1

Table 324 bull Fields in DEV_INTR_STICKY

Field Name Bit Access Description DefaultDEV_INTR_STICKY 140 Sticky This register is set based on device interrupt

sourec events See ICPU_CFGDEV_INTR_TRIGGER for more information Bits in this register remains set until cleared by software

0x0000

Table 325 bull Fields in DEV_INTR_BYPASS

Field Name Bit Access Description DefaultDEV_INTR_BYPASS 140 RW This register allows bypass of

ICPU_CFGDEV_INTR_STICKY for individual device interrupt sources When a device interrupt source is in bypass mode then ICPU_CFGDEV_INTR_RAW is used instead of ICPU_CFGDEV_INTR_STICKYSee note on bypass in ICPU_CFGINTR_BYPASS

0x0000

Table 326 bull Fields in DEV_INTR_ENA

Field Name Bit Access Description DefaultDEV_INTR_ENA 140 RW Set to enable propagation of individual

device interrupt sources to the main interrupt controller

0x0000

Registers

285 ICPU_CFGTIMERSParent ICPU_CFG

Instances 1

2851 ICPU_CFGTIMERSWDTParent ICPU_CFGTIMERS

Instances 1

Table 327 bull Fields in DEV_INTR_IDENT

Field Name Bit Access Description DefaultDEV_INTR_IDENT 140 RO Shows the currently active interrupt sources

For interrupt sources that are not bypassed this register is a result of ANDing ICPU_CFGDEV_INTR_STICKY with ICPU_CFGDEV_INTR_ENA

0x0000

Table 328 bull Registers in TIMERS

WDT 0x00000000 1 Watchdog timer Page 164

TIMER_TICK_DIV 0x00000004 1 Timer tick divider Page 165

TIMER_VALUE 0x00000008 30x00000004

Timer value Page 165

TIMER_RELOAD_VALUE 0x00000014 30x00000004

Timer reload value Page 166

TIMER_CTRL 0x00000020 30x00000004

Timer control Page 166

Table 329 bull Fields in WDT

Field Name Bit Access Description DefaultWDT_STATUS 9 RO Shows whether the last reset was caused by

a watchdog timer reset This field is updated during reset therefore it is always valid0 Reset was not caused by WDT1 Reset was caused by WDT timeout

WDT_ENABLE 8 RW Use this field to enable or disable the watchdog timer When the WDT is enabled it causes a reset after 2 seconds if it is not periodically reset This field is only read by the WDT after a sucessful lock sequence (see ICPU_CFGWDTWDT_LOCK)0 WDT is disabled1 WDT is enabled

Registers

2852 ICPU_CFGTIMERSTIMER_TICK_DIVParent ICPU_CFGTIMERS

Instances 1

2853 ICPU_CFGTIMERSTIMER_VALUEParent ICPU_CFGTIMERS

Instances 3

WDT_LOCK 70 RW Use this field to configure and reset the WDT When writing 0xBE to this field immediately followed by writing 0xEF the WDT resets and configurations are read from this register (as provided when the 0xEF is written) When the WDT is enabled writing any value other than 0xBE or 0xEF after 0xBE is written causes a WDT reset as if the timer had run out

Table 330 bull Fields in TIMER_TICK_DIV

Field Name Bit Access Description DefaultTIMER_TICK_DIV 170 RW The timer tick generator runs from the VCore

System frequency By default the divider value generates a timer tick every 100 us (10KHz) The timer tick is used for all of the timers (except the WDT) This field must not be set to generate a timer tick of less than 01 us (higher than 10MHz) If this field is changed it may take up to 2ms before the timers are running stable at the new frequencyThe timer tick frequency is 250MHz(TIMER_TICK_DIV+1)

0x061A7

Table 329 bull Fields in WDT (continued)

Registers

2854 ICPU_CFGTIMERSTIMER_RELOAD_VALUEParent ICPU_CFGTIMERS

Instances 3

2855 ICPU_CFGTIMERSTIMER_CTRLParent ICPU_CFGTIMERS

Instances 3

Table 331 bull Fields in TIMER_VALUE

Field Name Bit Access Description DefaultTIMER_VAL 310 RW The current value of the timer When enabled

via TIMER_CTRLTIMER_ENA the timer decrements at every timer tick (see TIMER_TICK_DIV for more info on timer tick frequency) When the timer has reached 0 and a timer-tick is received then an interrupt is generated For example If a periodic interrupt is needed every 1ms and the timer tick is generated every 100us then the TIMER_VALUE (and TIMER_RELOAD_VALUE) must be configured to 9By default the timer will reload from the TIMER_RELOAD_VALUE when interrupt is generated and then continue decrementing from the reloaded value It is possible to make the timer stop after generating interrupt by setting TIMER_CTRLONE_SHOT_ENA

0x00000000

Table 332 bull Fields in TIMER_RELOAD_VALUE

Field Name Bit Access Description DefaultRELOAD_VAL 310 RW The contents of this field are loaded into the

corresponding timer (TIMER_VALUE) when it wraps (decrements a zero)

0x00000000

Table 333 bull Fields in TIMER_CTRL

Field Name Bit Access Description DefaultONE_SHOT_ENA 2 RW When set the timer will automatically disable

itself after it has generated interrupt0x0

TIMER_ENA 1 RW When enabled the correponding timer decrements at each timer-tick If TIMER_CTRLONE_SHOT_ENA is set this field is cleared when the timer reach 0 and interrupt is generated0 Timer is disabled1 Timer is enabled

Registers

286 ICPU_CFGTWI_DELAYParent ICPU_CFG

Instances 1

2861 ICPU_CFGTWI_DELAYTWI_CONFIGParent ICPU_CFGTWI_DELAY

Instances 1

287 ICPU_CFGTWI_SPIKE_FILTERParent ICPU_CFG

Instances 1

FORCE_RELOAD 0 One-shot Set this field to force the reload of the timer this will set the TIMER_VALUE to TIMER_RELOAD_VALUE for the corresponding timer This field can be set at the same time as enabeling the counter in that case the counter will be reloaded and then enabled for counting

Table 334 bull Registers in TWI_DELAY

TWI_CONFIG 0x00000000 1 TWI hold time configuration Page 167

Table 335 bull Fields in TWI_CONFIG

Field Name Bit Access Description DefaultTWI_CNT_RELOAD 81 RW Configure the hold time delay to apply to

SDA after SCK when transmitting from the device This delay is expressed in a number of VCore System clock cycles The delay value should be as close to 300ns as possible without going below 300nsSet to (300ns48ns + 2) = 65

TWI_DELAY_ENABLE 0 RW Set this field to enable hold time on the TWI SDA output When enabled the TWI_CONFIGTWI_CNT_RELOAD field determines the amount of hold time to apply to SDA

Table 333 bull Fields in TIMER_CTRL (continued)

Registers

2871 ICPU_CFGTWI_SPIKE_FILTERTWI_SPIKE_FILTER_CFGParent ICPU_CFGTWI_SPIKE_FILTER

Instances 1

288 ICPU_CFGFDMAParent ICPU_CFG

Instances 1

For registers and fields in this group which are replicated per channel replication-index-0 correponds to extraction-channel 0 replication-index-1 corresponds to extraction-channel 1 and so on The injection channels follows after the extraction channels

Table 336 bull Registers in TWI_SPIKE_FILTER

TWI_SPIKE_FILTER_CFG 0x00000000 1 TWI spike filter configuration Page 168

Table 337 bull Fields in TWI_SPIKE_FILTER_CFG

SCL and SDA inputsFilters spikes with a width of (SPIKE_FILTER_CFG+1)SYSTEM_CLK or less

Table 338 bull Registers in FDMA

FDMA_DCB_LLP 0x00000000 100x00000004

Pointer to next DCB Page 169

FDMA_DCB_DATAP 0x00000028 100x00000004

Pointer to data block Page 170

FDMA_DCB_DATAL 0x00000050 100x00000004

Length of data block Page 170

FDMA_DCB_STAT 0x00000078 100x00000004

Status word Page 170

FDMA_DCB_LLP_PREV 0x000000A0 100x00000004

Pointer to current DCB Page 171

FDMA_CH_STAT 0x000000C8 1 Current channel status Page 171

FDMA_CH_SAFE 0x000000CC 1 Current channel safe-status Page 171

FDMA_CH_ACTIVATE 0x000000D0 1 Activate specific channels Page 172

Registers

2881 ICPU_CFGFDMAFDMA_DCB_LLPParent ICPU_CFGFDMA

Instances 10

FDMA_CH_DISABLE 0x000000D4 1 Disable specific channels Page 172

FDMA_CH_FORCEDIS 0x000000D8 1 Ungraceful disable of specific channels

FDMA_CH_CNT 0x000000DC 100x00000004

Channel counters Page 173

FDMA_CH_INJ_TOKEN_CNT 0x00000104 80x00000004

Injection channel token counter

FDMA_CH_INJ_TOKEN_TICK_RLD

0x00000124 80x00000004

Injection channel token tick counter reload value

FDMA_CH_INJ_TOKEN_TICK_CNT

0x00000144 80x00000004

Injection channel token tick counter

FDMA_EVT_ERR 0x00000164 1 Error event Page 175

FDMA_EVT_ERR_CODE 0x00000168 1 Additional error information Page 175

FDMA_INTR_LLP 0x0000016C 1 LLP-event Page 176

FDMA_INTR_LLP_ENA 0x00000170 1 LLP-event interrupt enable Page 176

FDMA_INTR_FRM 0x00000174 1 FRM-event Page 177

FDMA_INTR_FRM_ENA 0x00000178 1 FRM-event interrupt enable Page 177

FDMA_INTR_SIG 0x0000017C 1 SIG-event Page 177

FDMA_INTR_SIG_ENA 0x00000180 1 SIG-event interrupt enable Page 177

FDMA_INTR_ENA 0x00000184 1 Channel interrupt enable Page 178

FDMA_INTR_IDENT 0x00000188 1 Currently interrupting channels Page 178

FDMA_CH_CFG 0x0000018C 100x00000004

Channel specific configurations

FDMA_GCFG 0x000001B4 1 General FDMA configurations Page 179

FDMA_GSTAT 0x000001B8 1 General FDMA status Page 179

FDMA_IDLECNT 0x000001BC 1 FDMA idle Counter Page 180

FDMA_CONST 0x000001C0 1 Constants for this FDMA implementation

Table 338 bull Registers in FDMA (continued)

Registers

2882 ICPU_CFGFDMAFDMA_DCB_DATAPParent ICPU_CFGFDMA

Instances 10

2883 ICPU_CFGFDMAFDMA_DCB_DATALParent ICPU_CFGFDMA

Instances 10

2884 ICPU_CFGFDMAFDMA_DCB_STATParent ICPU_CFGFDMA

Instances 10

This register is updated by the FDMA during extraction or injection Software cannot rely on the value of this register

Table 339 bull Fields in FDMA_DCB_LLP

Field Name Bit Access Description DefaultLLP 310 RW This field is used by the FDMA for tracking

lists of DCBs This field is updated automatically when the FDMA load DCBs from memory This field can only be modified when the channel is in safe mode see ICPU_CFGFDMA_CH_SAFECH_SAFE for more information

0x00000000

Table 340 bull Fields in FDMA_DCB_DATAP

Field Name Bit Access Description DefaultDATAP 310 RO For debug current data-pointer 0x00000000

Table 341 bull Fields in FDMA_DCB_DATAL

Field Name Bit Access Description DefaultTOKEN 17 RO For debug current token-indication 0x0

DATAL 150 RO For debug current data-length 0x0000

Table 342 bull Fields in FDMA_DCB_STAT

Field Name Bit Access Description DefaultBLOCKO 3120 RO Block offset in bytes the value of this field is

loaded from the DCB0x000

PD 19 RO PrunedDone indication 0x0

ABORT 18 RO Abort indication 0x0

Registers

2885 ICPU_CFGFDMAFDMA_DCB_LLP_PREVParent ICPU_CFGFDMA

Instances 10

2886 ICPU_CFGFDMAFDMA_CH_STATParent ICPU_CFGFDMA

Instances 1

2887 ICPU_CFGFDMAFDMA_CH_SAFEParent ICPU_CFGFDMA

Instances 1

EOF 17 RO Set when the current DCB contains end-of-frame

SOF 16 RO Set when the current DCB contains start-of-frame

BLOCKL 150 RO Block size in bytes excluding offset (as specified in ICPU_CFGFDMA_DCB_STATBLOCKO) For frames that span multiple DCBs this field only shows the amount of data in the current DCB

0x0000

Table 343 bull Fields in FDMA_DCB_LLP_PREV

Field Name Bit Access Description DefaultLLP_PREV 312 RO This field holds the pointer to current DCB

(the previous ICPU_CFGFDMA_DCB_LLPLLP)

0x00000000

Table 344 bull Fields in FDMA_CH_STAT

Field Name Bit Access Description DefaultCH_STAT 90 RO Shows status for all FDMA channels there is

one bit per channel0Disabled1Updating or Active

Table 342 bull Fields in FDMA_DCB_STAT (continued)

Registers

2888 ICPU_CFGFDMAFDMA_CH_ACTIVATEParent ICPU_CFGFDMA

Instances 1

2889 ICPU_CFGFDMAFDMA_CH_DISABLEParent ICPU_CFGFDMA

Instances 1

28810 ICPU_CFGFDMAFDMA_CH_FORCEDISParent ICPU_CFGFDMA

Instances 1

Table 345 bull Fields in FDMA_CH_SAFE

Field Name Bit Access Description DefaultCH_SAFE 90 RO When set it is safe for software to

readmodifywrite ICPU_CFGFDMA_DCB_LLPLLP ICPU_CFGFDMA_CH_CNTCH_CNT_SIG ICPU_CFGFDMA_CH_CNTCH_CNT_DCB and ICPU_CFGFDMA_CH_INJ_TOKEN_CNTCH_INJ_TOKEN_CNT There is one bit per channelThis field is set when a channel is a) disabled or b) active and scheduled for disabling

Table 346 bull Fields in FDMA_CH_ACTIVATE

Field Name Bit Access Description DefaultCH_ACTIVATE 90 One-shot Enables specific FDMA channels there is

one bit per channel Setting a bit in this field will clear a corresponding pending ICPU_CFGFDMA_CH_DISABLECH_DISABLE request Bits in this field are cleared immediately when set

Table 347 bull Fields in FDMA_CH_DISABLE

Field Name Bit Access Description DefaultCH_DISABLE 90 One-shot Schedules specific FDMA channels to be

disabled there is one bit per channel The channel will finish the current DCB and then disable (after writing the DCB status word) Bits in this field is cleared either when the channel disables or by writing ICPU_CFGFDMA_CH_ACTIVATECH_ACTIVATE)

Registers

28811 ICPU_CFGFDMAFDMA_CH_CNTParent ICPU_CFGFDMA

Instances 10

28812 ICPU_CFGFDMAFDMA_CH_INJ_TOKEN_CNTParent ICPU_CFGFDMA

Instances 8

Table 348 bull Fields in FDMA_CH_FORCEDIS

Field Name Bit Access Description DefaultCH_FORCEDIS 90 One-shot Immediately disable specific FDMA

channels there is one bit per channel Unlike ICPU_CFGFDMA_CH_DISABLE using CH_FORCEDIS will not take the state of the channel into account if the channel is actively extracting or injecting fromto QS there is no guarantee that it will be functional after disabling the channel

Table 349 bull Fields in FDMA_CH_CNT

Field Name Bit Access Description DefaultCH_CNT_FRM 3116 RW This field is incremented every time the

channel saves status for a DCB that has EOFThis counter can only be modified safely when the corresponding channel is disabled (see ICPU_CFGFDMA_CH_STATCH_STAT for more information)

0x0000

CH_CNT_DCB 158 RW This field is incremented every time the channel loads a DCBThis counter can be modified safely while the corresponding channel is safe (see ICPU_CFGFDMA_CH_SAFECH_SAFE for more information)

CH_CNT_SIG 70 RW This field is incremented every time the channel loads a DCB that has the SIG field set The FDMA can generate interrupt whenever this counter is incremented (see ICPU_CFGFDMA_INTR_SIGINTR_SIG for more information)This counter can be modified safely while the corresponding channel is safe (see ICPU_CFGFDMA_CH_SAFECH_SAFE for more information)

Registers

28813 ICPU_CFGFDMAFDMA_CH_INJ_TOKEN_TICK_RLDParent ICPU_CFGFDMA

Instances 8

28814 ICPU_CFGFDMAFDMA_CH_INJ_TOKEN_TICK_CNTParent ICPU_CFGFDMA

Instances 8

Table 350 bull Fields in FDMA_CH_INJ_TOKEN_CNT

Field Name Bit Access Description DefaultCH_INJ_TOKEN_CNT 70 RW Every time a channel activates with a DCB

that has the TOKEN field set this counter is decremented by one Channels that loads a DCB with the TOKEN field set cannot activate unless this counter is different from zeroThis counter can be written by software or incremented automatically by using the token tick counter (see ICPU_CFGFDMA_CH_INJ_TOKEN_TICK_CNT for more information) This counter can be modified safely when automatic incrementing is not enabled and the corresponding injection channel is in safe mode (see ICPU_CFGFDMA_CH_INJ_TOKEN_CNT and ICPU_CFGFDMA_CH_SAFECH_SAFE for more information)

Table 351 bull Fields in FDMA_CH_INJ_TOKEN_TICK_RLD

Field Name Bit Access Description DefaultCH_INJ_TOKEN_TICK_RLD 310 RW Automatic incrementing of the token counter

is enabled by setting this field different from 0 This field holds the reload value for the ICPU_CFGFDMA_CH_INJ_TOKEN_TICK_CNTNote When changing the value of this field the same value should also be written to the ICPU_CH_INJ_TOKEN_TICK_CNT field this is needed for speeding up token counter increments when changing from a high reload value to a low reload value0 Token tick counter is disabledn Add one token every n 200ns clock cycles

0x00000000

Registers

28815 ICPU_CFGFDMAFDMA_EVT_ERRParent ICPU_CFGFDMA

Instances 1

28816 ICPU_CFGFDMAFDMA_EVT_ERR_CODEParent ICPU_CFGFDMA

Instances 1

Table 352 bull Fields in FDMA_CH_INJ_TOKEN_TICK_CNT

Field Name Bit Access Description DefaultCH_INJ_TOKEN_TICK_CNT 310 RW Down-counter when enabled by

ICPU_CFGFDMA_CH_INJ_TOKEN_TICK_RLD this field is decremented by one every 200ns When zero is reached one token will be added to ICPU_CFGFDMA_CH_INJ_TOKEN_CNT and this counted will load the value from ICPU_CFGFDMA_CH_INJ_TOKEN_TICK_RLD (subtract one and continue decrementing from that value)

0x00000000

Table 353 bull Fields in FDMA_EVT_ERR

Field Name Bit Access Description DefaultEVT_ERR 90 Sticky Shows if an Error-event has occurred there

is one bit per channel See ICPU_CFGFDMA_EVT_ERR_CODEEVT_ERR_CODE for description of errors for which the FDMA implements run-time checks

Registers

28817 ICPU_CFGFDMAFDMA_INTR_LLPParent ICPU_CFGFDMA

Instances 1

28818 ICPU_CFGFDMAFDMA_INTR_LLP_ENAParent ICPU_CFGFDMA

Instances 1

Table 354 bull Fields in FDMA_EVT_ERR_CODE

Field Name Bit Access Description DefaultEVT_ERR_CODE 30 RO This field shows information about Error-

events that has been recorded by the FDMA this can be used for software development and debugging If multiple errors happen in succession only the newest of the err-codes is shown0Default (no error has occurred)1CH_ACTIVATE set for channel w DCB_LLP==NULL2Got DCB w DATAP==NULL3Got extraction DCB w DATAL==04Got extraction DCB w DATALlt=BLOCKO5Got injection DCB w BLOCKL==06Got injection DCB w SOF for already active channel7Activate attempted for channel w error indication8Activate attempted for channel enabled for manual mode9Manual mode enabled for channel in active FDMA mode

Table 355 bull Fields in FDMA_INTR_LLP

Field Name Bit Access Description DefaultINTR_LLP 90 Sticky Shows if an LLP-event has occurred there is

one bit per channel See the data sheet for information on when this event can occur

Table 356 bull Fields in FDMA_INTR_LLP_ENA

Field Name Bit Access Description DefaultINTR_LLP_ENA 90 RW Enables LLP-event to be propagated as

interrupt there is one bit per channel See ICPU_CFGFDMA_INTR_LLPINTR_LLP for additional information

Registers

28819 ICPU_CFGFDMAFDMA_INTR_FRMParent ICPU_CFGFDMA

Instances 1

28820 ICPU_CFGFDMAFDMA_INTR_FRM_ENAParent ICPU_CFGFDMA

Instances 1

28821 ICPU_CFGFDMAFDMA_INTR_SIGParent ICPU_CFGFDMA

Instances 1

28822 ICPU_CFGFDMAFDMA_INTR_SIG_ENAParent ICPU_CFGFDMA

Instances 1

Table 357 bull Fields in FDMA_INTR_FRM

Field Name Bit Access Description DefaultINTR_FRM 90 Sticky Shows if a FRM-event has occurred there is

Table 358 bull Fields in FDMA_INTR_FRM_ENA

Field Name Bit Access Description DefaultINTR_FRM_ENA 90 RW Enables FRM-event to be propagated as

interrupt there is one bit per channel See ICPU_CFGFDMA_INTR_FRMINTR_FRM for additional information

Table 359 bull Fields in FDMA_INTR_SIG

Field Name Bit Access Description DefaultINTR_SIG 90 Sticky Shows if a SIG-event has occurred there is

Table 360 bull Fields in FDMA_INTR_SIG_ENA

Field Name Bit Access Description DefaultINTR_SIG_ENA 90 RW Enables SIG-event to be propagated as

interrupt there is one bit per channel See ICPU_CFGFDMA_INTR_SIGINTR_SIG for additional information

Registers

28823 ICPU_CFGFDMAFDMA_INTR_ENAParent ICPU_CFGFDMA

Instances 1

28824 ICPU_CFGFDMAFDMA_INTR_IDENTParent ICPU_CFGFDMA

Instances 1

28825 ICPU_CFGFDMAFDMA_CH_CFGParent ICPU_CFGFDMA

Instances 10

Table 361 bull Fields in FDMA_INTR_ENA

Field Name Bit Access Description DefaultINTR_ENA 90 RW Enables propagation of enabled channel

LLP-event FRM-event and SIG-event as interrupt there is one bit per channel ERR-events are always propagated when interrupt is enabled for a channel

Table 362 bull Fields in FDMA_INTR_IDENT

Field Name Bit Access Description DefaultINTR_IDENT 90 RO Shows currently interrupting channels there

is one bit per channel0x000

Table 363 bull Fields in FDMA_CH_CFG

Field Name Bit Access Description DefaultCH_INJ_GRP 6 RW This field is only applicable to injection

channels Use this field to map the injection channel to an injection group

CH_PRIO 52 RW The FDMA implements a strict priority scheme between all channels - both injection and extractionObserve The FDMA does not directly control the order in which ports are serviced in the Queuing System In order to adjust for this (and to avoid head of line blocking) all extraction channels are automatically assigned the highest priority of the extraction channels with available dataIf multiple channels are configured with equal priorities then the following strict scheme is in place Higher channel number takes priority over lower channel number This implies that injection takes priority over extraction

Registers

28826 ICPU_CFGFDMAFDMA_GCFGParent ICPU_CFGFDMA

Instances 1

28827 ICPU_CFGFDMAFDMA_GSTATParent ICPU_CFGFDMA

Instances 1

DONE_STOP_ENA 1 RW Set this field to automatically disable the channel after completing any DCB The channel will disable after saving DCB status An LLP-event will be generated at the same time as the channel is disabledBe careful when using this feature extraction channels may head-of-line block other extraction channels if not immediately re-activated

DONEEOF_STOP_ENA 0 RW Set this field to automatically disable the channel after completing any DCB with EOF indication The channel will disable after saving DCB status An LLP-event will be generated at the same time as the channel is disabledBe careful when using this feature extraction channels may head-of-line block other extraction channels if not immediately re-activated

Table 364 bull Fields in FDMA_GCFG

Field Name Bit Access Description DefaultFRM_AT_OFF 12 RW Set this field to make the FDMA emit FRM

event for extraction channels that are disabled because of LLP=NULL

INJ_RF_WM 117 RW Injection resync FIFO fill-level watermark when exceeded backpressure will be asserted towards SBAThe maximum fill-level for the FIFO is reported via ICPU_CFGFDMA_GSTATINJ_RF_HIGHn backpressure when n+1 or more words in buffer

RESERVED 63 RW Must be set to its default 0xA

PD_IGNORE 0 RW Set this field to make the FDMA ignore the value of the DCBs PD field when injecting frames By default the FDMA will treat the PD field in the same way as ABORT

Table 363 bull Fields in FDMA_CH_CFG (continued)

Registers

28828 ICPU_CFGFDMAFDMA_IDLECNTParent ICPU_CFGFDMA

Instances 1

28829 ICPU_CFGFDMAFDMA_CONSTParent ICPU_CFGFDMA

Instances 1

289 ICPU_CFGPCIEParent ICPU_CFG

Instances 1

These are VCore based registers for configuration of PCIe endpoint support logic PCIe configuration space registers are memory mapped via the PCIE region of the Chip Registers

Table 365 bull Fields in FDMA_GSTAT

Field Name Bit Access Description DefaultINJ_RF_HIGH 105 RO This field shows the highest fill level that the

injection resync FIFO has experienced since reset of the injection logic The depth of the FIFO is 32 words reaching a fill-level of 33 (or more) means that overflow has occurred

Table 366 bull Fields in FDMA_IDLECNT

Field Name Bit Access Description DefaultIDLECNT 230 RO The counter is reset whenever a channel is

enabled and when FDMA moves frame data to or from the queuing system When the FDMA is idle this counter is incremented once every 200ns The counter saturates at maximum value (approx 33 seconds of idle time)

0x000000

Table 367 bull Fields in FDMA_CONST

Field Name Bit Access Description DefaultCH_INJ_CNT 158 RO The number of injection channels 0x08

CH_XTR_CNT 70 RO The number of extraction channels 0x02

Registers

2891 ICPU_CFGPCIEPCIE_CFGParent ICPU_CFGPCIE

Instances 1

Table 368 bull Registers in PCIE

PCIE_CFG 0x00000004 1 PCIe endpoint configuration Page 181

PCIE_STAT 0x00000008 1 PCIe endpoint status Page 182

PCIE_AUX_CFG 0x0000000C 1 Auxiliary power configuration Page 182

PCIESLV_FDMA 0x00000028 1 FDMA access into PCIe address space

PCIESLV_SBA 0x0000002C 1 SBA access into PCIe address space

PCIEPCS_CFG 0x00000030 1 PCIe PCS configuration Page 183

PCIE_INTR 0x00000038 1 PCIe events Page 184

PCIE_INTR_ENA 0x0000003C 1 PCIe interrupt enable Page 184

PCIE_INTR_IDENT 0x00000040 1 Currently active PCIe interrupts

PCIE_INTR_COMMON_CFG 0x00000044 1 PCIe outbound interrupt configuration

PCIE_INTR_CFG 0x00000048 20x00000004

PCIe outbound MSI interrupt configuration

Table 369 bull Fields in PCIE_CFG

Field Name Bit Access Description DefaultPCIE_BAR_WR_ENA 2 RW Set this field to enable write of PCIe BAR

masks via PCIE register target Only registers PCIEBAR0 PCIEBAR1 and PCIEBAR2 may be written while this field is setThe minimum size for Memory and IO BARs are 64K (mask 0xFFFF) Note The low 4 bits of all BARs can be written via the PCIe target when this field is not set

LTSSM_DIS 1 RW Set this field to disable initialization of the PCIe linkBy default the PCIe core will start up and try to achieve link when the SERDES is started by setting this field before starting the SERDES it is possible to make changes to the PCIe configurationregisters prior to linking with the root complex

Registers

2892 ICPU_CFGPCIEPCIE_STATParent ICPU_CFGPCIE

Instances 1

2893 ICPU_CFGPCIEPCIE_AUX_CFGParent ICPU_CFGPCIE

Instances 1

2894 ICPU_CFGPCIEPCIESLV_FDMAParent ICPU_CFGPCIE

Instances 1

2895 ICPU_CFGPCIEPCIESLV_SBAParent ICPU_CFGPCIE

MEM_RING_CORE_ENA 0 RW Set to add the PCIe core memories to the RAM integrity ring

Table 370 bull Fields in PCIE_STAT

Field Name Bit Access Description DefaultPM_STATE 20 RO The current power management state of the

PCIe core0 D01 D12 D23 D34 D0-Uninitialized

Table 371 bull Fields in PCIE_AUX_CFG

Field Name Bit Access Description DefaultAUX_POWER_VAL 0 RW Set to force detection of PCIe auxiliary

power0x1

Table 372 bull Fields in PCIESLV_FDMA

Field Name Bit Access Description DefaultFDMA_OFFSET 10 RW The FDMA has access to one 1GByte region

(0xC0000000 though 0xFFFFFFFF) that maps accesses to PCIe interface The value of this field is used for address-bits [3130] towards the PCIe endpointSet this field to 1

Table 369 bull Fields in PCIE_CFG (continued)

Registers

Instances 1

2896 ICPU_CFGPCIEPCIEPCS_CFGParent ICPU_CFGPCIE

Instances 1

Table 373 bull Fields in PCIESLV_SBA

Field Name Bit Access Description DefaultSBA_BE 2724 RW This field allows configuration of outbound

PCIe-transaction Byte-Enable field This is applied to all SBA (non-FDMA) initiated outbound PCIe accessesThis field is not used for TYPE=MRrMWrMRdLk accesses Byte-enables are needed in order to support Zero-byte and non-contiguous byte IO and CFG transfers and Zero-byte Messages

SBA_MSG_CODE 2215 RW This field allows configuration of outbound PCIe-transaction MSG field This is applied to all SBA (non-FDMA) initiated outbound PCIe accesses

SBA_TC 1412 RW This field allows configuration of outbound PCIe-transaction TC field This is applied to all SBA (non-FDMA) initiated outbound PCIe accesses

SBA_EP 8 RW This field allows configuration of outbound PCIe-transaction EP field This is applied to all SBA (non-FDMA) initiated outbound PCIe accesses

SBA_OFFSET 10 RW SBA masters (non-FDMA) has access to one 1GByte region (0xC0000000 though 0xFFFFFFFF) that maps accesses to PCIe interface The value of this field is used for address-bits [3130] towards the PCIe endpointSet this field to 0

Table 374 bull Fields in PCIEPCS_CFG

WAKE_POL 2 RW Polarity of the PCIe WAKE output WAKE is typically an active low output - but if an amplifier is needed for driving a large WAKE net then polarity may need to be changed0 Active low1 Active high

Registers

2897 ICPU_CFGPCIEPCIE_INTRParent ICPU_CFGPCIE

Instances 1

2898 ICPU_CFGPCIEPCIE_INTR_ENAParent ICPU_CFGPCIE

Instances 1

2899 ICPU_CFGPCIEPCIE_INTR_IDENTParent ICPU_CFGPCIE

Instances 1

28910 ICPU_CFGPCIEPCIE_INTR_COMMON_CFGParent ICPU_CFGPCIE

WAKE_OE 1 RW Set to permanently drive PCIe WAKE output by default the WAKE output is only driven when active and thusly allowing pull-resistor network0 Only drive output when active1 Always drive output

BEACON_DIS 0 RW Set this field to disable outband PCIe beacon signaling when attempting to wake from D3 When beacon is disabled the WAKE signal (available as alternate GPIO function) must be used instead

Table 375 bull Fields in PCIE_INTR

Field Name Bit Access Description DefaultINTR_PM_STATE 0 Sticky This event is set whenever the

ICPU_CFGPCIE_STATPM_STATE field is changed

Table 376 bull Fields in PCIE_INTR_ENA

Field Name Bit Access Description DefaultINTR_PM_STATE_ENA 0 RW Set to enable propagation of the PM_STATE

interrupt0x0

Table 377 bull Fields in PCIE_INTR_IDENT

Field Name Bit Access Description DefaultINTR_PM_STATE_IDENT 0 RO Set if the PM_STATE interrupt is currently

active0x0

Table 374 bull Fields in PCIEPCS_CFG (continued)

Registers

Instances 1

28911 ICPU_CFGPCIEPCIE_INTR_CFGParent ICPU_CFGPCIE

Instances 2

Replicated per EXT_DST interrupt

2810 ICPU_CFGMANUAL_XTRINJParent ICPU_CFG

Instances 1

This group contains replicated register array for doing manual Extraction and Injection by use of the FDMA engine

Table 378 bull Fields in PCIE_INTR_COMMON_CFG

Field Name Bit Access Description DefaultWAKEUP_ON_INTR_DIS 2 RW Set to disable wake-up on interrupt By

default the PCIe endpoint will attempt to wake up from powerdown when a change in interrupt state is detected

LEGACY_MODE_INTR_SEL 1 RW Select the external interrupt from the VCore interrupt controller that must be used to generate PCIe legacy interrupt0 Use EXT_DST01 Use EXT_DST1

PCIE_INTR_ENA 0 RW Set to enable PCIe interrupts The PCIe endpoints MSI Capability Register Set must have been configured before enabling interrupts

Table 379 bull Fields in PCIE_INTR_CFG

Field Name Bit Access Description DefaultTRAFFIC_CLASS 1412 RW Configure MSI interrupt traffic class for

corresponding EXT_DST interrupt0x0

FALLING_VECTOR_VAL 117 RW Configure MSI interrupt vector for falling edge of corresponding EXT_DST interrupt

RISING_VECTOR_VAL 62 RW Configure MSI interrupt vector for rising edge of corresponding EXT_DST interrupt

INTR_FALLING_ENA 1 RW Set to enable MSI interrupt on falling edge of corresponding EXT_DST interrupt

INTR_RISING_ENA 0 RW Set to enable MSI interrupt on rising edge of corresponding EXT_DST interrupt

Registers

28101 ICPU_CFGMANUAL_XTRINJMANUAL_XTRParent ICPU_CFGMANUAL_XTRINJ

Instances 4096

28102 ICPU_CFGMANUAL_XTRINJMANUAL_INJParent ICPU_CFGMANUAL_XTRINJ

Instances 4096

28103 ICPU_CFGMANUAL_XTRINJMANUAL_CFGParent ICPU_CFGMANUAL_XTRINJ

Instances 1

Table 380 bull Registers in MANUAL_XTRINJ

MANUAL_XTR 0x00000000 40960x00000004

Manual extraction replicated register-array

MANUAL_INJ 0x00004000 40960x00000004

Manual injection replicated register-array

MANUAL_CFG 0x00008000 1 Manual extraction and injection configuration

MANUAL_INTR 0x00008004 1 Manual extraction and injection interrupt indications

MANUAL_INTR_ENA 0x00008008 1 Manual extraction and injection interrupt enables

Table 381 bull Fields in MANUAL_XTR

Field Name Bit Access Description DefaultXTR 310 RW Manual extraction is done by reading from

this block of registers The manual extraction status word is accessed by reading the last word-address in this block Manual extraction has to be enabled via ICPU_CFGMANUAL_CFGXTR_ENA

0x00000000

Table 382 bull Fields in MANUAL_INJ

Field Name Bit Access Description DefaultINJ 310 RW Manual injection is done by writing to this

block of registers The manual injection status word is located at the first word-address in this block Manual injection has to be enabled via ICPU_CFGMANUAL_CFGINJ_ENA

0x00000000

Registers

28104 ICPU_CFGMANUAL_XTRINJMANUAL_INTRParent ICPU_CFGMANUAL_XTRINJ

Instances 1

28105 ICPU_CFGMANUAL_XTRINJMANUAL_INTR_ENAParent ICPU_CFGMANUAL_XTRINJ

Instances 1

Table 383 bull Fields in MANUAL_CFG

Field Name Bit Access Description DefaultINJ_SWAP_ENA 3 RW Set to swap endianness of data injected to

the MANUAL_INJ region The manual injection status word is never swapped

XTR_SWAP_ENA 2 RW Set to byte-swap endianness of data extracted from the MANUAL_XTR region The manual extraction status word is never swapped

INJ_ENA 1 RW Set to enable manual injection by using FDMA channel number 9 When manual injection is enabled the FDMA cannot be used for regular FDMA injection operations (on any injection channel)

XTR_ENA 0 RW Set to enable manual extraction by using FDMA channel number 1 When manual extraction is enabled the FDMA cannot be used for regular FDMA extraction operations (on any extraction channel)

Table 384 bull Fields in MANUAL_INTR

Field Name Bit Access Description DefaultINTR_INJ_RDY 2 RO Set when there is room for more injection

data-words in injection fifo0x0

INTR_XTR_ANY_RDY 1 RO Set when any extraction word is ready for extraction

INTR_XTR_SOF_RDY 0 RO Set when there is an extraction word containing SOF ready for extraction

Table 385 bull Fields in MANUAL_INTR_ENA

Field Name Bit Access Description DefaultINTR_INJ_RDY_ENA 2 RW Set to enable FDMA interrupt while there is

room for more injection data This interrupt is asserted for as long as there is free space in the injection buffers

Registers

29 VCAP_CORE

291 VCAP_COREVCAP_CORE_CFGParent VCAP_CORE

Instances 1

2911 VCAP_COREVCAP_CORE_CFGVCAP_UPDATE_CTRLParent VCAP_COREVCAP_CORE_CFG

Instances 1

Operations on the VCAP cache is done via this register The UPDATE_CMD field specifies the operation to perform when UPDATE_SHOT is set For all of the operations it is possible to disable readwrite of entries actions andor counter by setting VCAP_UPDATE_CTRLUPDATE_ENTRY_DIS VCAP_UPDATE_CTRLUPDATE_ACTION_DIS andor VCAP_UPDATE_CTRLUPDATE_CNT_DIS

INTR_XTR_ANY_RDY_ENA 1 RW Set to enable FDMA interrupt while any data is ready for manual extraction This interrupt is asserted for as long as there is data ready in the extraction buffer

INTR_XTR_SOF_RDY_ENA 0 RW Set to enable FDMA interrupt when a new frame is waiting to be extracted This event is asserted when a frame-word with sof set is waiting to be extracted If a previous frame is only partially extracted then no interrupt will be generated until the previous frame is completely extracted

Table 386 bull Register Groups in VCAP_CORE

VCAP_CORE_CFG 0x00000000 1 VCAP operations Page 188

VCAP_CORE_CACHE 0x00000008 1 VCAP cache Page 191

VCAP_CORE_MAP 0x0000038C 1 Mapping of cores to interfaces Page 193

TCAM_BIST 0x000003C0 1 Build in test for TCAM Page 194

Table 387 bull Registers in VCAP_CORE_CFG

VCAP_UPDATE_CTRL 0x00000000 1 Initiation of readwritemoveinitialization operations

VCAP_MV_CFG 0x00000004 1 Configuration for moveinitialization

Table 385 bull Fields in MANUAL_INTR_ENA (continued)

Registers

respectively Writingmoving to unimplemented addresses are ignored Readingmoving from unimplemented addresses returns never-match for entries and zeros from actionscounters

Active rules may only be written to empty (initialized) addresses Software must not overwrite active rules (unless when initializing rules) To initialize a region of addresses use the init operation with CLEAR_CACHE bits set to 1 Move operations automatically disable rules when moved so it is OK when source and destination ranges overlap

Table 388 bull Fields in VCAP_UPDATE_CTRL

Field Name Bit Access Description DefaultUPDATE_CMD 2422 RW Write and read operations access VCAP

memory at address specified by UPDATE_ADDRMove up operation moves one or more VCAP addresses from a high address to a lower address this is equivalent to decreasing priority of a rule The starting address is specified by UPDATE_ADDR the number of addresses (the range) that is moved is defined by VCAP_MV_CFGMV_SIZE the distance to move is defined by VCAP_MV_CFG MV_NUM_POSMove down operation moves one or more VCAP addresses from a low address to a higher address this is equivalent to increasing priority of a rule This operation is equivalent to Move up except for the direction that it moves addresses see Move up for more detailsInit operation writes the contents of the cache to one or more VCAP addresses The starting address is specified by UPDATE_ADDR the number of addresses (the range) that is written is defined by VCAP_MV_CFGMV_SIZE Setting CLEAR_CACHE at the same time as starting the operation will clear the cache and cause the init operation to initialize the range of addresses000 Write from cache to VCAP001 Read from VCAP to cache010 Move entry andor action up (decreasing addresses)011 Move entry andor action down (increasing addresses)100 Initialize VCAP with the cache-value

UPDATE_ENTRY_DIS 21 RW Set to disable update of entries for VCAP operations For read-operations entry-cache will remain unchanged For writemoveinit operations the VCAP-entry will remain unchanged

Registers

2912 VCAP_COREVCAP_CORE_CFGVCAP_MV_CFGParent VCAP_COREVCAP_CORE_CFG

Instances 1

UPDATE_ACTION_DIS 20 RW Set to disable update of actions for VCAP operations For read-operations action-cache will remain unchanged For writemoveinit operations the VCAP-action will remain unchanged

UPDATE_CNT_DIS 19 RW Set to disable update of counter for VCAP operations For read-operations counter-cache will remain unchanged For writeinit operations the VCAP-counter will remain unchanged For move operations the destination VCAP-counters will be set to zeros

UPDATE_ADDR 183 RW The address to access for VCAP operations 0x0000

UPDATE_SHOT 2 One-shot Set to initiate the operation specified in UPDATE_CMD This bit is automatically cleared by hardware when the operation is finishedSoftware must not change write fields in the VCAP target while this field is set (while operation is active)

CLEAR_CACHE 1 One-shot Set to clear the cache This field is cleared immediately by hardware (at the same time as clearing the cache) The contents of the cache will be set to disabledempty

Table 389 bull Fields in VCAP_MV_CFG

Field Name Bit Access Description DefaultMV_NUM_POS 3116 RW Specifies the distance during move

operations Ie if this field is set to 4 for a move-down operation then source address n is moved to destination address n+50 Distance is one position1 Distance is two positionsn Distance is n+1 positions

0x0000

MV_SIZE 150 RW Specifies the number of addresses to moveinitialize during moveinit operations0 Address VCAP_UPDATE_CTRLUPDATE_ADDR is movedinitializedn Addresses VCAP_UPDATE_CTRLUPDATE_ADDR through VCAP_UPDATE_CTRLUPDATE_ADDR+n are movedinitialized

0x0000

Table 388 bull Fields in VCAP_UPDATE_CTRL (continued)

Registers

292 VCAP_COREVCAP_CORE_CACHEParent VCAP_CORE

Instances 1

2921 VCAP_COREVCAP_CORE_CACHEVCAP_ENTRY_DATParent VCAP_COREVCAP_CORE_CACHE

Instances 64

2922 VCAP_COREVCAP_CORE_CACHEVCAP_MASK_DATParent VCAP_COREVCAP_CORE_CACHE

Instances 64

Table 390 bull Registers in VCAP_CORE_CACHE

VCAP_ENTRY_DAT 0x00000000 640x00000004

Entry data cache Page 191

VCAP_MASK_DAT 0x00000100 640x00000004

Entry mask cache Page 191

VCAP_ACTION_DAT 0x00000200 640x00000004

Action cache Page 192

VCAP_CNT_DAT 0x00000300 320x00000004

Counter cache Page 192

VCAP_TG_DAT 0x00000380 1 Entry type-group Page 192

Table 391 bull Fields in VCAP_ENTRY_DAT

Field Name Bit Access Description DefaultENTRY_DAT 310 RW The cache register that holds entry data The

register is replicated index 0 is the 32 LSBs of the entry-dataTogether with VCAP_MASK_DATMASK_DAT this field defines match parameters for TCAM entries Version 2 VCAPs allows programming of never-match this is needed when disabling entries Version 1 VCAPs converts match-off to match-any when readingwriting entriesMatch-0 Entry=0 Mask=0Match-1 Entry=1 Mask=0Match-any (dont care) Entry=0 Mask=1Match-off (never-match) Entry=1 Mask=1

0x00000000

Registers

2923 VCAP_COREVCAP_CORE_CACHEVCAP_ACTION_DATParent VCAP_COREVCAP_CORE_CACHE

Instances 64

2924 VCAP_COREVCAP_CORE_CACHEVCAP_CNT_DATParent VCAP_COREVCAP_CORE_CACHE

Instances 32

2925 VCAP_COREVCAP_CORE_CACHEVCAP_TG_DATParent VCAP_COREVCAP_CORE_CACHE

Instances 1

Table 392 bull Fields in VCAP_MASK_DAT

Field Name Bit Access Description DefaultMASK_DAT 310 RW The cache register that holds entry mask

The register is replicated index 0 is the 32 LSBs of the entry-maskSee VCAP_MASK_DATMASK_DAT for encoding information

0x00000000

Table 393 bull Fields in VCAP_ACTION_DAT

Field Name Bit Access Description DefaultACTION_DAT 310 RW The cache register that holds action The

register is replicated index 0 is the 32 LSBs of the action

0x00000000

Table 394 bull Fields in VCAP_CNT_DAT

Field Name Bit Access Description DefaultCNT_DAT 310 RW The cache register that holds counter The

register is replicated index 0 is the 32 LSBs of the counterWhen the counter is 1 bit wide the counter operates as a 1 bit saturating counter it is set by VCAP when a rule is matched by a key

0x00000000

Registers

293 VCAP_COREVCAP_CORE_MAPParent VCAP_CORE

Instances 1

2931 VCAP_COREVCAP_CORE_MAPVCAP_CORE_IDXParent VCAP_COREVCAP_CORE_MAP

Instances 1

2932 VCAP_COREVCAP_CORE_MAPVCAP_CORE_MAPParent VCAP_COREVCAP_CORE_MAP

Instances 1

Table 395 bull Fields in VCAP_TG_DAT

Field Name Bit Access Description DefaultTG_DAT 310 RW This cache register holds the TypeGroup id

for each subword in the TCAM TypeGroup ids are place back to back with subword 0 at the LSBs when VCAP supports multiple subwordsThis field applies only to version 1 VCAPs for version 2 VCAPs it is not implemented and reading it will return zeros

0x00000000

Table 396 bull Registers in VCAP_CORE_MAP

VCAP_CORE_IDX 0x00000000 1 Core index Page 193

VCAP_CORE_MAP 0x00000004 1 Mapping of core Page 193

Table 397 bull Fields in VCAP_CORE_IDX

Field Name Bit Access Description DefaultCORE_IDX 30 RW Set to index of specific core to access the

mapping of that core via VCAP_COREVCAP_CORE_MAP

Registers

294 VCAP_CORETCAM_BISTParent VCAP_CORE

Instances 1

2941 VCAP_CORETCAM_BISTTCAM_CTRLParent VCAP_CORETCAM_BIST

Instances 1

2942 VCAP_CORETCAM_BISTTCAM_STATParent VCAP_CORETCAM_BIST

Instances 1

Table 398 bull Fields in VCAP_CORE_MAP

Field Name Bit Access Description DefaultCORE_MAP 20 RW Configure ownership of core n (defined by

VCAP_COREVCAP_CORE_IDX)When a core is mapped to a specific VCAP lookups for that VCAP will be applied to the core VCAP priority is still observed a match in two cores will only cause the most significant rule to be hit (highest address)After reset all cores are in power-save modeTBD

Table 399 bull Registers in TCAM_BIST

TCAM_CTRL 0x00000000 1 Control of the TCAM Page 194

TCAM_STAT 0x00000008 1 Status for the TCAM Page 194

Table 400 bull Fields in TCAM_CTRL

Field Name Bit Access Description DefaultTCAM_BIST 1 One-shot Set this field to start manual BIST of the

TCAM This field will be cleared once BIST is complete The BIST procedure requires that the TCAM is initialized before start setting TCAM_INIT at the same time as setting this field will first initialize the TCAM and then run BIST

TCAM_INIT 0 One-shot Set this field to start manual initialization of the TCAM This field is cleared once initialization is completeThe TCAM has random contents after reset and must be initialized prior to usage

Registers

210 PCIE

2101 PCIEPCIE_TYPE0_HDRParent PCIE

Instances 1

Table 401 bull Fields in TCAM_STAT

Field Name Bit Access Description DefaultBIST_ERR 2 RO Set if BIST failed 0x0

BIST_BUSY 1 RO Set while BIST is running When checking the BIST result this field must be cleared

TCAM_RDY 0 RO Indicates the current operational state of the TCAM0 Busy with initialization1 Ready to be used

Table 402 bull Register Groups in PCIE

PCIE_TYPE0_HDR 0x00000000 1 PCIe Header Type 0 Page 195

PCIE_PM_CAP 0x00000040 1 PCIe Power Management Interface

PCIE_MSI_CAP 0x00000050 1 PCIe Message Signaled Interrupts

PCIE_CAP 0x00000070 1 PCIe Capability Register Set Page 203

PCIE_AER_CAP 0x00000100 1 PCIe Advanced Error Capability and Control

PCIE_PORT_LOGIC 0x00000700 1 PCIe Port Logic Page 212

Table 403 bull Registers in PCIE_TYPE0_HDR

DEVICE_ID_VENDOR_ID 0x00000000 1 Word offset 0 Page 196

STATUS_COMMAND 0x00000004 1 Word offset 1 Page 196

CLASS_CODE_REVISION_ID 0x00000008 1 Word offset 2 Page 197

BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE

0x0000000C 1 Word offset 3 Page 197

BAR0 0x00000010 1 Word offset 4 Page 198

Registers

21011 PCIEPCIE_TYPE0_HDRDEVICE_ID_VENDOR_IDParent PCIEPCIE_TYPE0_HDR

Instances 1

21012 PCIEPCIE_TYPE0_HDRSTATUS_COMMANDParent PCIEPCIE_TYPE0_HDR

Instances 1

BAR3 0x0000001C 1 Word offset 7 Page 198

CARDBUS_CIS_PTR 0x00000028 1 Word offset 10 Page 199

SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID

EXP_ROM_BASE_ADDR 0x00000030 1 Word offset 12 Page 200

PCI_CAP_PTR 0x00000034 1 Word offset 13 Page 200

MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE

Table 404 bull Fields in DEVICE_ID_VENDOR_ID

Field Name Bit Access Description DefaultPCI_TYPE0_DEVICE_ID 3116 RW 0xB005

PCI_TYPE0_VENDOR_ID 150 RW 0x101B

Table 405 bull Fields in STATUS_COMMAND

Field Name Bit Access Description DefaultDETECTED_PARITY_ERR 31 One-shot 0x0

SIGNALED_SYS_ERR 30 One-shot 0x0

RCVD_MASTER_ABORT 29 One-shot 0x0

RCVD_TARGET_ABORT 28 One-shot 0x0

SIGNALED_TARGET_ABORT 27 One-shot 0x0

DEV_SEL_TIMING 2625 RO 0x0

MASTER_DPE 24 One-shot 0x0

FAST_B2B_CAP 23 RO 0x0

FAST_66MHZ_CAP 21 RO 0x0

Table 403 bull Registers in PCIE_TYPE0_HDR (continued)

Registers

21013 PCIEPCIE_TYPE0_HDRCLASS_CODE_REVISION_IDParent PCIEPCIE_TYPE0_HDR

Instances 1

21014 PCIEPCIE_TYPE0_HDRBIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZEParent PCIEPCIE_TYPE0_HDR

Instances 1

CAP_LIST 20 RO 0x1

INT_STATUS 19 One-shot 0x0

PCI_TYPE_RESERV 1611 RO 0x00

PCI_TYPE0_INT_EN 10 RW 0x0

PCI_TYPE0_SERREN 8 RW 0x0

PCI_TYPE_IDSEL_STEPPING 7 RO 0x0

PCI_TYPE0_PARITY_ERR_EN 6 RW 0x0

PCI_TYPE_VGA_PALETTE_SNOOP

5 RO 0x0

PCI_TYPE_MWI_ENABLE 4 RO 0x0

PCI_TYPE0_SPECIAL_CYCLE_OPERATION

3 RO 0x0

PCI_TYPE0_BUS_MASTER_EN 2 RW 0x0

PCI_TYPE0_MEM_SPACE_EN 1 RW 0x0

PCI_TYPE0_IO_EN 0 RW 0x0

Table 406 bull Fields in CLASS_CODE_REVISION_ID

Field Name Bit Access Description DefaultBASE_CLASS_CODE 3124 RW 0x02

SUBCLASS_CODE 2316 RW 0x80

PROGRAM_INTERFACE 158 RW 0x00

REVISION_ID 70 RW 0x00

Table 407 bull Fields in BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE

Field Name Bit Access Description DefaultBIST 3124 RO 0x00

MULTI_FUNC 23 RW 0x0

HEADER_TYPE 2216 RO 0x00

LATENCY_MASTER_TIMER 158 RO 0x00

Table 405 bull Fields in STATUS_COMMAND (continued)

Registers

21015 PCIEPCIE_TYPE0_HDRBAR0Parent PCIEPCIE_TYPE0_HDR

Instances 1

CACHE_LINE_SIZE 70 RW 0x00

Table 408 bull Fields in BAR0

Field Name Bit Access Description DefaultBAR0_START 314 RW 0x0000000

BAR0_PREFETCH 3 RW 0x0

BAR0_TYPE 21 RW 0x0

BAR0_MEM_IO 0 RW 0x0

BAR1_PREFETCH 3 RO 0x0

BAR1_TYPE 21 RO 0x0

BAR1_MEM_IO 0 RO 0x0

BAR2_TYPE 21 RW 0x0

Table 407 bull Fields in BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE (continued)

Registers

Instances 1

210111 PCIEPCIE_TYPE0_HDRCARDBUS_CIS_PTRParent PCIEPCIE_TYPE0_HDR

Instances 1

BAR3_TYPE 21 RO 0x0

BAR4_TYPE 21 RW 0x0

BAR5_TYPE 21 RO 0x0

Table 414 bull Fields in CARDBUS_CIS_PTR

Field Name Bit Access Description DefaultCARDBUS_CIS_POINTER 310 RW 0x00000000

Registers

210112 PCIEPCIE_TYPE0_HDRSUBSYSTEM_ID_SUBSYSTEM_VENDOR_IDParent PCIEPCIE_TYPE0_HDR

Instances 1

210113 PCIEPCIE_TYPE0_HDREXP_ROM_BASE_ADDRParent PCIEPCIE_TYPE0_HDR

Instances 1

210114 PCIEPCIE_TYPE0_HDRPCI_CAP_PTRParent PCIEPCIE_TYPE0_HDR

Instances 1

210115 PCIEPCIE_TYPE0_HDRMAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINEParent PCIEPCIE_TYPE0_HDR

Instances 1

2102 PCIEPCIE_PM_CAPParent PCIE

Instances 1

Table 415 bull Fields in SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID

Field Name Bit Access Description DefaultSUBSYS_DEV_ID 3116 RW 0x0000

SUBSYS_VENDOR_ID 150 RW 0x101B

Table 416 bull Fields in EXP_ROM_BASE_ADDR

Field Name Bit Access Description DefaultEXP_ROM_BASE_ADDRESS 3111 RW 0x000000

ROM_BAR_ENABLE 0 RO 0x0

Table 417 bull Fields in PCI_CAP_PTR

Field Name Bit Access Description DefaultCAP_POINTER 70 RW 0x40

Table 418 bull Fields in MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE

Field Name Bit Access Description DefaultINT_PIN 158 RW 0x01

INT_LINE 70 RW 0xFF

Registers

21021 PCIEPCIE_PM_CAPCAP_ID_NXT_PTRParent PCIEPCIE_PM_CAP

Instances 1

21022 PCIEPCIE_PM_CAPCON_STATUSParent PCIEPCIE_PM_CAP

Instances 1

Table 419 bull Registers in PCIE_PM_CAP

CAP_ID_NXT_PTR 0x00000000 1 Word offset 0 Page 201

CON_STATUS 0x00000004 1 Word offset 1 Page 201

Table 420 bull Fields in CAP_ID_NXT_PTR

Field Name Bit Access Description DefaultPME_SUPPORT 3127 RW 0x1B

D2_SUPPORT 26 RW 0x0

AUX_CURR 2422 RW 0x1

DSI 21 RW 0x1

PME_CLK 19 RO 0x0

PM_SPEC_VER 1816 RW 0x3

PM_NEXT_POINTER 158 RW 0x50

PM_CAP_ID 70 RO 0x01

Table 421 bull Fields in CON_STATUS

Field Name Bit Access Description DefaultDATA_REG_ADD_INFO 3124 RO 0x00

BUS_PWR_CLK_CON_EN 23 RO 0x0

B2_B3_SUPPORT 22 RO 0x0

PME_STATUS 15 One-shot 0x0

DATA_SCALE 1413 RO 0x0

DATA_SELECT 129 RO 0x0

PME_ENABLE 8 RW 0x0

NO_SOFT_RST 3 RW 0x0

POWER_STATE 10 RW 0x0

Registers

2103 PCIEPCIE_MSI_CAPParent PCIE

Instances 1

21031 PCIEPCIE_MSI_CAPPCI_MSI_CAP_ID_NEXT_CTRLParent PCIEPCIE_MSI_CAP

Instances 1

21032 PCIEPCIE_MSI_CAPMSI_LOWER_32Parent PCIEPCIE_MSI_CAP

Instances 1

21033 PCIEPCIE_MSI_CAPMSI_UPPER_32Parent PCIEPCIE_MSI_CAP

Instances 1

Table 422 bull Registers in PCIE_MSI_CAP

PCI_MSI_CAP_ID_NEXT_CTRL 0x00000000 1 Word offset 0 Page 202

MSI_LOWER_32 0x00000004 1 Word offset 1 Page 202

MSI_UPPER_32 0x00000008 1 Word offset 2 Page 202

MSI_PENDING_BIT 0x00000014 1 Word offset 5 Page 203

Table 423 bull Fields in PCI_MSI_CAP_ID_NEXT_CTRL

Field Name Bit Access Description DefaultPCI_PVM_SUPPORT 24 RO 0x0

PCI_MSI_64_BIT_ADDR_CAP 23 RW 0x1

PCI_MSI_MULTIPLE_MSG_EN 2220 RW 0x0

PCI_MSI_MULTIPLE_MSG_CAP 1917 RW 0x2

PCI_MSI_ENABLE 16 RW 0x0

PCI_MSI_CAP_NEXT_OFFSET 158 RW 0x70

PCI_MSI_CAP_ID 70 RO 0x05

Table 424 bull Fields in MSI_LOWER_32

Field Name Bit Access Description DefaultPCI_MSI_LOWER_32 312 RW 0x00000000

Registers

21034 PCIEPCIE_MSI_CAPMSI_PENDING_BITParent PCIEPCIE_MSI_CAP

Instances 1

2104 PCIEPCIE_CAPParent PCIE

Instances 1

21041 PCIEPCIE_CAPPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAPParent PCIEPCIE_CAP

Instances 1

Table 425 bull Fields in MSI_UPPER_32

Field Name Bit Access Description DefaultPCI_MSI_UPPER_32 310 RW 0x00000000

Table 426 bull Fields in MSI_PENDING_BIT

Field Name Bit Access Description DefaultPCI_MSI_PENDING_BIT 310 RO 0x00000000

Table 427 bull Registers in PCIE_CAP

PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP

0x00000000 1 Word offset 0 Page 203

DEVICE_CAPABILITIES 0x00000004 1 Word offset 1 Page 204

DEVICE_CONTROL_DEVICE_STATUS

LINK_CAPABILITIES 0x0000000C 1 Word offset 3 Page 205

LINK_CONTROL_LINK_STATUS 0x00000010 1 Word offset 4 Page 206

DEVICE_CAPABILITIES2 0x00000024 1 Word offset 9 Page 206

DEVICE_CONTROL2_DEVICE_STATUS2

LINK_CAPABILITIES2 0x0000002C 1 Word offset 11 Page 207

LINK_CONTROL2_LINK_STATUS2

Registers

21042 PCIEPCIE_CAPDEVICE_CAPABILITIESParent PCIEPCIE_CAP

Instances 1

21043 PCIEPCIE_CAPDEVICE_CONTROL_DEVICE_STATUSParent PCIEPCIE_CAP

Instances 1

Table 428 bull Fields in PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP

Field Name Bit Access Description DefaultRSVD 30 RO 0x0

PCIE_INT_MSG_NUM 2925 RW 0x00

PCIE_SLOT_IMP 24 RW 0x0

PCIE_DEV_PORT_TYPE 2320 RO 0x0

PCIE_CAP 1916 RO 0x2

PCIE_CAP_NEXT_PTR 158 RW 0x00

PCIE_CAP_ID 70 RO 0x10

Table 429 bull Fields in DEVICE_CAPABILITIES

Field Name Bit Access Description DefaultPCIE_CAP_FLR_CAP 28 RW 0x0

PCIE_CAP_ROLE_BASED_ERR_REPORT

15 RW 0x1

PCIE_CAP_EP_L1_ACCPT_LATENCY

119 RW 0x7

PCIE_CAP_EP_L0S_ACCPT_LATENCY

86 RW 0x5

PCIE_CAP_EXT_TAG_SUPP 5 RW 0x0

PCIE_CAP_PHANTOM_FUNC_SUPPORT

43 RW 0x0

PCIE_CAP_MAX_PAYLOAD_SIZE

20 RW 0x0

Table 430 bull Fields in DEVICE_CONTROL_DEVICE_STATUS

Field Name Bit Access Description DefaultPCIE_CAP_TRANS_PENDING 21 RO 0x0

PCIE_CAP_AUX_POWER_DETECTED

20 RO 0x1

PCIE_CAP_UNSUPPORTED_REQ_DETECTED

19 One-shot 0x0

Registers

21044 PCIEPCIE_CAPLINK_CAPABILITIESParent PCIEPCIE_CAP

Instances 1

PCIE_CAP_FATAL_ERR_DETECTED

18 One-shot 0x0

PCIE_CAP_NON_FATAL_ERR_DETECTED

17 One-shot 0x0

PCIE_CAP_CORR_ERR_DETECTED

16 One-shot 0x0

PCIE_CAP_INITIATE_FLR 15 RW 0x0

PCIE_CAP_MAX_READ_REQ_SIZE

1412 RW 0x2

PCIE_CAP_EN_NO_SNOOP 11 RO 0x0

PCIE_CAP_AUX_POWER_PM_EN

10 RW 0x0

PCIE_CAP_PHANTOM_FUNC_EN

9 RO 0x0

PCIE_CAP_EXT_TAG_EN 8 RO 0x0

PCIE_CAP_MAX_PAYLOAD_SIZE_CS

75 RW 0x0

PCIE_CAP_EN_REL_ORDER 4 RW 0x1

PCIE_CAP_UNSUPPORT_REQ_REP_EN

3 RW 0x0

PCIE_CAP_FATAL_ERR_REPORT_EN

2 RW 0x0

PCIE_CAP_NON_FATAL_ERR_REPORT_EN

1 RW 0x0

PCIE_CAP_CORR_ERR_REPORT_EN

0 RW 0x0

Table 431 bull Fields in LINK_CAPABILITIES

Field Name Bit Access Description DefaultPCIE_CAP_PORT_NUM 3124 RW 0x00

PCIE_CAP_ASPM_OPT_COMPLIANCE

22 RW 0x1

PCIE_CAP_LINK_BW_NOT_CAP 21 RO 0x0

PCIE_CAP_DLL_ACTIVE_REP_CAP

20 RO 0x0

PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP

19 RO 0x0

Table 430 bull Fields in DEVICE_CONTROL_DEVICE_STATUS (continued)

Registers

21045 PCIEPCIE_CAPLINK_CONTROL_LINK_STATUSParent PCIEPCIE_CAP

Instances 1

21046 PCIEPCIE_CAPDEVICE_CAPABILITIES2Parent PCIEPCIE_CAP

PCIE_CAP_CLOCK_POWER_MAN

18 RW 0x0

PCIE_CAP_L1_EXIT_LATENCY 1715 RW 0x0

PCIE_CAP_L0S_EXIT_LATENCY 1412 RW 0x3

PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT

1110 RW 0x3

PCIE_CAP_MAX_LINK_WIDTH 94 RW 0x01

PCIE_CAP_MAX_LINK_SPEED 30 RW 0x1

Table 432 bull Fields in LINK_CONTROL_LINK_STATUS

Field Name Bit Access Description DefaultPCIE_CAP_LINK_AUOT_BW_STATUS

31 RO 0x0

PCIE_CAP_LINK_BW_MAN_STATUS

30 RO 0x0

PCIE_CAP_DLL_ACTIVE 29 RO 0x0

PCIE_CAP_SLOT_CLK_CONFIG 28 RW 0x0

PCIE_CAP_LINK_TRAINING 27 RO 0x0

PCIE_CAP_NEGO_LINK_WIDTH 2420 RO 0x01

PCIE_CAP_LINK_SPEED 1916 RO 0x1

PCIE_CAP_LINK_AUTO_BW_INT_EN

11 RO 0x0

PCIE_CAP_LINK_BW_MAN_INT_EN

10 RW 0x0

PCIE_CAP_EN_CLK_POWER_MAN

8 RW 0x0

PCIE_CAP_EXTENDED_SYNCH 7 RW 0x0

PCIE_CAP_COMMON_CLK_CONFIG

6 RW 0x0

PCIE_CAP_RETRAIN_LINK 5 RO 0x0

PCIE_CAP_LINK_DISABLE 4 RO 0x0

PCIE_CAP_RCB 3 RO 0x0

PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL

10 RW 0x0

Table 431 bull Fields in LINK_CAPABILITIES (continued)

Registers

Instances 1

21047 PCIEPCIE_CAPDEVICE_CONTROL2_DEVICE_STATUS2Parent PCIEPCIE_CAP

Instances 1

21048 PCIEPCIE_CAPLINK_CAPABILITIES2Parent PCIEPCIE_CAP

Instances 1

Table 433 bull Fields in DEVICE_CAPABILITIES2

Field Name Bit Access Description DefaultPCIE_CAP_OBFF_SUPPORT 1918 RO 0x0

PCIE_CAP_TPH_CMPLT_SUPPORT_1

13 RO 0x0

12 RO 0x0

PCIE_CAP_LTR_SUPP 11 RO 0x0

PCIE_CAP_NO_RO_EN_PR2PR_PAR

10 RW 0x0

PCIE_CAP_128_CAS_CPL_SUPP 9 RO 0x0

PCIE_CAP_64_ATOMIC_CPL_SUPP

8 RO 0x0

7 RO 0x0

PCIE_CAP_ATOMIC_ROUTING_SUPP

6 RO 0x0

PCIE_CAP_ARI_FORWARD_SUPPORT

5 RO 0x0

PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT

4 RO 0x1

PCIE_CAP_CPL_TIMEOUT_RANGE

30 RW 0x0

Table 434 bull Fields in DEVICE_CONTROL2_DEVICE_STATUS2

Field Name Bit Access Description DefaultPCIE_CAP_ARI_FORWARD_SUPPORT_CS

5 RO 0x0

PCIE_CAP_CPL_TIMEOUT_DISABLE

4 RW 0x0

Registers

21049 PCIEPCIE_CAPLINK_CONTROL2_LINK_STATUS2Parent PCIEPCIE_CAP

Instances 1

2105 PCIEPCIE_AER_CAPParent PCIE

Instances 1

Table 435 bull Fields in LINK_CAPABILITIES2

Field Name Bit Access Description DefaultPCIE_CAP_CROSS_LINK_SUPPORT

8 RO 0x0

PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR

71 RO 0x01

Table 436 bull Fields in LINK_CONTROL2_LINK_STATUS2

Field Name Bit Access Description DefaultPCIE_CAP_LINK_EQ_REQ 21 One-shot 0x0

PCIE_CAP_EQ_CPL_P3 20 RW 0x0

PCIE_CAP_EQ_CPL_P1 18 RO 0x0

PCIE_CAP_EQ_CPL 17 RO 0x0

PCIE_CAP_CURR_DEEMPHASIS 16 RO 0x0

Table 437 bull Registers in PCIE_AER_CAP

AER_EXT_CAP_HDR 0x00000000 1 Word offset 0 Page 209

UNCORR_ERR_STATUS 0x00000004 1 Word offset 1 Page 209

UNCORR_ERR_MASK 0x00000008 1 Word offset 2 Page 209

UNCORR_ERR_SEV 0x0000000C 1 Word offset 3 Page 210

CORR_ERR_STATUS 0x00000010 1 Word offset 4 Page 211

CORR_ERR_MASK 0x00000014 1 Word offset 5 Page 211

ADV_ERR_CAP_CTRL 0x00000018 1 Word offset 6 Page 211

HDR_LOG_REG_0 0x0000001C 1 Word offset 7 Page 212

HDR_LOG_REG_1 0x00000020 1 Word offset 8 Page 212

Registers

21051 PCIEPCIE_AER_CAPAER_EXT_CAP_HDRParent PCIEPCIE_AER_CAP

Instances 1

21052 PCIEPCIE_AER_CAPUNCORR_ERR_STATUSParent PCIEPCIE_AER_CAP

Instances 1

21053 PCIEPCIE_AER_CAPUNCORR_ERR_MASKParent PCIEPCIE_AER_CAP

Instances 1

Table 438 bull Fields in AER_EXT_CAP_HDR

Field Name Bit Access Description DefaultNEXT_OFFSET 3120 RO 0x000

CAP_VERSION 1916 RO 0x2

CAP_ID 150 RO 0x0001

Table 439 bull Fields in UNCORR_ERR_STATUS

Field Name Bit Access Description DefaultATOMIC_EGRESS_BLOCKED_ERR_STATUS

24 One-shot 0x0

INTERNAL_ERR_STATUS 22 One-shot 0x0

UNSUPPORTED_REQ_ERR_STATUS

20 One-shot 0x0

ECRC_ERR_STATUS 19 One-shot 0x0

MALF_TLP_ERR_STATUS 18 One-shot 0x0

REC_OVERFLOW_ERR_STATUS 17 One-shot 0x0

UNEXP_CMPLT_ERR_STATUS 16 One-shot 0x0

CMPLT_ABORT_ERR_STATUS 15 One-shot 0x0

CMPLT_TIMEOUT_ERR_STATUS 14 One-shot 0x0

FC_PROTOCOL_ERR_STATUS 13 One-shot 0x0

POIS_TLP_ERR_STATUS 12 One-shot 0x0

SUR_DWN_ERR_STATUS 5 RO 0x0

DL_PROTOCOL_ERR_STATUS 4 One-shot 0x0

Table 440 bull Fields in UNCORR_ERR_MASK

Field Name Bit Access Description DefaultATOMIC_EGRESS_BLOCKED_ERR_MASK

24 RO 0x0

Registers

21054 PCIEPCIE_AER_CAPUNCORR_ERR_SEVParent PCIEPCIE_AER_CAP

Instances 1

INTERNAL_ERR_MASK 22 RW 0x1

UNSUPPORTED_REQ_ERR_MASK

20 RW 0x0

ECRC_ERR_MASK 19 RW 0x0

MALF_TLP_ERR_MASK 18 RW 0x0

REC_OVERFLOW_ERR_MASK 17 RW 0x0

UNEXP_CMPLT_ERR_MASK 16 RW 0x0

CMPLT_ABORT_ERR_MASK 15 RW 0x0

CMPLT_TIMEOUT_ERR_MASK 14 RW 0x0

FC_PROTOCOL_ERR_MASK 13 RW 0x0

POIS_TLP_ERR_MASK 12 RW 0x0

SUR_DWN_ERR_MASK 5 RO 0x0

DL_PROTOCOL_ERR_MASK 4 RW 0x0

Table 441 bull Fields in UNCORR_ERR_SEV

Field Name Bit Access Description DefaultATOMIC_EGRESS_BLOCKED_ERR_SEVERITY

24 RO 0x0

INTERNAL_ERR_SEVERITY 22 RW 0x1

UNSUPPORTED_REQ_ERR_SEVERITY

20 RW 0x0

ECRC_ERR_SEVERITY 19 RW 0x0

MALF_TLP_ERR_SEVERITY 18 RW 0x1

REC_OVERFLOW_ERR_SEVERITY

17 RW 0x1

UNEXP_CMPLT_ERR_SEVERITY 16 RW 0x0

CMPLT_ABORT_ERR_SEVERITY 15 RW 0x0

CMPLT_TIMEOUT_ERR_SEVERITY

14 RW 0x0

FC_PROTOCOL_ERR_SEVERITY

13 RW 0x1

POIS_TLP_ERR_SEVERITY 12 RW 0x0

SUR_DWN_ERR_SEVERITY 5 RO 0x1

DL_PROTOCOL_ERR_SEVERITY

4 RW 0x1

Table 440 bull Fields in UNCORR_ERR_MASK (continued)

Registers

21055 PCIEPCIE_AER_CAPCORR_ERR_STATUSParent PCIEPCIE_AER_CAP

Instances 1

21056 PCIEPCIE_AER_CAPCORR_ERR_MASKParent PCIEPCIE_AER_CAP

Instances 1

21057 PCIEPCIE_AER_CAPADV_ERR_CAP_CTRLParent PCIEPCIE_AER_CAP

Instances 1

Table 442 bull Fields in CORR_ERR_STATUS

Field Name Bit Access Description DefaultCORRECTED_INT_ERR_STATUS 14 One-shot 0x0

ADVISORY_NON_FATAL_ERR_STATUS

13 One-shot 0x0

RPL_TIMER_TIMEOUT_STATUS 12 One-shot 0x0

REPLAY_NO_ROLEOVER_STATUS

8 One-shot 0x0

BAD_DLLP_STATUS 7 One-shot 0x0

BAD_TLP_STATUS 6 One-shot 0x0

RX_ERR_STATUS 0 One-shot 0x0

Table 443 bull Fields in CORR_ERR_MASK

Field Name Bit Access Description DefaultCORRECTED_INT_ERR_MASK 14 RW 0x1

ADVISORY_NON_FATAL_ERR_MASK

13 RW 0x1

RPL_TIMER_TIMEOUT_MASK 12 RW 0x0

REPLAY_NO_ROLEOVER_MASK 8 RW 0x0

BAD_DLLP_MASK 7 RW 0x0

BAD_TLP_MASK 6 RW 0x0

RX_ERR_MASK 0 RW 0x0

Table 444 bull Fields in ADV_ERR_CAP_CTRL

Field Name Bit Access Description DefaultECRC_CHECK_EN 8 RW 0x0

ECRC_CHECK_CAP 7 RO 0x1

ECRC_GEN_EN 6 RW 0x0

Registers

21058 PCIEPCIE_AER_CAPHDR_LOG_REG_0Parent PCIEPCIE_AER_CAP

Instances 1

2106 PCIEPCIE_PORT_LOGICParent PCIE

ECRC_GEN_CAP 5 RO 0x1

FIRST_ERR_POINTER 40 RO 0x00

Table 445 bull Fields in HDR_LOG_REG_0

Field Name Bit Access Description DefaultFIRST_DWORD 310 RO 0x00000000

Field Name Bit Access Description DefaultSECOND_DWORD 310 RO 0x00000000

Field Name Bit Access Description DefaultTHIRD_DWORD 310 RO 0x00000000

Field Name Bit Access Description DefaultFOURTH_DWORD 310 RO 0x00000000

Table 444 bull Fields in ADV_ERR_CAP_CTRL (continued)

Registers

Instances 1

21061 PCIEPCIE_PORT_LOGICATU_REGIONParent PCIEPCIE_PORT_LOGIC

Instances 1

The address translation unit supports 2 outbound regions The registers PCIEATU_CFG1 PCIEATU_CFG2 PCIEATU_BASE_ADDR_LOW PCIEATU_BASE_ADDR_HIGH PCIEATU_LIMIT_ADDR PCIEATU_TGT_ADDR_LOW and PCIEATU_TGT_ADDR_HIGH all maps to the currently configured region (as configured in this register)

21062 PCIEPCIE_PORT_LOGICATU_CFG1Parent PCIEPCIE_PORT_LOGIC

Instances 1

Table 449 bull Registers in PCIE_PORT_LOGIC

ATU_REGION 0x00000200 1 Address translation region Page 213

ATU_CFG1 0x00000204 1 Address translation configuration register 1

ATU_BASE_ADDR_LOW 0x0000020C 1 Address translation lower base address

ATU_BASE_ADDR_HIGH 0x00000210 1 Address translation upper base address

ATU_LIMIT_ADDR 0x00000214 1 Address translation limit address

ATU_TGT_ADDR_LOW 0x00000218 1 Address translation lower target address

ATU_TGT_ADDR_HIGH 0x0000021C 1 Address translation upper target address

Table 450 bull Fields in ATU_REGION

Field Name Bit Access Description DefaultATU_IDX 20 RW Selects region index set to 0 or 1 0x0

Table 451 bull Fields in ATU_CFG1

Field Name Bit Access Description DefaultATU_ATTR 109 RW When the address of an outbound TLP is

matched to this region then the ATTR field of the TLP is changed to the value in this register

Registers

Instances 1

21064 PCIEPCIE_PORT_LOGICATU_BASE_ADDR_LOWParent PCIEPCIE_PORT_LOGIC

Instances 1

21065 PCIEPCIE_PORT_LOGICATU_BASE_ADDR_HIGHParent PCIEPCIE_PORT_LOGIC

Instances 1

ATU_TD 8 RW When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register

ATU_TC 75 RW When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register

ATU_TYPE 40 RW When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register0 MRdMWr1 MRdLk2 IORdIOWr4 CfgRd0CfgWr05 CfgRd1CfgWr116-23 MsgMsgD

Field Name Bit Access Description DefaultATU_REGION_ENA 31 RW This bit must be set for address translation to

take place0x0

ATU_MSG_CODE 70 RW When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD then the Message field of the TLP is changed to the value in this register

Table 453 bull Fields in ATU_BASE_ADDR_LOW

Field Name Bit Access Description DefaultATU_BASE_ADDR_LOW 3116 RW Bits 3116 of the starting address of the

address region to be translated0x0000

Table 451 bull Fields in ATU_CFG1 (continued)

Registers

21066 PCIEPCIE_PORT_LOGICATU_LIMIT_ADDRParent PCIEPCIE_PORT_LOGIC

Instances 1

21067 PCIEPCIE_PORT_LOGICATU_TGT_ADDR_LOWParent PCIEPCIE_PORT_LOGIC

Instances 1

21068 PCIEPCIE_PORT_LOGICATU_TGT_ADDR_HIGHParent PCIEPCIE_PORT_LOGIC

Instances 1

Table 454 bull Fields in ATU_BASE_ADDR_HIGH

Field Name Bit Access Description DefaultATU_BASE_ADDR_HIGH 310 RW Outbound Not used

Inbound Bits 6332 of the starting address of the address region to be translated

0x00000000

Table 455 bull Fields in ATU_LIMIT_ADDR

Field Name Bit Access Description DefaultATU_LIMIT_ADDR 3116 RW Bits 3116 of the ending address of the

RESERVED_3 150 RO 0xFFFF

Table 456 bull Fields in ATU_TGT_ADDR_LOW

Field Name Bit Access Description DefaultATU_TGT_ADDR_LOW 3116 RW Bits 3116 of the new address of the

translated region0x0000

Table 457 bull Fields in ATU_TGT_ADDR_HIGH

Field Name Bit Access Description DefaultATU_TGT_ADDR_HIGH 310 RW Bits 6332 of the new address of the

translated regionSet to 0 to force new address into 32bit PCIe memory space

0x00000000

Registers

211 QSYS

2111 QSYSSYSTEMParent QSYS

Instances 1

Table 458 bull Register Groups in QSYS

SYSTEM 0x00011200 1 Switch configuration Page 216

TIMED_FRAME_CFG 0x00011310 1 Page 221

RES_QOS_ADV 0x00011338 1 Advanced QoS Configuration Page 224

RES_CTRL 0x00012000 10240x00000008

Watermarks and status for egress queue system

DROP_CFG 0x0001137C 1 Watermarks for egress queue system

MMGT 0x00011380 1 Memory manager status Page 227

HSCH 0x00000000 5480x00000080

Configuration of scheduling system and shapers

HSCH_MISC 0x00011388 1 Miscellaneous scheduler configuration

Table 459 bull Registers in SYSTEM

PORT_MODE 0x00000000 130x00000004

SWITCH_PORT_MODE 0x00000034 120x00000004

Various switch port mode settings per switch port

STAT_CNT_CFG 0x00000064 1 Statistics configuration Page 218

EEE_CFG 0x00000068 110x00000004

Control Energy Efficient Ethernet operation per front port

EEE_THRES 0x00000094 1 Thresholds for delayed EEE queues

IGR_NO_SHARING 0x00000098 1 Control shared memory users Page 219

EGR_NO_SHARING 0x0000009C 1 Control shared memory users Page 219

SW_STATUS 0x000000A0 120x00000004

Various status information per switch port

EXT_CPU_CFG 0x000000D0 1 External CPU port configuration

Registers

21111 QSYSSYSTEMPORT_MODEParent QSYSSYSTEM

Instances 13

These configurations exists per front port and for each of the two CPU ports (11+12)

21112 QSYSSYSTEMSWITCH_PORT_MODEParent QSYSSYSTEM

Instances 12

CPU_GROUP_MAP 0x000000D8 1 Map CPU extraction queues to CPU ports

Field Name Bit Access Description DefaultDEQUEUE_DIS 1 RW Disable dequeuing from the egress queues

Frames are not discarded but may become aged when dequeuing is re-enabled

DEQUEUE_LATE 0 RW Delay dequeuing from the egress queues This might be necessary for minimising flow control tails

Table 461 bull Fields in SWITCH_PORT_MODE

Field Name Bit Access Description DefaultPORT_ENA 14 RW Enable port for any frame transfer

Frames to or from a port with PORT_ENA cleared are discarded

SCH_NEXT_CFG 1311 RW Configures the time at which next frame for a port is decided A low value can result in IFGs but that the arbitration be tween multiple queues can run true round-robin A high value will result in back-to-back transmissions but with an overshoot compared to shaper burst configurations and PFC blocking events0 At EOF cell1 When one cell is yet to transmitn When n cells are yet to be transmitted7 When all cells are yet to be transmitted

Table 459 bull Registers in SYSTEM (continued)

Registers

21113 QSYSSYSTEMSTAT_CNT_CFGParent QSYSSYSTEM

Instances 1

21114 QSYSSYSTEMEEE_CFGParent QSYSSYSTEM

Instances 11

INGRESS_DROP_MODE 9 RW When enabled for a port frames -from- that port are discarded when the controlling watermarks are hit If disabled - the frame will stay in memory until resources are available If INGRESS_DROP_MODE or EGRESS_DROP_MODE applies for a frame copy it will be discared

TX_PFC_ENA 81 RW When set the MAC sends PRIO pause control frames in the Tx direction when congested

TX_PFC_MODE 0 RW When set a congested priority request pause of all lower priorities as well

Table 462 bull Fields in STAT_CNT_CFG

Field Name Bit Access Description DefaultTX_GREEN_CNT_MODE 5 RW Counter mode for the Tx priority counters for

green frames (C_TX_GREEN_PRIO_x)0 Count octets1 Count frames

TX_YELLOW_CNT_MODE 4 RW Counter mode for the Tx priority counters for green frames (C_TX_YELLOW_PRIO_x)0 Count octets1 Count frames

DROP_GREEN_CNT_MODE 3 RW Counter mode for the drop counters for green frames (C_DR_GREEN_PRIO_x)0 Count octets1 Count frames

DROP_YELLOW_CNT_MODE 2 RW Counter mode for the drop counters for green frames (C_DR_YELLOW_PRIO_x)0 Count octets1 Count frames

DROP_COUNT_EGRESS 0 RW When set a frame discarded due to lack of resources is counted on the egress port instead of the ingress Side effect is a slower processing of multiple drops on the same frame causing potential head-of-line blocking

Table 461 bull Fields in SWITCH_PORT_MODE (continued)

Registers

21115 QSYSSYSTEMEEE_THRESParent QSYSSYSTEM

Instances 1

21116 QSYSSYSTEMIGR_NO_SHARINGParent QSYSSYSTEM

Instances 1

21117 QSYSSYSTEMEGR_NO_SHARINGParent QSYSSYSTEM

Instances 1

Field Name Bit Access Description DefaultEEE_FAST_QUEUES 70 RW Queues set in this mask activate the egress

port immediately when any of the queues have data available

Table 464 bull Fields in EEE_THRES

Field Name Bit Access Description DefaultEEE_HIGH_BYTES 158 RW Maximum number of bytes in a queue before

egress port is activated Unit is 60 bytes0x00

EEE_HIGH_FRAMES 70 RW Maximum number of frames in a queue before the egress port is activated Unit is 1 frame

Table 465 bull Fields in IGR_NO_SHARING

Field Name Bit Access Description DefaultIGR_NO_SHARING 110 RW Control whether frames received on the port

may use shared resources If ingress port or queue has reserved memory left to use frame enqueuing is always allowed0 Use shared memory as well1 Do not use shared memory

Registers

21118 QSYSSYSTEMSW_STATUSParent QSYSSYSTEM

Instances 12

21119 QSYSSYSTEMEXT_CPU_CFGParent QSYSSYSTEM

Instances 1

211110 QSYSSYSTEMCPU_GROUP_MAPParent QSYSSYSTEM

Instances 1

Table 466 bull Fields in EGR_NO_SHARING

Field Name Bit Access Description DefaultEGR_NO_SHARING 110 RW Control whether frames forwarded to the port

may use shared resources If egress port or queue has reserved memory left to use frame enqueuing is always allowed0 Use shared memory as well1 Do not use shared memory

Table 467 bull Fields in SW_STATUS

Field Name Bit Access Description DefaultEQ_AVAIL 70 RO Status bit per egress queue indicating

whether data is ready for transmission0x00

Table 468 bull Fields in EXT_CPU_CFG

Field Name Bit Access Description DefaultEXT_CPU_PORT 128 RW Select the port to use as the external CPU

port0x08

EXT_CPUQ_MSK 70 RW Frames destined for a CPU extraction queue set in this mask are sent to the external CPU defined by EXT_CPU_PORT instead of the internal CPU

Registers

2112 QSYSTIMED_FRAME_CFGParent QSYS

Instances 1

21121 QSYSTIMED_FRAME_CFGTFRM_MISCParent QSYSTIMED_FRAME_CFG

Instances 1

Table 469 bull Fields in CPU_GROUP_MAP

Field Name Bit Access Description DefaultCPU_GROUP_MAP 70 RW Map the 8 CPU extraction queues to the two

CPU ports Bit ltngt set to 1 directs CPU extraction queue ltngt to CPU port 12 Bit ltngt set to 0 directs CPU extraction queue ltngt to CPU port 11

Table 470 bull Registers in TIMED_FRAME_CFG

TFRM_MISC 0x00000000 1 Timed frame configuration Page 221

TFRM_PORT_DLY 0x00000004 1 Interleaved transmission setup Page 222

TFRM_TIMER_CFG_1 0x00000008 1 Configures timers for timed transmissions

TFRM_TIMER_CFG_2 0x0000000C 1 Configures timers for timed transmissions

Table 471 bull Fields in TFRM_MISC

Field Name Bit Access Description DefaultTIMED_CANCEL_SLOT 189 RW Specify slot of timed frame to cancel 0x000

Registers

21122 QSYSTIMED_FRAME_CFGTFRM_PORT_DLYParent QSYSTIMED_FRAME_CFG

Instances 1

21123 QSYSTIMED_FRAME_CFGTFRM_TIMER_CFG_1Parent QSYSTIMED_FRAME_CFG

Instances 1

TIMED_CANCEL_1SHOT 8 One-shot Set this field to cancel a timed transmission Auto cleared when complete

Table 472 bull Fields in TFRM_PORT_DLY

Field Name Bit Access Description DefaultTFRM_PORT_DLY_ENA 120 RW When multiple timed frames are ready for

transmission at the same time they are by default transmitted as fast as they can resulting in a burst of frames By enabling the interleave mode timer 8 must run out between each frame being transmitted on a port0 Send frames in burst1 Send frames interleaved

0x0000

Table 473 bull Fields in TFRM_TIMER_CFG_1

Field Name Bit Access Description DefaultTFRM_TIMER_CFG_1 310 RW Configures timer 1 Default 33 ms

Unit 1982 ns0x0000410A

Field Name Bit Access Description DefaultTFRM_TIMER_CFG_2 310 RW Configures timer 2 Default 10 us

Unit 1982 ns0x00000033

Table 471 bull Fields in TFRM_MISC (continued)

Registers

Instances 1

Unit 1982 ns0x000001F9

Unit 1982 ns0x000013B5

Unit 1982 ns0x0000C516

Unit 1982 ns0x0007B2DD

Registers

Instances 1

2113 QSYSRES_QOS_ADVParent QSYS

Instances 1

21131 QSYSRES_QOS_ADVRED_PROFILEParent QSYSRES_QOS_ADV

Instances 16

Configuration of Weighted Random Early Detection (WRED) profile per QoS class per drop precedence level Profiles 0-7 are for frames with QoS class 0-7 and drop precedence level 0 Profiles 8-15 are for frames with QoS class 0-7 and drop precedence level 1

Field Name Bit Access Description DefaultTFRM_TIMER_CFG_7 310 RW Configures timer 7 Default 1sec

Unit 1982 ns0x004CFCA1

Field Name Bit Access Description DefaultTFRM_TIMER_CFG_8 310 RW Configures timer 8 Default 1982 ns

Unit 1982 ns0x00000001

Table 481 bull Registers in RES_QOS_ADV

RED_PROFILE 0x00000000 160x00000004

Weighted Random Early Detection (WRED) configuration

RES_QOS_MODE 0x00000040 1 Shared QOS resource mode Page 225

Registers

21132 QSYSRES_QOS_ADVRES_QOS_MODEParent QSYSRES_QOS_ADV

Instances 1

2114 QSYSRES_CTRLParent QSYS

Instances 1024

21141 QSYSRES_CTRLRES_CFGParent QSYSRES_CTRL

Instances 1

The queue system tracks four resource consumptions

Resource 0 Memory tracked per source

Resource 1 Frame references tracked per source

Resource 2 Memory tracked per destination

Table 482 bull Fields in RED_PROFILE

Field Name Bit Access Description DefaultWM_RED_LOW 158 RW When enqueuing a frame RED is active if

the ingress memory consumption by the frames QoS class is above WM_RED_LEVEL The probability of random early discarding is calculated as (Memory consumption by the frames QoS class - WM_RED_LOW)(WM_RED_HIGH - WM_RED_LOW)Unit is 960 bytes

WM_RED_HIGH 70 RW See WM_RED_LOW Unit is 960 bytes 0xFF

Table 483 bull Fields in RES_QOS_MODE

Field Name Bit Access Description DefaultRES_QOS_RSRVD 70 RW When a QoS class is enabled in this mask

the class will have guaranteed shared space The watermarks found in RES_CFG are used for setting the amount of space set aside

Table 484 bull Registers in RES_CTRL

RES_CFG 0x00000000 1 Watermark configuration Page 225

RES_STAT 0x00000004 1 Resource status Page 227

Registers

Resource 3 Frame references tracked per destination

Before a frame is added to the queue system some conditions must be met

- Reserved memory for the specific (SRC PRIO) or for the specific SRC is available

- Reserved memory for the specific (DSTPRIO) or for the specific DST is available

- Shared memory is available

The frame reference resources are checked for availability like the memory resources Enqueuing of a frame is allowed if both the memory resource check and the frame reference resource check succeed

The extra resources consumed when enqueuing a frame are first taken from the reserved (SRCPRIO) next from the reserved SRC and last from the shared memory area The same is done for DST Both memory consumptions and frame reference consumptions are updated

The register is laid out in the following way for source memory (resource 0)

Index 0-95 Q_RSRV - Reserved amount for (SRCPRIO) at index 8SRC+PRIO

Index 216-223 PRIO_SHR - Maximum allowed use of the shared buffer for PRIO at index PRIO+216

Index 224-235 P_RSRV - Reserved amount for SRC at index SRC+224

Index 254 COL_SHR - Maximum allowed use of the shared buffer for frames with DP=1

Index 255 COL_SHR Maximum allowed use of the shared buffer for source

The layout is similar for resources 1 2 and 3 Resource 1 uses indices 256-511 resource 2 uses indices 512-767 and resource 3 uses indices 768-1023

Note the default values depend on the index used

The allocation unit for memory tracking is 60 bytes and the allocation unit for reference tracking is 1 frame reference All frames are prepended with a 16-byte header

Table 485 bull Fields in RES_CFG

Field Name Bit Access Description DefaultWM_HIGH 80 RW Watermark for resource

Note the default value depends on the indexBit 8 Selects multiplier unit for watermark Bit 8 = 0 Multiply watermark value with 1 bit 8 = 1 Multiply watermark value with 16Bits 7-0 Watermark value Allocation unit is 60 bytes for memory and 1 frame reference for references

Registers

21142 QSYSRES_CTRLRES_STATParent QSYSRES_CTRL

Instances 1

2115 QSYSDROP_CFGParent QSYS

Instances 1

21151 QSYSDROP_CFGEGR_DROP_MODEParent QSYSDROP_CFG

Instances 1

2116 QSYSMMGTParent QSYS

Instances 1

Table 486 bull Fields in RES_STAT

Field Name Bit Access Description DefaultINUSE 2312 RW Current consumption for corresponding

watermark in RES_CFG0x000

MAXUSE 110 RW Maximum consumption since last read for corresponding watermark in RES_CFG

Table 487 bull Registers in DROP_CFG

EGR_DROP_MODE 0x00000000 1 Configures egress ports for flowcontrol

Table 488 bull Fields in EGR_DROP_MODE

Field Name Bit Access Description DefaultEGRESS_DROP_MODE 110 RW When enabled for a port frames -to- that port

are discarded when the controlling watermarks are hit If disabled - the frame will stay in memory until resources are available If INGRESS_DROP_MODE or EGRESS_DROP_MODE applies for a frame copy it will be discared

Registers

21161 QSYSMMGTEQ_CTRLParent QSYSMMGT

Instances 1

2117 QSYSHSCHParent QSYS

Instances 548

General purpose scheduling elements are used to form a hierarchy of queue scheduling There are 192 elements

The first 146 elements connect directly to frame queues These elements have extra shapers on inputs 6 and 7 which can be used for strictDWRR mixed priority schedulling These shapers are configurable through this set of registers at indexes 256+2SE_NO (shaper 6) and indexes 256+2SE_NO+1 (shaper 7) Only the CIR_CFG and CIR_STATE registers are valid for these indexes

Example To set the priority 7 shaper on scheduling element 67 access HSCH391CIR_CFG

Table 489 bull Registers in MMGT

EQ_CTRL 0x00000000 1 Egress queue status Page 228

Table 490 bull Fields in EQ_CTRL

Field Name Bit Access Description DefaultFP_FREE_CNT 150 RO Number of free frame references 0x0000

Table 491 bull Registers in HSCH

CIR_CFG 0x00000000 1 Shaping configuration of the SE

EIR_CFG 0x00000004 1 Excess rate configuration Page 229

SE_CFG 0x00000008 1 Configuration of shaper and scheduling algorithm

SE_DWRR_CFG 0x0000000C 120x00000004

Configuration of the DWRR costs

SE_CONNECT 0x0000003C 1 Configuration of the connections between SEs

Registers

21171 QSYSHSCHCIR_CFGParent QSYSHSCH

Instances 1

21172 QSYSHSCHEIR_CFGParent QSYSHSCH

Instances 1

21173 QSYSHSCHSE_CFGParent QSYSHSCH

Instances 1

SE_DLB_SENSE 0x00000040 1 Configuration of which fill levels in the queue system that the DLB shapers use to trigger excess information rate

CIR_STATE 0x00000044 1 CIR status Page 233

EIR_STATE 0x00000048 1 EIR status Page 233

Table 492 bull Fields in CIR_CFG

Field Name Bit Access Description DefaultCIR_RATE 206 RW Leak rate for this shaper Unit is 100 kbps 0x0000

CIR_BURST 50 RW Burst capacity of this shaper Unit is 4 kilobytes The shaper is disabled when CIR_BURST=0

Table 493 bull Fields in EIR_CFG

Field Name Bit Access Description DefaultEIR_RATE 217 RW Leak rate for this shaper Unit is 100 kbps 0x0000

EIR_BURST 61 RW Burst capacity of this shaper Unit is 4 kilobytes The dual leaky bucket shaper operates as a single leaky bucket shaper when EIR_BURST=0

EIR_MARK_ENA 0 RW If a frame is scheduled with excess information rate the frame color can be changed to yellow

Table 491 bull Registers in HSCH (continued)

Registers

21174 QSYSHSCHSE_DWRR_CFGParent QSYSHSCH

Instances 12

21175 QSYSHSCHSE_CONNECTParent QSYSHSCH

Instances 1

Table 494 bull Fields in SE_CFG

Field Name Bit Access Description DefaultSE_DWRR_CNT 96 RW Number of inputs running with DWRR

algorithm otherwise strict Strict inputs always have the highest input index

SE_RR_ENA 5 RW The DWRR algorithm is replaced with frame-based round robin

SE_AVB_ENA 4 RW Enable AVB mode for this shaper creating burst capacity only when data is available

SE_FRM_MODE 32 RW Accounting mode for this shaper0 Line rate Shape bytes including QSYSHSCH_MISC_CFGFRM_ADJ1 Data rate Shape bytes excluding IPG2 Frame rate Shape frames with rate unit = 100 fps and burst unit = 328 frames3 Frame rate Shape framed with rate unit = 1 fps and burst unit = 03 frames

SE_EXC_ENA 1 RW Allow bandwidth out of this element to exceed configured levels Still - arbitrations always prefers inputs not exceeding configured levels

Table 495 bull Fields in SE_DWRR_CFG

Field Name Bit Access Description DefaultDWRR_COST 40 RW DWRR cost configuration 0x00

Registers

21176 QSYSHSCHSE_DLB_SENSEParent QSYSHSCH

Instances 1

Table 496 bull Fields in SE_CONNECT

Field Name Bit Access Description DefaultSE_OUTP_IDX 2417 RW The output port on this SE is connected to

the SE selected by SE_OUTP_IDX SE_OUTP_CON selects the input port number on the SE If the SE_TERMINAL is set the output port on this SE is connected to the egress port selected by SE_OUTP_IDX instead

The connections are automatically configured after reset to a source port fair strict priority schemeSEs 0-7 connect to SE 146 Priority scheduler for port 0SEs 8-15 connect to SE 147 Priority scheduler for port 1SEs 96-103 connect to SE 158 Priority scheduler for CPU port 12

SEs 146+N connect to egress port N with SE_TERMINAL set

SE_INP_IDX 169 RW The inputs on this SE are the output ports of the consequtive range of SEs starting at index SE_INP_IDX and ending at SE_INP_IDX+SE_INP_CNT-1The queues connect 12 at a time to the first 146 SEs and the SE_INP_IDX does not apply for those

SE_OUTP_CON 85 RW The input port on the next SE which this SE connects to The next SE is selected by SE_OUTP_IDX

SE_INP_CNT 41 RW Number of input ports on to this SE Default values matches the default scheduling hierarchy described in the datasheet

SE_TERMINAL 0 RW If set this SE is connected to egress port SE_OUTP_IDX

Table 497 bull Fields in SE_DLB_SENSE

Field Name Bit Access Description DefaultSE_DLB_PRIO 1311 RW QoS class used when SE_DLB_PRIO_ENA

is set0x0

SE_DLB_SPORT 107 RW Source port used when SE_DLB_SPORT_ENA is set

Registers

SE_DLB_DPORT 63 RW Destination port used when SE_DLB_DPORT_ENA is set

SE_DLB_PRIO_ENA 2 RW Enable priority awareness by the DLB shaper If set the DLB shaper allows excess information rate when the egress buffer use for QoS class SE_DLB_PRIO has reached threshold BUF_PRIO_SHR_E[SE_DLB_PRIO] minus 3000 bytes

If both SE_DLB_PRIO_ENA and SE_DLB_SPORT_ENA are set the excess information rate is alllowed when the ingress buffer use for QoS class per source port has reached threshold BUF_Q_RSRV_I[SE_DLB_PRIO SE_DLB_SPORT] minus 3000 bytes

If both SE_DLB_PRIO_ENA and SE_DLB_DPORT_ENA are set the excess information rate is alllowed when the egress buffer use for QoS class per destination port has reached threshold BUF_Q_RSRV_E[SE_DLB_PRIO SE_DLB_DPORT] minus 3000 bytes

If multiple awareness functions (SE_DLB_PRIO_ENA SE_DLB_SPORT_ENA SE_DLB_DPORT_ENA) are enabled all relevant thresholds must be exceeded before excess information rate is allowed

SE_DLB_SPORT_ENA 1 RW Enable source port awareness by the DLB shaper If set the DLB shaper allows excess information rate when the ingress buffer use for source port SE_DLB_SPORT has reached threshold BUF_P_RSRV_I[SE_DLB_SPORT] minus 3000 bytes

Table 497 bull Fields in SE_DLB_SENSE (continued)

Registers

21177 QSYSHSCHCIR_STATEParent QSYSHSCH

Instances 1

21178 QSYSHSCHEIR_STATEParent QSYSHSCH

Instances 1

2118 QSYSHSCH_MISCParent QSYS

Instances 1

SE_DLB_DPORT_ENA 0 RW Enable destination port awareness by the DLB shaper If set the DLB shaper allows excess information rate when the egress buffer use for destination port SE_DLB_SPORT has reached threshold BUF_P_RSRV_E[SE_DLB_DPORT] minus 3000 bytes

Table 498 bull Fields in CIR_STATE

Field Name Bit Access Description DefaultCIR_LVL 254 RW Current fill level Unit is 05 bits 0x000000

Table 499 bull Fields in EIR_STATE

Field Name Bit Access Description DefaultEIR_LVL 210 RW Current fill level Unit is 05 bits 0x000000

Table 500 bull Registers in HSCH_MISC

HSCH_MISC_CFG 0x00000000 1 Common config for HSCH and policer module

Registers

21181 QSYSHSCH_MISCHSCH_MISC_CFGParent QSYSHSCH_MISC

Instances 1

212 REW

2121 REWPORTParent REW

Instances 13

Table 501 bull Fields in HSCH_MISC_CFG

Field Name Bit Access Description DefaultSE_CONNECT_VLD 8 RW Set to one when the SE connection

configuration is valid Set to zero when reconfiguring SE inter connections

FRM_ADJ 73 RW Values to add each frame when frame length adjustment is in use

QSHP_EXC_ENA 1 RW When set closed queue shapers will be schedulled as excessed and can be schedulled if no other inputs are available

Table 502 bull Register Groups in REW

PORT 0x00000000 130x00000080

Per port configurations for Rewriter

COMMON 0x00000690 1 Common configurations for Rewriter

PORT_VLAN_CFG 0x00000000 1 Port VLAN configuration Page 235

TAG_CFG 0x00000004 1 Tagging configuration Page 235

DSCP_CFG 0x0000000C 1 DSCP updates Page 236

PCP_DEI_QOS_MAP_CFG 0x00000010 160x00000004

Mapping of DP level and QoS class to PCP and DEI values

PTP_CFG 0x00000050 1 Precision time protocol configuration

Registers

21211 REWPORTPORT_VLAN_CFGParent REWPORT

Instances 1

21212 REWPORTTAG_CFGParent REWPORT

Instances 1

PTP_DLY1_CFG 0x00000054 1 Asymmetric delay Page 238

Table 504 bull Fields in PORT_VLAN_CFG

Field Name Bit Access Description DefaultPORT_TPID 3116 RW Tag Protocol Identifier for port 0x0000

PORT_DEI 15 RW DEI value for port 0x0

PORT_PCP 1412 RW PCP value for port 0x0

PORT_VID 110 RW VID value for port 0x001

Table 505 bull Fields in TAG_CFG

Field Name Bit Access Description DefaultTAG_CFG 87 RW Enable VLAN port tagging

0 Port tagging disabled1 Tag all frames except when VID=PORT_VLAN_CFGPORT_VID or VID=02 Tag all frames except when VID=03 Tag all frames

TAG_TPID_CFG 65 RW Select TPID EtherType in port tag0 Use 0x81001 Use 0x88A82 Use custom value from PORT_VLAN_CFGPORT_TPID3 Use PORT_VLAN_CFGPORT_TPID unless ingress tag was a C-tag (EtherType = 0x8100)

TAG_VID_CFG 4 RW Select VID in port tag0 Use classified VID1 Use PORT_VLAN_CFGPORT_VID

Registers

21213 REWPORTPORT_CFGParent REWPORT

Instances 1

21214 REWPORTDSCP_CFGParent REWPORT

Instances 1

TAG_PCP_CFG 32 RW Select PCP in port tag0 Classified PCP1 PORT_PCP2 DP and QoS mapped to PCP (PCP_DEI_QOS_MAP_CFG)3 QoS class

TAG_DEI_CFG 10 RW Select DEI in port tag0 Classified DEI1 PORT_DEI2 DP and QoS mapped to DEI (PCP_DEI_QOS_MAP_CFG)3 DP level

Field Name Bit Access Description DefaultES0_ENA 5 RW Enable ES0 lookup 0x0

FCS_UPDATE_NONCPU_CFG 43 RW FCS update mode for frames not received on the CPU port0 Update FCS if frame data has changed1 Never update FCS2 Always update FCS

FCS_UPDATE_CPU_ENA 2 RW If set update FCS for all frames injected by the CPU If cleared never update the FCS

FLUSH_ENA 1 RW If set all frames destined for the egress port are discarded

AGE_DIS 0 RW Disable frame ageing for this egress port 0x0

Table 505 bull Fields in TAG_CFG (continued)

Registers

21215 REWPORTPCP_DEI_QOS_MAP_CFGParent REWPORT

Instances 16

21216 REWPORTPTP_CFGParent REWPORT

Instances 1

Field Name Bit Access Description DefaultDSCP_REWR_CFG 10 RW Egress DSCP rewrite

0 No update of DSCP value in frame1 Update with DSCP value from analyzer2 Update with DSCP value from analyzer remapped through DSCP_REMAP_CFG3 Update with DSCP value from analyzer remapped based on drop precedence level through DSCP_REMAP_CFG or DSCP_REMAP_DP1_CFGl

Table 508 bull Fields in PCP_DEI_QOS_MAP_CFG

Field Name Bit Access Description DefaultDEI_QOS_VAL 3 RW Map the frames DP level and QoS class to a

DEI value DEI = PCP_DEI_QOS_MAP_CFG[8DP level + QoS class]DEI_QOS_VAL This must be enabled in TAG_CFGTAG_DEI_CFG

PCP_QOS_VAL 20 RW Map the frames DP level and QoS class to a PCP value PCP = PCP_DEI_QOS_MAP_CFG[8DP level + QoS class]PCP_QOS_VAL This must be enabled in TAG_CFGTAG_PCP_CFG

Field Name Bit Access Description DefaultPTP_BACKPLANE_MODE 7 RW Backplane mode for PTP If set the frames

receive timestamp is written into the PTP header (4 reserved bytes at offset 16)

PTP_1STEP_DIS 2 RW Overrules the one-step and the origin PTP commands from IS2 This disables updating the correction field or the origin timestamp field in the PTP frame

Registers

21217 REWPORTPTP_DLY1_CFGParent REWPORT

Instances 1

2122 REWCOMMONParent REW

Instances 1

21221 REWCOMMONDSCP_REMAP_DP1_CFGParent REWCOMMON

Instances 64

PTP_2STEP_DIS 1 RW Overrules the two-step PTP command from IS2 This effectively disables saving the frames departure time into the timestamp FIFO queue

Field Name Bit Access Description DefaultPTP_DLY1_VAL 310 RW Delay to add to frames residence time This

is applicable to one-step PTP and it is enabled by setting the IS2 action REW_OP[5] to 1 Unit is ns Value is signed

0x00000000

DSCP_REMAP_DP1_CFG 0x00000000 640x00000004

Remap table of DSCP values for frames with drop precedence set

DSCP_REMAP_CFG 0x00000100 640x00000004

Remap table of DSCP values Page 239

Table 512 bull Fields in DSCP_REMAP_DP1_CFG

Field Name Bit Access Description DefaultDSCP_REMAP_DP1_VAL 50 RW One to one DSCP remapping table common

for all ports This table is used if ANADSCP_CFG[DSCP]DSCP_REWR_ENA=3 and DP=1

Table 509 bull Fields in PTP_CFG (continued)

Registers

21222 REWCOMMONDSCP_REMAP_CFGParent REWCOMMON

Instances 64

213 SBA

2131 SBASBAParent SBA

Instances 1

Configurations for the shared bus of the VCore System

21311 SBASBAPL_CPUParent SBASBA

Table 513 bull Fields in DSCP_REMAP_CFG

Field Name Bit Access Description DefaultDSCP_REMAP_VAL 50 RW One to one DSCP remapping table common

for all ports This table is used if ANADSCP_CFG[DSCP]DSCP_REWR_ENA=2 or if DSCP_CFG[DSCP]DSCP_REWR_ENA=3 and DP=0

Table 514 bull Register Groups in SBA

SBA 0x00000000 1 Shared bus arbiter registers Page 239

Table 515 bull Registers in SBA

PL_CPU 0x00000000 1 Master 1 arbitration priority Page 239

PL_PCIE 0x00000004 1 Master 2 arbitration priority Page 240

PL_CSR 0x00000008 1 Master 3 arbitration priority Page 240

WT_EN 0x0000004C 1 Weighted-token arbitration scheme enable

WT_TCL 0x00000050 1 Clock tokens refresh period Page 241

WT_CPU 0x00000054 1 Master 1 clock tokens Page 241

WT_PCIE 0x00000058 1 Master 2 clock tokens Page 241

WT_CSR 0x0000005C 1 Master 3 clock tokens Page 241

Registers

Instances 1

21312 SBASBAPL_PCIEParent SBASBA

Instances 1

21313 SBASBAPL_CSRParent SBASBA

Instances 1

21314 SBASBAWT_ENParent SBASBA

Instances 1

When weighted token arbitration is enabled each master on the shared bus is granted a configurable number of tokens at the start of each refresh period The length of each refresh period is configurable In each clock-cycle that a master uses the bus the token counter for that master decreases Once all tokens are spent the master is forced to a low priority A master with tokens remaining always takes priority over masters with no tokens remaining

Table 516 bull Fields in PL_CPU

Field Name Bit Access Description DefaultPL1 30 RW Arbitration priority for the master When

multiple masters request the bus at the same time the one with the highest priority is granted bus accessValues 0x1 through 0xF higher values are prioritized over lower values

Table 517 bull Fields in PL_PCIE

Field Name Bit Access Description DefaultPL2 30 RW See SBAPL1 for description 0xD

Table 518 bull Fields in PL_CSR

Field Name Bit Access Description DefaultPL3 30 RW See SBAPL1 for description 0xC

Table 519 bull Fields in WT_EN

Field Name Bit Access Description DefaultWT_EN 0 RW Set this field to enable weighted-token

arbitration scheme0x0

Registers

21315 SBASBAWT_TCLParent SBASBA

Instances 1

21316 SBASBAWT_CPUParent SBASBA

Instances 1

21317 SBASBAWT_PCIEParent SBASBA

Instances 1

21318 SBASBAWT_CSRParent SBASBA

Instances 1

Table 520 bull Fields in WT_TCL

Field Name Bit Access Description DefaultWT_TCL 150 RW Refresh period length for the weighted-token

arbitration scheme0xFFFF

Table 521 bull Fields in WT_CPU

Field Name Bit Access Description DefaultWT_CL1 150 RW Number of tokens to grant the master at the

start of each refresh period for weighted-token arbitration scheme If configured with a value of zero the master is considered to have infinite tokens

0x000F

Table 522 bull Fields in WT_PCIE

Field Name Bit Access Description DefaultWT_CL2 150 RW See SBAWT_CL1 for description 0x000F

Table 523 bull Fields in WT_CSR

Registers

214 SFR

2141 SFRSFRParent SFR

Instances 1

The SFR registers are only accessible from software running on the 8051 based VCore CPU

Table 524 bull Register Groups in SFR

SFR 0x00000000 1 VCore CPU SFR Page 242

Table 525 bull Registers in SFR

SP 0x00000081 1 Stack pointer Page 243

DPL 0x00000082 1 Data pointer low Page 243

DPH 0x00000083 1 Data pointer high Page 244

DPL2 0x00000084 1 Second data pointer low Page 244

DPH2 0x00000085 1 Second data pointer high Page 244

DPS 0x00000086 1 Data pointer select Page 244

PCON 0x00000087 1 Power control Page 245

TCON 0x00000088 1 Interrupt control Page 245

MPAGE 0x00000092 1 MOVX memory page Page 246

IE 0x000000A8 1 Interrupt enable Page 247

PG 0x000000B0 1 Paging Page 247

IP 0x000000B8 1 Interrupt priority Page 248

EPG 0x000000C0 1 Paging extended Page 248

EEPG 0x000000C1 1 Paging extended2 Page 249

EMAP 0x000000C3 1 External memory map Page 249

PSW 0x000000D0 1 Program status word Page 250

ACC 0x000000E0 1 Accumulator Page 250

B 0x000000F0 1 B register Page 251

RMAP 0x000000F1 1 MPU8051_MMAP Page 251

MMAP 0x000000F2 1 On-chip memory map Page 251

RA_AD0_RD 0x000000F6 1 SBA address byte 0 - start read

Registers

21411 SFRSFRGPRParent SFRSFR

Instances 1

21412 SFRSFRSPParent SFRSFR

Instances 1

21413 SFRSFRDPLParent SFRSFR

Instances 1

RA_AD0_WR 0x000000F7 1 SBA address byte 0 - start write

RA_AD1 0x000000F9 1 SBA address byte 1 Page 253

RA_AD2 0x000000FA 1 SBA address byte 2 Page 253

RA_AD3 0x000000FB 1 SBA address byte 3 Page 254

RA_DA0 0x000000FC 1 SBA data byte 0 Page 254

RA_DA1 0x000000FD 1 SBA data byte 1 Page 254

RA_DA2 0x000000FE 1 SBA data byte 2 Page 254

RA_DA3 0x000000FF 1 SBA data byte 3 Page 254

Field Name Bit Access Description DefaultGPR 70 RW Bit addressable General Purpose Register

for software to use The value of this register is available for debug via ICPU_CFGMPU8051_STATMPU8051_GPR (can be read from external CPU)

Table 527 bull Fields in SP

Field Name Bit Access Description DefaultSP 70 RW Stack pointer as defined by 8051 standard

register set0x07

Table 525 bull Registers in SFR (continued)

Registers

21414 SFRSFRDPHParent SFRSFR

Instances 1

21415 SFRSFRDPL2Parent SFRSFR

Instances 1

21416 SFRSFRDPH2Parent SFRSFR

Instances 1

21417 SFRSFRDPSParent SFRSFR

Instances 1

Table 528 bull Fields in DPL

Field Name Bit Access Description DefaultDPL 70 RW Instructions that use the data pointer will use

this field (as low data pointer) when SFRDPSSEL==0

Table 529 bull Fields in DPH

Field Name Bit Access Description DefaultDPH 70 RW Instructions that use the data pointer will use

this field (as high data pointer) when SFRDPSSEL==0

Table 530 bull Fields in DPL2

Field Name Bit Access Description DefaultDPL2 70 RW Instructions that use the data pointer will use

Table 531 bull Fields in DPH2

Field Name Bit Access Description DefaultDPH2 70 RW Instructions that use the data pointer will use

Registers

21418 SFRSFRPCONParent SFRSFR

Instances 1

21419 SFRSFRTCONParent SFRSFR

Instances 1

Table 532 bull Fields in DPS

Field Name Bit Access Description DefaultSEL 0 RW Instructions that use the data pointer will use

SFRDPH SFRDPL when SFRDPSSEL==0 else SFRDPH2 SFRDPL2Tip This field can be changed in a single instruction by using INC DPS This saves application code from having to save source and destination addresses when doing a block move

Table 533 bull Fields in PCON

Field Name Bit Access Description DefaultGF 32 RW Bit addressable General Purpose Bits 0x0

STOP 1 One-shot Set to place the 8051 in stop mode Stop mode can only be exited by soft or hard reset of the 8051

IDLE 0 One-shot Set to place the 8051 in idle mode and suspend processing of instructions Idle mode can be exited by interrupt when this happens the 8051 will resume execution at the instruction after writing to this field Idle mode can also be exited by soft or hard reset of the 8051

Registers

214110 SFRSFRMPAGEParent SFRSFR

Instances 1

Table 534 bull Fields in TCON

Field Name Bit Access Description DefaultIE1 3 RW Set when interrupt 1 is detected If interrupt 1

is configued as edge sensitive (see SFRTCONIT1) then this field is automatically cleared when the 8051 vectors the corresponding interrupt routine or it can be cleared by softwareIf interrupt 1 is configured as level sensitive (see SFRTCONIT1) then this field cannot be written by software in this case the the interrupt rutine must then make sure that the interrupt source has been cleared before returning from interrupt handler

IT1 2 RW Configures interrupt 1 trigger mechanism When configured as edge sensitive then a rising edge on the VCore CPU interrupt 1 will trigger interrupt When configured as level sensitive then interrupt is considdered active for as long as VCore CPU tnterrupt 1 is asserted0 Edge sensitive1 Level sensitive

IE0 1 RW Set when interrupt 0 is detected If interrupt 0 is configued as edge sensitive (see SFRTCONIT0) then this field is automatically cleared when the 8051 vectors the corresponding interrupt routine or it can be cleared by softwareIf interrupt 0 is configured as level sensitive (see SFRTCONIT0) then this field cannot be written by software in this case the the interrupt rutine must then make sure that the interrupt source has been cleared before returning from interrupt handler

Registers

214111 SFRSFRIEParent SFRSFR

Instances 1

214112 SFRSFRPGParent SFRSFR

Instances 1

Table 535 bull Fields in MPAGE

Field Name Bit Access Description DefaultMPAGE 70 RW MPAGE replaces the Port 2 latch function

During MOVX A Ri and MOVX Ri A instructions the contents of this register is placed on the upper eight address bits (addresses[158]) This provides the paging function that is normally provided by the Port 2 latch

Table 536 bull Fields in IE

Field Name Bit Access Description DefaultEA 7 RW Global interrupt enable Disabling interrupts

via this field overrides individual interrupt enable bits in this register0 Disable all interrupts1 Interrupts controlled by individual enables

ET1 3 RW Set to enable Timer 1 interrupt This interrupt vectors to address 0x001B

EX1 2 RW Set to enable VCore CPU interrupt 1 This interrupt vectors to address 0x0013

Table 537 bull Fields in PG

Field Name Bit Access Description DefaultIFP4 7 RW Code-accesses to the VCore Shared Bus will

have Address[19] set to the value of this field0x0

IFP2 6 RW Code-accesses to the VCore Shared Bus will have Address[18] set to the value of this field

Registers

214113 SFRSFRIPParent SFRSFR

Instances 1

214114 SFRSFREPGParent SFRSFR

Instances 1

OP3 3 RW Data-accesses to the VCore Shared Bus will have Address[19] set to the value of this field

Table 538 bull Fields in IP

Field Name Bit Access Description DefaultPT1 3 RW Timer 0 interrupt priority

0 Low priority1 High priority

PX1 2 RW External interrupt 1 priority control0 Low priority1 High priority

PT0 1 RW Timer 0 interrupt priority0 Low priority1 High priority

Table 539 bull Fields in EPG

Field Name Bit Access Description DefaultEIFP4 7 RW Code-accesses to the VCore Shared Bus will

EIFP2 6 RW Code-accesses to the VCore Shared Bus will have Address[22] set to the value of this field

Table 537 bull Fields in PG (continued)

Registers

214115 SFRSFREEPGParent SFRSFR

Instances 1

214116 SFRSFREMAPParent SFRSFR

Instances 1

EOP3 3 RW Data-accesses to the VCore Shared Bus will have Address[23] set to the value of this field

Table 540 bull Fields in EEPG

Field Name Bit Access Description DefaultEEIFP4 7 RW Code-accesses to the VCore Shared Bus will

EEIFP2 6 RW Code-accesses to the VCore Shared Bus will have Address[26] set to the value of this field

EEOP3 3 RW Data-accesses to the VCore Shared Bus will have Address[27] set to the value of this field

Table 541 bull Fields in EMAP

Field Name Bit Access Description DefaultIFPH 7 RW Code-accesses to the VCore Shared Bus

with Address[15]==1 will have Address[15] overwritten by the value of this field

Table 539 bull Fields in EPG (continued)

Registers

214117 SFRSFRPSWParent SFRSFR

Instances 1

214118 SFRSFRACCParent SFRSFR

Instances 1

IFPL 6 RW Code-accesses to the VCore Shared Bus with Address[15]==0 will have Address[15] overwritten by the value of this field

OPH 5 RW Data-accesses to the VCore Shared Bus with Address[15]==1 will have Address[15] overwritten by the value of this field

OPL 4 RW Data-accesses to the VCore Shared Bus with Address[15]==0 will have Address[15] overwritten by the value of this field

Table 542 bull Fields in PSW

Field Name Bit Access Description DefaultCY 7 RW Carry flag Set to 1 when last arithmetic

operation resulted in a carry (during addition) or borrow (during subtraction) otherwise cleared to 0 by all arithmetic operations

AC 6 RW Auxiliary carry flag Set to 1 when last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high-order nibble otherwise cleared to 0 by all arithmetic operations

F0 5 RW Bit addressable General Purpose Bit 0x0

RS 43 RW Register bank select selects a register blank in internal RAM0 Register bank 0 addresses 0x00-0x071 Register bank 1 addresses 0x08-0x0F2 Register bank 2 addresses 0x10-0x173 Register bank 3 addresses 0x18-0x1F

OV 2 RW Overflow flag Set to 1 when last arithmetic operation resulted in a carry (addition) borrow (subtraction) or overflow (multiply or divide) otherwise cleared to 0 by all arithmetic operations

P 0 RW Parity flag Set to 1 when modulo-2 sum of 8 bits in accumulator is 1 (odd parity) cleared to 0 on even parity

Table 541 bull Fields in EMAP (continued)

Registers

214119 SFRSFRBParent SFRSFR

Instances 1

214120 SFRSFRRMAPParent SFRSFR

Instances 1

214121 SFRSFRMMAPParent SFRSFR

Instances 1

Table 543 bull Fields in ACC

Field Name Bit Access Description DefaultACC 70 RW As defined by 8051 standard register set 0x00

Table 544 bull Fields in B

Field Name Bit Access Description DefaultB 70 RW As defined by 8051 standard register set 0x00

Table 545 bull Fields in RMAP

Field Name Bit Access Description DefaultRMAP 70 RO This is a read only copy of the

ICPU_CFGMPU8051_MMAP registerDuring booting of the 8051 it may be benneficial for software to determine active memory mapping schemes without having to read ICPU_CFGMPU8051_MMAP via the VCore Shared Bus

Table 546 bull Fields in MMAP

Field Name Bit Access Description DefaultACH 7 RW Code-accesses to the on-chip memory with

Address[15]==1 will have Address[15] overwritten by the value of this field

ACL 6 RW Code-accesses to the on-chip memory with Address[15]==0 will have Address[15] overwritten by the value of this field

ADH 5 RW Data-accesses to the on-chip memory with Address[15]==1 will have Address[15] overwritten by the value of this field

Registers

214122 SFRSFRRA_AD0_RDParent SFRSFR

Instances 1

To perform a read from the VCore Shared Bus write SFRRA_AD3 SFRRA_AD2 SFRRA_AD1 followed by write to SFRRA_AD0_RD the last write initiates the read operation and read data will be provided in SFRRA_DA3 SFRRA_DA2 SFRRA_DA1 and SFRRA_DA0

ADL 4 RW Data-accesses to the on-chip memory with Address[15]==0 will have Address[15] overwritten by the value of this field

MCH 3 RW Enable redirect to on-chip memory for code-accesses with Address[15]==1 Address[15] will then be overwritten with the value of the SFRMMAPACH fieldWhen this field is cleared code-accesses with Address[15]==1 will be forwarded to the VCore Shared Bus after applying changes as configured in the SFRPG SFREPG and SFREMAP registers

MCL 2 RW Enable redirect to on-chip memory for code-accesses with Address[15]==0 Address[15] will then be overwritten with the value of the SFRMMAPACL fieldWhen this field is cleared code-accesses with Address[15]==0 will be forwarded to the VCore Shared Bus after applying changes as configured in the SFRPG SFREPG and SFREMAP registers

MDH 1 RW Enable redirect to on-chip memory for data-accesses with Address[15]==1 Address[15] will then be overwritten with the value of the SFRMMAPADH fieldWhen this field is cleared data-accesses with Address[15]==1 will be forwarded to the VCore Shared Bus after applying changes as configured in the SFRPG SFREPG and SFREMAP registers

MDL 0 RW Enable redirect to on-chip memory for data-accesses with Address[15]==0 Address[15] will then be overwritten with the value of the SFRMMAPADL fieldWhen this field is cleared data-accesses with Address[15]==0 will be forwarded to the VCore Shared Bus after applying changes as configured in the SFRPG SFREPG and SFREMAP registers

Table 546 bull Fields in MMAP (continued)

Registers

214123 SFRSFRRA_AD0_WRParent SFRSFR

Instances 1

To perform a write to the VCore Shared Bus write SFRRA_DA3 SFRRA_DA2 SFRRA_DA1 SFRRA_DA0 SFRRA_AD3 SFRRA_AD2 SFRRA_AD1 followed by write to SFRRA_AD0_WR the last write initiates the write operation

Do optimized read-modify-write operations on the VCore Shared Bus by first reading a 32-bit word as decribed for SFRRA_AD0_RD Now do the necessary modification direcly in the SFRRA_DA3 SFRRA_DA2 SFRRA_DA1 andor SFRRA_DA0 registers followed by writing this register with the value of SFRRA_AD0_RDRA_AD0_RD this will write back the modified value to the VCore Shared Bus

214124 SFRSFRRA_AD1Parent SFRSFR

Instances 1

Table 547 bull Fields in RA_AD0_RD

Field Name Bit Access Description DefaultRA_AD0_RD 70 RW VCore Shared Bus address[70] and read

access initiation Physically this is the same register as SFRRA_AD0_WR writing to one register will change the read-value of the other register

Table 548 bull Fields in RA_AD0_WR

Field Name Bit Access Description DefaultRA_AD0_WR 70 RW VCore Shared Bus address[70] and write

access initiation Physically this is the same register as SFRRA_AD0_RD writing to one register will change the read-value of the other register

Table 549 bull Fields in RA_AD1

Field Name Bit Access Description DefaultRA_AD1 70 RW VCore Shared Bus address[158] 0x00

Registers

Instances 1

214127 SFRSFRRA_DA0Parent SFRSFR

Instances 1

Table 552 bull Fields in RA_DA0

Field Name Bit Access Description DefaultRA_DA0 70 RW VCore Shared Bus data[70] 0x00

Registers

Instances 1

215 SIMC

2151 SIMCSIMCParent SIMC

Instances 1

Table 556 bull Register Groups in SIMC

SIMC 0x00000000 1 SI Master Controller Page 255

Table 557 bull Registers in SIMC

CTRLR0 0x00000000 1 Control Register 0 Page 256

SIMCEN 0x00000008 1 SIMC Enable Page 257

SER 0x00000010 1 Slave Enable Page 258

BAUDR 0x00000014 1 Baud Rate Select Page 258

TXFTLR 0x00000018 1 Transmit FIFO Threshold Level

RXFTLR 0x0000001C 1 Receive FIFO Threshold level Page 259

TXFLR 0x00000020 1 Transmit FIFO Level Page 259

RXFLR 0x00000024 1 Receive FIFO Level Page 260

SR 0x00000028 1 Status Register Page 260

IMR 0x0000002C 1 Interrupt Mask Page 260

ISR 0x00000030 1 Interrupt Status Page 261

RISR 0x00000034 1 Raw Interrupt Status Page 261

TXOICR 0x00000038 1 Transmit FIFO Overflow Interrupt Clear

RXOICR 0x0000003C 1 Receive FIFO Overflow Interrupt Clear

Registers

21511 SIMCSIMCCTRLR0Parent SIMCSIMC

Instances 1

This register controls the serial data transfer This register can only be written when master is disabled (SIMCSIMCENSIMCEN = 0)

RXUICR 0x00000040 1 Receive FIFO Underflow Interrupt Clear

DR 0x00000060 360x00000004

TransmitReceive FIFO Page 262

RX_SAMPLE_DLY 0x000000F0 1 RXD Sample Delay Page 263

Table 558 bull Fields in CTRLR0

Field Name Bit Access Description DefaultSRL 11 RW Shift Register Loop Used for testing

purposes only Set to connect the transmit shift register output to the receive shift register input0 Normal Mode Operation1 Test Mode Operation

TMOD 98 RW Selects the mode of transfer for serial communication In transmit-only mode data received from the external device is not valid and is not stored in the receive FIFO memory it is overwritten on the next transfer In receive-only mode transmitted data are not valid After the first write to the transmit FIFO the same word is retransmitted for the duration of the transfer In transmit-and-receive mode both transmit and receive data are valid The transfer continues until the transmit FIFO is empty Data received from the external device are stored into the receive FIFO memory where it can be accessed by the host processor0 Transmit and Receive1 Transmit Only2 Receive Only3 Reserved

SCPOL 7 RW Valid when the frame format (FRF) is set to Motorola SPI Used to select the polarity of the inactive serial clock which is held inactive when the master is not actively transferring data on the serial bus0 Inactive state of serial clock is low1 Inactive state of serial clock is high

Table 557 bull Registers in SIMC (continued)

Registers

Instances 1

Control register 1 controls the end of serial transfers when in receive-only mode This register can only be written when master is disabled (SIMCSIMCENSIMCEN = 0)

21513 SIMCSIMCSIMCENParent SIMCSIMC

Instances 1

SCPH 6 RW Valid when the frame format (FRF) is set to Motorola SPI The serial clock phase selects the relationship of the serial clock with the slave select signal When SCPH = 0 data are captured on the first edge of the serial clock When SCPH = 1 the serial clock starts toggling one cycle after the slave select line is activated and data are captured on the second edge of the serial clock0 Serial clock toggles in middle of first data bit1 Serial clock toggles at start of first data bit

FRF 54 RW Selects which serial protocol transfers the dataNote In addition to this field software must also configure ICPU_CFGGENERAL_CTRLSIMC_SSP_ENA0 Motorola SPI1 Texas Instruments SSP2-3 Reserved

DFS 30 RW Selects the data frame length See SIMCDR register description for how to readwrite words of less than 16 bit0-2 Reservedn n+1 bit serial data transfer

Field Name Bit Access Description DefaultNDF 150 RW When SIMCCTRLR0TMOD = 2 this

register field sets the number of data frames to be continuously received by the master The master continues to receive serial data until the number of data frames received is equal to this register value plus 1 which enables receiving up to 64 KB of data in a continuous transfer

0x0000

Table 558 bull Fields in CTRLR0 (continued)

Registers

21514 SIMCSIMCSERParent SIMCSIMC

Instances 1

The register enables the individual slave select output lines from the master 16 slave-select output pins are available on the master This register can only be written when master is disabled and not busy

21515 SIMCSIMCBAUDRParent SIMCSIMC

Instances 1

The register derives the frequency of the serial clock that regulates the data transfer The 16-bit field in this register defines the SI divider value This register can only be written when master is disabled (SIMCSIMCENSIMCEN = 0)

Table 560 bull Fields in SIMCEN

Field Name Bit Access Description DefaultSIMCEN 0 RW Set to enable master operations When

disabled all serial transfers are halted immediately Transmit and receive FIFO buffers are cleared when disabled It is impossible to program some of the master control registers when enabledNote The SI Master Controller must own the SI interface before it is enabled see ICPU_CFGGENERAL_CTRLIF_SI_OWNER for more information

Table 561 bull Fields in SER

Field Name Bit Access Description DefaultSER 150 RW Each bit in this register corresponds to a

slave select line from the master When a bit in this register is set the corresponding slave select line from the master is activated when a serial transfer begins Setting or clearing bits in this register have no effect on the corresponding slave select outputs until a transfer is started Before beginning a transfer enable the bit in this register that corresponds to the slave device with which the master wants to communicate When not operating in broadcast mode only one bit in this field should be set1 Selected0 Not Selected

0x0000

Registers

21516 SIMCSIMCTXFTLRParent SIMCSIMC

Instances 1

21517 SIMCSIMCRXFTLRParent SIMCSIMC

Instances 1

21518 SIMCSIMCTXFLRParent SIMCSIMC

Instances 1

Table 562 bull Fields in BAUDR

Field Name Bit Access Description DefaultSCKDV 150 RW The LSB for this field is always set to 0 and is

unaffected by a write operation which ensures an even value is held in this register If the value is 0 the serial output clock (si_clk) is disabled The frequency of the si_clk is derived from the following equation Fsclk_out = Fsystem_clkSCKDV where SCKDV is any even value between 2 and 65534 and Fsystem_clk is 250MHz

0x0000

Table 563 bull Fields in TXFTLR

Field Name Bit Access Description DefaultTFT 20 RW When the number of transmit FIFO entries is

less than or equal to this value the transmit FIFO empty interrupt is triggered The transmit FIFO depth is 8 do not program value exceeding 7

Table 564 bull Fields in RXFTLR

Field Name Bit Access Description DefaultRFT 50 RW When the number of receive FIFO entries is

greater than or equal to this value + 1 the receive FIFO full interrupt is triggered The receive FIFO depth is 40 do not program value exceeding 39

Registers

21519 SIMCSIMCRXFLRParent SIMCSIMC

Instances 1

215110 SIMCSIMCSRParent SIMCSIMC

Instances 1

215111 SIMCSIMCIMRParent SIMCSIMC

Instances 1

Table 565 bull Fields in TXFLR

Field Name Bit Access Description DefaultTXTFL 20 RO Contains the number of valid data entries in

the transmit FIFO0x0

Table 566 bull Fields in RXFLR

Field Name Bit Access Description DefaultRXTFL 50 RO Contains the number of valid data entries in

the receive FIFO0x00

Table 567 bull Fields in SR

Field Name Bit Access Description DefaultRFF 4 RO Set when receive FIFO is full 0x0

RFNE 3 RO Set when receive FIFO has one or more data-word

TFE 2 RO Set when transmit FIFO is empty 0x1

TFNF 1 RO Set when transmit FIFO has room for one or more data-word

BUSY 0 RO Set when serial transfer is in progress Cleared when master is idle or disabled

Table 568 bull Fields in IMR

RXFIM 4 RW Set to enable Receive FIFO Full Interrupt 0x1

RXOIM 3 RW Set to enable Receive FIFO Overflow Interrupt

Registers

215112 SIMCSIMCISRParent SIMCSIMC

Instances 1

If any bit is set in this register then the SI Master Controller is indicating interrupt towards the VCore Interrupt Controller

215113 SIMCSIMCRISRParent SIMCSIMC

Instances 1

RXUIM 2 RW Set to enable Receive FIFO Underflow Interrupt

TXOIM 1 RW Set to enable Transmit FIFO Overflow Interrupt

TXEIM 0 RW Set to enable Transmit FIFO Empty Interrupt 0x1

Table 569 bull Fields in ISR

Field Name Bit Access Description DefaultRXFIS 4 RO Receive FIFO Full Interrupt Status this field

is masked by SIMCIMRRXFIM This interrupt is based on programmable fill level see SIMCRXFTLR for more information

RXOIS 3 RO Receive FIFO Overflow Interrupt Status this field is masked by SIMCIMRRXOIM

RXUIS 2 RO Receive FIFO Underflow Interrupt Status this field is masked by SIMCIMRRXUIM

TXOIS 1 RO Transmit FIFO Overflow Interrupt Status this field is masked by SIMCIMRTXOIM

TXEIS 0 RO Transmit FIFO Empty Interrupt Status this field is masked by SIMCIMRTXEIM This interrupt is based on programmable fill level see SIMCTXFTLR for more information

Table 570 bull Fields in RISR

Field Name Bit Access Description DefaultRXFIR 4 RO Current status of Receive FIFO Full Interrupt

before masking0x0

RXOIR 3 RO Current status of Receive FIFO Overflow Interrupt before masking

RXUIR 2 RO Current status of Receive FIFO Underflow Interrupt before masking

Table 568 bull Fields in IMR (continued)

Registers

215114 SIMCSIMCTXOICRParent SIMCSIMC

Instances 1

215115 SIMCSIMCRXOICRParent SIMCSIMC

Instances 1

215116 SIMCSIMCRXUICRParent SIMCSIMC

Instances 1

215117 SIMCSIMCDRParent SIMCSIMC

Instances 36

16-bit readwrite buffer for the transmitreceive FIFOs When the register is read data in the receive FIFO buffer is accessed When it is written to data are moved into the transmit FIFO buffer a write can occur only when SIMCSIMCENSIMCEN = 1 FIFOs are reset when SIMCSIMCENSIMCEN = 0 This

TXOIR 1 RO Current status of Transmit FIFO Overflow Interrupt before masking

TXEIR 0 RO Current status of Transmit FIFO Empty Interrupt before masking

Table 571 bull Fields in TXOICR

Field Name Bit Access Description DefaultTXOICR 0 RO This field is set when Transmit FIFO

Overflow Interrupt is active interrupt is cleared by reading this register

Table 572 bull Fields in RXOICR

Field Name Bit Access Description DefaultRXOICR 0 RO This field is set when Receive FIFO Overflow

Interrupt is active interrupt is cleared by reading this register

Table 573 bull Fields in RXUICR

Field Name Bit Access Description DefaultRXUICR 0 RO This field is set when Receive FIFO

Underflow Interrupt is active interrupt is cleared by reading this register

Table 570 bull Fields in RISR (continued)

Registers

register is replicated to allow burst access to fifos the replication index is not used when accessing the FIFO

215118 SIMCSIMCRX_SAMPLE_DLYParent SIMCSIMC

Instances 1

This register controls the number of VCore system clock cycles that are delayed -from the default sample time- before the actual sample of the rxd input signal occurs It is impossible to write to this register when the SSI is enabled the SSI is enabled and disabled by writing to the SIMCEN register

216 SYS

2161 SYSSYSTEMParent SYS

Table 574 bull Fields in DR

Field Name Bit Access Description DefaultDR 150 RW Data is aligned to bit 0 (right-justified) when

accessing less than 16 bit data-words Read = Receive FIFO buffer Write = Transmit FIFO buffer

0x0000

Table 575 bull Fields in RX_SAMPLE_DLY

Field Name Bit Access Description DefaultRSD 70 RW This field is used to delay the sample of the

rxd input signal Each value represents a single VCore system clock delay on the sample of the rxd signal If this field is programmed with a value that exceeds 25 a zero (0) delay will be applied to the rxd sample

Table 576 bull Register Groups in SYS

PAUSE_CFG 0x00000608 1 Watermarks for egress queue system

MMGT 0x0000069C 1 Memory manager status Page 270

STAT 0x00000000 1920x00000004

Frame statistics Page 271

PTP 0x000006B8 1 Precision Time Protocol configuration

Registers

Instances 1

21611 SYSSYSTEMRESET_CFGParent SYSSYSTEM

Instances 1

Controls reset and initialization of the switching core Proper startup sequence is

- Enable memories

- Initialize memories

- Enable core

21612 SYSSYSTEMVLAN_ETYPE_CFGParent SYSSYSTEM

Instances 1

RESET_CFG 0x00000000 1 Core reset control Page 264

VLAN_ETYPE_CFG 0x00000008 1 S-tag Ethernet Type Page 264

PORT_MODE 0x0000000C 130x00000004

Per device port configuration Page 265

FRONT_PORT_MODE 0x00000040 110x00000004

Various Ethernet port configurations per front port

FRM_AGING 0x0000006C 1 Frame aging configuration Page 266

STAT_CFG 0x00000070 1 Statistics configuration Page 267

REW_MAC_HIGH_CFG 0x000000A8 110x00000004

Mac address to patch into frames transmitted

REW_MAC_LOW_CFG 0x000000D4 110x00000004

Table 578 bull Fields in RESET_CFG

Field Name Bit Access Description DefaultCORE_ENA 2 RW Switch core is enabled when this field is set 0x0

MEM_ENA 1 RW Core memory controllers are enabled when this field is set

MEM_INIT 0 One-shot Initialize core memories Field is automatically cleared when operation is complete ( approx 40 us)

Registers

21613 SYSSYSTEMPORT_MODEParent SYSSYSTEM

Instances 13

Table 579 bull Fields in VLAN_ETYPE_CFG

Field Name Bit Access Description DefaultVLAN_S_TAG_ETYPE_VAL 150 RW Custom Ethernet Type for S-tags Tags with

TPID = 0x88A8 are always recognized as S-tags

0x88A8

Field Name Bit Access Description DefaultDATA_WO_TS 65 RW 0x0

INCL_INJ_HDR 43 RW Set the mode for the formatting of incoming frames If INCL_INJ_HDRgt0 incoming frames are expected to contain the selected prefix followed by the 16-byte CPU injection header as the first part of the frame Frames are forwarded based on the contents in the CPU injection header instead of normal forwarding

Three different prefixes are supported- No prefix- Short prefix 0x8880000A- Long prefix any DMAC any SMAC EtherType=0x8880 payload=0x000A

In modes 2 and 3 if the incoming frames format does not comply with the prefix then sticky bit INJ_HDR_PREFIX_ERR is set A non-complying frame is discarded

0 No CPU injection header (normal frames)1 CPU injection header without prefix2 CPU injection header with short prefix3 CPU injection header with long prefix

Registers

21614 SYSSYSTEMFRONT_PORT_MODEParent SYSSYSTEM

Instances 11

21615 SYSSYSTEMFRM_AGINGParent SYSSYSTEM

Instances 1

INCL_XTR_HDR 21 RW Set the mode for the formatting of outgoing frames If INCL_XTR_HDRgt0 outgoing frames are prepended the selected prefix followed by the 16-byte CPU extraction header as the first part of the frame Inserting the CPU extraction header prevents other rewriter operations on the same frame

Three different prefixes are supported- No prefix- Short prefix 0x8880000A- Long prefix DMAC=0xFFFFFFFFFFFF SMAC=0xFEFFFFFFFFFF EtherType=0x8880 payload=0x000A0 No CPU extraction header (normal frames)1 CPU extraction header without prefix2 CPU extraction header with short prefix3 CPU extraction header with long prefix

INJ_HDR_ERR 0 Sticky If set a frame has been received with prefix not complying with the setting in INCL_INJ_HDR

Table 581 bull Fields in FRONT_PORT_MODE

Field Name Bit Access Description DefaultHDX_MODE 0 RW Enables the queue system to support the

half-duplex mode Must be set for a port when enabled for half-duplex mode (MAC_MODE_ENAFDX_ENA cleared)

Table 582 bull Fields in FRM_AGING

Field Name Bit Access Description DefaultAGE_TX_ENA 20 RW If set frames exceeding the frame aging time

while waiting head-of-line in a port due to a link partner signaling pause are allowed to be aged Note that frames aged in this case are not counted by the normal frame aging counter C_TX_AGED

Table 580 bull Fields in PORT_MODE (continued)

Registers

21616 SYSSYSTEMSTAT_CFGParent SYSSYSTEM

Instances 1

21617 SYSSYSTEMREW_MAC_HIGH_CFGParent SYSSYSTEM

Instances 11

21618 SYSSYSTEMREW_MAC_LOW_CFGParent SYSSYSTEM

MAX_AGE 190 RW Frames are aged and removed from the queue system when the frames age timer becomes two The frame age timer is increased for all frames whenever the configured time MAX_AGE has passed The unit is 65usEffectively this means that a frame is aged when the frame has waited in the queue system between one or two times the period specified by MAX_AGE

A value of zero disables frame aging

0x00000

Table 583 bull Fields in STAT_CFG

Field Name Bit Access Description DefaultSTAT_CLEAR_SHOT 1210 One-shot Set STAT_CLEAR_SHOT to clear counters

in the counter group for the port selected by STAT_VIEW Auto-cleared when complete (1us) Multiple counter groups can be cleared at the same time by setting multiple bits in STAT_CLEAR_SHOTBit 0 Group 0 - Rx countersBit 1 Group 1 - Tx countersBit 2 Group 2 - Drop counters

STAT_VIEW 30 RW Selects the port which counters are readable through the SYSSTATCNT register or can be cleared through STAT_CLEAR_SHOT

Table 584 bull Fields in REW_MAC_HIGH_CFG

Field Name Bit Access Description DefaultREW_MAC_HIGH 150 RW Upper part of MAC address used when

replacing source MAC address VCAP_IS2 action SMAC_REPLACE_ENA enables replacement of the source MAC address

0x0000

Table 582 bull Fields in FRM_AGING (continued)

Registers

Instances 11

2162 SYSPAUSE_CFGParent SYS

Instances 1

21621 SYSPAUSE_CFGPAUSE_CFGParent SYSPAUSE_CFG

Instances 12

Table 585 bull Fields in REW_MAC_LOW_CFG

Field Name Bit Access Description DefaultREW_MAC_LOW 310 RW Lower part of MAC address used when

0x00000000

Table 586 bull Registers in PAUSE_CFG

PAUSE_CFG 0x00000000 120x00000004

Watermarks for flow control condition per switch port

PAUSE_TOT_CFG 0x00000030 1 Configure total memory pause condition

ATOP 0x00000034 120x00000004

Tail dropping level Page 269

ATOP_TOT_CFG 0x00000064 1 Total raw memory use before tail dropping is activated

MAC_FC_CFG 0x00000068 110x00000004

MAC Flow Control Configuration Register

Table 587 bull Fields in PAUSE_CFG

Field Name Bit Access Description DefaultPAUSE_START 1810 RW Start pausing ingress stream when the

amount of memory consumed by the port exceeds this watermark The TOTPAUSE condition must also be metSee RES_CFG

PAUSE_STOP 91 RW Stop pausing ingress stream when the amount of memory consumed by the port is below this watermarkSee RES_CFG

Registers

21622 SYSPAUSE_CFGPAUSE_TOT_CFGParent SYSPAUSE_CFG

Instances 1

21623 SYSPAUSE_CFGATOPParent SYSPAUSE_CFG

Instances 12

21624 SYSPAUSE_CFGATOP_TOT_CFGParent SYSPAUSE_CFG

Instances 1

21625 SYSPAUSE_CFGMAC_FC_CFGParent SYSPAUSE_CFG

PAUSE_ENA 0 RW Enable pause feedback to the MAC allowing transmission of pause frames or HDX collisions to limit ingress data rate

Table 588 bull Fields in PAUSE_TOT_CFG

Field Name Bit Access Description DefaultPAUSE_TOT_START 179 RW Assert TOTPAUSE condition when total

memory allocation is above this watermarkSee RES_CFG

PAUSE_TOT_STOP 80 RW Deassert TOTPAUSE condition when total memory allocation is below this watermarkSee RES_CFG

Table 589 bull Fields in ATOP

Field Name Bit Access Description DefaultATOP 80 RW When a source port consumes more than this

level in the packet memory frames are tail dropped unconditionally of destination See RES_CFG

Table 590 bull Fields in ATOP_TOT_CFG

Field Name Bit Access Description DefaultATOP_TOT 80 RW Tail dropping is activate on a port when the

port use has exceeded the ATOP watermark for the port and the total memory use has exceeded this watermarkSee RES_CFG

Table 587 bull Fields in PAUSE_CFG (continued)

Registers

Instances 11

2163 SYSMMGTParent SYS

Instances 1

21631 SYSMMGTMMGTParent SYSMMGT

Instances 1

Table 591 bull Fields in MAC_FC_CFG

Field Name Bit Access Description DefaultFC_LINK_SPEED 2726 RW Configures the link speed This is used to

evaluate the time specification in incoming pause frames0 2500 Mbps1 1000 Mbps2 100 Mbps3 10 Mbps

FC_LATENCY_CFG 2520 RW Accepted reaction time for link partner after the port has transmitted a pause frame Frames starting after this latency are aborted Unit is 64 byte times

ZERO_PAUSE_ENA 18 RW If set a zero-delay pause frame is transmitted when flow control is deasserted0 Dont send zero pause frame1 Send zero pause frame

TX_FC_ENA 17 RW When set the MAC will send pause control frames in the Tx direction0 Dont send pause control frames1 Send pause control frames

RX_FC_ENA 16 RW When set the MAC obeys received pause control frames0 Dont obey received pause control frames1 Obey received pause control frames

PAUSE_VAL_CFG 150 RW Pause timer value inserted in generated pause frames0 Insert timer value 0 in TX pause frameN Insert timer value N in TX pause frame

0x0000

MMGT 0x00000000 1 Packet memory status Page 270

Registers

2164 SYSSTATParent SYS

Instances 192

21641 SYSSTATCNTParent SYSSTAT

Instances 1

2165 SYSPTPParent SYS

Instances 1

Table 593 bull Fields in MMGT

Field Name Bit Access Description DefaultFREECNT 150 RO Number of 192-byte free memory words 0x0000

Table 594 bull Registers in STAT

CNT 0x00000000 1 Counter values Page 271

Table 595 bull Fields in CNT

Field Name Bit Access Description DefaultCNT 310 RW Counter values The counters are layed-out

in three counter groupsGroup 0 0-63 Receive counters for port specified in STAT_CFGSTAT_VIEWGroup 1 64-127 Transmit counters for port specified in STAT_CFGSTAT_VIEWGroup 2 128-191 Drop counters for port specified in STAT_CFGSTAT_VIEW

QSYSSTAT_CNT_CFG and ANAAGENCTRL control whether bytes or frames are counted for specific counters Counters are cleared through STAT_CFGSTAT_CLEAR_SHOT

0x00000000

Registers

21651 SYSPTPPTP_STATUSParent SYSPTP

Instances 1

21652 SYSPTPPTP_TXSTAMPParent SYSPTP

Instances 1

Table 596 bull Registers in PTP

PTP_STATUS 0x00000000 1 Stored timestamp and timestamp queue status

PTP_TXSTAMP 0x00000004 1 Timestamp value Page 272

PTP_NXT 0x00000008 1 Advancing the timestamp queue

PTP_CFG 0x0000000C 1 System configuration of PTP Page 273

Table 597 bull Fields in PTP_STATUS

Field Name Bit Access Description DefaultPTP_OVFL 28 RO If set the timestamp queue has overflown

implying a timestamp entry could not be enqueued The PTP_OVFL bit is not cleared until the timestamp queue is completely empty

PTP_MESS_VLD 27 RO A timestamp entry is ready for reading PTP_MESS_ID PTP_MESS_TXPORT and PTP_DELAY contain the data of the timestamp entry

PTP_MESS_ID 2621 RO Timestamp identifier for head-of-line timestamp entry

PTP_MESS_TXPORT 2016 RO The transmit port for the head-of-line timestamp entry

PTP_MESS_SEQ_ID 150 RO Timestamp sequence identifier for head-of-line timestamp entry

0x0000

Registers

21653 SYSPTPPTP_NXTParent SYSPTP

Instances 1

21654 SYSPTPPTP_CFGParent SYSPTP

Instances 1

Table 598 bull Fields in PTP_TXSTAMP

Field Name Bit Access Description DefaultPTP_TXSTAMP_SEC 31 RO The timestamp value for the head-of-line

timestamp entry The timestamp value is the frames departure time plus DEVPORT_MODETX_PATH_DELAYTX_PATH_DELAY This is the LSB of the TOD_SEC value at time of event

PTP_TXSTAMP 290 RO The timestamp value for the head-of-line timestamp entry The timestamp value is the frames departure time plus DEVPORT_MODETX_PATH_DELAYTX_PATH_DELAY Unit is ns

0x00000000

Table 599 bull Fields in PTP_NXT

Field Name Bit Access Description DefaultPTP_NXT 0 One-shot Advance to the next timestamp entry

Registers PTP_STATUS and PTP_DELAY points to the next entry

Field Name Bit Access Description DefaultPTP_STAMP_WID 72 RW Determines how many LSbits from the

timestamp value are used by the timestamp transfer function

PTP_CF_ROLL_MODE 10 RW Configures how rollover protection is done when doing addsubtract transfer0 The four LSbits of CF sub-nano is filled out with the MSbits of the timestamp1 The LSbit of the CF sub-nano field is set to the MSbit of the timestamp2 The CF bit 62 is set to the MSbit of the timestamp3 Reserved

Registers

217 TWI

2171 TWITWIParent TWI

Instances 1

Table 601 bull Register Groups in TWI

TWI 0x00000000 1 Two-Wire Interface controller Page 274

Table 602 bull Registers in TWI

CFG 0x00000000 1 TWI configuration Page 275

TAR 0x00000004 1 Target address Page 276

SAR 0x00000008 1 Slave address Page 277

DATA_CMD 0x00000010 1 RxTx data buffer and command

SS_SCL_HCNT 0x00000014 1 Standard speed TWI clock SCL high count

SS_SCL_LCNT 0x00000018 1 Standard speed TWI clock SCL low count

FS_SCL_HCNT 0x0000001C 1 Fast speed TWI clock SCL high count

FS_SCL_LCNT 0x00000020 1 Fast speed TWI clock SCL low count

INTR_STAT 0x0000002C 1 Interrupt status Page 280

INTR_MASK 0x00000030 1 Interrupt mask Page 280

RAW_INTR_STAT 0x00000034 1 Raw interrupt status Page 281

RX_TL 0x00000038 1 Receive FIFO threshold Page 284

TX_TL 0x0000003C 1 Transmit FIFO threshold Page 284

CLR_INTR 0x00000040 1 Clear combined and individual interrupt

CLR_RX_UNDER 0x00000044 1 Clear RX_UNDER interrupt Page 285

CLR_RX_OVER 0x00000048 1 Clear RX_OVER interrupt Page 285

CLR_TX_OVER 0x0000004C 1 Clear TX_OVER interrupt Page 285

CLR_RD_REQ 0x00000050 1 Clear RD_REQ interrupt Page 286

CLR_TX_ABRT 0x00000054 1 Clear TX_ABRT interrupt Page 286

CLR_RX_DONE 0x00000058 1 Clear RX_DONE interrupt Page 286

Registers

21711 TWITWICFGParent TWITWI

Instances 1

CLR_ACTIVITY 0x0000005C 1 Clear ACTIVITY interrupt Page 286

CLR_STOP_DET 0x00000060 1 Clear STOP_DET interrupt Page 287

CLR_START_DET 0x00000064 1 Clear START_DET interrupt Page 287

CLR_GEN_CALL 0x00000068 1 Clear GEN_CALL interrupt Page 287

CTRL 0x0000006C 1 TWI control Page 288

STAT 0x00000070 1 TWI status Page 288

TXFLR 0x00000074 1 Transmit FIFO level Page 289

RXFLR 0x00000078 1 Receive FIFO level Page 289

TX_ABRT_SOURCE 0x00000080 1 Transmit abort source Page 290

SDA_SETUP 0x00000094 1 SDA setup Page 291

ACK_GEN_CALL 0x00000098 1 Acknowledge general call Page 291

ENABLE_STATUS 0x0000009C 1 Enable status Page 292

Table 603 bull Fields in CFG

Field Name Bit Access Description DefaultSLAVE_DIS 6 RW This bit controls whether the TWI controller

has its slave disabled If this bit is set (slave is disabled) the controller functions only as a master and does not perform any action that requires a slave0 slave is enabled1 slave is disabled

Table 602 bull Registers in TWI (continued)

Registers

21712 TWITWITARParent TWITWI

Instances 1

RESTART_ENA 5 RW Determines whether RESTART conditions may be sent when acting as a master Some older slaves do not support handling RESTART conditions however RESTART conditions are used in several operationsWhen RESTART is disabled the master is prohibited from performing the following functions Change direction within a transfer (split) Send a START BYTE Combined format transfers in 7-bit addressing modes Read operation with a 10-bit address Send multiple bytes per transferBy replacing RESTART condition followed by a STOP and a subsequent START condition split operations are broken down into multiple transfers If the above operations are performed it will result in setting RAW_INTR_STATR_TX_ABRT0 disable1 enable

MASTER_10BITADDR 4 RW Controls whether transfers starts in 7- or 10-bit addressing mode when acting as a master0 7-bit addressing1 10-bit addressing

SLAVE_10BITADDR 3 RW Controls whether the the TWI controller responds to 7- or 10-bit addresses in slave mode In 7-bit mode transactions that involve 10-bit addressing are ignored and only the lower 7 bits of the SAR register are compared 0 7-bit addressing 1 10-bit addressing

SPEED 21 RW These bits control at which speed the TWI controller operates its setting is relevant only in master mode Hardware protects against illegal values being programmed by software1 standard mode (100 kbits)2 fast mode (400 kbits)

MASTER_ENA 0 RW This bit controls whether the TWI master is enabled0 master disabled1 master enabled

Table 603 bull Fields in CFG (continued)

Registers

21713 TWITWISARParent TWITWI

Instances 1

21714 TWITWIDATA_CMDParent TWITWI

Instances 1

Table 604 bull Fields in TAR

Field Name Bit Access Description DefaultGC_OR_START_ENA 11 RW This bit indicates whether software performs

a General Call or START BYTE command0 ignore bit 10 GC_OR_START and use TAR normally1 perform special TWI command as specified in GC_OR_START bit

GC_OR_START 10 RW If TARGC_OR_START_ENA is set to 1 then this bit indicates whether a General Call or START byte command is to be performed0 General Call Address - after issuing a General Call only writes may be performed Attempting to issue a read command results in setting RAW_INTR_STATR_TX_ABRT The TWI controller remains in General Call mode until the TARGC_OR_START_ENA field is cleared1 START BYTE

TAR 90 RW This is the target address for any master transaction When transmitting a General Call these bits are ignored To generate a START BYTE the CPU needs to write only once into these bitsIf the TAR and SAR are the same loopback exists but the FIFOs are shared between master and slave so full loopback is not feasible Only one direction loopback mode is supported (simplex) not duplex A master cannot transmit to itself it can transmit to only a slave

Table 605 bull Fields in SAR

Field Name Bit Access Description DefaultSAR 90 RW The SAR holds the slave address when the

TWI is operating as a slave For 7-bit addressing only SAR[60] is usedThis register can be written only when the TWI interface is disabled (ENABLE = 0)

Registers

21715 TWITWISS_SCL_HCNTParent TWITWI

Instances 1

The clock for the TWI controller is the VCore system clock This field must be set accordingly to the VCore system frequency value = (4us VCore clock period) - 8

Example a 1786MHz clock correspond to a period of 56ns for this frequency this field must not be set lower than (round up) 707 = (4us 56ns) - 8

Table 606 bull Fields in DATA_CMD

Field Name Bit Access Description DefaultCMD 8 RW This bit controls whether a read or a write is

performed This bit does not control the direction when the TWI acts as a slave It controls only the direction when it acts as a masterWhen a command is entered in the TX FIFO this bit distinguishes the write and read commands In slave-receiver mode this bit is a dont care because writes to this register are not required In slave-transmitter mode a 0 indicates that CPU data is to be transmitted and as DATA When programming this bit remember the following attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (RAW_INTR_STATR_TX_ABRT) unless TARGC_OR_START_ENA has been clearedIf a 1 is written to this bit after receiving a RD_REQ interrupt then a TX_ABRT interrupt occursNOTE It is possible that while attempting a master TWI read transfer a RD_REQ interrupt may have occurred simultaneously due to a remote TWI master addressing this controller In this type of scenario the TWI controller ignores the DATA_CMD write generates a TX_ABRT interrupt and waits to service the RD_REQ interrupt1 = Read0 = Write

DATA 70 RW This register contains the data to be transmitted or received on the TWI bus If you are writing to this register and want to perform a read this field is ignored by the controller However when you read this register these bits return the value of data received on the TWI interface

Registers

21716 TWITWISS_SCL_LCNTParent TWITWI

Instances 1

21717 TWITWIFS_SCL_HCNTParent TWITWI

Instances 1

21718 TWITWIFS_SCL_LCNTParent TWITWI

Instances 1

Table 607 bull Fields in SS_SCL_HCNT

Field Name Bit Access Description DefaultSS_SCL_HCNT 150 RW This register sets the SCL clock divider for

the high-period in standard speed This value must result in a high period of no less than 4us

0x033A

Table 608 bull Fields in SS_SCL_LCNT

Field Name Bit Access Description DefaultSS_SCL_LCNT 150 RW This register sets the SCL clock divider for

the low-period in standard speed This value must result in a value no less than 47us

0x03D3

Table 609 bull Fields in FS_SCL_HCNT

Field Name Bit Access Description DefaultFS_SCL_HCNT 150 RW This register sets the SCL clock divider for

the high-period in fast speed This value must result in a value no less than 06us

0x0075

Registers

21719 TWITWIINTR_STATParent TWITWI

Instances 1

Each field in this register has a corresponding mask field in the INTR_MASK register These fields are cleared by reading the matching interrupt clear register The unmasked raw versions of these fields are available in the RAW_INTR_STAT register

See RAW_INTR_STAT for a description of these fields

217110 TWITWIINTR_MASKParent TWITWI

Instances 1

These fields mask the corresponding interrupt status fields (RAW_INTR_STAT) They are active high a value of 0 prevents the corresponding field in RAW_INTR_STAT from generating an interrupt

Table 610 bull Fields in FS_SCL_LCNT

Field Name Bit Access Description DefaultFS_SCL_LCNT 150 RW This register sets the SCL clock divider for

the low-period in fast speed This value must result in a value no less than 13us

0x010E

Table 611 bull Fields in INTR_STAT

Field Name Bit Access Description DefaultGEN_CALL 11 RO 0x0

START_DET 10 RO 0x0

STOP_DET 9 RO 0x0

ACTIVITY 8 RO 0x0

RX_DONE 7 RO 0x0

TX_ABRT 6 RO 0x0

RD_REQ 5 RO 0x0

TX_EMPTY 4 RO 0x0

TX_OVER 3 RO 0x0

RX_FULL 2 RO 0x0

RX_OVER 1 RO 0x0

RX_UNDER 0 RO 0x0

Table 612 bull Fields in INTR_MASK

Field Name Bit Access Description DefaultM_GEN_CALL 11 RW 0x1

M_START_DET 10 RW 0x0

Registers

217111 TWITWIRAW_INTR_STATParent TWITWI

Instances 1

Unlike the INTR_STAT register these fields are not masked so they always show the true status of the TWI controller

M_STOP_DET 9 RW 0x0

M_ACTIVITY 8 RW 0x0

M_RX_DONE 7 RW 0x1

M_TX_ABRT 6 RW 0x1

M_RD_REQ 5 RW 0x1

M_TX_EMPTY 4 RW 0x1

M_TX_OVER 3 RW 0x1

M_RX_FULL 2 RW 0x1

M_RX_OVER 1 RW 0x1

M_RX_UNDER 0 RW 0x1

Table 613 bull Fields in RAW_INTR_STAT

Field Name Bit Access Description DefaultR_GEN_CALL 11 RO Set only when a General Call address is

received and it is acknowledged It stays set until it is cleared either by disabling TWI controller or when the CPU reads bit 0 of the CLR_GEN_CALL register The TWI controller stores the received data in the Rx buffer

R_START_DET 10 RO Indicates whether a START or RESTART condition has occurred on the TWI regardless of whether the TWI controller is operating in slave or master mode

R_STOP_DET 9 RO Indicates whether a STOP condition has occurred on the TWI controller regardless of whether the TWI controller is operating in slave or master mode

Table 612 bull Fields in INTR_MASK (continued)

Registers

R_ACTIVITY 8 RO This bit captures TWI activity and stays set until it is cleared There are four ways to clear it Disabling the TWI controller Reading the CLR_ACTIVITY register Reading the CLR_INTR register VCore system resetOnce this bit is set it stays set unless one of the four methods is used to clear it Even if the TWI controller module is idle this bit remains set until cleared indicating that there was activity on the bus

R_RX_DONE 7 RO When the TWI controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte This occurs on the last byte of the transmission indicating that the transmission is done

R_TX_ABRT 6 RO This bit is set to 1 when the TWI controller is acting as a master is unable to complete a command that the processor has sent The conditions that set this field are No slave acknowledges the address byte The addressed slave receiver does not acknowledge a byte of data Attempting to send a master command when configured only to be a slave When CFGRESTART_ENA is set to 0 (RESTART condition disabled) and the processor attempts to issue a TWI function that is impossible to perform without using RESTART conditions High-speed master code is acknowledged (this controller does not support high-speed) START BYTE is acknowledged General Call address is not acknowledged When a read request interrupt occurs and the processor has previously placed data in the Tx buffer that has not been transmitted yet This data could have been intended to service a multi-byte RD_REQ that ended up having fewer numbers of bytes requestedThe TWI controller loses arbitration of the bus between transfers and is then accessed as a slave-transmitter If a read command is issued after a General Call command has been issued Disabling the TWI reverts it back to normal operation If the CPU attempts to issue read command before a RD_REQ is servicedAnytime this bit is set the contents of the transmit and receive buffers are flushed

Table 613 bull Fields in RAW_INTR_STAT (continued)

Registers

R_RD_REQ 5 RO This bit is set to 1 when the TWI controller acts as a slave and another TWI master is attempting to read data from this controller The TWI controller holds the TWI bus in a wait state (SCL=0) until this interrupt is serviced which means that the slave has been addressed by a remote master that is asking for data to be transferred The processor must respond to this interrupt and then write the requested data to the DATA_CMD register This bit is set to 0 just after the required data is written to the DATA_CMD register

R_TX_EMPTY 4 RO This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_TL register It is automatically cleared by hardware when the buffer level goes above the threshold When ENABLE is 0 the TX FIFO is flushed and held in reset There the TX FIFO looks like it has no data within it so this bit is set to 1 provided there is activity in the master or slave state machines When there is no longer activity then with ENABLE_STATUSBUSY=0 this bit is set to 0

R_TX_OVER 3 RO Set during transmit if the transmit buffer is filled to TX_BUFFER_DEPTH and the processor attempts to issue another TWI command by writing to the DATA_CMD register When the module is disabled this bit keeps its level until the master or slave state machines go into idle and when ENABLE_STATUSBUSY goes to 0 this interrupt is cleared

R_RX_FULL 2 RO Set when the receive buffer reaches or goes above the RX_TL threshold in the RX_TL register It is automatically cleared by hardware when buffer level goes below the threshold If the module is disabled (ENABLE=0) the RX FIFO is flushed and held in reset therefore the RX FIFO is not full So this bit is cleared once the ENABLE field is programmed with a 0 regardless of the activity that continues

Registers

217112 TWITWIRX_TLParent TWITWI

Instances 1

217113 TWITWITX_TLParent TWITWI

Instances 1

R_RX_OVER 1 RO Set if the receive buffer is completely filled to RX_BUFFER_DEPTH and an additional byte is received from an external TWI device The TWI controller acknowledges this but any data bytes received after the FIFO is full are lost If the module is disabled (ENABLE=0) this bit keeps its level until the master or slave state machines go into idle and when ENABLE_STATUSBUSY goes to 0 this interrupt is cleared

R_RX_UNDER 0 RO Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register If the module is disabled (ENABLE=0) this bit keeps its level until the master or slave state machines go into idle and when ENABLE_STATUSBUSY goes to 0 this interrupt is cleared

Table 614 bull Fields in RX_TL

Field Name Bit Access Description DefaultRX_TL 20 RW Controls the level of entries (or above) that

triggers the RX_FULL interrupt (bit 2 in RAW_INTR_STAT register) The valid range is 0-7 A value of 0 sets the threshold for 1 entry and a value of 7 sets the threshold for 8 entries

Table 615 bull Fields in TX_TL

Field Name Bit Access Description DefaultTX_TL 20 RW Controls the level of entries (or below) that

trigger the TX_EMPTY interrupt (bit 4 in RAW_INTR_STAT register) The valid range is 0-7 A value of 0 sets the threshold for 0 entries and a value of 7 sets the threshold for 7 entries

Registers

217114 TWITWICLR_INTRParent TWITWI

Instances 1

217115 TWITWICLR_RX_UNDERParent TWITWI

Instances 1

217116 TWITWICLR_RX_OVERParent TWITWI

Instances 1

217117 TWITWICLR_TX_OVERParent TWITWI

Instances 1

Table 616 bull Fields in CLR_INTR

Field Name Bit Access Description DefaultCLR_INTR 0 RO Read this register to clear the combined

interrupt all individual interrupts and the TX_ABRT_SOURCE register This bit does not clear hardware clearable interrupts but software clearable interrupts Refer to Bit 9 of the TX_ABRT_SOURCE register for an exception to clearing TX_ABRT_SOURCE

Table 617 bull Fields in CLR_RX_UNDER

Field Name Bit Access Description DefaultCLR_RX_UNDER 0 RO Read this register to clear the R_RX_UNDER

interrupt (bit 0) of the RAW_INTR_STAT register

Table 618 bull Fields in CLR_RX_OVER

Field Name Bit Access Description DefaultCLR_RX_OVER 0 RO Read this register to clear the R_RX_OVER

Registers

217118 TWITWICLR_RD_REQParent TWITWI

Instances 1

217119 TWITWICLR_TX_ABRTParent TWITWI

Instances 1

217120 TWITWICLR_RX_DONEParent TWITWI

Instances 1

217121 TWITWICLR_ACTIVITYParent TWITWI

Instances 1

Table 619 bull Fields in CLR_TX_OVER

Field Name Bit Access Description DefaultCLR_TX_OVER 0 RO Read this register to clear the R_TX_OVER

Table 620 bull Fields in CLR_RD_REQ

Field Name Bit Access Description DefaultCLR_RD_REQ 0 RO Read this register to clear the R_RD_REQ

Table 621 bull Fields in CLR_TX_ABRT

Field Name Bit Access Description DefaultCLR_TX_ABRT 0 RO Read this register to clear the R_TX_ABRT

interrupt (bit 6) of the RAW_INTR_STAT register and the TX_ABRT_SOURCE register Refer to Bit 9 of the TX_ABRT_SOURCE register for an exception to clearing TX_ABRT_SOURCE

Table 622 bull Fields in CLR_RX_DONE

Field Name Bit Access Description DefaultCLR_RX_DONE 0 RO Read this register to clear the R_RX_DONE

Registers

217122 TWITWICLR_STOP_DETParent TWITWI

Instances 1

217123 TWITWICLR_START_DETParent TWITWI

Instances 1

217124 TWITWICLR_GEN_CALLParent TWITWI

Instances 1

Table 623 bull Fields in CLR_ACTIVITY

Field Name Bit Access Description DefaultCLR_ACTIVITY 0 RO Reading this register clears the ACTIVITY

interrupt if the TWI controller is not active anymore If the TWI controller is still active on the bus the ACTIVITY interrupt bit continues to be set It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus The value read from this register to get status of the R_ACTIVITY interrupt (bit 8) of the RAW_INTR_STAT register

Table 624 bull Fields in CLR_STOP_DET

Field Name Bit Access Description DefaultCLR_STOP_DET 0 RO Read this register to clear the R_STOP_DET

Table 625 bull Fields in CLR_START_DET

Field Name Bit Access Description DefaultCLR_START_DET 0 RO Read this register to clear the

R_START_DET interrupt (bit 10) of the RAW_INTR_STAT register

Table 626 bull Fields in CLR_GEN_CALL

Field Name Bit Access Description DefaultCLR_GEN_CALL 0 RO Read this register to clear the R_GEN_CALL

interrupt (bit 11) of RAW_INTR_STAT register

Registers

217125 TWITWICTRLParent TWITWI

Instances 1

217126 TWITWISTATParent TWITWI

Instances 1

Table 627 bull Fields in CTRL

Field Name Bit Access Description DefaultENABLE 0 RW Controls whether the TWI controller is

enabled Software can disable the controller while it is active However it is important that care be taken to ensure that the controller is disabled properlyWhen TWI controller is disabled the following occurs The TX FIFO and RX FIFO get flushed The interrupt bits in the RAW_INTR_STAT register are cleared Status bits in the INTR_STAT register are still active until the TWI controller goes into IDLE stateIf the module is transmitting it stops as well as deletes the contents of the transmit buffer after the current transfer is complete If the module is receiving the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer0 Disables TWI controller1 Enables TWI controller

Table 628 bull Fields in STAT

Field Name Bit Access Description DefaultSLV_ACTIVITY 6 RO Slave FSM Activity Status When the Slave

Finite State Machine (FSM) is not in the IDLE state this bit is set0 Slave FSM is in IDLE state so the Slave part of the controller is not Active1 Slave FSM is not in IDLE state so the Slave part of the controller is Active

MST_ACTIVITY 5 RO Master FSM Activity Status When the Master Finite State Machine (FSM) is not in the IDLE state this bit is set0 Master FSM is in IDLE state so the Master part of the controller is not Active1 Master FSM is not in IDLE state so the Master part of the controller is Active

Registers

217127 TWITWITXFLRParent TWITWI

Instances 1

217128 TWITWIRXFLRParent TWITWI

Instances 1

RFF 4 RO Receive FIFO Completely Full When the receive FIFO is completely full this bit is set When the receive FIFO contains one or more empty location this bit is cleared0 Receive FIFO is not full1 Receive FIFO is full

RFNE 3 RO Receive FIFO Not Empty Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty This bit can be polled by software to completely empty the receive FIFO0 Receive FIFO is empty1 Receive FIFO is not empty

TFE 2 RO Transmit FIFO Completely Empty When the transmit FIFO is completely empty this bit is set When it contains one or more valid entries this bit is cleared This bit field does not request an interrupt0 Transmit FIFO is not empty1 Transmit FIFO is empty

TFNF 1 RO Transmit FIFO Not Full Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full0 Transmit FIFO is full1 Transmit FIFO is not full

BUS_ACTIVITY 0 RO TWI Activity Status 0x0

Field Name Bit Access Description DefaultTXFLR 20 RO Transmit FIFO Level Contains the number of

valid data entries in the transmit FIFO0x0

Field Name Bit Access Description DefaultRXFLR 20 RO Receive FIFO Level Contains the number of

valid data entries in the receive FIFO0x0

Table 628 bull Fields in STAT (continued)

Registers

217129 TWITWITX_ABRT_SOURCEParent TWITWI

Instances 1

Table 631 bull Fields in TX_ABRT_SOURCE

Field Name Bit Access Description DefaultABRT_SLVRD_INTX 15 RW When the processor side responds to a slave

mode request for data to be transmitted to a remote master and user writes a 1 to DATA_CMDCMD

ABRT_SLV_ARBLOST 14 RW Slave lost the bus while transmitting data to a remote master TX_ABRT_SOURCE[12] is set at the same timeNote Even though the slave never owns the bus something could go wrong on the bus This is a fail safe check For instance during a data transmission at the low-to-high transition of SCL if what is on the data bus is not what is supposed to be transmitted then the TWI controller no longer own the bus

ABRT_SLVFLUSH_TXFIFO 13 RW Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO

ARB_LOST 12 RW Master has lost arbitration or if TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitrationNote the TWI controller can be both master and slave at the same time

ABRT_MASTER_DIS 11 RW User tries to initiate a Master operation with the Master mode disabled

ABRT_10B_RD_NORSTRT 10 RW The restart is disabled (RESTART_ENA bit (CFG[5]) = 0) and the master sends a read command in 10-bit addressing mode

ABRT_SBYTE_NORSTRT 9 RW To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (CFG[5]=1) the SPECIAL bit must be cleared (TAR[11]) or the GC_OR_START bit must be cleared (TAR[10]) Once the source of the ABRT_SBYTE_NORSTRT is fixed then this bit can be cleared in the same manner as other bits in this register If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit bit 9 clears for one cycle and then gets re-asserted1 The restart is disabled (RESTART_ENA bit (CFG[5]) = 0) and the user is trying to send a START Byte

Registers

217130 TWITWISDA_SETUPParent TWITWI

Instances 1

This field must be set accordingly to the VCore system frequency value = 100ns VCore clock period

Example a 1786MHz clock correspond to a period of 56ns for this frequency and fast TWI speed this field must not be set lower than (round up) 18 = 100ns 56ns For normal TWI speed this field must not be set lower than (round up) 45 = 250ns 56ns

217131 TWITWIACK_GEN_CALLParent TWITWI

ABRT_SBYTE_ACKDET 7 RW Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)

ABRT_GCALL_READ 5 RW TWI controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (DATA_CMD[9] is set to 1)

ABRT_GCALL_NOACK 4 RW TWI controller in master mode sent a General Call and no slave on the bus acknowledged the General Call

ABRT_TXDATA_NOACK 3 RW This is a master-mode only bit Master has received an acknowledgement for the address but when it sent data byte(s) following the address it did not receive an acknowledge from the remote slave(s)

ABRT_10ADDR2_NOACK 2 RW Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave

ABRT_10ADDR1_NOACK 1 RW Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave

ABRT_7B_ADDR_NOACK 0 RW Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave

Table 632 bull Fields in SDA_SETUP

Field Name Bit Access Description DefaultSDA_SETUP 70 RW This register controls the amount of time

delay (in terms of number of VCore clock periods) introduced in the rising edge of SCL relative to SDA changing when the TWI controller services a read request in a slave-receiver operation The minimum for fast mode is 100ns for normal mode the minimum is 250ns

Table 631 bull Fields in TX_ABRT_SOURCE (continued)

Registers

Instances 1

217132 TWITWIENABLE_STATUSParent TWITWI

Instances 1

Table 633 bull Fields in ACK_GEN_CALL

Field Name Bit Access Description DefaultACK_GEN_CALL 0 RW ACK General Call When set to 1 the TWI

controller responds with a ACK when it receives a General Call Otherwise the controller responds with a NACK

Table 634 bull Fields in ENABLE_STATUS

Field Name Bit Access Description DefaultSLV_FIFO_FILLED_AND_FLUSHED

2 RO Slave FIFO Filled and Flushed This bit indicates if a Slave-Receiver operation has been aborted with at least 1 data byte received from a TWI transfer due to the setting of ENABLE from 1 to 0When read as 1 the TWI controller is deemed to have been actively engaged in an aborted TWI transfer (with matching address) and the data phase of the TWI transfer has been entered even though the data byte has been responded with a NACKWhen read as 0 the TWI controller is deemed to have been disabled when the TWI bus is idle

SLV_RX_ABORTED 1 RO Slave-Receiver Operation Aborted This bit indicates if a Slave-Receiver operation has been aborted due to the setting of the ENABLE register from 1 to 0When read as 1 the TWI controller is deemed to have forced a NACK during any part of a TWI transfer irrespective of whether the TWI address matches the slave address set in the TWI controller (SAR register)When read as 0 the TWI controller is deemed to have been disabled when the TWI bus is idle

BUSY 0 RO When read as 1 the TWI controller is deemed to be actively involved in an TWI transfer irrespective of whether being in an address or data phase for all master or slave modes When read as 0 the TWI controller is deemed completely inactive

Registers

218 UART

2181 UARTUARTParent UART

Instances 1

21811 UARTUARTRBR_THRParent UARTUART

Instances 1

When the LCRDLAB is set this register is the lower 8 bits of the 16-bit Divisor register that contains the baud rate divisor for the UART

The output baud rate is equal to the VCore system clock frequency divided by sixteen times the value of the baud rate divisor as follows baud rate = (VCore clock freq) (16 divisor) Note that with the Divisor set to zero the baud clock is disabled and no serial communications occur In addition once this register is set wait at least 01us before transmitting or receiving data

Table 635 bull Register Groups in UART

UART 0x00000000 1 UART Page 293

Table 636 bull Registers in UART

RBR_THR 0x00000000 1 Receive buffer transmit holding divisor (low)

IER 0x00000004 1 Interrupt enable divisor (high) Page 294

IIR_FCR 0x00000008 1 Interrupt identification FIFO control register

LCR 0x0000000C 1 Line control Page 296

MCR 0x00000010 1 Modem control Page 298

LSR 0x00000014 1 Line status Page 298

MSR 0x00000018 1 Modem status Page 301

SCR 0x0000001C 1 Scratchpad Page 301

USR 0x0000007C 1 UART status Page 301

Registers

21812 UARTUARTIERParent UARTUART

Instances 1

When the LCRDLAB is set this register is the upper 8 bits of the 16-bit Divisor register that contains the baud rate divisor for the UART For more information and a description of how to calculate the baud rate see RBR_THR

Table 637 bull Fields in RBR_THR

Field Name Bit Access Description DefaultRBR_THR 70 RW Use this register to access the Rx and Tx

FIFOsWhen reading The data in this register is valid only if LSRDR is set If FIFOs are disabled (IIR_FCRFIFOE) the data in this register must be read before the next data arrives otherwise it is overwritten resulting in an overrun error When FIFOs are enabled (IIR_FCRFIFOE) this register accesses the head of the receive FIFO If the receive FIFO is full and this register is not read before the next data character arrives then the data already in the FIFO is preserved but any incoming data is lost and an overrun error occursWhen writing Data should only be written to this register when the LSRTHRE indicates that there is room in the FIFO If FIFOs are disabled (IIR_FCRFIFOE) writes to this register while LSRTHRE is zero causes the register to be overwritten When FIFOs are enabled (IIR_FCRFIFOE) and LSRTHRE is set 16 characters may be written to this register before the FIFO is full Any attempt to write data when the FIFO is full results in the write data being lost

Table 638 bull Fields in IER

Field Name Bit Access Description DefaultPTIME 7 RW Programmable THRE interrupt mode enable

This is used to enable or disable the generation of THRE interrupt0 Disabled1 Enabled

EDSSI 3 RW Enable modem status interrupt This is used to enable or disable the generation of Modem Status interrupt This is the fourth highest priority interrupt0 Disabled1 Enabled

Registers

21813 UARTUARTIIR_FCRParent UARTUART

Instances 1

This register has special meaning when reading here the lowest 4 bits indicate interrupting sources The encoding is as follows

0110 type Receiver line status priority Highest Overrunparity framing errors or break interrupt Cleared by reading LSR

0100 type Received data available priority Second RCVR FIFO trigger level reached Cleared when FIFO drops below the trigger level

1100 type Character timeout indication priority Second No characters in or out of the RCVR FIFO during the last four character times and there is at least 1 character in it during this time Cleared by reading the receiver buffer register

0010 type Transmit holding register empty priority Third Transmitter holding register empty (Prog THRE Mode disabled) or XMIT FIFO at or below threshold (Prog THRE Mode enabled) Cleared by reading the IIR register (if source of interrupt) or writing into THR (THRE Mode disabled) or XMIT FIFO above threshold (THRE Mode enabled)

0000 type Modem status priority Fourth Clear to send Note that if auto flow control mode is enabled a change in CTS (that is DCTS set) does not cause an interrupt Cleared by reading the Modem status register

0111 type Busy detect indication priority Fifth Master has tried to write to the Line Control register while the UART is busy (USR[0] is set to one) Cleared by reading the UART status register

0001 No interrupting sources

ELSI 2 RW Enable receiver line status interrupt This is used to enable or disable the generation of Receiver Line Status interrupt This is the highest priority interrupt0 Disabled1 Enabled

ETBEI 1 RW Enable transmit holding register empty interrupt This is used to enable or disable the generation of Transmitter Holding Register Empty interrupt This is the third highest priority interrupt0 Disabled1 Enabled

ERBFI 0 RW Enable received data available interrupt This is used to enable or disable the generation of Received Data Available interrupt and the Character Timeout interrupt (if FIFOs are enabled) These are the second highest priority interrupts0 Disabled1 Enabled

Table 638 bull Fields in IER (continued)

Registers

21814 UARTUARTLCRParent UARTUART

Instances 1

Table 639 bull Fields in IIR_FCR

Field Name Bit Access Description DefaultFIFOSE_RT 76 RW When reading this field the current status of

the FIFO is returned 00 for disabled or 11 for enabled Writing this field selects the trigger level in the receive FIFO at which the Received Data Available interrupt is generated (see encoding) In auto flow control mode it is used to determine when to generate back-pressure using the RTS signal00 1 character in the Rx FIFO01 Rx FIFO 14 full10 Rx FIFO 12 full11 Rx FIFO 2 less than full

TET 54 RW Tx empty trigger When the THRE mode is enabled (IERPTIME) this field selects the empty threshold level at which the THRE Interrupts are generated00 Tx FIFO empty01 2 characters in the Tx FIFO10 Tx FIFO 14 full11 Tx FIFO 12 full

XFIFOR 2 RW This description is valid for writes only Reading this field has special meaning for more information see the general register descriptionTx FIFO Reset This resets the control portion of the transmit FIFO and treats the FIFO as empty Note that this bit is self-clearing It is not necessary to clear this bit

RFIFOR 1 RW This description is valid for writes only Reading this field has special meaning for more information see the general register descriptionRx FIFO Reset This resets the control portion of the receive FIFO and treats the FIFO as empty Note that this bit is self-clearing It is not necessary to clear this bit

FIFOE 0 RW This description is valid for writes only Reading this field has special meaning for more information see the general register descriptionFIFO Enable This enables or disables the transmit (XMIT) and receive (RCVR) FIFOs Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs are reset

Registers

Writes can be made to this register with the exception of the BC field only when UART is not busy that is when USRBUSY is zero This register can always be read

Table 640 bull Fields in LCR

Field Name Bit Access Description DefaultDLAB 7 RW Divisor latch access bit This bit is used to

enable reading and writing of the Divisor registers (RBR_THR and IER) to set the baud rate of the UART To access other registers this bit must be cleared after initial baud rate setup

BC 6 RW Break control bitThis bit is used to cause a break condition to be transmitted to the receiving device If set to one the serial output is forced to the spacing (logic 0) state When not in Loopback Mode as determined by MCR[4] the serial output is forced low until the Break bit is cleared

EPS 4 RW Even parity select This bit is used to select between even and odd parity when parity is enabled (PEN set to one) If set to one an even number of logic 1s is transmitted or checked If set to zero an odd number of logic 1s is transmitted or checked

PEN 3 RW Parity enable This bit is used to enable or disable parity generation and detection in both transmitted and received serial characters0 Parity disabled1 Parity enabled

STOP 2 RW Number of stop bits This is used to select the number of stop bits per character that the peripheral transmits and receives If set to zero one stop bit is transmitted in the serial dataIf set to one and the data bits are set to 5 (LCRDLS) one and a half stop bits are transmitted Otherwise two stop bits are transmitted Note that regardless of the number of stop bits selected the receiver checks only the first stop bit0 1 stop bit1 15 stop bits when LCRDLS is zero otherwise 2 stop bits

DLS 10 RW Data length select This is used to select the number of data bits per character that the peripheral transmits and receives The following settings specify the number of bits that may be selected00 5 bits01 6 bits10 7 bits11 8 bits

Registers

21815 UARTUARTMCRParent UARTUART

Instances 1

21816 UARTUARTLSRParent UARTUART

Instances 1

Table 641 bull Fields in MCR

Field Name Bit Access Description DefaultAFCE 5 RW Auto flow control enable This mode requires

that FIFOs are enabled and that MCRRTS is set0 Auto flow control mode disabled1 Auto flow control mode enabled

LB 4 RW Loopback Bit This is used to put the UART into a diagnostic mode for test purposesThe transmit line is held high while serial transmit data is looped back to the receive line internally In this mode all the interrupts are fully functional In addition in loopback mode the modem control input CTS is disconnected and the modem control output RTS is looped back to the input internally

RTS 1 RW Request to send This is used to directly control the Request to Send (RTS) output The RTS output is used to inform the partner that the UART is ready to exchange dataThe RTS is still controlled from this field when Auto RTS Flow Control is enabled (MCRAFCE) but the output can be forced high by the flow control mechanism If this field is cleared the UART permanently indicates backpressure to the partner0 RTS is set high1 RTS is set low

Registers

Table 642 bull Fields in LSR

Field Name Bit Access Description DefaultRFE 7 RW Receiver FIFO error bit This bit is only valid

when FIFOs are enabled This is used to indicate whether there is at least one parity error framing error or break indication in the FIFOThis bit is cleared when the LSR is read the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO0 No error in Rx FIFO1 Error in Rx FIFO

TEMT 6 RW Transmitter empty bit If FIFOs are enabled this bit is set whenever the Transmitter Shift Register and the FIFO are both empty

THRE 5 RW If FIFO (IIR_FCRFIFOE) and THRE mode are enabled (IERPTIME) this bit indicates that the Tx FIFO is full Otherwise this bit indicates that the Tx FIFO is empty

BI 4 RW Break interrupt bit This is used to indicate the detection of a break sequence on the serial input dataIt is set whenever the serial input is held in a logic 0 state for longer than the sum of start time + data bits + parity + stop bitsA break condition on serial input causes one and only one character consisting of all-zeros to be received by the UARTIn the FIFO mode the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO Reading the LSR clears the BI bit In the non-FIFO mode the BI indication occurs immediately and persists until the LSR is read

Registers

FE 3 RW Framing error bit This is used to indicate the a framing error in the receiver A framing error occurs when the receiver does not detect a valid STOP bit in the received dataA framing error is associated with a received character Therefore in FIFO mode an error is revealed when the character with the framing error is at the top of the FIFO When a framing error occurs the UART tries to resynchronize It does this by assuming that the error was due to the start bit of the next character and then continues to receive the other bit that is data andor parity and then stops Note that this field is set if a break interrupt has occurred as indicated by Break Interrupt (LSRBI)This field is cleared on read0 No framing error1 Framing error

PE 2 RW Parity error bit This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable bit (LCRPEN) is setA parity error is associated with a received character Therefore in FIFO mode an error is revealed when the character with the parity error arrives at the top of the FIFO Note that this field is set if a break interrupt has occurred as indicated by Break Interrupt (LSRBI)This field is cleared on read0 No parity error1 Parity error

OE 1 RW Overrun error bit This is used to indicate the occurrence of an overrun error This occurs if a new data character was received before the previous data was readIn non-FIFO mode the OE bit is set when a new character arrives before the previous character was read When this happens the data in the RBR is overwritten In FIFO mode an overrun error occurs when the FIFO is full and a new character arrives at the receiver The data in the FIFO is retained and the data in the receive shift register is lostThis field is cleared on read0 No overrun error1 Overrun error

DR 0 RW Data ready This is used to indicate that the receiver contains at least one character in the receiver FIFO This bit is cleared when the RX FIFO is empty0 No data ready1 Data ready

Table 642 bull Fields in LSR (continued)

Registers

21817 UARTUARTMSRParent UARTUART

Instances 1

21818 UARTUARTSCRParent UARTUART

Instances 1

21819 UARTUARTUSRParent UARTUART

Instances 1

Table 643 bull Fields in MSR

Field Name Bit Access Description DefaultCTS 4 RO Clear to send This field indicates the current

state of the modem control line CTS When the Clear to Send input (CTS) is asserted it is an indication that the partner is ready to exchange data with the UART0 CTS input is deasserted (logic 0)1 CTS input is asserted (logic 1)

DCTS 0 RO Delta clear to send This is used to indicate that the modem control line CTS has changed since the last time the MSR was read Reading the MSR clears the DCTS bitNote If the DCTS bit is not set the CTS signal is asserted and a reset occurs (software or otherwise) then the DCTS bit is set when the reset is removed if the CTS signal remains asserted A read of the MSR after reset can be performed to prevent unwanted interrupts0 No change on CTS since the last read of the MSR1 Change on CTS since the last read of the MSR

Table 644 bull Fields in SCR

Field Name Bit Access Description DefaultSCR 70 RW This register is for programmers to use as a

temporary storage space It has no functional purpose for the UART

Registers

219 PHY

2191 PHYPHY_STDParent PHY

Instances 1

The following section lists the standard register set for the PHY

Table 645 bull Fields in USR

Field Name Bit Access Description DefaultBUSY 0 RO UART busy

0 UART is idle or inactive1 UART is busy (actively transferring data)

Table 646 bull Register Groups in PHY

PHY_STD 0x00000000 1 IEEE Standard and Main Registers

PHY_EXT1 0x00000080 1 Extended Page 1 Registers Page 325

PHY_EXT2 0x000000FC 1 Extended Page 2 Registers Page 331

PHY_GP 0x00000168 1 General Purpose Registers Page 336

PHY_EEE 0x000001E0 1 Clause 45 Registers to Support Energy Efficient

Table 647 bull Registers in PHY_STD

PHY_CTRL 0x00000000 1 Control (Address 0) Page 304

PHY_STAT 0x00000004 1 Status (Address 1) Page 304

PHY_IDF1 0x00000008 1 PHY Identifier Number 1 (Address 2)

PHY_IDF2 0x0000000C 1 PHY Identifier Number 2 (Address 3)

PHY_AUTONEG_ADVERTISMENT

0x00000010 1 Auto-Negotiation Advertisement (Address 4)

PHY_AUTONEG_LP_ABILITY 0x00000014 1 Auto-Negotiation Link Partner Base Page Ability (Address 5)

PHY_AUTONEG_EXP 0x00000018 1 Auto-Negotiation Expansion (Address 6)

Registers

PHY_AUTONEG_NEXTPAGE_TX 0x0000001C 1 Auto-Negotiation Next-Page Transmit (Address 7)

PHY_AUTONEG_LP_NEXTPAGE_RX

0x00000020 1 Auto-Negotiation Next-Page Receive (Address 8)

PHY_CTRL_1000BT 0x00000024 1 1000BASE-T Control (Address 9)

PHY_STAT_1000BT 0x00000028 1 1000BASE-T Status (Address 10)

MMD_ACCESS_CFG 0x00000034 1 MMD Access Control Register (Address 13)

MMD_ADDR_DATA 0x00000038 1 MMD Address or Data Register (Address 14)

PHY_STAT_1000BT_EXT1 0x0000003C 1 1000BASE-T Status Extension Number 1 (Address 15)

PHY_STAT_100BTX 0x00000040 1 100BASE-TX Status (Address 16)

PHY_STAT_1000BT_EXT2 0x00000044 1 1000BASE-T Status Extension Number 2 (Address 17)

PHY_BYPASS_CTRL 0x00000048 1 Bypass Control (Address 18) Page 312

PHY_ERROR_CNT1 0x0000004C 1 Error Counter Number 1 (Address 19)

PHY_ERROR_CNT2 0x00000050 1 Error Counter Number 2 (Address 20)

PHY_CTRL_STAT_EXT 0x00000058 1 Extended Control and Status (Address 22)

PHY_CTRL_EXT1 0x0000005C 1 Extended Control Number 1 (Address 23)

PHY_CTRL_EXT2 0x00000060 1 Extended Control Number 2 (Address 24)

PHY_INT_MASK 0x00000064 1 Interrupt Mask (Address 25) Page 317

PHY_INT_STAT 0x00000068 1 Interrupt Status (Address 26) Page 319

PHY_AUX_CTRL_STAT 0x00000070 1 Auxiliary Control and Status (Address 28)

PHY_LED_MODE_SEL 0x00000074 1 LED Mode Select (Address 29)

PHY_LED_BEHAVIOR_CTRL 0x00000078 1 LED Behavior Control (Address 30)

PHY_MEMORY_PAGE_ACCESS 0x0000007C 1 Memory Page Access (Address 31)

Table 647 bull Registers in PHY_STD (continued)

Registers

21911 PHYPHY_STDPHY_CTRLParent PHYPHY_STD

Instances 1

21912 PHYPHY_STDPHY_STATParent PHYPHY_STD

Table 648 bull Fields in PHY_CTRL

Field Name Bit Access Description DefaultSOFTWARE_RESET_ENA 15 RW Initiate software reset This field is cleared as

part of this operation After enabling this field you must wait at least 4 us before PHY registers can be accessed again

LOOPBACK_ENA 14 RW Enable loopback mode The loopback mechanism works at the current speed If the link is down (see PHY_STATLINK_STATUS) SPEED_SEL_LSB_CFG and SPEED_SEL_MSB_CFG determine the operating speed of the loopback

SPEED_SEL_LSB_CFG 13 RW Least significant bit of the speed selection along with SPEED_SEL_MSB_CFG this field determines the speed when auto-negotiation is disabled (See AUTONEG_ENA)00 10 Mbps01 100 Mbps10 1000 Mbps11 Reserved

AUTONEG_ENA 12 RW Enable auto-negotiation When cleared the speed and duplex-mode are determined by SPEED_SEL_LSB_CFG SPEED_SEL_MSB_CFG and DUPLEX_MODE_CFG

POWER_DOWN_ENA 11 RW Enable power-down mode This disables PHY operation until this bit is cleared or the PHY is reset

ISOLATE_ENA 10 RW Isolate the PHY from the integrated MAC 0x0

AUTONEG_RESTART_ENA 9 RW Restart an auto-negotiation cycle the PHY clears this field when auto-negotiation is restarted

DUPLEX_MODE_CFG 8 RW Configure duplex mode when auto-negotiation is disabled (see AUTONEG_ENA)0 Half-duplex1 Full-duplex

COLLISION_TEST_ENA 7 RW Enable collision indication test-mode when enabled the PHY indicate collision when the MAC transmits data to the PHY

SPEED_SEL_MSB_CFG 6 RW See SPEED_SEL_LSB_CFG 0x1

Registers

Instances 1

21913 PHYPHY_STDPHY_IDF1Parent PHYPHY_STD

Instances 1

Field Name Bit Access Description DefaultMODE_100BT4 15 RO The PHY is not 100BASE-T4 capable 0x0

MODE_100BX_FDX 14 RO The PHY is 100BASE-X FDX capable 0x1

MODE_100BX_HDX 13 RO The PHY is 100BASE-X HDX capable 0x1

MODE_10BT_FDX 12 RO The PHY is 10BASE-T FDX capable 0x1

MODE_10BT_HDX 11 RO The PHY is 10BASE-T HDX capable 0x1

MODE_100BT2_FDX 10 RO The PHY is not 100BASE-T2 FDX capable 0x0

MODE_100BT2_HDX 9 RO The PHY is not 100BASE-T2 HDX capable 0x0

EXT_STATUS 8 RO Extended status information are available see the PHY_STAT_EXT register

PREAMBLE_SUPPRESS 6 RO The PHY accepts management frames with preamble suppressed

AUTONEG_COMPLETE 5 RO This field is set when auto-negotiation is completed and cleared during active auto-negotiation cycles

REMOTE_FAULT 4 RO This field is set when the PHY detects a remote fault condition and cleared on register read

AUTONEG_ABILITY 3 RO The PHY is capable of auto-negotiation 0x1

LINK_STAT 2 RO This field is cleared when the link is down It is set when the link is up and a previous link-down indication was read from the register

JABBER_DETECT 1 RO This field is set when the PHY detects a jabber condition and cleared on register read

EXT_CAPABILITY 0 RO The PHY provides an extended set of capabilities

Table 650 bull Fields in PHY_IDF1

Field Name Bit Access Description DefaultOUI_MS 150 RO Vitesses organizationally unique identifier

bits 3 through 18 0x0007

Registers

21915 PHYPHY_STDPHY_AUTONEG_ADVERTISMENTParent PHYPHY_STD

Instances 1

21916 PHYPHY_STDPHY_AUTONEG_LP_ABILITYParent PHYPHY_STD

Instances 1

Field Name Bit Access Description DefaultOUI_LS 1510 RO Vitesses organizationally unique identifier

MODEL_NUMBER 94 RO The device model number 0x2D

REVISION_NUMBER 30 RO The device revision number 0x0

Table 652 bull Fields in PHY_AUTONEG_ADVERTISMENT

Field Name Bit Access Description DefaultNEXT_PAGE_ENA 15 RW Advertises desire to engage in next-page

exchange When this field is set next-page control is returned to the user for additional next-pages following the 1000BASE-T next-page exchange

REMOTE_FAULT_CFG 13 RW Transmit Remote Fault 0x0

ASYM_PAUSE_CFG 11 RW Advertise asymmetric pause capability 0x0

SYM_PAUSE_CFG 10 RW Advertise symmetric pause capability 0x0

ADV_100BT4_CFG 9 RW Advertise 100BASE-T4 capability 0x0

ADV_100BX_FDX_CFG 8 RW Advertise 100BASE-X FDX capability 0x1

ADV_100BX_HDX_CFG 7 RW Advertise 100BASE-X HDX capability 0x1

ADV_10BT_FDX_CFG 6 RW Advertise 10BASE-T FDX capability 0x1

ADV_10BT_HDX_CFG 5 RW Advertise 10BASE-T HDX capability 0x1

SELECTOR_FIELD_CFG 40 RW Select types of message send by auto-negotiation

Table 653 bull Fields in PHY_AUTONEG_LP_ABILITY

Field Name Bit Access Description DefaultLP_NEXT_PAGE 15 RO Link partner advertises desire to engage in

next-page exchange0x0

LP_ACKNOWLEDGE 14 RO Link partner advertises that link code word was successfully received

LP_REMOTE_FAULT 13 RO Link partner advertises remote fault 0x0

Registers

21917 PHYPHY_STDPHY_AUTONEG_EXPParent PHYPHY_STD

Instances 1

21918 PHYPHY_STDPHY_AUTONEG_NEXTPAGE_TXParent PHYPHY_STD

Instances 1

LP_ASYM_PAUSE 11 RO Link partner advertises asymmetric pause capability

LP_SYM_PAUSE 10 RO Link partner advertises symmetric pause capability

LP_100BT4 9 RO Link partner advertises 100BASE-T4 capability

LP_100BX_FDX 8 RO Link partner advertises 100BASE-X FDX capability

LP_100BX_HDX 7 RO Link partner advertises 100BASE-X HDX capability

LP_10BT_FDX 6 RO Link partner advertises 10BASE-T FDX capability

LP_10BT_HDX 5 RO Link partner advertises 10BASE-T HDX capability

LP_SELECTOR_FIELD 40 RO Link partner advertises select type of message send by auto-negotiation

Table 654 bull Fields in PHY_AUTONEG_EXP

Field Name Bit Access Description DefaultPARALLEL_DET_FAULT 4 RO This field is set when the PHY detects a

Receive Link Integrity Test Failure condition and cleared on register read

LP_NEXT_PAGE_ABLE 3 RO Set if link partner is next-page capable 0x0

NEXT_PAGE_ABLE 2 RO The PHY is next-page capable 0x1

NEXT_PAGE_RECEIVED 1 RO This field is set when the PHY receives a valid next-page and cleared on register read

LP_AUTONEG_ABLE 0 RO Set if link partner is auto-negotiation capable 0x0

Table 655 bull Fields in PHY_AUTONEG_NEXTPAGE_TX

Field Name Bit Access Description DefaultNEXT_PAGE_CFG 15 RW Set to indicate that more pages will follow

clear if current page is the last0x0

Table 653 bull Fields in PHY_AUTONEG_LP_ABILITY (continued)

Registers

21919 PHYPHY_STDPHY_AUTONEG_LP_NEXTPAGE_RXParent PHYPHY_STD

Instances 1

219110 PHYPHY_STDPHY_CTRL_1000BTParent PHYPHY_STD

Instances 1

MESSAGE_PAGE_CFG 13 RW Set to indicate that this is a message page clear if the current page consists of unformatted code

ACKNOWLEDGE2_CFG 12 RW Set to indicate ability to comply with the request of the last received page

TOGGLE 11 RO Alternates between 0 and 1 for each transmitted page

MESSAGE_FIELD_CFG 100 RW Contains page information - either message or unformatted code MESSAGE_PAGE_CFG must indicate if this page contains either a message or unformatted code

Table 656 bull Fields in PHY_AUTONEG_LP_NEXTPAGE_RX

Field Name Bit Access Description DefaultLP_NEXT_PAGE_RX 15 RO Set by link partner to indicate that more

pages follow When cleared this is the last of the next-pages

LP_ACKNOWLEDGE_RX 14 RO Set by link partner to acknowledge the reception of last message

LP_MESSAGE_PAGE 13 RO Set by Link partner if this page contains a message When cleared this page contains unformatted code

LP_ACKNOWLEDGE2 12 RO Set by link partner to indicate that it is able to act on transmitted information

LP_TOGGLE 11 RO Will alternate between 0 and 1 for each received page Used to check for errors

LP_MESSAGE_FIELD 100 RO Contains page information MESSAGE_PAGE indicates if this page contains either a message or unformatted code

Table 655 bull Fields in PHY_AUTONEG_NEXTPAGE_TX (continued)

Registers

219111 PHYPHY_STDPHY_STAT_1000BTParent PHYPHY_STD

Instances 1

Table 657 bull Fields in PHY_CTRL_1000BT

Field Name Bit Access Description DefaultTX_TEST_MODE_CFG 1513 RW Configure 1000BASE-T test modes this field

is only valid in 1000BASE-T mode Other encodings are reserved and must not be selected 0 Normal operation1 Transmit waveform test2 Transmit jitter test in master mode3 Transmit jitter test in slave mode4 Transmit distortion test

MS_MANUAL_CFG_ENA 12 RW Enable manual configuration of masterslave value

MS_MANUAL_CFG 11 RW Configure if the PHY should configure itself as either master or slave during masterslave negotiations This field is only valid when MS_MANUAL_CFG_ENA is set0 Configure as slave1 Configure as master

PORT_TYPE_CFG 10 RW Set to indicate multi-port device clear to indicate single-port device

ADV_1000BT_FDX_CFG 9 RW Set to advertise 1000BASE-T FDX capability 0x1

ADV_1000BT_HDX_CFG 8 RW Set to advertise 1000BASE-T HDX capability 0x1

Table 658 bull Fields in PHY_STAT_1000BT

Field Name Bit Access Description DefaultMS_CFG_FAULT 15 RO This field is set when the PHY detects a

masterslave configuration fault condition and cleared on register read

MS_CFG_RESOLUTION 14 RO This field indicates the result of a masterslave Negotiation0 Local PHY is resolved to slave1 Local PHY is resolved to master

LOCAL_RECEIVER_STAT 13 RO The status of the local receiver (loc_rcvr_status as defined in IEEE Std 8023)0 Local receiver status is NOT_OK1 Local receiver status is OK

REMOTE_RECEIVER_STAT 12 RO The status of the remote receiver (rem_rcvr_status as defined in IEEE Std 8023)0 Remote receiver status is NOT_OK1 Remote receiver status is OK

Registers

219112 PHYPHY_STDMMD_ACCESS_CFGParent PHYPHY_STD

Instances 1

The bits in this register of the main register space are a window to the EEE registers as

defined in IEEE 8023az Clause 45

219113 PHYPHY_STDMMD_ADDR_DATAParent PHYPHY_STD

Instances 1

219114 PHYPHY_STDPHY_STAT_1000BT_EXT1Parent PHYPHY_STD

LP_1000BT_FDX 11 RO Set if link partner advertises 1000BASE-T FDX capability

LP_1000BT_HDX 10 RO Set if link partner advertises 1000BASE-T HDX capability

IDLE_ERR_CNT 70 RO Counts each occurrence of rxerror_status = Error (rx_error_status as defined in IEEE Std 8023 This field is cleared on read and saturates at all-ones

Table 659 bull Fields in MMD_ACCESS_CFG

Field Name Bit Access Description DefaultMMD_FUNCTION 1514 RW Function

0 Address1 Data no post increment2 Data post increment for read and write3 Data post increment for write only

MMD_DVAD 40 RW Device address as defined in IEEE 8023az table 45-1

Table 660 bull Fields in MMD_ADDR_DATA

Field Name Bit Access Description DefaultMMD_ADDR_DATA 150 RW If MMD_ACCESS_CFGMMD_FUNCTION is

0 MMD_ADDR_DATA specifies the address of register of the device that is specified by MMD_ACCESS_CFGMMD_DVAD Otherwise MMD_ADDR_DATA specifies the data to be written to or read from the register

0x0000

Table 658 bull Fields in PHY_STAT_1000BT (continued)

Registers

Instances 1

219115 PHYPHY_STDPHY_STAT_100BTXParent PHYPHY_STD

Instances 1

These fields are only valid in 100BASE-T mode

Instances 1

Table 661 bull Fields in PHY_STAT_1000BT_EXT1

Field Name Bit Access Description DefaultMODE_1000BX_FDX 15 RO The PHY is not 1000BASE-X FDX capable 0x0

MODE_1000BX_HDX 14 RO The PHY is not 1000BASE-X HDX capable 0x0

Table 662 bull Fields in PHY_STAT_100BTX

Field Name Bit Access Description DefaultDESCRAM_LOCKED 15 RO This field is set when the 100BASE-TX

descrambler is in lock and cleared when it is out of lock

DESCRAM_ERR 14 RO This field is set when the PHY detects a descrambler error condition and cleared on register read

LINK_DISCONNECT 13 RO This field is set when the PHY detects a 100BASE-TX link disconnect condition and cleared on register read

LINK_STAT_100 12 RO This field is set when the 100BASE-TX link status is active and cleared when inactive

RECEIVE_ERR 11 RO This field is set when the PHY detects a receive error condition and cleared on register read

TRANSMIT_ERR 10 RO This field is set when the PHY detects a transmit error condition and cleared on register read

SSD_ERR 9 RO This field is set when the PHY detects a Start-of-Stream Delimiter Error condition and cleared on register read

ESD_ERR 8 RO This field is set when the PHY detects an End-of-Stream Delimiter Error condition and cleared on register read

Registers

219117 PHYPHY_STDPHY_BYPASS_CTRLParent PHYPHY_STD

Instances 1

Field Name Bit Access Description DefaultDESCRAM_LOCKED_1000 15 RO This field is set when the 1000BASE-T

DESCRAM_ERR_1000 14 RO This field is set when the PHY detects a Descrambler Error condition and cleared on register read

LINK_DISCONNECT_1000 13 RO This field is set when the PHY detects a 1000BASE-T link disconnect condition and cleared on register read

LINK_STAT_1000 12 RO This field is set when the 1000BASE-T link status is active and cleared when inactive

RECEIVE_ERR_1000 11 RO This field is set when the PHY detects a Receive Error condition and cleared on register read

TRANSMIT_ERR_1000 10 RO This field is set when the PHY detects a Transmit Error condition and cleared on register read

SSD_ERR_1000 9 RO This field is set when the PHY detects a Start-of-Stream Delimiter Error condition and cleared on register read

ESD_ERR_1000 8 RO This field is set when the PHY detects an End-of-Stream Delimiter Error condition and cleared on register read

CARRIER_EXT_ERR_1000 7 RO This field is set when the PHY detects a 1000BASE-T Carrier Extension Error condition and cleared on register read

BCM5400_ERR_1000 6 RO This field is set when the PHY detects a non-compliant BCM5400 condition This field is only valid when the 1000BASE-T descrambler is in locked state (see DESCRAM_LOCKED_1000)

MDI_CROSSOVER_ERR 5 RO This field is set when the PHY detects an MDI crossover error condition

Table 664 bull Fields in PHY_BYPASS_CTRL

Field Name Bit Access Description DefaultTX_DIS 15 RW Disable the PHY transmitter When set the

analog blocks are powered down and zeros are send to the DAC

ENC_DEC_4B5B 14 RW If set bypass the 4B5B encoderdecoder 0x0

Registers

219118 PHYPHY_STDPHY_ERROR_CNT1Parent PHYPHY_STD

Instances 1

SCRAMBLER 13 RW If set bypass the scrambler 0x0

DESCRAMBLER 12 RW If set bypass the descrambler 0x0

PCS_RX 11 RW If set bypass the PCS receiver 0x0

PCS_TX 10 RW If set bypass the PCS transmit 0x0

LFI_TIMER 9 RW If set bypass the link fail inhibit (LFI) timer 0x0

FORCED_SPEED_AUTO_MDIX_DIS

7 RW Bit for disabling HP AutoMDIX in forced 10100 speeds even though auto-negotiation is disabled0 The HP Auto-MDIX function is enabled1 Default value The HP Auto-MDIX function is disabled Use the default value when in auto-negotiation mode

PAIR_SWAP_DIS 5 RW Disable automatic pair swap correction This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

POL_INV_DIS 4 RW Disable automatic polarity inversion correction This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

PARALLEL_DET_DIS 3 RW When cleared the PHY ignores its advertised abilities when performing parallel detect This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

PULSE_SHAPING_DIS 2 RW If set disable the pulse shaping filter 0x0

AUTO_NP_EXCHANGE_DIS 1 RW Disable automatic exchange of 1000BASE-T next pages If this feature is disabled you have the responsibility of sending next pages determining capabilities and configuration of the PHY after successful exchange of pages This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

Table 665 bull Fields in PHY_ERROR_CNT1

Field Name Bit Access Description DefaultRX_ERR_CNT 70 RO Counter containing the number of packets

received with errors for 1001000BASE-TX The counter saturates at 255 and it is cleared when read

Table 664 bull Fields in PHY_BYPASS_CTRL (continued)

Registers

Instances 1

219121 PHYPHY_STDPHY_CTRL_STAT_EXTParent PHYPHY_STD

Instances 1

Field Name Bit Access Description DefaultFALSE_CARRIER_CNT 70 RO Counter containing the number of false

carrier incidents for 1001000BASE-TX The counter saturates at 255 and it is cleared when read

Field Name Bit Access Description DefaultLINK_DIS_CNT 70 RO Counter containing the number of copper

media link disconnects The counter saturates at 255 and it is cleared when read

Table 668 bull Fields in PHY_CTRL_STAT_EXT

Field Name Bit Access Description DefaultLINK_10BT_FORCE_ENA 15 RW When this field is set the PHY link integrity

state machine is bypassed and the PHY is forced into link pass status This is a sticky field see PHY_CTRL_EXTSTICKY_RESET_ENA

JABBER_DETECT_DIS 14 RW Disable jabber detect function When this is disabled the PHY allows transmission requests to be arbitrarily long without shutting down the transmitter When cleared the PHY shuts down the transmitter after the specified time limit specified by IEEE This is a sticky field see PHY_CTRL_EXTSTICKY_RESET_ENA

Registers

ECHO_10BT_DIS 13 RW When this field is set the state of the TX_EN pin does not echo onto the CRS pin which effectively disables CRS from being asserted in half-duplex operation When cleared the TX_EN pin is echoed onto the CRS pin This applies only in 10BASE-T mode This is a sticky field see PHY_CTRL_EXTSTICKY_RESET_ENA

SQE_10BT_DIS 12 RW Disable SQE (Signal Quality Error) pulses on the MAC interface This applies only in 10BASE-T mode This is a sticky field see PHY_CTRL_EXTSTICKY_RESET_ENA

SQUELCH_10BT_CFG 1110 RW Configure squelch control (this only applies in the 10BASE-T mode) This is a sticky field see PHY_CTRL_EXTSTICKY_RESET_ENA0 The PHY uses the squelch threshold levels prescribed by the IEEE 10BASE-T specification1 In this mode the squelch levels are decreased which may improve the bit error rate performance on long loops2 In this mode the squelch levels are increased which may improve the bit error rate in high-noise environments3 Reserved

STICKY_RESET_ENA 9 RW When set all fields described as sticky retain their value during software reset When cleared all fields marked as sticky are reset to their default values during software reset This does not affect hardware resets This is a super-sticky field which means that it always retain its value during software reset

EOF_ERR 8 RO When set this field indicates that a defective EOF (End Of Frame) sequence was received since the last time this field was read This field is cleared on read

LINK_10BT_DISCONNECT 7 RO When set this field indicates that the carrier integrity monitor has broken the 10BASE-T connection since the last read of this bit This field is cleared on read

LINK_10BT_STAT 6 RO This field is set when a 10BASE-T link is active Cleared when inactive

BROADCAST_WRITE_ENA 0 RW Enable any MII write operation (regardless of destination PHY) to be interpreted as a write to this PHY This only applies to writes read-operations are still interpreted with correct address This is particularly useful when similar settings should be propagated to multiple PHYs This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

Table 668 bull Fields in PHY_CTRL_STAT_EXT (continued)

Registers

219122 PHYPHY_STDPHY_CTRL_EXT1Parent PHYPHY_STD

Instances 1

Table 669 bull Fields in PHY_CTRL_EXT1

Field Name Bit Access Description DefaultFAR_END_LOOPBACK_ENA 3 RW Enable far end loopback in this PHY In this

mode all incoming traffic on the media interface is retransmitted back to the link partner In addition the incoming data also appears on the internal Rx interface to the MAC Any data send to the PHY from the internal MAC is ignored when this mode is active

Field Name Bit Access Description DefaultEDGE_RATE_CFG 1513 RW Control the transmit DAC slew rate in

100BASE-TX mode only The difference between each setting is approximately 200ps to 300ps with the +3 setting resulting in the slowest edge rate and the -4 setting resulting in the fastest edge rate This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA011 +5 Edge rate (slowest)010 +4 Edge rate001 +3 Edge rate000 +2 Edge rate111 +1 Edge rate110 Nominal edge rate101 -1 Edge rate100 -2 Edge rate (fastest)

Registers

219124 PHYPHY_STDPHY_INT_MASKParent PHYPHY_STD

Instances 1

PICMG_REDUCED_POWER_ENA

12 RW Enable PICMC reduce power mode In this mode portions of the DSP processor are turned off which reduces the PHYs operating power The DSP performance characteristics in this mode are configured to support the channel characteristics specified in the PICMC 216 and PICMC 30 specifications The application of this mode is in environments that have a high signal to noise ratio on the media For example Ethernet over backplane or where cable length is short (less than 10m) When this field is cleared the PHY operates in normal DSP mode This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

JUMBO_PKT_ENA 54 RW Controls the symbol buffering for the receive synchronization FIFO used in 1000BASE-T mode Other encodings are reserved and must not be selected This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENANote When set the default maximum packet values are based on 100 ppm driven reference clock to the device Controlling the ppm offset between the MAC and the PHY as specified in the field encoding description results in a higher jumbo packet length00 Normal IEEE 1518-byte packet length01 9-kilobyte jumbo packet length (12 kilobytes with 60 ppm or better reference clock)10 12-kilobyte jumbo packet length (16 kilobytes with 70 ppm or better reference clock)11 Reserved

CON_LOOPBACK_1000BT_ENA 0 RW Set PHY into 1000BASE-T connector loopback mode When enabled the PHY only works with a connector loopback

Table 670 bull Fields in PHY_CTRL_EXT2 (continued)

Registers

Table 671 bull Fields in PHY_INT_MASK

Field Name Bit Access Description DefaultPHY_INT_ENA 15 RW Enable global PHY interrupt This is a sticky

field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

SPEED_STATE_CHANGE_INT_ENA

14 RW Set to unmask speed change interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

LINK_STATE_CHANGE_INT_ENA 13 RW Set to unmask link stateenergy detected change interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

FDX_STATE_CHANGE_INT_ENA 12 RW Set to unmask FDX change interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

AUTONEG_ERR_INT_ENA 11 RW Set to unmask auto-negotiation error interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

AUTONEG_DONE_INT_ENA 10 RW Set to unmask auto-negotiation-doneinterlock done interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

INLINE_POW_DET_INT_ENA 9 RW Set to unmask In-line Powered Device Detected interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

SYMBOL_ERR_INT_ENA 8 RW Set to unmask Symbol Error interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

FAST_LINK_FAIL_INT_ENA 7 RW Set to unmask fast link failure interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

WOL_INT_ENA 6 RW Set to unmask Wake-On-Lan interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

EXTENDED_INT_ENA 5 RW Set to unmask EXTENDED interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

Reserve 4 RW Reserved 0x0

Registers

219125 PHYPHY_STDPHY_INT_STATParent PHYPHY_STD

Instances 1

FALSE_CARRIER_INT_ENA 3 RW Set to unmask False Carrier interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

LINK_SPEED_DOWNSHIFT_INT_ENA

2 RW Set to unmask link speed downshift interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

MASTER_SLAVE_INT_ENA 1 RW Set to unmask masterslave interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

RX_ER_INT_ENA 0 RW Set to unmask RX_ER interrupt This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

Table 672 bull Fields in PHY_INT_STAT

Field Name Bit Access Description DefaultPHY_INT_PEND 15 RO Set when an unacknowledged global PHY

interrupt is pending the cause of the interrupt can be determined by examining the other fields of this register This field is set no matter the state of PHY_INT_MASKPHY_INT_ENA This field is self-clearing ie interrupt is acknowledged on read

SPEED_STATE_CHANGE_INT_PEND

14 RO Set when a speed interrupt is pending this is activated when the operating speed of the PHY changes (requires that auto-negotiation is enabled see PHY_CTRLAUTONEG_ENA) This field is self-clearing ie interrupt is acknowledged on read

LINK_STATE_CHANGE_INT_PEND

13 RO Set when a Link StateEnergy Detected interrupt is pending This interrupt occurs when the link status of the PHY changes or if ActiPHY mode is enabled and energy is detected on the media (see PHY_AUX_CTRL_STATACTIPHY_ENA) This field is self-clearing ie interrupt is acknowledged on read

Table 671 bull Fields in PHY_INT_MASK (continued)

Registers

FDX_STATE_CHANGE_INT_PEND

12 RO Set when an FDX interrupt is pending FDX interrupt is caused when the FDXHDX state of the PHY changes (requires that auto-negotiation is enabled see PHY_CTRLAUTONEG_ENA) This field is self-clearing ie interrupt is acknowledged on read

AUTONEG_ERR_INT_PEND 11 RO Set when an auto-negotiation Error interrupt is pending this is caused when an error is detected by the auto-negotiation state machine This field is self-clearing ie interrupt is acknowledged on read

AUTONEG_DONE_INT_PEND 10 RO Set when an auto-negotiation-DoneInterlock Done interrupt is pending this is caused when the Auto-negotiation finishes a negotiation process This field is self-clearing ie interrupt is acknowledged on read

INLINE_POW_DET_INT_PEND 9 RO Set when an In-line Powered Device Detected interrupt is pending This interrupt is caused when a device requiring in-line power is detected (requires that detection is enabled see PHY_CTRL_EXT4INLINE_DETECT_ENA) This field is self-clearing ie interrupt is acknowledged on read

SYMBOL_ERR_INT_PEND 8 RO Set when a Symbol Error interrupt is pending this is caused by detection of a symbol error by the descrambler This field is self-clearing ie interrupt is acknowledged on read

FAST_LINK_FAIL_INT_PEND 7 RO Set when a fast link failure interrupt is pending This field is self-clearing ie interrupt is acknowledged on read

WOL_INT_PEND 6 RO Set when a Wake-On-Lan interrupt is pending This field is self-clearing ie interrupt is acknowledged on read

EXTENDED_INT_PEND 4 RO Set when an Extended interrupt is pending This field is self-clearing ie interrupt is acknowledged on read

FALSE_CARRIER_INT_PEND 3 RO Set when a False Carrier interrupt is pending False Carrier interrupt is generated when the PHY detects a false carrier This field is self-clearing ie interrupt is acknowledged on read

LINK_SPEED_DOWNSHIFT_INT_PEND

2 RO Set when a link speed downshift interrupt is pending This field is self-clearing ie interrupt is acknowledged on read

Table 672 bull Fields in PHY_INT_STAT (continued)

Registers

219126 PHYPHY_STDPHY_AUX_CTRL_STATParent PHYPHY_STD

Instances 1

Copied fields have the same default values as their source fields

MASTER_SLAVE_ERR_INT_PEND

1 RO Set when a masterslave interrupt is pending This interrupt is set when a masterslave resolution error us detected This field is self-clearing ie interrupt is acknowledged on read

RX_ER_INT_PEND 0 RO Set when a RX_ER interrupt is pending This interrupt is set when an RX_ER condition occurs This field is self-clearing ie interrupt is acknowledged on read

Table 673 bull Fields in PHY_AUX_CTRL_STAT

Field Name Bit Access Description DefaultAUTONEG_COMPLETE_AUX 15 RO A read-only copy of

PHY_STATAUTONEG_COMPLETE Repeated here for convenience See note for this register

AUTONEG_STAT 14 RO When set the auto-negotiation function has been disabled (in PHY_CTRLAUTONEG_ENA)

NO_MDI_X_IND 13 RO When this field is set the auto-negotiation state machine has determined that crossover does not exist in the signal path This field is only valid after descrambler lock has been achieved (see PHY_STAT_1000BT_EXTDESCRAM_LOCKED) and automatic pair swap correction is enabled (see PHY_BYPASS_CTRLPAIR_SWAP_DISABLE)

CD_PAIR_SWAP 12 RO When this field is set the PHY has determined that the subchannel cable pairs C and D were swapped between the far-end transmitter and the receiver In this case the PHY corrects this internally This field is only valid when auto-negotiation is complete (see AUTONEG_COMPLETE)

Registers

A_POL_INVERSION 11 RO When set this field indicates that the polarity of pair A was inverted between the far-end transmitter and the receiver In this case the PHY corrects this internally This field is only valid when auto-negotiation is complete (see AUTONEG_COMPLETE)0 Polarity is swapped on pair A1 Polarity is not swapped on pair A

B_POL_INVERSION 10 RO When set this field indicates that the polarity of pair B was inverted between the far-end transmitter and the receiver In this case the PHY corrects this internally This field is only valid when auto-negotiation is complete (see AUTONEG_COMPLETE)0 Polarity is swapped on pair B1 Polarity is not swapped on pair B

C_POL_INVERSION 9 RO When set this field indicates that the polarity of pair C was inverted between the far-end transmitter and the receiver In this case the PHY corrects this internally This field is only valid when auto-negotiation is complete (see AUTONEG_COMPLETE) and in 1000BASE-T mode0 Polarity is swapped on pair C1 Polarity is not swapped on pair C

D_POL_INVERSION 8 RO When set this field indicates that the polarity of pair D was inverted between the far-end transmitter and the receiver In this case the PHY corrects this internally This field is only valid when auto-negotiation is complete (see AUTONEG_COMPLETE) and in 1000BASE-T mode0 Polarity is swapped on pair D1 Polarity is not swapped on pair D

ACTIPHY_LINK_TIMER_MSB_CFG

7 RW Most significant bit of the link status time-out timer Together with ACTIPHY_LINK_TIMER_LSB_CFG this field determines the duration from losing the link to the ActiPHY enters low power state0 1 seconds1 2 seconds2 3 seconds3 4 seconds

ACTIPHY_ENA 6 RW Enable ActiPHY power management mode This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

FDX_STAT 5 RO This field indicates the actual FDXHDX operating mode of the PHY0 Half-duplex1 Full-duplex

Table 673 bull Fields in PHY_AUX_CTRL_STAT (continued)

Registers

219127 PHYPHY_STDPHY_LED_MODE_SELParent PHYPHY_STD

Instances 1

219128 PHYPHY_STDPHY_LED_BEHAVIOR_CTRLParent PHYPHY_STD

Instances 1

SPEED_STAT 43 RO This field indicates the actual operating speed of the PHY0 Speed is 10BASE-T1 Speed is 100BASE-TX2 Speed is 1000-BASE-T3 Reserved

ACTIPHY_LINK_TIMER_LSB_CFG

2 RW See ACTIPHY_LINK_TIMER_MSB_CFG 0x1

Table 674 bull Fields in PHY_LED_MODE_SEL

LED1_MODE_SEL 74 RW Select from LED modes 0 through 15 This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

LED0_MODE_SEL 30 RW Select from LED modes 0 through 15 This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA0 LinkActivity1 Link1000Activity2 Link100Activity3 Link10Activity4 Link1001000Activity5 Link101000Activity6 Link10100Activity7 Reserved8 DuplexCollision9 Collision10 Activity11 Reserved12 Auto-Negotiation Fault13 Reserved14 Force LED Off15 Force LED On

Registers

219129 PHYPHY_STDPHY_MEMORY_PAGE_ACCESSParent PHYPHY_STD

Table 675 bull Fields in PHY_LED_BEHAVIOR_CTRL

Field Name Bit Access Description DefaultPULSING_ENA 12 RW Enable LED pulsing with programmable duty

cycle The duty cycle is programmed in PHY_GPPHY_ENHANCED_LED_CTRLLED_PULSE_DUTY This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA0 Normal operation1 LEDs pulse with a 5 kHz programmable duty cycle when active

BLINK_RATE_CFG 1110 RW Configure blink rate of LEDs when applicable If pulse stretching has been selected rather than blink this controls the stretch-period rather than frequency This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA00 25 Hz blink rate400 ms pulse-stretch01 5 Hz blink rate200 ms pulse-stretch10 10 Hz blink rate100 ms pulse-stretch11 20 Hz blink rate50 ms pulse-stretch The blink rate selection for PHY0 globally sets the rate used for all LED pins on all PHY ports

LED1_PULSE_STRETCH_ENA 6 RW Enable pulse-stretch behavior instead of blinking for LED1 This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

LED1_COMBINE_DIS 1 RW Disabling of the LED1 combine feature This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA0 Combine enabled (linkactivity duplexcollision)1 Disable combination (link only duplex only)

Registers

Instances 1

2192 PHYPHY_EXT1Parent PHY

Instances 1

Set register 0x1F to 0x0001 to make the extended set of registers visible in the address range 0x10 through 0x1E Set register 0x1F to 0x0000 to revert back to the standard register set

Table 676 bull Fields in PHY_MEMORY_PAGE_ACCESS

Field Name Bit Access Description DefaultPAGE_ACCESS_CFG 40 RW This bit controls the mapping of PHY

registers 0x10 through 0x1E When changing pages all registers in the range 0x10 through 0x1E are replaced - even if the new memory-page does not define all addresses in the range 0x10 through 0x1E0 Register Page 0 is mapped (standard set)1 Register Page 1 is mapped (extended set 1)2 Register Page 2 is mapped (extended set 2)16 Register Page 16 is mapped (general purpose)

Table 677 bull Registers in PHY_EXT1

PHY_CRC_GOOD_CNT 0x00000048 1 CRC Good Counter (Address 18E1)

PHY_EXT_MODE_CTRL 0x0000004C 1 Extended Mode Control (Address 19E1)

PHY_CTRL_EXT3 0x00000050 1 Extended Control Number 3 (Address 20E1)

PHY_CTRL_EXT4 0x0000005C 1 Extended Control Number 4 (Address 23E1)

PHY_VERIPHY_CTRL1 0x00000060 1 VeriPHY Control Number 1 (Address 24E1)

PHY_1000BT_EPG1 0x00000074 1 1000BASE-T Ethernet Packet Generator Number 1 (Address 29E1)

Registers

21921 PHYPHY_EXT1PHY_CRC_GOOD_CNTParent PHYPHY_EXT1

Instances 1

21922 PHYPHY_EXT1PHY_EXT_MODE_CTRLParent PHYPHY_EXT1

Instances 1

Table 678 bull Fields in PHY_CRC_GOOD_CNT

Field Name Bit Access Description DefaultPACKET_SINCE_LAST_READ 15 RO Packet received since last read This is a

self-clearing bit0x0

CRC_GOOD_PKT_CNT 130 RO Counter containing the number of packets with valid CRCs this counter does not saturate and rolls over This is a self-clearing field

0x0000

Table 679 bull Fields in PHY_EXT_MODE_CTRL

Field Name Bit Access Description DefaultLED1_EXT_MODE_ENA 13 RW Enable extended LED mode for LED1 For

available LED modes see LED0_EXT_MODE_ENA

LED0_EXT_MODE_ENA 12 RW Enable extended LED mode for LED0 If set the available LED modes selected in PHY_LED_MODE_SELLED0_MODE_SEL are0-3 Reserved4 Force LED Off5 Force LED On LED pulsing is disabled in this mode6 Fast Link Fail 7-15 Reserved

LED_BLINK_SUPPRESS 11 RW Suppress LED blink after reset0 Suppress LED blink after COMA_MODE is deasserted1 Blink LEDs after COMA_MODE is deasserted

Table 677 bull Registers in PHY_EXT1 (continued)

Registers

21923 PHYPHY_EXT1PHY_CTRL_EXT3Parent PHYPHY_EXT1

Instances 1

FORCE_MDI_CROSSOVER_ENA 32 RW Force MDI crossover00 Normal HP Auto-MDIX operation01 Reserved10 Copper media forced to MDI11 Copper media forced MDI-X

Field Name Bit Access Description DefaultRESERVED 15 RO Must be set to its default 0x1

ACTIPHY_SLEEP_TIMER 1413 RW This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA00 1 second01 2 seconds10 3 seconds11 4 seconds

ACTIPHY_WAKEUP_TIMER 1211 RW This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA00 160 ms01 400 ms10 800 ms11 2 seconds

NO_PREAMBLE_10BT_ENA 5 RW If set 10BASE-T asserts RX_DV indication when data is presented to the receiver even without a preamble preceding itThis is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

SPEED_DOWNSHIFT_ENA 4 RW Enables automatic downshift the auto-negotiation advertisement to the next lower available speed after the number of failed 1000BASE-T auto-negotiation attempts specified in SPEED_DOWNSHIFT_CFG This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

Table 679 bull Fields in PHY_EXT_MODE_CTRL (continued)

Registers

Instances 1

The reset value of the address fields (PHY_ADDR) corresponds to the PHY in which it resides

SPEED_DOWNSHIFT_CFG 32 RW Configures the number of unsuccessful 1000BASE-T auto-negotiation attempts that are required before the auto-negotiation advertisement is downshifted to the next lower available speed This field applies only if automatic downshift of speed is enabled (see SPEED_DOWNSHIFT_ENA) This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA00 Downshift after 2 failed attempts01 Downshift after 3 failed attempts10 Downshift after 4 failed attempts11 Downshift after 5 failed attempts

SPEED_DOWNSHIFT_STAT 1 RO This status field indicates that a downshift is required in order for link to be established If automatic downshifting is enabled (see SPEED_DOWNSHIFT_ENA) the current link speed is a result of a downshift

Field Name Bit Access Description DefaultPHY_ADDR 1511 RO This field contains the PHY address of the

current PHY port0x00

INLINE_POW_DET_ENA 10 RW Enables detection of inline powered device as part of the auto-negotiation process This is a sticky field see PHY_CTRL_STAT_EXTSTICKY_RESET_ENA

INLINE_POW_DET_STAT 98 RO This field shows the status if a device is connected to the PHY that requires inline power This field is only valid if inline powered device detection is enabled (see INLINE_POW_DET_ENA)00 Searching for devices01 Device found that requires inline power10 Device found that does not require inline power11 Reserved

CRC_1000BT_CNT 70 RO This field indicates how many packets are received that contain a CRC error This field is cleared on read and saturates at all ones

Registers

21925 PHYPHY_EXT1PHY_VERIPHY_CTRL1Parent PHYPHY_EXT1

Instances 1

Table 682 bull Fields in PHY_VERIPHY_CTRL1

Field Name Bit Access Description DefaultVERIPHY_TRIGGER 15 RW Set to trigger a VeriPHY operation This field

is cleared by hardware when acknowledged0x0

VERIPHY_RES_VALID 14 RO This field indicates whether VeriPHY results are valid

PAIR_A_DIST 138 RO Loop length or distance to anomaly for pair A (1 2) Resolution is 3 meters

PAIR_B_DIST 50 RO Loop length or distance to anomaly for pair B (3 6) Resolution is 3 meters

Field Name Bit Access Description DefaultPAIR_C_DIST 138 RO Loop length or distance to anomaly for pair C

(4 5) Resolution is 3 meters0x00

PAIR_D_DIST 50 RO Loop length or distance to anomaly for pair D (7 8) Resolution is 3 meters

Field Name Bit Access Description DefaultPAIR_A_TERMINATION_STAT 1512 RO Termination fault for pair A (1 2) See

PAIR_D_TERMINATION_STAT for encoding0x0

PAIR_B_TERMINATION_STAT 118 RO Termination fault for pair B (3 6) See PAIR_D_TERMINATION_STAT for encoding

PAIR_C_TERMINATION_STAT 74 RO Termination fault for pair C (4 5) See PAIR_D_TERMINATION_STAT for encoding

Registers

21928 PHYPHY_EXT1PHY_1000BT_EPG1Parent PHYPHY_EXT1

Instances 1

PAIR_D_TERMINATION_STAT 30 RO Termination fault for pair D (7 8)0000 Correctly terminated pair0001 Open pair0010 Shorted pair0100 Abnormal termination1000 Cross-pair short to pair A1001 Cross-pair short to pair B1010 Cross-pair short to pair C1011 Cross-pair short to pair D

Table 685 bull Fields in PHY_1000BT_EPG1

Field Name Bit Access Description DefaultEPG_ENA 15 RW Enables the Ethernet packet generator

When this field is set the EPG is selected as the driving source for the PHY transmit signals and the MAC transmit pins are disabled

EPG_RUN_ENA 14 RW Begin transmission of Ethernet packets Clear to stop the transmission of packets If a transmission is in progress the transmission of packets is stopped after the current packet is transmitted This field is valid only when the EPG is enabled (see EPG_ENA)

TRANSMIT_DURATION_CFG 13 RW Configure the duration of the packet generation When set the EPG continuously transmits packets as long as field EPG_RUN_ENA is set When cleared the EPG transmits 30000000 packets when field EPG_RUN_ENA is set after which time field EPG_RUN_ENA is automatically cleared This field is latched when packet generation begins by setting EPG_RUN_ENA in this register

PACKET_LEN_CFG 1211 RW This field selects the length of packets to be generated by the EPG This field is latched when generation of packets begins by setting EPG_RUN_ENA in this register00 125-byte packets01 64-byte packets10 1518-byte packets11 10000-byte packets

Table 684 bull Fields in PHY_VERIPHY_CTRL3 (continued)

Registers

Instances 1

INTER_PACKET_GAB_CFG 10 RW This field configures the inter packet gab for packets generated by the EPG This field is latched when generation of packets begins by setting EPG_RUN_ENA in this register0 96 ns inter-packet gap1 9192 ns inter-packet gap

DEST_ADDR_CFG 96 RW This field configures the low nibble of the most significant byte of the destination MAC address The rest of the destination MAC address is all-ones For example setting this field to 0x2 results in packets generated with a destination MAC address of 0xF2FFFFFFFFFF This field is latched when generation of packets begins by setting EPG_RUN_ENA in this register

SRC_ADDR_CFG 52 RW This field configures the low nibble of the most significant byte of the source MAC address The rest of the source MAC address is all-ones For example setting this field to 0xE results in packets generated with a source MAC address of 0xFEFFFFFFFFFF This field is latched when generation of packets begins by setting EPG_RUN_ENA in this register

PAYLOAD_TYPE 1 RW Payload type0 Fixed based on payload pattern1 Randomly generated payload pattern

BAD_FCS_ENA 0 RW When this field is set the EPG generates packets containing an invalid Frame Check Sequence (FCS) When cleared the EPG generates packets with a valid FCS This field is latched when generation of packets begins by setting EPG_RUN_ENA in this register

Field Name Bit Access Description DefaultPACKET_PAYLOAD_CFG 150 RW Each packet generated by the EPG contains

a repeating sequence of this field as payload This field is latched when generation of packets begins by setting PHY_1000BT_EPG1EPG_RUN_ENA

0x0000

Table 685 bull Fields in PHY_1000BT_EPG1 (continued)

Registers

Instances 1

21931 PHYPHY_EXT2PHY_PMD_TX_CTRLParent PHYPHY_EXT2

Instances 1

This register consists of the bits that provide control over the amplitude settings for the transmit side Cu PMD interface These bits provide the ability to make small adjustments in the signal amplitude to compensate for minor variations in the magnetic from different vendors Extreme caution must be exercised when changing these settings from the default values as they have a direct impact on the signal quality Changing these settings also affects the linearity and harmonic distortion of the transmitted signals Please contact the Vitesse Applications Support team for further help with changing these values

PHY_PMD_TX_CTRL 0x00000040 1 Cu PMD Transmit Control (Address 16E2)

PHY_EEE_CTRL 0x00000044 1 EEE and LED Control (Address 17E2)

PHY_WOL_MAC_ADDR0 0x00000048 1 Wake-On-LAN MAC address [150]

PHY_WOL_MAC_ADDR1 0x0000004C 1 Wake-On-LAN MAC address [3116]

PHY_SECURE_ON_PASSWD0 0x00000054 1 Secure-On password [150] Page 334

PHY_SECURE_ON_PASSWD2 0x0000005C 1 Secure-On password [4732] Page 334

PHY_WOL_MDINT_CTRL 0x00000060 1 Page 335

PHY_EXT_INT_MASK 0x00000064 1 Extended Interrupt mask Page 335

PHY_EXT_INT_STAT 0x00000068 1 Extended Interrupt Status Page 335

Table 688 bull Fields in PHY_PMD_TX_CTRL

Field Name Bit Access Description DefaultSIG_AMPL_1000BT 1512 RW 1000BT signal amplitude trim 0x0

SIG_AMPL_100BTX 118 RW 100BASE-TX signal amplitude trim 0x0

SIG_AMPL_10BT 74 RW 10BASE-T signal amplitude trim 0x5

SIG_AMPL_10BTE 30 RW 10BASE-Te signal amplitude trim 0x0

Registers

21932 PHYPHY_EXT2PHY_EEE_CTRLParent PHYPHY_EXT2

Instances 1

21933 PHYPHY_EXT2PHY_WOL_MAC_ADDR0Parent PHYPHY_EXT2

Instances 1

Wake-On-LAN MAC address [150]

Instances 1

Table 689 bull Fields in PHY_EEE_CTRL

Field Name Bit Access Description DefaultEEE_10BTE_ENA 15 RW Enable energy efficient (IEEE 8023az)

10BASE-Te operating mode0x0

FORCE_1000BT_ENA 5 RW Enable 1000BT force mode to allow PHY to link up in 1000BT mode without forcing masterslave when PHY_STDPHY_CTRLSPEED_SEL_LSB_CFG=0 and PHY_STDPHY_CTRLSPEED_SEL_MSB_CFG=1

FORCE_LPI_TX_ENA 4 RW Force transmit LPI0 Transmit idles being received from the MAC1 Enable the EPG to transmit LPI on the MDI instead of normal idles when receiving normal idles from the MAC

EEE_LPI_TX_100BTX_DIS 3 RW Disable transmission of EEE LPI on transmit path MDI in 100BASE-TX mode when receiving LPI from MAC

EEE_LPI_RX_100BTX_DIS 2 RW Disable transmission of EEE LPI on receive path MAC interface in 100BASE-TX mode when receiving LPI from the MDI

EEE_LPI_TX_1000BT_DIS 1 RW Disable transmission of EEE LPI on transmit path MDI in 1000BT mode when receiving LPI from MAC

EEE_LPI_RX_1000BT_DIS 0 RW Disable transmission of EEE LPI on receive path MAC interface in 1000BT mode when receiving LPI from the MDI

Table 690 bull Fields in PHY_WOL_MAC_ADDR0

Field Name Bit Access Description DefaultWOL_MAC_ADDR0 150 RW Wake-On-LAN MAC address bits [150] 0x0000

Registers

Instances 1

21936 PHYPHY_EXT2PHY_SECURE_ON_PASSWD0Parent PHYPHY_EXT2

Instances 1

Secure-On password [150]

Instances 1

Table 693 bull Fields in PHY_SECURE_ON_PASSWD0

Field Name Bit Access Description DefaultSECURE_ON_PASSWD0 150 RW Secure-On password for Wake-on-LAN bits

[150]0x0000

[3116]0x0000

Registers

21939 PHYPHY_EXT2PHY_WOL_MDINT_CTRLParent PHYPHY_EXT2

Instances 1

219310 PHYPHY_EXT2PHY_EXT_INT_MASKParent PHYPHY_EXT2

Instances 1

Extended Interrupt mask

219311 PHYPHY_EXT2PHY_EXT_INT_STATParent PHYPHY_EXT2

Instances 1

[4732]0x0000

Table 696 bull Fields in PHY_WOL_MDINT_CTRL

Field Name Bit Access Description DefaultSEC_ON_ENA 13 RW Secure-On enable 0x0

SEC_ON_PWD_LEN 12 RW Secure-On password length 0 6 byte password 1 4 byte password

MAGIC_PKT_ADD_REP_CNT 118 RW Address repetition count in the Magic packet 0x0 =1 0xF=16

MDINT_CTRL 1 RW MDINT signal control 0 Interrupt signal from both ports are combined and then driven onto both MDINT pins 1 Interrupt signals from Port 0 are indicated on MDINT_0 and interrupt signals from Port 1 are indicated on MDINT_1

Table 697 bull Fields in PHY_EXT_INT_MASK

Field Name Bit Access Description DefaultRX_FIFO_ERR_INT_ENA 13 RW Rx FIFO overflowunderflow interrupt mask 0x0

TX_FIFO_ERR_INT_ENA 12 RW Tx FIFO overflowunderflow interrupt mask 0x0

RR_SWC_COMPLETE_INT_ENA 4 RW RR switch over complete interrupt mask 0x0

EEE_LINK_FAIL_INT_ENA 3 RW EEE link fail interrupt mask 0x0

EEE_RX_TQ_INT_ENA 2 RW EEE Rx TQ timer interrupt mask 0x0

EEE_WAIT_TS_INT_ENA 1 RW EEE wait quietRx TS timer interrupt mask 0x0

EEE_WAKE_ERR_INT_ENA 0 RW EEE wake error interrupt mask 0x0

Registers

Extended Interrupt Status

2194 PHYPHY_GPParent PHY

Instances 1

Set register 0x1F to 0x0010 to access the general purpose registers This sets all 32 registers to the general purpose register space Set register 0x1F to 0x0000 to revert back to the standard register set

21941 PHYPHY_GPPHY_COMA_MODE_CTRLParent PHYPHY_GP

Instances 1

Table 698 bull Fields in PHY_EXT_INT_STAT

Field Name Bit Access Description DefaultRX_FIFO_ERR_INT_STAT 13 RO 0x0

TX_FIFO_ERR_INT_STAT 12 RO Tx FIFO overflowunderflow interrupt status 0x0

EEE_LINK_FAIL_INT_STAT 3 RO EEE link fail interrupt status 0x0

EEE_RX_TQ_INT_STAT 2 RO EEE Rx TQ timer interrupt status 0x0

EEE_WAIT_TS_INT_STAT 1 RO EEE wait quietRx TS timer interrupt status 0x0

EEE_WAKE_ERR_INT_STAT 0 RW EEE wake error interrupt mask 0x0

Table 699 bull Registers in PHY_GP

PHY_COMA_MODE_CTRL 0x00000038 1 Coma Mode Control (Address 14G)

PHY_RCVD_CLK0_CTRL 0x0000005C 1 Recovered Clock 0 Control (Address 23G)

PHY_RCVD_CLK1_CTRL 0x00000060 1 Recovered Clock 1 Control (Address 24G)

PHY_ENHANCED_LED_CTRL 0x00000064 1 Enhanced LED Control (Address 25G)

PHY_GLOBAL_INT_STAT 0x00000074 1 Global Interrupt Status (Address 29G)

Table 700 bull Fields in PHY_COMA_MODE_CTRL

Field Name Bit Access Description DefaultCOMA_MODE_OE 13 RW COMA_MODE output enable Active low

0 COMA_MODE pin is an output1 COMA_MODE pin is an input

COMA_MODE_OUTPUT 12 RW COMA_MODE output data 0x0

Registers

21942 PHYPHY_GPPHY_RCVD_CLK0_CTRLParent PHYPHY_GP

Instances 1

COMA_MODE_INPUT 11 RO COMA_MODE input data 0x0

LED_TRISTATE_ENA 9 RW Tri-state enable for LEDs0 Drive LED bus output signals to high and low values as appropriate1 Tri-state LED output signals instead of driving them high This allows those signals to be pulled above VDDIO using an external pull-up resistor

Table 701 bull Fields in PHY_RCVD_CLK0_CTRL

Field Name Bit Access Description DefaultRCVD_CLK0_ENA 15 RW Enable RCVRD_CLK[0] 0x0

CLK_SRC_SEL0 1411 RW Clock source select0000 PHY00001 PHY10010 PHY20011 PHY30100 PHY40101 PHY50110 PHY60111 PHY71000 PHY81001 PHY91010 PHY101011 PHY111100-1111 Reserved

CLK_FREQ_SEL0 108 RW Clock frequency select 000 25 MHz output clock001 125 MHz output clock010 3125 MHz output clock011-111 Reserved

Table 700 bull Fields in PHY_COMA_MODE_CTRL (continued)

Registers

Instances 1

CLK_SQUELCH_LVL0 54 RW Select clock squelch level Note that a clock from the Cu PHY will be output on the recovered clock output in this mode when the link is down00 Automatically squelch clock to low when the link is not up is unstable is up in a mode that does not support the generation of a recovered clock (1000BASE-T master or 10BASE-T) or is up in EEE mode (100BASE-TX or 1000BASE-T slave) 01 Same as 00 except that the clock is also generated in 1000BASE-T master and 10BASE-T link-up modes This mode also generates a recovered clock output in EEE mode during reception of LP_IDLE10 Squelch only when the link is not up11 Disable clock squelch

CLK_SEL_PHY0 20 RW Clock selection for specified PHY000 Reserved001 Copper PHY recovered clock010 Copper PHY transmitter TCLK011-111 Reserved

Table 701 bull Fields in PHY_RCVD_CLK0_CTRL (continued)

Registers

21944 PHYPHY_GPPHY_ENHANCED_LED_CTRLParent PHYPHY_GP

Instances 1

21945 PHYPHY_GPPHY_GLOBAL_INT_STATParent PHYPHY_GP

Instances 1

Table 703 bull Fields in PHY_ENHANCED_LED_CTRL

Field Name Bit Access Description DefaultLED_PULSE_DUTY 158 RW LED pulsing duty cycle control

Programmable control for LED pulsing duty cycle when PHY_STDPHY_LED_BEHAVIOR_CTRLPULSING_ENA is set to 1 Valid settings are between 0 and 198 A setting of 0 corresponds to a 05 duty cycle and 198 corresponds to a 995 duty cycle Intermediate values change the duty cycle in 05 increments

Registers

Table 704 bull Fields in PHY_GLOBAL_INT_STAT

PHY11_INT_SRC 11 RO Indicates that PHY11 is the source of the interrupt when this bit is cleared This bit is set high when reading register PHY_INT_STAT in PHY11

Registers

2195 PHYPHY_EEEParent PHY

Instances 1

Access to these registers is through the IEEE standard registers MMD_ACCESS_CFG and MMD_ADDR_DATA

21951 PHYPHY_EEEPHY_PCS_STATUS1Parent PHYPHY_EEE

Instances 1

Status of the EEE operation from the PCS for the link that is currently active

Table 705 bull Registers in PHY_EEE

PHY_PCS_STATUS1 0x00000000 1 PCS Status 1 (Address 31) Page 341

PHY_EEE_CAPABILITIES 0x00000004 1 EEE Capabilities (Address 320)

PHY_EEE_WAKE_ERR_CNT 0x00000008 1 EEE Wake Error Counter (Address 322)

PHY_EEE_ADVERTISEMENT 0x0000000C 1 EEE Advertisement (Address 760)

PHY_EEE_LP_ADVERTISEMENT 0x00000010 1 EEE Link Partner Advertisement (Address 761)

Table 706 bull Fields in PHY_PCS_STATUS1

Field Name Bit Access Description DefaultTX_LPI_RECV 11 RO

0 LPI not received1 Tx PCS has received LPI

RX_LPI_RECV 10 RO1 Rx PCS has received LPI0 LPI not received

TX_LPI_INDICATION 9 RO1 Tx PCS is currently receiving LPI0 PCS is not currently receiving LPI

Table 704 bull Fields in PHY_GLOBAL_INT_STAT (continued)

Registers

21952 PHYPHY_EEEPHY_EEE_CAPABILITIESParent PHYPHY_EEE

Instances 1

Indicate the capability of the PCS to support EEE functions for each PHY type

21953 PHYPHY_EEEPHY_EEE_WAKE_ERR_CNTParent PHYPHY_EEE

Instances 1

This register is used by PHY types that support EEE to count wake time faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type The definition of the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as defined by the PHY This 16-bit counter is reset to all zeros when the EEE wake error counter is read or when the PHY undergoes hardware or software reset

21954 PHYPHY_EEEPHY_EEE_ADVERTISEMENTParent PHYPHY_EEE

Instances 1

Defines the EEE advertisement that is sent in the unformatted next page following a EEE technology message code

RX_LPI_INDICATION 8 RO1 Rx PCS is currently receiving LPI0 PCS is not currently receiving LPI

PCS_RECV_LINK_STAT 2 RO1 PCS receive link up0 PCS receive link down

Table 707 bull Fields in PHY_EEE_CAPABILITIES

Field Name Bit Access Description DefaultEEE_1000BT 2 RO Set if EEE is supported for 1000BASE-T

1 EEE is supported for 1000BASE-T0 EEE is not supported for 1000BASE-T

EEE_100BTX 1 RO Set if EEE is supported for 100BASE-TX1 EEE is supported for 100BASE-TX0 EEE is not supported for 100BASE-TX

Table 708 bull Fields in PHY_EEE_WAKE_ERR_CNT

Field Name Bit Access Description DefaultEEE_WAKE_ERR_CNT 150 RO Count of wake time faults for a PHY 0x0000

Table 706 bull Fields in PHY_PCS_STATUS1 (continued)

Registers

21955 PHYPHY_EEEPHY_EEE_LP_ADVERTISEMENTParent PHYPHY_EEE

Instances 1

All the bits in the EEE LP Advertisement register are read only A write to the EEE LP advertisement register has no effect When the AN process has been completed this register will reflect the contents of the link partners EEE advertisement register

Table 709 bull Fields in PHY_EEE_ADVERTISEMENT

Field Name Bit Access Description DefaultEEE_1000BT_ADV 2 RW Set if EEE is supported for 1000BASE-T

1 Advertise that the 1000BASE-T has EEE capability0 Do not advertise that the 1000BASE-T has EEE capability

EEE_100BTX_ADV 1 RW Set if EEE is supported for 100BASE-TX1 Advertise that the 100BASE-TX has EEE capability0 Do not advertise that the 100BASE-TX has EEE capability

Table 710 bull Fields in PHY_EEE_LP_ADVERTISEMENT

Field Name Bit Access Description DefaultEEE_1000BT_LP_ADV 2 RO Set if EEE is supported for 1000BASE-T by

link partner1 Link partner is advertising EEE capability for 1000BASE-T0 Link partner is not advertising EEE capability for 1000BASE-T

EEE_100BTX_LP_ADV 1 RO Set if EEE is supported for 100BASE-TX by link partner1 Link partner is advertising EEE capability for 100BASE-TX0 Link partner is not advertising EEE capability for 100BASE-TX

1 Revision History

11 Revision 42

12 Revision 41

13 Revision 40

14 Revision 20

2 Registers

21 ANA

211 ANAANA

212 ANAPGID

213 ANAANA_TABLES

214 ANAPORT

215 ANAPFC

216 ANACOMMON

217 ANAPOL

218 ANAPOL_MISC

22 DEV

221 DEVPORT_MODE

222 DEVMAC_CFG_STATUS

223 DEVPCS1G_CFG_STATUS

224 DEVPCS1G_TSTPAT_CFG_STATUS

225 DEVPCS_FX100_CONFIGURATION

226 DEVPCS_FX100_STATUS

23 DEVCPU_GCB

231 DEVCPU_GCBCHIP_REGS

232 DEVCPU_GCBVCORE_ACCESS

233 DEVCPU_GCBGPIO

234 DEVCPU_GCBMIIM

235 DEVCPU_GCBMIIM_READ_SCAN

236 DEVCPU_GCBMIIM_SLAVE

237 DEVCPU_GCBPHY

238 DEVCPU_GCBSIO_CTRL

239 DEVCPU_GCBFAN_CTRL

2310 DEVCPU_GCBMEMITGR

2311 DEVCPU_GCBVRAP

24 DEVCPU_ORG

241 DEVCPU_ORGDEVCPU_ORG

25 DEVCPU_PTP

251 DEVCPU_PTPPTP_CFG

252 DEVCPU_PTPPTP_STATUS

253 DEVCPU_PTPPTP_PINS

26 DEVCPU_QS

261 DEVCPU_QSXTR

262 DEVCPU_QSINJ

27 HSIO

271 HSIOPLL5G_CFG

272 HSIOPLL5G_STATUS

273 HSIORCOMP_STATUS

274 HSIOSYNC_ETH_CFG

275 HSIOSERDES1G_ANA_CFG

276 HSIOSERDES1G_DIG_CFG

277 HSIOSERDES1G_DIG_STATUS

278 HSIOMCB_SERDES1G_CFG



2711 HSIOSERDES6G_ANA_STATUS


2713 HSIOHW_CFGSTAT

2714 HSIOTEMP_SENSOR

28 ICPU_CFG

281 ICPU_CFGCPU_SYSTEM_CTRL

282 ICPU_CFGSPI_MST

283 ICPU_CFGMPU8051

284 ICPU_CFGINTR

285 ICPU_CFGTIMERS

286 ICPU_CFGTWI_DELAY

287 ICPU_CFGTWI_SPIKE_FILTER

288 ICPU_CFGFDMA

289 ICPU_CFGPCIE

2810 ICPU_CFGMANUAL_XTRINJ

29 VCAP_CORE

291 VCAP_COREVCAP_CORE_CFG

292 VCAP_COREVCAP_CORE_CACHE

293 VCAP_COREVCAP_CORE_MAP

294 VCAP_CORETCAM_BIST

210 PCIE

2101 PCIEPCIE_TYPE0_HDR

2102 PCIEPCIE_PM_CAP

2103 PCIEPCIE_MSI_CAP

2104 PCIEPCIE_CAP

2105 PCIEPCIE_AER_CAP

2106 PCIEPCIE_PORT_LOGIC

211 QSYS

2111 QSYSSYSTEM

2112 QSYSTIMED_FRAME_CFG

2113 QSYSRES_QOS_ADV

2114 QSYSRES_CTRL

2115 QSYSDROP_CFG

2116 QSYSMMGT

2117 QSYSHSCH

2118 QSYSHSCH_MISC

212 REW

2121 REWPORT

2122 REWCOMMON

213 SBA

2131 SBASBA

214 SFR

2141 SFRSFR

215 SIMC

2151 SIMCSIMC

216 SYS

2161 SYSSYSTEM

2162 SYSPAUSE_CFG

2163 SYSMMGT

2164 SYSSTAT

2165 SYSPTP

217 TWI

2171 TWITWI

218 UART

2181 UARTUART

219 PHY

2191 PHYPHY_STD

2192 PHYPHY_EXT1

2193 PHYPHY_EXT2

2194 PHYPHY_GP

2195 PHYPHY_EEE

I30495
File Attachment
VSC7511_Registerspdf

Electrical Specifications


7 Electrical Specifications

This section provides the DC characteristics AC characteristics recommended operating conditions and stress ratings for the VSC7511 device

71 DC SpecificationsThis section contains the DC characteristics for the VSC7511 device

711 Internal Pull-Up or Pull-Down ResistorsThe following table lists the specifications for the internal resistors used by IO signals in the device For more information see Pins by Function page 287

712 Reference Clock InputsThe following table lists the reference clock input specifications

713 PLL Clock OutputsThe following table lists the PLL clock outputs specifications

Table 214 bull Internal Resistor Characteristics

Parameter Symbol Minimum Maximum UnitInternal Pull-up resistor RPU 25 90 kΩ

Internal Pull-down resistor RPD 25 112 kΩ

Table 215 bull Reference Clock Input Characteristics

Parameter Symbol Minimum Typical Maximum UnitInput voltage range VIP VIN ndash25 1200 mV

Single-ended input swing |VSE| 600 10001

1 Input common-mode voltage and amplitude must not exceed 1200 mV

mVpp

Differential peak-to-peak input swing |VID| 200 1200 mVppd

Input common-mode voltage VCM 23 x VDD mV

Table 216 bull PLL Clock Outputs Characteristics

Parameter Symbol Minimum Typical Maximum Unit ConditionDifferential resistance RDIFF 80 100 120 Ω

Differential peak-to-peak output swing1

1 Output swing is register programmable in 16 steps

VOD 290 510 mVppd VDD_A = 10 V

Differential peak-to-peak output swing1 VOD 360 635 mVppd VDD_A = 10 V2

2 Driver amplitude depends on driver-to-receiver adaptation configured in register Increased amplitudes can be achieved if receiver is common-mode terminated to VDD_A and if driver is configured accordingly

Output common-mode voltage VCM VDD_A ndash 500 mV

VDD_A mV



714 SERDES1GThe following table lists the SERDES1G specifications


Table 217 bull SERDES1G Characteristics for 1G Transmitter


Output voltage high VOH 1050 mV

Output voltage low VOL 0 mV

Differential peak-to-peak output voltage1 VO_DIFF 300 800 mVppd 100BASE-FX SGMII

Differential peak-to-peak output voltage1 VO_DIFF 500 1200 mVppd SFP

Differential peak-to-peak output voltage1

1 Output amplitude is configurable in 16 steps

VO_DIFF 800 1100 mVppd 1000BASE-KX

Differential peak-to-peak output voltage with Tx disabled

VO_IDLE 30 mVppd

Table 218 bull SERDES1G Characteristics for 1G Receiver

Parameter Symbol Minimum Typical Maximum Unit ConditionsDifferential resistance RDIFF 80 100 120 Ω

Absolute input voltage range VIN ndash25 1200 mV

Common-mode voltage VCM_AC 0 VDD_A mV AC-coupled operation1

1 Compatibility to SGMII transmitters requires external AC-coupling The maximum common-mode voltage is provided without a differential signal It is limited by the minimum and maximum input voltage range and the signal amplitude of input

Common-mode voltage VCM_DC 07 x VDD_A mV DC-coupled operation2 3

2 For more information about optional DC-coupling contact your Microsemi sales representative3 Common-mode termination disabled The maximum differential peal-to-peak input is limited by the maximum input voltage

range

Differential peak-to-peak input voltage VIN_DIFF 100 1600 mVppd See note4

4 Applies to all the supported modes For 100BASE-FX mode disable internal AC-coupling



Output voltage high VOH VDD_VS mV


Differential peak-to-peak output voltage1 VO_DIFF 300 800 mVppd 100BASE-FX SGMII2

Differential peak-to-peak output voltage1 VO_DIFF 400 750 mVppd QSGMIIob_post0 = 6ob_lv = 39



716 GPIO SI JTAG and Miscellaneous SignalsThe following table lists the specifications of GPIO SI JTAG and miscellaneous signals

Differential peak-to-peak output voltage1 VO_DIFF 500 1200 mVppd SFP 25G

Differential peak-to-peak output voltage1 VO_DIFF 800 1200 mVppd 1000BASE-KX and PCIe3


VO_IDLE 30 mVppd

Output current driver shorted to GND T_ISG 40 mA

1 Drive level depends on register configuration2 Compatibility to SGMII receiver requires AC-coupling3 Compatibility to supported standards requires 12 V supply for driver




Common-mode voltage VCM 0 Internal VCM

mV AC-coupled operation1

Common-mode voltage VCM VDD_A mV DC-coupled operation load type 21


1 Mode for common-mode termination is specified by configuration register setting Input amplitude in DC-coupled mode must not exceed maximum input voltage range For more information about optional DC-coupling contact your Microsemi representative

2 Compatibility to SGMII transmitter requires AC-coupling

Table 221 bull GPIO SI JTAG and Miscellaneous Signals Characteristics

Parameter Symbol Minimum Typical Maximum Unit ConditionOutput high voltage1

1 VDD_IO=238 V for minimum VDD_IO=250 V for typical

VOH 21 235 V IOH = ndash2 mA

Output high voltage1 VOH 17 20 V IOH = ndash12 mA

Output low voltage VOL 04 V IOL = 2 mA


Input high voltage VIH 185 36 V

Input low voltage VIL ndash03 08 V

Input high current2

2 Input high current and input low current equals the maximum leakage current excluding the current in the built-in pull resistors

IIH 10 microA VI = VDD_IO

Input low current2 IIL ndash10 microA VI = 0 V

Input capacitance CI 10 pF

Table 219 bull SERDES6G Characteristics (continued) for 6G Transmitter (continued)

Parameter Symbol Minimum Typical Maximum Unit Condition



717 Thermal DiodeThe device includes an on-die diode and internal circuitry for monitoring die temperature (junction temperature) The operation and accuracy of the diode is not guaranteed and should only be used as a reference

The on-die thermal diode requires an external thermal sensor located on the board or in a stand-alone measurement kit Temperature measurement using a thermal diode is very sensitive to noise The following illustration shows a generic application design

Figure 99 bull Thermal Diode

Note Microsemi does not support or recommend operation of the thermal diode under reverse bias

The following table provides the diode parameter and interface specifications with the pins connected internally to VSS in the device

The ideality factor n represents the deviation from ideal diode behavior as exemplified by the following diode equation

where IS = saturation current q = electron charge VD = voltage across the diode k = Boltzmann constant and T = absolute temperature (Kelvin)

72 AC SpecificationsThis section contains the AC characteristics for the VSC7511 device

721 REFCLK Reference Clock (1G and 6G Serdes)The following table lists the REFCLK reference clock input specifications

Table 222 bull Thermal Diode Parameters

Parameter Symbol Typical Maximum UnitForward bias current IFW See note1

1 Typical value is device dependent

1 mA

Diode ideality factor n 1008


Parameter Symbol Minimum Typical Maximum Unit ConditionREFCLK frequency REFCLK_CONF = 100 ndash100 ppm 25 100 ppm MHz

REFCLK frequency REFCLK_CONF = 000 ndash100 ppm 125 100 ppm MHz



VitesseDie Cell

TemperatureDiode

ExternalDevice

2200 pF

Anode

Cathode

Anode

Cathode

Isolated Sensor Circuit

D+

Dndash

VitesseDie Cell

TemperatureDiode

ExternalDevice

2200 pF

Grounded Sensor Circuit

DXP

GND

IFW IS eqVD( ) nkT( )frasl

1ndash( )=




Clock duty cycle 40 60 Measured at 50 threshold

Rise time and fall time tR tF 15 ns Within +ndash 200 mV relative to VDD x 23

Jitter transfer from REFCLK to SERDES outputs bandwidth from 10 kHz to 100 kHz

03 dB REFCLK = 25 MHz

Jitter transfer from REFCLK to SERDES outputs bandwidth from 100 kHz to 4 MHz


Jitter transfer from REFCLK to SERDES outputs bandwidth above 4 MHz

1 ndash 20 times log (ƒ4 MHz)

dB REFCLK = 25 MHz


03 dB REFCLK ge 125 MHz



Jitter transfer from REFCLK to SERDES outputs bandwidth from 3 MHz to 12 MHz




dB REFCLK ge 125 MHz

REFCLK input peak-to-peak jitter bandwidth from 25 kHz and 10 MHz1

20 ps To meet G8262 1G SyncE jitter generation specification

1 Peak-to-peak values are typically higher than the RMS value by a factor of 10 to 14


Parameter Symbol Minimum Maximum Unit ConditionData rate 625 MHz

Clock duty cycle tC 45 55 Measured at 50 threshold

Rise time and fall time tR tF 100 300 ps 20 to 80 of VS

Intrapair skew tSKEW 100 ps

Jitter generation 10 kHz to 50 MHz 4 psRMS Jitter-free input used forREFCLK

Table 223 bull Reference Clock Input Characteristics (continued)




723 SERDES1GThe following table lists the SERDES1G specifications (applies to the S[50]_TXNP pins)

Table 225 bull SERDES1G Characteristics for 100BASE-FX SGMII SFP 1000BASE-KX Transmitter

Parameter Symbol Minimum Maximum Unit ConditionData rate 125 ndash 100

ppm125 + 100 ppm Mbps 100BASE-FX

Data rate 125 ndash 100 ppm

125 + 100 ppm Gbps SGMII SFP 1000BASE-KX

Differential output return loss RLOSDD22 ndash 10 dB 50 MHz to 625 MHz

Differential output return loss RLOSDD22 ndash10 + 10 x log(f625 MHz)

dB 625 MHz to 1250 MHz

Rise time and fall time1

1 Slew rate is programmable

tR tF 60 300 ps 20 to 80

Interpair skew tSKEW 20 ps

Deterministic jitter DJ 80 ps Measured according to IEEE 8023 Clause 385

Total jitter TJ 192 ps Measured according to IEEE 8023 Clause 385

Wideband SyncE jitter WJT 05 UIP-P Measured according to ITU-T G8262 section 83

Table 226 bull SERDES1G Characteristics for 100BASE-FX SGMII SFP 1000BASE-KX Receiver

Parameter Symbol Minimum Maximum Unit ConditionData rate 125 ndash 100 ppm 125 + 100 ppm Mbps 100BASE-FX

Data rate 125 ndash 100 ppm 125 + 100 ppm Gbps SGMII SFP 1000BASE-KX

Differential input return loss

RLISDD11 ndash 10 dB 50 MHz to 625 MHz


RLISDD11 ndash10 + 10 x log(f625 MHz) dB 625 MHz to 1250 MHz

Jitter tolerance total1 TOLTJ 600 ps SGMII SFP 1000BASE-KX Measured according to IEEE 8023 Clause 3868

Jitter tolerance deterministic1

TOLDJ 370 ps SGMII SFP 1000BASE-KX Measured according to IEEE 8023 Clause 3868

Jitter tolerance duty cycle distortion

TOLDCD 14 ns p-p 100BASE-FX Measured according to ISOIEC 9314-31990




Jitter tolerance data dependent

TOLDDJ 22 ns p-p 100BASE-FX Measured according to ISOIEC 9314-31990

Jitter tolerance random TOLRJ 227 ns p-p 100BASE-FX Measured according to ISOIEC 9314-31990

Wideband SyncE jitter tolerance

WJT 3125 UIP-P 10 Hz to 121 Hz Measured according to ITU-T G8262 section 92


WJT 3750f UIP-P 121 Hz to 25 kHz (f) Measured according to ITU-T G8262 section 92


WJT 15 UIP-P 25 kHz to 50 kHz Measured according to ITU-T G8262 section 92

1 Jitter requirements represent high-frequency jitter (above 637 kHz) and not low-frequency jitter or wander

Table 227 bull SERDES6G Characteristics for 100BASE-FX SGMII SFP 25G 1000BASE-KX Transmitter



Data rate 3125 ndash 100 ppm 3125 + 100 ppm Gbps 25G

Differential output return loss RLOSDD22 ndash10 dB 50 MHz to 625 MHz

Differential output return loss RLOSDD22 ndash10 + 10 x log(f625 MHz) dB 625 GHz to 1250 MHz

Rise time and fall time1 tR tF 60 320 ps 20 to 80


Random jitter RJ 015 UIP-P At BER 10ndash12

Deterministic jitter DJ 010 UIP-P

Total jitter TJ 025 UIP-P

Wideband SyncE jitter TWJ 05 UIP-P Measured according to ITU-T G8262 section 83

Eye mask X1 0125 UI

Eye mask X2 0325 UI

Table 226 bull SERDES1G Characteristics (continued) for 100BASE-FX SGMII SFP 1000BASE-KX Receiver

Parameter Symbol Minimum Maximum Unit Condition



Eye mask Y1 3502 mV

Eye mask Y2 800 mV

1 Slew rate is programmable2 Compatibility to supported standards requires 12 V supply for driver

Table 228 bull SERDES6G Characteristics for 100BASE-FX SGMII SFP 25G 1000BASE-KX Receiver




3125 + 100 Gbps 25G


RLISDD11 ndash10 dB 50 MHz to 625 MHz


RLISDD11 ndash10 + 10 x log(f65 MHz)2 dB 625 MHz to 1250 MHz

Jitter tolerance total1 TOLTJ 600 ps Measured according to IEEE 8023 Clause 3868


TOLDJ 370 ps Measured according to IEEE 8023 Clause 3868
















1 Jitter requirements represent high-frequency jitter (above 637kHz) and not low-frequency jitter or wander

Table 229 bull SERDES6G Characteristics for QSGMII Transmitter


ppm50 + 100 ppm Gbps

Differential output return loss RLOSDD22 ndash8 dB 100 MHz to 25 GHz

Differential output return loss RLOSDD22 ndash8 + 166 x log(f25 GHz) dB 25 GHz to 50 GHz

Common-mode output return loss

RLOSCC22 ndash6 dB 100 MHz to 25 GHz

Rise time and fall time1 tR tF 30 130 ps 20 to 80 Recommended value

Random jitter RJ 015 UIP-P


Duty cycle distortion (part of DJ)

DCD 005 UIP-P


Eye mask X1 015 UIP-P Near-end


Eye mask Y1 200 mV Near-end



Table 230 bull SERDES6G Characteristics for QSGMII Receiver

Parameter Symbol Minimum Maximum Unit ConditionData rate 50 ndash 100 ppm 50 + 100 ppm Gbps

Differential input return loss RLISDD11 ndash8 dB 100 MHz to 25 GHz

Differential input return loss RLISDD11 ndash8 + 166 x log(f25 GHz) dB 25 GHz to 50 GHz

Common-mode return loss RLISCC11 ndash6 dB 100 MHz to 25 GHz

Sinusoidal jitter maximum SJMAX 5 UIP-P For low sinusoidal jitter frequencies below (baud1667)

Sinusoidal jitter high frequency SJHF 005 UIP-P

Deterministic jitter (uncorrelated bounded high-probability jitter)

UBHPJ 015 UIP-P

Data-dependent jitter (correlated bounded high-probability jitter)

CBHPJ 030 UIP-P



725 Reset Timing SpecificationsThe following illustration shows the nReset signal waveform and the required measurement points for the timing specification

Total jitter TJ 060 UIP-P Sinusoidal jitter excluded

Eye mask R_X1 030 UIP-P

Eye mask R_Y1 50 mV

Eye mask R_Y2 450 mV

Table 231 bull SERDES6G Characteristics for PCIe Transmitter

Parameter Symbol Minimum Typical Maximum Unit ConditionData rate 25 ndash 300 ppm 25 + 300 ppm Gbps


Common-mode return loss RLOSCC22 ndash6 dB 50 MHz to 125 GHz

Demphasized differential output voltage (ratio)

Tode ndash4 ndash35 ndash3 dB Register setting post0 = 18


Total jitter TJ 025 UIP-P Near-end

Differential amplitude VTX_DIFF_PP 8002 1200 mVP-P Near-end

1 Slew rate is programmable Configure accordingly for compliance to supported standard2 Compatibility to supported standards requires 12 V supply for driver

Table 232 bull SERDES6G Characteristics for PCIe Receiver




Total jitter tolerance TJ 060 UIP-P

Eye mask R_X1 020 UI


Eye mask R_Y1 85 mV


Table 230 bull SERDES6G Characteristics for QSGMII Receiver (continued)




Figure 100 bull Reset Signal Timing

The following table lists the specifications for the signal applied to the nReset input at the reset pin

726 MIIM Timing SpecificationsThe following table lists the specifications for the signal applied to the MIM input at the MIM pin

Table 233 bull Reset Timing Characteristics

Parameter Symbol Minimum Maximum UnitnReset assertion time after power supplies and clock stabilizes

tW 2 ms

Recovery time from reset inactive to device fully active

tREC 10 ms

nReset pulse width tW(RL) 100 ns

Hold time for GPIO-mapped strapping pins relative to nRESET

tHCFG 50 ns

Table 234 bull MIIM Timing Characteristics

Parameter Symbol Minimum Maximum Unit ConditionMDC frequency1

1 For the maximum value the device supports an MDC clock speed of up to 20 MHz for faster communication with the PHYs If the standard frequency of 25 MHz is used the MIIM interface is designed to meet or exceed the IEEE 8023 requirements of the minimum MDC high and low times of 160 ns and an MDC cycle time of minimum 400 ns which is not possible at faster speeds

f 0448 2083 MHz

MDC cycle time2

2 Calculated as tC = 1ƒ

tC 48 2048 ns

MDC time high tW(CH) 20 ns CL = 50 pF

MDC time low tW(CL) 20 ns CL = 50 pF

MDIO setup time to MDC on write tSU(W) 15 ns CL = 50 pF

MDIO setup time from MDC on write tH(W) 15 ns CL = 50 pF

MDIO setup time to MDC on read tSU(R) 30 ns CL = 50 pF on MDC

MDIO hold time from MDC on read tH(R) 0 ns CL = 50 pF

VDDx

nReset

tW

VDDxmin

tW(RL)tREC tREC

RefClk

tHCFG

VCore_CFG

tHCFG



727 SI Boot Timing Master Mode SpecificationsThe following table lists the specifications for the signal applied to the SI boot timing master mode input at the SI boot timing master mode pin

728 SI Timing Master Mode SpecificationsAll serial interface (SI) timing requirements for master mode are specified relative to the input low and input high threshold levels The following illustration shows the timing parameters and measurement points

Figure 101 bull SI Timing Diagram for Master Mode

The following table lists the specifications for the signal applied to the SI timing master mode input at the SI timing master mode pin

Table 235 bull SI Boot Timing Master Mode Characteristics

Parameter Symbol Minimum Maximum Unit ConditionClock frequency f 31151

1 Frequency is programmable The startup frequency is 81 MHz

MHz

Clock cycle time tC 32 ns

Clock time high tW(CH) 12 ns

Clock time low tW(CL) 12 ns

Clock rise time and fall time tR tF 5 ns Between VIL(MAX) and VIH(MIN) CL= 30 pF

SI_DO setup time to clock tSU(DO) 10 ns

SI_DO hold time from clock tH(DO) 10 ns

Enable active before first clock tLEAD 10 ns

Enable inactive after clock tLAG 5 ns

SI_DI setup time to clock tSU(DIB) 20 ns

SI_DI hold time from clock tH(DIB) 0 ns

Table 236 bull SI Timing Master Mode Characteristics

Parameter Symbol Minimum Maximum Unit ConditionClock frequency f 31251 MHz



SI_nCS0(output)

tLEAD tC

tW(CH)

tSU(DO)tH(DO)

tSU(DI) tH(DI)

tLAG

tW(CL)SI_Clk(output)

SI_DO(output)

SI_DI(input)



729 SI Timing Slave Mode SpecificationsAll serial interface (SI) slave mode timing requirements are specified relative to the input low and input high threshold levels The following illustrations show the timing parameters and measurement points for SI input and output data

Figure 102 bull SI Input Data Timing Diagram for Slave Mode







SI_DI sampling time delay2 tRSD 0 tC ns

SI_DI setup time to clock tSU(DI) 18 ns

SI_DI hold time from clock tH(DI) 0 ns

1 Frequency is programmable The startup frequency is 81 MHz2 Delay is programmable in 4 ns steps using register bitfield SIMCRX_SAMPLE_DLYRSD



tCtW(CH)tLAG1

tLEAD tW(CL)

tSU(DI) tH(DI)

tF

tR

SI_nCS0(Input)

SI_CLK(Input)

SI_DO(Output) High Impedance

SI_DI(Input)



Figure 103 bull SI Output Data Timing Diagram for Slave Mode

The following table lists the specifications for the signal applied to the SI timing slave mode input at the SI timing slave mode pin

Table 237 bull SI Timing Slave Mode Characteristics








Enable inactive after clock (input cycle)1

1 tLAG1 is defined only for write operations to the devices not for read operations

tLAG1 25 ns

Enable inactive after clock (output cycle) tLAG2 See note2

2 The last rising edge on the clock is necessary for the external master to read in the data The lag time depends on the necessary hold time on the external master data input

ns

Enable inactive width tW(EH) 20 ns

SI_DO valid after clock tV(C) 25 ns CL = 30 pF

SI_DO hold time from clock tH(DO) 0 ns CL = 0 pF

SI_DO disable time3

3 Pin begins to float when a 300 mV change from the loaded VOH or VOL level occurs

TDIS1 20 ns See Figure 161 page 610

SI_DO disable time3 TDIS2 20 ns See Figure 161 page 610

tLAG2

tW(EH)

Last data bit

tV(C) tH(DO)tDIS1tDIS2

SI_nCS0(Input)

SI_CLK(Input)

SI_DO(Output)

SI_DI(Input)



7210 JTAG Interface SpecificationsThe following table lists the JTAG interface specifications

7211 Serial IO Timing SpecificationsThe following table lists the serial IO timing specifications

7212 Recovered Clock Outputs SpecificationsThe following table lists the recovered clock outputs specifications

Table 238 bull JTAG Interface Characteristics

Parameter Symbol Minimum Typical Maximum Unit ConditionJTAG_TCK frequency f 10 MHz

JTAG_TCK cycle time tC 100 ns

JTAG_TCK high time tW(CH) 40 ns

JTAG_TCK low time tW(CL) 40 ns

Setup time to JTAG_TCK rising tSU 10 ns

Hold time from JTAG_TCK rising tH 10 ns

JTAG_TDO valid after JTAG_TCK falling

tV(c) 28 ns CL = 10 pF

JTAG_TDO hold time from JTAG_TCK falling

tH(TDO) 0 ns CL = 0 pF

JTAG_TDO disable time1

1 The pin begins to float when a 300 mV change from the actual VOHVOL level occurs

tDIS 30 ns See Figure 171 page 651

JTAG_nTRST time low tW(TL) 30 ns

Table 239 bull Serial IO Timing Characteristics

Parameter Symbol Minimum Typical Maximum UnitClock frequency1

1 SIO clock frequency is programmable

f 25 MHz

SG0_CLK clock pulse width tW(CLK) 40 60

SG0_DO valid after clock falling tV(DO) 6 ns

SG0_DO hold time from clock falling tH(DO) 6 ns

SG0_LD propagation delay from clock falling tPD(LATCH) 40 ns

SG0_LD width tW(LATCH) 10 ns

SG0_DI setup time to clock tSU(DI) 25 ns

SG0_DI hold time from clock tH(DI) 4 ns

Table 240 bull Recovered Clock Outputs Characteristics

Parameter Symbol Minimum Maximum Unit ConditionRECO_CLK[10] clock frequency f 15625 MHz



7213 Two-Wire Serial Interface SpecificationsThis section contains information about the device two-wire serial slave interface The following table lists the two-wire serial timing specifications


RECO_CLK[10] rise time and fall time tR tF 15 ns

Squelching delay from SGMII signal to RECO_CLK[10]

200 ns Squelch enabled

RECO_CLK[10] peak-to-peak jitter bandwidth between 12 kHz and 10 MHz1 60 second gate time

200 ps Jitter-free input to SerDes Rx

RECO_CLK[10] peak-to-peak jitter bandwidth between 10 MHz and 80 MHz1 60 second gate time


1 Maximum jitter on the recovered signal

Table 241 bull Two-Wire Serial Timing Characteristics

Parameter SymbolStandard Standard Fast Mode Fast Mode

Unit Minimum Maximum Minimum Maximum ConditionTWI_SCL clock frequency ƒ 100 400 kHz

TWI_SCL low period tLOW 47 13 micros

TWI_SCL high period tHIGH 40 06 micros

TWI_SCL and TWI_SDA rise time

1000 300 ns

TWI_SCL and TWI_SDA fall time

300 300 ns

TWI_SDA setup time to TWI_SCL fall

tSU_DAT 250 100 300 ns

TWI_SDA hold time to TWI_SCL fall1

tHD_DAT 300 3450 300 900 ns 300 ns delay enabled in ICPU_CFGTWI_CONFIGregister

Setup time for repeated START condition

tSU_STA 47 06 micros

Hold time after repeated START condition

tHD_STA 40 06 micros

Bus free time between STOP and START conditions

tBUF 47 13 micros

Clock to valid data out2 tVD_DAT 300 300 ns

Pulse width of spike suppressed by input filter on TWI_SCL or TWI_SDA3

4 128 4 128 ns

Table 240 bull Recovered Clock Outputs Characteristics (continued)




The following illustration shows the two-wire serial interface timing

Figure 104 bull Two-Wire Serial Interface Timing

7214 IEEE1588 Time Tick Output SpecificationsThe following table lists the IEEE1588 Time Tick Output specifications

73 Current and Power ConsumptionThe following tables lists the current and power consumption for the VSC7511 device respectively

1 An external device must provide a hold time of at least 300 ns for the TWI_SDA signal to bridge the undefined region of the falling edge of the TWI_SCL signal

2 Some external devices may require more data in hold time (target devicersquos tHD_DAT) than what is provided by tVD_DAT for example 300 ns to 900 ns The minimum value of tVD_DAT is adjustable the given value represents the recommended minimum value which is enabled in ICPU_CFGTWI_CONFIGTWI_DELAY_ENABLE

3 Configurable in the register ICPU_CFGTWI_SPIKE_FILTER_CFG The default register value results in spike suppression up to 4 ns The recommended register value is 12 resulting in spike suppression up to 52 ns

Table 242 bull IEEE1588 Time Tick Output Characteristics

Parameter Symbol Minimum Maximum Unit ConditionPTP[30] frequency1

1 Frequency is programmable

f 25 MHz

Clock duty cycle2

2 Both high and low periods are configured to the identical value using DEVCPU_PTPPIN_WF_HIGH_PERIOD and DEVCPU_PTPPIN_WF_LOW_PERIOD

45 55 Measured at 50 threshold

PTP[30] rise time and fall time tR tF 1 ns 20 to 80 threshold

PTP[30] peak-to-peak jitter bandwidth between 12 kHz and 10 MHz3

3 Timing corrections performed by register writes and highlow periods that do not match a fixed number of 15625 MHz clock cycles will create jitter up to 35 ns

200 ps

PTP[30] peak-to-peak jitter bandwidth between 10 MHz and 80 MHz3

200 ps

Table 243 bull Current and Power Consumption

Parameter Symbol TypicalMaximum(TJ_MAX = 110 degC)

Maximum(TJ_MAX = 125 degC) Unit

VDD operating current 10 V IDD 08 13 16 A

VDD_A operating current 10 V IDD_A 015 015 015 A

VDD_VS operating current 10 V V IDD_VS 011 011 011 A

tLOW tRtF

SDA

SCL

S Sr SP

tFtSUDAT

tHDSTA tHDDAT tHIGHtSUSTA tSUSTO

tBUFtRtHDSTA

S = START P = STOP and Sr = repeated START



74 Operating ConditionsThe following table lists the recommended operating conditions for the VSC7511 device

741 Power Supply SequencingDuring power on and off VDD_A and VDD_VS must never be more than 300 mV above VDD

VDD_VS must be powered even if the associated interfaces are not used These power supplies must not remain at ground or be left floating

A maximum delay of 100 ms from VDD_IODDR to VDD is recommended There is no requirement from VDD to VDD_IODDR

The VDD_IODDR supply can remain at ground or be left floating if not used If VDD_IODDR is grounded DDR_Vref must also be grounded

There are no sequencing requirements for VDD_IO

The nRESET and JTAG_nTRST inputs must be held low until all power supply voltages have reached their recommended operating condition values

VDD_AL operating current 10 V IDD_AL 008 01 01 A

VDD_AH operating current 25 V IDD_AH 045 058 058 A

VDD_IO operating current1 25 V IDD_IO 002 002 002 A

Total Power 23 33 36 W

Saving per disabled CuPHY port 04 055 055 W

Saving per disabled SerDes1G port 002 003 003 W


1 Unloaded pins

Table 244 bull Recommended Operating Conditions

Parameter Symbol Minimum Typical Maximum UnitPower supply voltage for core supply VDD 095 100 105 V

Power supply voltage for analog circuits VDD_A 095 100 105 V

Power supply voltage for 1G and 6G interfaces 10 V

VDD_VS 095 100 105 V


VDD_VS 114 12 126 V

Power supply voltage for copper PHY analog circuits

VDD_AL 095 10 105 V

Power supply voltage for copper PHY interface

VDD_AH 2375 25 2625 V

Power supply voltage for GPIO and miscellaneous IO

VDD_IO 2375 25 2625 V

Operating temperature1

1 Minimum specification is ambient temperature and the maximum is junction temperature

T ndash40 125 degC

Table 243 bull Current and Power Consumption (continued)





75 Stress RatingsThis section contains the stress ratings for the VSC7511 device

Warning Stresses listed in the following table may be applied to devices one at a time without causing permanent damage Functionality at or exceeding the values listed is not implied Exposure to these values for extended periods may affect device reliability

Note This device can be damaged by electrostatic discharge (ESD) voltage Microsemi recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures may adversely affect reliability of the device

Table 245 bull Stress Ratings

Parameter Symbol Minimum Maximum Unit ConditionPower supply voltage for core supply VDD ndash03 110 V Design

Power supply voltage for analog circuits VDD_A ndash03 110 V Design

Power supply voltage for 1G and 6G interfaces VDD_VS ndash03 132 V Design

Power supply voltage for copper PHY analog circuits VDD_AL ndash03 110 V Design

Power supply voltage for copper PHY interface VDD_AH ndash03 275 V Design

Power supply voltage for DDR IO buffers VDD_IODDR ndash03 198 V Design

Power supply voltage for GPIO and miscellaneous IO VDD_IO ndash03 275 V Design

Storage temperature TS ndash55 125 degC Design

Electrostatic discharge voltage charged device model VESD_CDM ndash250 250 V

Electrostatic discharge voltage human body model VESD_HBM See note1

1 This device has completed all required testing as specified in the JEDEC standard JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) and complies with a Class 2 rating The definition of Class 2 is any part that passes an ESD pulse of 2000 V but fails an ESD pulse of 4000 V

V

Pin Descriptions


8 Pin Descriptions

The VSC7511 device has 172 pins which are described in this section The pin information is also provided in the attached file which you can copy sort or manipulate as desired

81 Pin DiagramThe following illustration is a representation of the VSC7511 device as seen from the bottom view

Figure 105 bull Pin Diagram

82 Pins by FunctionThis section describes the functional pin descriptions for the VSC7511 device

The following table lists the definitions for the pin type symbols

Table 246 bull Pin Type Symbol Definitions

Symbol Pin Type DescriptionA Analog input Analog input for sensing variable voltage levels

ABIAS Analog bias Analog bias pin

DIFF Differential Differential signal pair

I Input Input signal

O Output Output signal

IO Bidirectional Bidirectional input or output signal

OZ 3-state output Output

LVDS Input or output Low voltage differential signal

12345678910111213141516171819202122232425262728293031323334353637383940414243

12912812712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796959493929190898887

172171170169168167166165164163162161160159158157156155154153152151150149148147146145144143142141140139138137136135134133132131130

44454647484950515253545556575859606162636465666768697071727374757677787980818283848586

Sheet1

Sheet2

Sheet3

I30495
File Attachment
VSC7511_Pinsxls

Pin Descriptions


The following table lists the functional pin descriptions for the VSC7511 device

Table 247 bull Pins by Function

LVCMOS Input or output Low voltage CMOS signal

3V 33 V-tolerant

ST Schmitt-trigger Input has Schmitt-trigger circuitry

TD Termination differential Internal differential termination

Group Name Number IO Type Level Description

ANALOG REF_FILT 152 A ABIAS AnalogCopper media reference filter pin Connect a 10 F external capacitor between pin and ground

ANALOG REF_Rext 153 A ABIAS AnalogCopper media reference external pin Connect a 20 k (1) resistor between pin and ground

ANALOG SERDES_Rext_0 85 A Analog AnalogAnalog bias calibration Connect an external 620 plusmn1 resistor between SERDES_Rext_1 and SERDES_Rext_0

ANALOG SERDES_Rext_1 86 A AnalogAnalog bias calibration Connect an external 620 plusmn1 resistor between SERDES_Rext_1 and SERDES_Rext_0

ANALOG THERMDA 127 A Analog Analog Thermal diode anode (p-junction)

ANALOG THERMDC 129 A Analog Analog Thermal diode cathode (n-junction) Connected on-die to VSS

ANALOG VSS 119 A AnalogANALOG VSS 109 A AnalogCLOCK CLKOUTPLL_N 79 O LVDS PLL clock out Leave floating if not usedCLOCK CLKOUTPLL_P 81 O LVDS PLL clock out Leave floating if not used

Table 246 bull Pin Type Symbol Definitions (continued)

Symbol Pin Type Description

Pin Descriptions


CLOCK REFCLK_N 82 I TD LVDS

Reference clock inputsThe inputs can be either differential or single-endedIn differential mode (LVDS) REFCLK_P is the true part of the differential signal and REFCLK_NREFCLK_N is thecomplement part of the differential signalIn single-ended mode (LVCMOS) REFCLK_P is used as single-ended LVTTL input REFCLK_N should beleft floating and the PLL registers must be configured for singleendedoperationRequired applied frequency depends on REFCLK_CONF[20] input state

CLOCK REFCLK_P 84 I TD LVDS


GPIO GPIO_0 4 IO PUST3V CMOS_25 General-purpose inputoutputstrapping


GPIO GPIO_2 6 IO PUST3V CMOS_25 General-purpose inputs and outputs


GPIO GPIO_4 8 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_5 9 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_6 10 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_7 11 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_8 12 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_9 13 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_10 14 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_11 15 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_12 16 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_13 17 IO PUST3V CMOS_25 General-purpose inputs and outputs

Pin Descriptions


GPIO GPIO_14 18 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_15 19 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_16 20 IO PUST3V CMOS_25 General-purpose inputs and outputsGPIO GPIO_17 21 IO PUST3V CMOS_25 General-purpose inputs and outputs



GPIO GPIO_20 27 IO PU3V CMOS_25 General-purpose inputoutputstrapping


JTAG JTAG_nTRST 35 I PUST3V CMOS_25JTAG test reset active low For normal device operation JTAG_nTRST should be pulled low

JTAG JTAG_TCK 38 I PUST3V CMOS_25 JTAG clockJTAG JTAG_TDI 37 I PUST3V CMOS_25 JTAG test data inJTAG JTAG_TDO 34 O OZ 3V CMOS_25 JTAG test data outJTAG JTAG_TMS 36 I PUST3V CMOS_25 JTAG test mode selectMISC nRESET 33 I PUST3V CMOS_25 Global device reset active low

PHY P0_D0N 141 IO ADIFF Analog 25

TxRx channel A negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the A data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 2

PHY P0_D0P 143 IO ADIFF Analog 25

TxRx channel A positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the A data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 1


TxRx channel B negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the B data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 6

Pin Descriptions



TxRx channel B positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the B data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 3


TxRx channel C negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the C data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 5 (pins not used in 10100 Mbps modes)


TxRx channel C positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the C data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 4 (pins not used in 10100 Mbps modes)


TxRx channel D negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the D data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 8 (pins not used in 10100 Mbps modes)


TxRx channel D positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the D data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 7 (pins not used in 10100 Mbps modes)

Pin Descriptions












Pin Descriptions












Pin Descriptions












Pin Descriptions












Pin Descriptions










POWER NC 45 PPOWER NC 53 PPOWER NC 71 PPOWER NC 87 PPOWER NC 88 PPOWER NC 89 PPOWER NC 90 PPOWER NC 91 PPOWER NC 94 PPOWER NC 106 PPOWER NC 111 P

Pin Descriptions


POWER NC 113 PPOWER NC 115 PPOWER NC 117 PPOWER NC 121 PPOWER NC 123 PPOWER NC 124 PPOWER NC 125 PPOWER NC 126 PPOWER NC 128 PPOWER NC 171 PPOWER VDD 43 PPOWER VDD 23 PPOWER VDD 1 PPOWER VDD 136 PPOWER VDD 130 PPOWER VDD 122 PPOWER VDD 120 PPOWER VDD 118 PPOWER VDD 116 PPOWER VDD 114 PPOWER VDD 112 PPOWER VDD 110 PPOWER VDD 108 PPOWER VDD 107 PPOWER VDD 105 PPOWER VDD 104 PPOWER VDD 103 PPOWER VDD 102 PPOWER VDD 101 PPOWER VDD 100 PPOWER VDD 99 PPOWER VDD 98 PPOWER VDD 97 PPOWER VDD 96 PPOWER VDD 95 PPOWER VDD 93 PPOWER VDD 92 PPOWER VDD 83 PPOWER VDD 61 PPOWER VDD 47 PPOWER VDD_AH 166 P Analog 25POWER VDD_AH 140 P Analog 25POWER VDD_AL 168 P Analog 10

Pin Descriptions


POWER VDD_AL 139 P Analog 10POWER VDD_IO 39 PPOWER VDD_IO 24 P IO_VDD_25 POWER VDD_IO 22 P IO_VDD_25 POWER VDD_IO 2 P IO_VDD_25 POWER VDD_IO 80 PPOWER VDD_IO 59 PPOWER VDD_VS 74 PPOWER VDD_VS 68 PPOWER VDD_VS 63 PPOWER VDD_VS 56 PPOWER VDD_VS 50 PPOWER VDDA 42 PPOWER VDDA 41 PPOWER VDDA 40 PPOWER VDDA 77 PPOWER VDDA 65 PPOWER VDDA 58 PPOWER VDDA 48 PReserved RESERVED_0 133 A Analog Analog 25 Leave floatingto testpointReserved RESERVED_1 131 A Analog Analog 25 Leave floatingto testpointReserved RESERVED_3 3 P Analog Tie to VSSSERDES1G S4_RXN 49 I TD LVDS Differential 1G data inputsSERDES1G S4_RXP 51 I TD LVDS Differential 1G data inputsSERDES1G S4_TXN 44 O LVDS Differential 1G data outputsSERDES1G S4_TXP 46 O LVDS Differential 1G data outputsSERDES1G S5_RXN 55 I TD LVDS Differential data inputs 1G25GSERDES1G S5_RXP 57 I TD LVDS Differential data inputs 1G25GSERDES1G S5_TXN 52 O LVDS Differential data outputs 1G25GSERDES1G S5_TXP 54 O LVDS Differential data outputs 1G25G

SERDES6G S6_RXN 64 I TD CML Differential data inputs 1G25GQSGMII

SERDES6G S6_RXP 66 I TD CML Differential data inputs 1G25GQSGMII

SERDES6G S6_TXN 60 O CML Differential data outputs 1G25GQSGMII

SERDES6G S6_TXP 62 O CML Differential data outputs 1G25GQSGMII

SERDES6G S7_RXN 70 I TD CML Differential 1G data inputsSERDES6G S7_RXP 72 I TD CML Differential 1G data inputsSERDES6G S7_TXN 67 O CML Differential data outputs 1G25GSERDES6G S7_TXP 69 O CML Differential data outputs 1G25GSERDES6G S8_RXN 76 I TD CML Differential 1G data inputsSERDES6G S8_RXP 78 I TD CML Differential 1G data inputs

Pin Descriptions


SERDES6G S8_TXN 73 O CML Differential data outputs PCIe2G51GSERDES6G S8_TXP 75 O CML Differential data outputs PCIe2G51G

SI SI_CLK 32 IO ST 3V CMOS_25

Slave mode Input receiving serial interface clock from external masterMaster mode Output driven with clock to external deviceBoot mode Output driven with clock to external serial memory device

SI SI_DI 29 I ST 3V CMOS_25

Slave mode Input receiving serial interface data from external masterMaster mode Input data from external deviceBoot mode Input boot data from external serial memory device

SI SI_DO 30 O OZ 3V CMOS_25

Slave mode Output transmitting serial interface data to externalmasterMaster mode Output data to external deviceBoot mode Output boot control data to external serial memory device

SI SI_nCS0 31 IO ST 3V CMOS_25

Slave mode Input used to enable SI slave interface0 = Enabled1 = DisabledMaster mode Output driven low while accessing external deviceBoot mode Output driven low while booting from EEPROM or serialflash to internal VCore-III CPU system Released when booting iscompleted

Package Information


9 Package Information

The VSC7511XMY is a lead-free (Pb-free) 172-pin dual-row plastic quad flat no-lead (QFN) package with an exposed pad 13 mm times 13 mm body size 05 mm pin pitch and 09 mm maximum height

Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPCJEDEC J-STD-020 For more information see the IPC and JEDEC standard

This section provides the package drawing thermal specifications and moisture sensitivity rating for the VSC7511 device

91 Package DrawingThe following illustration shows the package drawing for the VSC7511 device The drawing contains the top view bottom view side view detail views dimensions tolerances and notes

Package Information


Figure 106 bull Package Drawing

92 Thermal SpecificationsThermal specifications for this device are based on the JEDEC JESD51 family of documents These documents are available on the JEDEC Web site at wwwjedecorg The thermal specifications are modeled using a four-layer test board with two signal layers a power plane and a ground plane (2s2p

Pin A1 corner

Pin A1 cornerD X

010 Z X Y (4times)

(4times)020 X Y

D1 D2 042 plusmn018

042 plusmn018

E E2E1

Y

L L

LL

1973

1973

0450

Detail A

Seating plane

A

008 ZA1

A2

Z

eTeT

eR

eR

5degndash15deg

129128127

89

848586 444546

172171170

132131130

8887

414243

123

Dimensions and Tolerances

Reference Minimum Nominal MaximumAA1A2DE

D1E1D2E2eTeRbL

000

735735

016020

0701300 BSC1300 BSC1275 BSC1275 BSC

745745

050 BSC050 BSC

020030

090005075

755755750

028040

005010 ZM

M ZX Y

b

010 Z

4

2

5

010 ZM X Y

010 Z

MX

Y

4

4

Top View Bottom View

Side View Detail A

Notes1 All dimensions and tolerances are in mil l imeters (mm)2 Dimension applies to plated terminal and is measured

between 020 and 025 mm from terminal tip3 Maximum package warpage is 008 mm4 Applied for exposed pad and terminals Excludes

embedded part of exposed pad5 Applied only to terminals

Package Information


PCB) For more information about the thermal measurement method used for this device see the JESD51-1 standard

To achieve results similar to the modeled thermal measurements the guidelines for board design described in the JESD51 family of publications must be applied For information about applications using QFN packages see the following

bull JESD51-2A Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air)

bull JESD51-6 Integrated Circuit Thermal Test Method Environmental Conditions Forced Convection (Moving Air)

bull JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Boardbull JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packagesbull JESD51-5 Extension of Thermal Test Board Standards for Packages with Direct Thermal

Attachment Mechanisms

93 Moisture SensitivityThis device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard IPCJEDEC J-STD-020 For more information see the IPC and JEDEC standard

Table 248 bull Thermal Resistances

Symbol degCW ParameterθJCtop 408 Die junction to package case top

θJB 777 Die junction to printed circuit board

θJA 1715 Die junction to ambient

θJMA at 1 ms 1312 Die junction to moving air measured at an air speed of 1 ms


Design Guidelines


10 Design Guidelines

This section provides information about design guidelines for the VSC7511 device

101 Power SuppliesThe following guidelines apply to designing power supplies for use with the VSC7511 device

bull Make at least one unbroken ground plane (GND)bull Use the power and ground plane combination as an effective power supply bypass capacitor The

capacitance is proportional to the area of the two planes and inversely proportional to the separation between the planes Typical values with a 025 mm (001 inch) separation are 100 pFin2 This capacitance is more effective than a capacitor of equivalent value because the planes have no inductance or Equivalent Series Resistance (ESR)

bull Do not cut up the power or ground planes in an effort to steer current paths This usually produces more noise not less Furthermore place vias and clearances in a configuration that maintains the integrity of the plane Groups of vias spaced close together often overlap clearances This can form a large slot in the plane As a result return currents are forced around the slot which increases the loop area and EMI emissions Signals should never be placed on a ground plane because the resulting slot forces return currents around the slot

bull Vias connecting power planes to the supply and ground balls must be at least 025 mm (0010 inch) in diameter preferably with no thermal relief and plated closed with copper or solder Use separate (or even multiple) vias for each supply and ground ball

102 Power Supply DecouplingEach power supply voltage should have both bulk and high-frequency decoupling capacitors Recommended capacitors are as follows

bull For bulk decoupling use 10 microF high capacity and low ESR capacitors or equivalent distributed across the board

bull For high-frequency decoupling use 01 microF high frequency (for example X7R) ceramic capacitors placed on the side of the PCB closest to the plane being decoupled and as close as possible to the power ball A larger value in the same housing unit produces even better results

bull Use surface-mounted components for lower lead inductance and pad capacitance Smaller form factor components are best (that is 0402 is better than 0603)

1021 Reference ClockThe device reference clock can be a 25 MHz 125 MHz 15625 MHz or 250 MHz clock signal It can be either a differential reference clock or a single-ended clock For more information see Reference Clock Inputs page 268

1022 Single-Ended REFCLK InputAn external resistor network is required to use a single-ended reference clock The network limits the amplitude and adjusts the center of the swing Depending on the clock driver output impedance the resistor values may need to be adjusted so that the REFCLK_P signal meets requirements For information about these requirements see Table 215 page 268

The following illustrations show configurations for a single-ended reference clock

Design Guidelines


Figure 107 bull 25 V CMOS Single-Ended REFCLK Input Resistor Network


103 InterfacesThis section provides general recommendations for all interfaces and information related to the specific interfaces on the device

1031 General RecommendationsHigh-speed signals require excellent frequency and phase response up to the third harmonic The best designs provide excellent frequency and phase response up to the seventh harmonic The following recommendations can improve signal quality and minimize transmission distances

bull Keep traces as short as possible Initial component placement should be considered very carefullybull The impedance of the traces must match the impedance of the termination resistors connectors

and cable This reduces reflections due to impedance mismatchesbull Differential impedance must be maintained in a 100 Ω differential application Routing two 50 Ω

traces is not adequate The two traces must be separated by enough distance to maintain differential impedance When routing differential pairs keep the two trace lengths identical Differences in trace lengths translate directly into signal skew Note that the differential impedance may be affected when separations occur

bull Keep differential pair traces on the same layer of the PCB to minimize impedance discontinuities In other words avoid using vias

bull Do not group all the passive components together The pads of the components add capacitance to the traces At the frequencies encountered this can result in unwanted reductions in impedance Use surface-mounted 0603 (or smaller) components to reduce this effect

bull Eliminate or reduce stub lengthsbull Reduce if not eliminate vias to minimize impedance discontinuities Remember that vias and their

clearance holes in the powerground planes can cause impedance discontinuities in nearby signals Keep vias away from other traces

bull Keep signal traces away from other signals that might capacitively couple noise into the signals A good rule of thumb is to keep the traces apart by ten times the width of the trace

bull Do not route digital signals from other circuits across the area of the high-speed transmitter and receiver signals

bull Using grounded guard traces is typically not effective for improving signal quality A ground plane is more effective However a common use of guard traces is to route them during the layout but remove them prior to design completion This has the benefit of enforcing keep-out areas around sensitive high-speed signals so that vias and other traces are not accidentally placed incorrectly

180 Ω

560 Ω

REFCLK_P

REFCLK_N

25 VCMOS

10 nF VSS

VDD_A

270 Ω

430 Ω

REFCLK_P33 VCMOS

REFCLK_N

VDD_A

VSS

10 nF

Design Guidelines


bull When signals in a differential pair are mismatched the result is a common-mode current In a well-designed system common-mode currents should make up less than one percent of the total differential currents Mode currents represent a primary source of EMI emissions To reduce common-mode currents route differential traces so that their lengths are the same For example a 5-mm (02-inch) length mismatch between differential signals having the rise and fall times of 200 ps results in the common-mode current being up to 18 of the differential current

Note Because of the high application frequency proper care must be taken when choosing components (such as the termination resistors) in the designing of the layout of a printed circuit board The use of surface-mount components is highly recommended to minimize parasitic inductance and lead length of the termination resistor

Matching the impedance of the PCB traces connectors and balanced interconnect media is also highly recommended Impedance variations along the entire interconnect path must be minimized because these degrade the signal path and may cause reflections of the signal

1032 SerDes Interfaces (SGMII 25GQSGMII)The SGMII interface consists of a Tx and Rx differential pair operating at 1250 Mbps The 25G interface consists of a Tx and Rx differential pair operating at 3125 MbpsThe QSGMII interface consists of a Tx and Rx differential pair operating at 5 Gbps

The SerDes signals can be routed on any PCB trace layer with the following constraints

bull Tx output signals in a pair should have matched electrical lengthsbull Rx input signals in a pair should have matched electrical lengthsbull SerDes Tx and Rx pairs must be routed as 100 Ω differential traces with ground plane as referencebull Keep differential pair traces on the same layer of the PCB to minimize impedance discontinuities In

other words avoid the use of vias wherever possiblebull AC-coupling of Tx and Rx may be needed depending on the attached PHY or module External AC-

coupling is recommended for use with most PHYs SFP modules have internal AC-coupling so they do not require additional AC-coupling capacitors If AC-coupled the VSC7511 SerDes inputs are self-biased It is recommended to use small form factor capacitors 0402 or smaller to reduce the impedance mismatch caused by the capacitor pads

bull To reduce the crosstalk between pairs or other PCB lines it is recommended that the spacing on each side of the pair be larger than four times the track width The characteristic impedance of the pairs must predominantly be determined by the distance to the reference plane and not the distance to neighboring traces

1033 Serial InterfaceIf the serial CPU interface is not used all input signals can be left floating

The SI bus consists of the SI_CLK clock signal the SI_DO and SI_DI data signals and the SI_nCS0 device select signal

When routing the SI_CLK signal be sure to create clean edges If the SI bus is connected to more than one slave device route it in a daisy-chain configuration with no stubs Terminate the SI_CLK signal properly to avoid reflections and double clocking

If it is not possible (or desirable) to route the bus in a daisy-chain configuration the SI_CLK signal should be buffered and routed in a star topology from the buffers Each buffered clock should be terminated at its source

1034 PCI Express InterfaceThe VSC7511 device does not accept spread spectrum modulated PCIe input Although the device only supports PCI Express Base Specification Revision 11 the PCIe transmitter and receiver support the PCI Express Base Specification Revision 20 Electrical sub-block specifications under the following conditions

bull Only 25 gigatransfers per second (GTs) is supported bull Full swing output signaling is only supported when VDD_VS = 12 V bull Low swing signaling is supported for VDD_VS = 12 V and VDD_VS = 10 V

Design Guidelines


During PCIe startup (VCORE_CFG = 1001) only low swing signaling with no de-emphasis is supported regardless of the VDD_VS voltage After startup configure the PCIe interface as desired

1035 Two-Wire Serial InterfaceThe two-wire serial interface is capable of suppressing small amplitude glitches The duration of the glitch which can be suppressed is set in register ICPU_CFGTWI_SPIKE_FILTER_CFG The default value of 0 will suppress a 4ns glitch It is recommended that SPIKE_FILTER_CFG be set to 12 which will suppress a 52ns glitch

1036 DDR3 SDRAM InterfaceThe DDR3 SDRAM interface is designed to interface with 8-bit or 16-bit DDR SDRAM devices The maximum amount of physical memory that can be addressed is one gigabyte Possible combinations of memory modules are

bull One 8-bit device connect to CS0 byte lane 0bull Two 8-bit devices connect to CS0 and both byte lanesbull Four 8-bit devices connect to both chip-selects and both byte lanesbull One 16-bit device connect to CS0 and both byte lanesbull Two 16-bit devices connect to both chip-selects and both byte lanesWhen using a single 8-bit device the memory controller must be configured for 8-bit mode All other configurations use 16-bit mode

All signals on this interface must be connected one-to-one with the corresponding signals on the DDR SDRAM device When using only one 8-bit device the DDR_UDQS DDR_UDQSn DDR_UDM and DDR_DQ[158] signals must be left unconnected When using DDR2 SDRAM devices that has only four banks the DDR_BA[2] signal must be left unconnected

When using four 8-bit devices or two 16-bit devices the CS1 memory modules must be placed in-between the VSC7511 device and the CS0 memory modules so that the DDR-DQS DDR-DM and DDR_DQ signals pass the CS1 devices first before reaching the CS0 devices

The placement of the VSC7511 interface signals is optimized for point-to-point routing directly to a single DDR3 16-bit SDRAM

Figure 109 bull 16-Bit DDR3 SDRAM Point-to-Point Routing

Because reflections are absorbed by the devices keep the physical distance of all the SDRAM interface signals as low as possible Omit external discrete termination on the address command control and clock lines

When routing the DDR interface attention must be paid to the skew primary concern is skew within the byte lane between the differential strobe and the single-ended signals Skew recommendations for the DDR interface are listed in the following table

Table 249 bull Recommended Skew Budget

Description Signal Maximum SkewSkew within byte lane 0 DDR_LDQSDDR_LDQSn 50 ps

Skew within byte lane 1 DDR_UDQSDDR_UDQSn 50 ps

DRAMDevice

Switch

Address

Clock

Address

Data Lane

Design Guidelines


Power supply recommendations

bull Use a shared voltage reference between the VSC7511rsquos devicersquos DDR_Vref supply and the DDR devicersquos reference voltage

bull Generate the DDR_Vref from the VDD_IODDR supply using a resistor divider with value of 1 kΩ and an accuracy of 1 or better

bull Use a decoupling capacitance of at least 01 microF on the supply in a manner similar to VDD_IODDR and VSS to ensure tracking of supply variations however the time constant of the resistor divider and decoupling capacitance should not exceed the nRESET assertion time after power on

bull VDD_IODDR pins must not share vias Use at least one through for each VDD_IODDR pin The extra inductance from sharing vias may cause bit errors in the DDR interface

Routing recommendations

bull DDR_CKDDR_CKn must be routed as a differential pair with a 100 Ω differential characteristic impedance

bull DDR_xDQSDDR_xDQSn must be routed as a differential pair with a 100 Ω differential characteristic impedance

bull To minimize crosstalk the characteristic impedance of the single-ended signals should be determined predominantly by the distance to the reference plane and not the distance to the neighboring traces

bull The crosstalk should be below ndash20 dBbull If the DDR interface is not used connect VDD_IODDR and DDR_VREF to ground Leave all other DDR

signals unconnected (floating) VDD_IODDR can also be left floating however DDR_VREF must also then be left floating

1037 Thermal Diode External ConnectionThe internal on-die thermal diode can be used with an external temperature monitor to easily and accurately measure the junction temperature of this device

The thermal diode is extremely sensitive to noise To minimize the temperature measurement errors follow these guidelines

bull Route the THERMDC and THERMDA signals as a differential pair with a differential impedance less than 100 Ω

bull Place the external temperature monitor as close as is possible to this devicebull Add a 47 Ω resistor in series with the external temperature monitor supply to filter noisebull When using a grounded sensor circuit place a de-coupling capacitor between the external

temperature monitor supply pin and the THERMDC signal For more information about using a grounded sensor circuit see Figure 99 page 271

Place the capacitor close to the external temperature sensor as shown in the following illustration

Skew within address command and control bus DDR_CKDDR_CKnDDR_nRASDDR_CKEDDR_ODT[10]DDR_nCASDDR_nWEDDR_BA[20]DDR_A[150]

100 ps

Skew between control bus clock and byte lane 0 clock DDR_CKDDR_CKnDDR_LDQSDDR_LDQSn

1250 ps

Skew between control bus clock and byte lane 1 clock DDR_CKDDR_CKnDDR_UDQSDDR_UDQSn

1250 ps

Control bus differential clock intra-pair skew DDR_CKDDR_CKn 5 ps


Description Signal Maximum Skew

Design Guidelines


Connect the external temperature monitor VSS pin directly to the THERMDC pin which has the connection to VSS as shown in the following illustration Do not connect the external temperature monitor VSS pin to the global VSS plane

Figure 110 bull External Temperature Monitor ConnectionSupply

ExternalTemperature

Monitor

Sense

VSC741x VDD

VSSVSS

VSS

ThermDA

ThermDCData Bus

Ordering Information


11 Ordering Information



The following table lists the ordering information for the VSC7511 device

Table 250 bull Ordering Information

Part Order Number DescriptionVSC7511XMY Lead-free (Pb-free) 172-pin dual-row plastic quad flat no-lead (QFN)

package with an exposed pad 13 mm times 13 mm body size 05 mm pin pitch and 09 mm maximum height

1 Revision History

11 Revision 42

12 Revision 41

13 Revision 40

14 Revision 21

15 Revision 20

2 Product Overview

21 General Features

211 Layer 2 Switching

212 Layer 2 Multicast

213 Quality of Service

214 Security

215 Management

216 Product Parameters

22 Applications

23 Functional Overview

231 Frame Arrival

232 Basic and Advanced Frame Classification

233 Versatile Content Aware Processor (VCAP)

234 Policing

235 Layer-2 Forwarding

236 Shared Queue System and Egress Scheduler

237 Rewriter and Frame Departure

238 CPU Port Module

239 Synchronous Ethernet and Precision Time Protocol

2310 CPU System and Interfaces


31 Port Numbering and Mappings

311 Supported SerDes Interfaces

312 PCIe Mode

313 Logical Port Numbers

32 Port Modules

321 MAC

322 PCS

33 SERDES1G

331 SERDES1G Basic Configuration

332 SERDES1G Loopback Modes

333 Synchronous Ethernet

334 SERDES1G Deserializer Configuration

335 SERDES1G Serializer Configuration

336 SERDES1G Input Buffer Configuration

337 SERDES1G Output Buffer Configuration

338 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX

339 Energy Efficient Ethernet

3310 SERDES1G Data Inversion

34 SERDES6G











3411 SERDES6G Signal Detection Enhancements

3412 High-Speed IO Configuration Bus

35 Copper Transceivers

351 Register Access

352 Cat5 Twisted Pair Media Interface

353 Wake-On-LAN and SecureOn

354 Ethernet Inline Powered Devices

355 IEEE 8023af PoE Support

356 ActiPHYtrade Power Management

357 Testing Features

358 VeriPHYtrade Cable Diagnostics

36 Statistics

361 Port Statistics

362 Accessing and Clearing Counters

37 Basic Classifier

371 General Data Extraction Setup

372 Frame Acceptance Filtering

373 QoS DP and DSCP Classification

374 VLAN Classification

375 Link Aggregation Code Generation

376 CPU Forwarding Determination

38 VCAP

381 Port Configuration

382 VCAP IS1

383 VCAP IS2

384 VCAP ES0

385 Range Checkers

386 VCAP Configuration

387 Advanced VCAP Operations

39 Analyzer

391 MAC Table

392 VLAN Table

393 Forwarding Engine

394 Analyzer Monitoring

310 Policers

3101 Policer Allocation

3102 Policer Burst and Rate Configuration

311 Shared Queue System

3111 Buffer Management

3112 Frame Reference Management

3113 Resource Depletion Condition

3114 Configuration Example

3115 Watermark Programming and Consumption Monitoring

3116 Advanced Resource Management

3117 Ingress Pause Request Generation

3118 Tail Dropping

3119 Test Utilities


312 Scheduler and Shapers

3121 Scheduler Element

3122 Egress Shapers

3123 Deficit Weighted Round Robin

3124 Round Robin

3125 Shaping and DWRR Scheduling Examples

313 Rewriter

3131 VLAN Editing

3132 DSCP Remarking

3133 FCS Updating

3134 PTP Time Stamping

3135 Special Rewriter Operations

314 CPU Port Module

3141 Frame Extraction

3142 Frame Injection

3143 Node Processor Interface (NPI)

3144 Frame Generation Engine for Periodic Transmissions

315 VRAP Engine

3151 VRAP Request Frame Format

3152 VRAP Response Frame Format

3153 VRAP Header Format

3154 VRAP READ Command

3155 VRAP WRITE Command

3156 VRAP READ-MODIFY-WRITE Command

3157 VRAP IDLE Command

3158 VRAP PAUSE Command

316 Layer 1 Timing

317 Hardware Time Stamping

3171 Time Stamp Classification

3172 Time of Day Generation

3173 Hardware Time Stamping Module

3174 Configuring IO Delays

318 Clocking and Reset

3181 Pin Strapping


41 VCore-Ie Configurations


421 Watchdog Timer

43 Shared Bus

431 VCore-Ie Shared Bus Arbitration

432 Chip Register Region

433 SI Flash Region

434 PCIe Region

435 Starting the VCore-Ie CPU

436 Accessing the VCore-Ie Shared Bus

437 Paged Access to VCore-Ie Shared Bus

438 Software Debug and Development

44 VCore-Ie CPU

45 Load on-chip memory with code-image For more information see External CPU Support

451 Register Access and Multimaster Systems

452 Serial Interface in Slave Mode

453 MIIM Interface in Slave Mode

454 Access to the VCore Shared Bus

455 Mailbox and Semaphores

46 PCIe Endpoint Controller

461 Accessing Endpoint Registers

462 Enabling the Endpoint

463 Base Address Registers Inbound Requests

464 Outbound Interrupts

465 Outbound Access

466 Power Management

467 Device Reset Using PCIe

47 Frame DMA

471 DMA Control Block Structures

472 Enabling and Disabling FDMA Channels

473 Channel Counters

474 FDMA Events and Interrupts

475 FDMA Extraction

476 FDMA Injection

477 Manual Mode

48 VCore-Ie System Peripherals

481 SI Boot Controller

482 SI Master Controller

483 Timers

484 UARTs

485 Two-Wire Serial Interface

486 MII Management Controller

487 GPIO Controller

488 Serial GPIO Controller

489 Fan Controller

4810 Temperature Sensor

4811 Memory Integrity Monitor

4812 Interrupt Controller

5 Features

51 Switch Control

511 Switch Initialization

52 Port Module Control

521 Port Reset Procedure

522 Port Counters

53 Layer-2 Switch

531 Basic Switching

532 Standard VLAN Operation

533 Provider Bridges and Q-in-Q Operation

534 Private VLANs

535 Asymmetric VLANs

536 Spanning Tree Protocols

537 IEEE 8021X Network Access Control

538 Link Aggregation

539 Simple Network Management Protocol (SNMP)

5310 Mirroring

54 IGMP and MLD Snooping

541 IGMP and MLD Snooping Configuration

542 IP Multicast Forwarding Configuration

55 Quality of Service (QoS)

551 Basic QoS Configuration

552 IPv4 and IPv6 DSCP Remarking

553 Voice over IP (VoIP)

56 VCAP Applications

561 Notation for Control Lists Entries

562 Ingress Control Lists

563 Access Control Lists

564 Source IP Filter (SIP Filter)

565 DHCP Application

566 ARP Filtering

567 Ping Policing

568 TCP SYN Policing

57 CPU Extraction and Injection

571 Forwarding to CPU


573 Frame Injection

574 Frame Extraction and Injection Using An External CPU

6 Registers


71 DC Specifications

711 Internal Pull-Up or Pull-Down Resistors

712 Reference Clock Inputs

713 PLL Clock Outputs

714 SERDES1G

715 SERDES6G

716 GPIO SI JTAG and Miscellaneous Signals

717 Thermal Diode

72 AC Specifications

721 REFCLK Reference Clock (1G and 6G Serdes)


723 SERDES1G

724 SERDES6G

725 Reset Timing Specifications

726 MIIM Timing Specifications

727 SI Boot Timing Master Mode Specifications

728 SI Timing Master Mode Specifications

729 SI Timing Slave Mode Specifications

7210 JTAG Interface Specifications

7211 Serial IO Timing Specifications

7212 Recovered Clock Outputs Specifications

7213 Two-Wire Serial Interface Specifications

7214 IEEE1588 Time Tick Output Specifications

73 Current and Power Consumption

74 Operating Conditions

741 Power Supply Sequencing

75 Stress Ratings

8 Pin Descriptions

81 Pin Diagram

82 Pins by Function


91 Package Drawing

92 Thermal Specifications

93 Moisture Sensitivity


101 Power Supplies

102 Power Supply Decoupling

1021 Reference Clock

1022 Single-Ended REFCLK Input

103 Interfaces

1031 General Recommendations

1032 SerDes Interfaces (SGMII 25GQSGMII)

1033 Serial Interface

1034 PCI Express Interface


1036 DDR3 SDRAM Interface

1037 Thermal Diode External Connection



ANALOG REF_FILT 152 A ABIAS Analog Copper media reference filter pin Connect a 10 μF external capacitor between pin and ground

ANALOG REF_Rext 153 A ABIAS Analog Copper media reference external pin Connect a 20 kΩ (1) resistor between pin and ground

ANALOG SERDES_Rext_0 85 A Analog Analog Analog bias calibration Connect an external 620 Ω plusmn1 resistor between SERDES_Rext_1 and SERDES_Rext_0

ANALOG SERDES_Rext_1 86 A Analog Analog bias calibration Connect an external 620 Ω plusmn1 resistor between SERDES_Rext_1 and SERDES_Rext_0



ANALOG VSS 119 A Analog


CLOCK CLKOUTPLL_N 79 O LVDS PLL clock out Leave floating if not used

CLOCK CLKOUTPLL_P 81 O LVDS PLL clock out Leave floating if not used

CLOCK REFCLK_N 82 I TD LVDS Reference clock inputsThe inputs can be either differential or single-endedIn differential mode (LVDS) REFCLK_P is the true part of the differential signal and REFCLK_NREFCLK_N is thecomplement part of the differential signalIn single-ended mode (LVCMOS) REFCLK_P is used as single-ended LVTTL input REFCLK_N should beleft floating and the PLL registers must be configured for singleendedoperationRequired applied frequency depends on REFCLK_CONF[20] input state

CLOCK REFCLK_P 84 I TD LVDS Reference clock inputsThe inputs can be either differential or single-endedIn differential mode (LVDS) REFCLK_P is the true part of the differential signal and REFCLK_NREFCLK_N is thecomplement part of the differential signalIn single-ended mode (LVCMOS) REFCLK_P is used as single-ended LVTTL input REFCLK_N should beleft floating and the PLL registers must be configured for singleendedoperationRequired applied frequency depends on REFCLK_CONF[20] input state























JTAG JTAG_nTRST 35 I PUST3V CMOS_25 JTAG test reset active low For normal device operation JTAG_nTRST should be pulled low

JTAG JTAG_TCK 38 I PUST3V CMOS_25 JTAG clock

JTAG JTAG_TDI 37 I PUST3V CMOS_25 JTAG test data in

JTAG JTAG_TDO 34 O OZ 3V CMOS_25 JTAG test data out

JTAG JTAG_TMS 36 I PUST3V CMOS_25 JTAG test mode select

MISC nRESET 33 I PUST3V CMOS_25 Global device reset active low

PHY P0_D0N 141 IO ADIFF Analog 25 TxRx channel A negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the A data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 2

PHY P0_D0P 143 IO ADIFF Analog 25 TxRx channel A positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the A data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 1

PHY P0_D1N 138 IO ADIFF Analog 25 TxRx channel B negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the B data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 6

PHY P0_D1P 142 IO ADIFF Analog 25 TxRx channel B positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the B data channel In all three speeds these pins generate the secondary side signal normally connected to RJ-45 pin 3

PHY P0_D2N 135 IO ADIFF Analog 25 TxRx channel C negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the C data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 5 (pins not used in 10100 Mbps modes)

PHY P0_D2P 137 IO ADIFF Analog 25 TxRx channel C positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the C data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 4 (pins not used in 10100 Mbps modes)

PHY P0_D3N 132 IO ADIFF Analog 25 TxRx channel D negative signalNegative differential signal connected to the negative primary side of the transformerThis pin signal forms the negative signal of the D data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 8 (pins not used in 10100 Mbps modes)

PHY P0_D3P 134 IO ADIFF Analog 25 TxRx channel D positive signalPositive differential signal connected to the positive primary side of the transformerThis pin signal forms the positive signal of the D data channel In 1000-Mbps mode these pins generate the secondary side signal normally connected to RJ-45 pin 7 (pins not used in 10100 Mbps modes)

























POWER NC 45 P

POWER NC 53 P

POWER NC 71 P

POWER NC 87 P

POWER NC 88 P

POWER NC 89 P

POWER NC 90 P

POWER NC 91 P

POWER NC 94 P

POWER NC 106 P

POWER NC 111 P

POWER NC 113 P

POWER NC 115 P

POWER NC 117 P

POWER NC 121 P

POWER NC 123 P

POWER NC 124 P

POWER NC 125 P

POWER NC 126 P

POWER NC 128 P

POWER NC 171 P

POWER VDD 43 P

POWER VDD 23 P

POWER VDD 1 P

POWER VDD 136 P

POWER VDD 130 P

POWER VDD 122 P

POWER VDD 120 P

POWER VDD 118 P

POWER VDD 116 P

POWER VDD 114 P

POWER VDD 112 P

POWER VDD 110 P

POWER VDD 108 P

POWER VDD 107 P

POWER VDD 105 P

POWER VDD 104 P

POWER VDD 103 P

POWER VDD 102 P

POWER VDD 101 P

POWER VDD 100 P

POWER VDD 99 P

POWER VDD 98 P

POWER VDD 97 P

POWER VDD 96 P

POWER VDD 95 P

POWER VDD 93 P

POWER VDD 92 P

POWER VDD 83 P

POWER VDD 61 P

POWER VDD 47 P

POWER VDD_AH 166 P Analog 25


POWER VDD_AL 168 P Analog 10


POWER VDD_IO 39 P

POWER VDD_IO 24 P IO_VDD_25



POWER VDD_IO 80 P

POWER VDD_IO 59 P

POWER VDD_VS 74 P

POWER VDD_VS 68 P

POWER VDD_VS 63 P

POWER VDD_VS 56 P

POWER VDD_VS 50 P

POWER VDDA 42 P

POWER VDDA 41 P

POWER VDDA 40 P

POWER VDDA 77 P

POWER VDDA 65 P

POWER VDDA 58 P

POWER VDDA 48 P

Reserved RESERVED_0 133 A Analog Analog 25 Leave floatingto testpoint


Reserved RESERVED_3 3 P Analog Tie to VSS

SERDES1G S4_RXN 49 I TD LVDS Differential 1G data inputs

SERDES1G S4_RXP 51 I TD LVDS Differential 1G data inputs

SERDES1G S4_TXN 44 O LVDS Differential 1G data outputs

SERDES1G S4_TXP 46 O LVDS Differential 1G data outputs

SERDES1G S5_RXN 55 I TD LVDS Differential data inputs 1G25G

SERDES1G S5_RXP 57 I TD LVDS Differential data inputs 1G25G

SERDES1G S5_TXN 52 O LVDS Differential data outputs 1G25G

SERDES1G S5_TXP 54 O LVDS Differential data outputs 1G25G





SERDES6G S7_RXN 70 I TD CML Differential 1G data inputs

SERDES6G S7_RXP 72 I TD CML Differential 1G data inputs

SERDES6G S7_TXN 67 O CML Differential data outputs 1G25G

SERDES6G S7_TXP 69 O CML Differential data outputs 1G25G



SERDES6G S8_TXN 73 O CML Differential data outputs PCIe2G51G

SERDES6G S8_TXP 75 O CML Differential data outputs PCIe2G51G

SI SI_CLK 32 IO ST 3V CMOS_25 Slave mode Input receiving serial interface clock from external masterMaster mode Output driven with clock to external deviceBoot mode Output driven with clock to external serial memory device

SI SI_DI 29 I ST 3V CMOS_25 Slave mode Input receiving serial interface data from external masterMaster mode Input data from external deviceBoot mode Input boot data from external serial memory device

SI SI_DO 30 O OZ 3V CMOS_25 Slave mode Output transmitting serial interface data to externalmasterMaster mode Output data to external deviceBoot mode Output boot control data to external serial memory device

SI SI_nCS0 31 IO ST 3V CMOS_25 Slave mode Input used to enable SI slave interface0 = Enabled1 = DisabledMaster mode Output driven low while accessing external deviceBoot mode Output driven low while booting from EEPROM or serialflash to internal VCore-III CPU system Released when booting iscompleted