Vsia Test Access

8/2/2019 Vsia Test Access

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VSI AllianceTM

Test Access Architecture

Standard

Version 1.0(Test 2 1.0)

Manufacturing-Related TestDevelopment Working Group

September 2001


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Copyright 2000-2001 by

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VSI Alliance (TST 2 1.0)

Copyright 2000 - 2001 by the VSI Alliance, Inc. i

All Rights Reserved. VSIA CONFIDENTIAL LICENSED DOCUMENT

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Test Access Architecture StandardVersion 1.0

(TST 2 1.0)

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The VSI Alliance is the copyright owner of the document identifiedabove.

The VSI Alliance will make royalty-free copyright licenses for thisdocument available to VSI Alliance Members. Non-members mustpay a fee for the copyright license.

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Copyright 2000 - 2001 by the VSI Alliance, Inc. ii



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Copyright 2000 - 2001 by the VSI Alliance, Inc. iii


Manufacturing-Related TestDevelopment Working Group

Company Members of the Development Working Group:

Individual Member of the Development Working Group:

Prab Varma

Chairman:

Ramamurti Chandramouli

TechnicalEditors:

Samy Makar

Herbert Leeds

Advantest ARM

Cadence Design Systems ECSI

Fujitsu Limited Agilent Technologies

Hitachi Semiconductor America LogicVision

LSI Logic Mentor Graphics

National Semiconductor Oki Electric Industry Co.

Palmchip Philips Semiconductor

Schlumberger Technologies Sonics

STMicroelectronics Toshiba

Synopsys


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Copyright 2000 - 2001 by the VSI Alliance, Inc. iv



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Copyright 2000 - 2001 by the VSI Alliance, Inc. v


Revision History

06May99 Version 0.01 Samy Makar Wrote initial version

27May99 Version0 .02 Samy Makar Fixed TAM figures to reflect separate clock instead of clk/

4, added Figure 8, added numbers to sections, minor edits

02Jun99 Version 0.03 Samy Makar Renamed Section 2 to VC Requirements, changed Section

3 to VC Implementation, moved Section 3.1 to Section 3,

edited based on last meeting discussion, deleted Section3.2 and beyond to reflect only issues discussed

03Nov99 Version 0.04 Samy Makar Restarting using P2_12

17Nov99 Version 0.05 Samy Makar Added all sections from P2_12

18Nov99 Version 0.06 Samy Makar Made table format changes and fixed figures

10Dec99 Version 0.07 Pat Made most of the changes based on phone meeting of 08Dec99, and added an introduction

21Dec99 Version 0.08 Samy Added global tristate, made changes to figures, correctedminor errors.

27Jan00 Version 0.09 Samy Made corrections from feedback of task force e-mail

08Mar00 Version 0.10 Samy Made changes based on discussion from 29Mar00 meeting

11May00 Version 0.11 Samy Makar Made changes based on DWG feedback meeting of

26Apr00

04Oct00 Version 0.12 Samy Makar Made changes based on P1500 feedback

29Mar01 Version 0.13 Samy Makar Made changes based on participating company reviews

with task force discussion

11Apr01 Version 0.14 Samy Makar Made changes based on feedback from DWG feedback onVersion 0.13 (pages 7, 8, 15, 21)

22Apr01 Version 1.0 Editorial Staff Converted to FrameMaker, edited

26Apr01 Version 1.0 Editorial Staff Applied editors written input

30Apr01 Version 1.0 Editorial Staff Applied editors written input

04May01 Version 1.0 Editorial Staff Applied clarifications from review by Chandramouli

11July01 Version 1.0 Editorial Staff Edit/update graphics

12July01 Version 1.0 Editorial Staff Made formatting edits


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Copyright 2000 - 2001 by the VSI Alliance, Inc. vi



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Copyright 2000 - 2001 by the VSI Alliance, Inc. vii


Contents

1. VSI Alliance Test Access Architecture. . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Introduction VC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32.1 Structure of This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 VSIA Test Standards and IEEE P1500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3. Requirements for VC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.4 Wrapper Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4.1 Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.4.2 Wrapper Cells With Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4.3 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6 Test Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.6.1 Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.2 Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.3 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.4 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.1 Normal Operation Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 Safe State (Isolation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 External Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4 Internal Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.1 Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.2 Iddq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.4.3 Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.4 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Appendix

A.1 Extest Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

A.1.1 Example Verilog model soc.v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25A.1.2 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


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Copyright 2000 - 2001 by the VSI Alliance, Inc. viii


List of Tables

Table 1: VSIA VC Ports for VCs with TCB . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2: VSIA VC Ports for VCs with Normal VC Ports . . . . . . . . . . . . . . . . . 9

Table 3: VSIA VC Ports for VCs With No TCB . . . . . . . . . . . . . . . . . . . . . . . 10Table 4: Normal VC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5: Example of Internal Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 6: Input Wrapper Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 7: Output Wrapper Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8: Input Wrapper Cell With 0-Output During Shift . . . . . . . . . . . . . . . . 15

Table 9: Input Wrapper Cell Definition With 0-Protection . . . . . . . . . . . . . . . 15Table 10: Input Wrapper Cell Definition With 1-Protection . . . . . . . . . . . . . . 16

Table 11: Input Wrapper Cell Definition With External Source . . . . . . . . . . . 17

Table 12: TCB Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 13: TCB Cell Definition With Capture . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 14: Example of TCB Cell Assignments for Instructions . . . . . . . . . . . . 23

List of FiguresFigure 1: Wrapper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2: An Architecture for Test Access Between VCs . . . . . . . . . . . . . . . . . 8Figure 3: Example of Input Wrapper Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4: Example of Output Wrapper Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5: Wrapper Cells in Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 6: Examples of Input Wrapper Cell With Protection . . . . . . . . . . . . . . 16

Figure 7: Example of Wrapper With External Source . . . . . . . . . . . . . . . . . . . 17

Figure 8: Global Control of VC Tristate Outputs . . . . . . . . . . . . . . . . . . . . . . 17Figure 9: Example Bypass Register with Anti-Skew Latch . . . . . . . . . . . . . . . 18

Figure 10: TCB Register Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 11: TCB Cell Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 12: TCB Cell With Capture Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13: TCB Register With Capture Option . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14: Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


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2. Introduction VC

Increasing complexity as well as time-to-market pressures are forcing shorter ASIC design cycles. Million-gate

ASIC designs are not feasible in such time frames using traditional gate-based designs. More and more larger

designs are shifting to the use of pre-designed virtual components (VC). VCs are developed to be either soft VCsor hard VCs. Soft VCs are usually HDL (Hardware Description Language) models of complex functions that are

reconfigurable and that can be targeted towards any technology. Hard VCs are models that are technology-specific

implementations of various complex functions and cannot be modified.

VC-based design methodology is well suited for higher levels of integration, as well as a system-on-silicon

concept.The designer can build the system-on-a-chip using various VCs (similar to the lower-level cells in a

library), that are connected using glue logic. The resulting densely packed SoC presents a formidable testchallenge.

Test is one of the significant barriers faced in the SoC design environment. The test strategy should address the

access and test of the VC after it is embedded in the chip, and the integration of such VCs with user logic andembedded memories at the chip level. The main issues include testing individual VCs, interaction between VCs,

isolation of the VCs, and the glue logic.

As designers move into the high-level, structured design environment, the VCs are delivered as RTL (RegisterTransfer Level) models. These models, also called soft VCs, enable end users to optimize the VCs for targeted

applications or as hard VCs with built-in testability. Many of the soft VCs are delivered to the end user without

any testability, since most of the current design-for-test (DFT) techniques (such as scan) are not suitable forimplementation at the RT level. In case of the hard VCs, the preferred DFT (design-for-test) approach is some

form of scan testing that has proven effective for manufacturing test.

For soft VCs, the VC vendors provide only functional vectors that verify VC functionality. In general, thesevectors are not targeted toward manufacturing test. Typically, the functional vectors do not satisfy the very high

fault coverage (>95%) requirement for manufacturing test. The system integrator then creates the manufacturing

test for the VC. These vectors, which are valid only at the VC I/O level, must be mapped to the chip I/O to ensuremanufacturability of the system chip. This is true for hard VCs too, where scan DFT is implemented. It becomes

difficult to access (control and observe) the VC I/O when it is embedded within a larger design, especially when

the VC I/Os are not directly accessible from the chip I/O. The lack of common VC test interface is another issuein accessing embedded VCs from chip I/O, especially when the designer has to use VCs with scan DFT from

multiple sources that may not conform to a common scan-test standard. Hence, a standard VC test access approach

becomes important both for reuse and for VC interoperability. At present, there are no standards that define theinterface for VC test access. Existing approaches are ad hoc and vary from design to design.

As the VC-based design environment grows, the lack of VC test access standards will definitely create a

bottleneck for manufacturing high-quality products. Recognizing this need, the VSIA Test DWG has created thisstandard that can be easily adopted by both VC developers and VC integrators.

2.1 Structure of This Document

This standard defines the architecture and a set of rules and recommendations for accessing the test structures of

embedded VCs.

Section 3 introduces a set of rules that specify various test modes required for testing embedded VCs. Section 4

describes the basic architecture for VC test access and the associated set of interface signals for test access.Sections 4.1, 4.2, and 4.3 specify the architecture requirement in terms of rules, recommendations andpermissions. Every VC must be wrapped using a wrapper register, which is needed to access the VC I/O from an

external source. Section 4.4 describes various types of input and output wrapper registers and the associated rules,

recommendations, and permissions. Section 4.5 describes the bypass register required to bypass the surroundingVCs when accessing a single VC. Section 4.6 describes a Test Control Block (TCB), which manages all the test

control signals that interface with the wrapped VC. This section also specifies all the rules , recommendations, and

permissions associated with the TCB and the interface signals.

Section 5 summarizes the control signals associated with various test modes that are described in Section 3.

Appendix A explains the implementation details for Extest operation.


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This standard does not specify any DFT solution for use by the VC internal structure.

2.2 VSIA Test Standards and IEEE P1500

With increasing demand for multiple functionalities in next generation SoC products, including wireless telecomand consumer electronic products, designers are rapidly adopting VC-based design methodology. However, the

lack of industry-wide standards for many aspects of Virtual Component/VC-based design, especially in test, poses

a challenge to designers who integrate Virtual Components from multiple sources without a standard interface.The need for a set of standards becomes critical especially when these emerging design methodologies are driven

by Virtual Component reuse.

Both VSIA and the IEEE P1500 Working group realized the need for test interoperability standard for embeddedVirtual Components to ensure test reuse and to enable plug-and-play at the chip level. There was general

agreement between the IEEE P1500 working group and the VSIA Manufacturing Test DWG on having a single

standard for test interoperability. Industry demand for a timely standard has prompted VSIA to provide a simplestandard that fills the need until the complete IEEE standard (wrapper and information model) is available. The

VSIA test DWG worked closely with the IEEE P1500 working group to ensure that the VSIA Test AccessStandard is compatible with IEEE P1500. It is the intent of the VSIA that the users of the VSIA Test AccessStandard are compliant with the IEEE P1500 wrappers when this becomes a standard. VSIA will specify the 1500

standard at that point.


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3. Requirements for VC Testing

3.1 Rule

A VC must have a minimum of four modes of operation: Normal Mode, Safe State (Isolation), External Test, andInternal Test.

3.2 Discussion

In order to completely test an SoC, each VC requires four modes of operation. The active mode of operation of aVC depends on the state of the control signals to the VC. In the case where an SoC contains multiple VCs, there

must be a sufficient number of control signals to control the mode of operation of each VC in the SoC. The four

modes of operation of a VC are as follows:

Normal Mode In this mode, the VC operates in its intended functional or operational mode. The Design

For Testability (DFT) structures in the VC are not activated.

Safe State (Isolation) Mode In this mode, the VC is in a safe state because it is isolated from thesurrounding logic or other VCs. Techniques for isolation are described in the isolation section of this

Specification External Test Mode In this mode, the VC is set up to allow testing of the interconnect wiring between

it and other VCs or the User-Defined Logic (UDL) in the SoC. This implies access to the outputs of the

VC (for driving the interconnects), as well as access of the inputs to the VC (to observe what travels on

the interconnects to the inputs of the VC).

Internal Test Mode In this mode, the VC itself is being tested. Of course, there could be multiple tests

that need to be applied to the VC, and therefore multiple modes that need to be assigned to internal test.


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4. Architecture

Achieving the VC requirements described in Section 3 implies a need to break the normal functional paths on the

SoC during testing time. This can be achieved by using the test wrapper register shown in Figure 1. As shown in

this figure, the wrapper register is made of wrapper cells. Each of the wrapper cells is connected to one of the portsof the VC, allowing a wrapper cell to drive an input of the VC or to capture the signal on an output of the VC.

In addition to the wrapper register, we also need a Test Control Block (TCB) for controlling the wrapper based on

the type of test being applied. A bypass register is also included to speed up the transfer of the vectors goingthrough the VCs. The full architecture is shown in Figure 2. Here, for simplicity, only two VCs are shown to

illustrate the communication between them. Table 1 gives l ist of all of the ports that are required, or are optional

for the wrapper. The first group of signals is required for all wrappers. The remaining signals may be required,depending on the type of test methods that are built into the VC itself. For example, VC_SI and VC_SO are

required only if scan is used as a test method for the VC.

Figure 1: Wrapper Register

VC

SI SO

Wrapper Cel l


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Figure 2: An Architecture for Test Access Between VCs

Wrappe

dVC

WP

_PI

WP

_SI

VC_

SI

Clocks

Asyncs

TC

_SI

VC

_SI_BYPASS

VC

_TDI_BYPASS

TC

_SO

VC_

SO

F

unc

_ou

t

Func

_in

VC

Tes

tCon

tro

lBloc

k

Wrapper

Reg

Wrappe

dVC

WP

_PI

WP

_SI

VC_

SI

Clocks

Asyncs

TC

_SI

VC

_SI_BYPASS

VC

_TDI_BYPASS

TC

_SO

VC_

SO

WP

_SO

VC

Tes

tCon

tro

lBloc

k

Wrapper

Reg

TCLK

TC

_RESET

TC

_SHIFT

TC

_UPDATE

VC

_SHIFT

B y p a s s

B y p a s s

UDL

Scan

Chain

Scan

Chain

BIST

Control

TC_

CAPTURE

WP

_SO

MAS

MAS

MAS

MAS

Scan

Chain

Scan

Chain

BIST

Control


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The wrapper register can be split into multiple parallel registers. Each register has one of the WP_SI bits as aninput, and one of the WP_SO bits as an output. (Figure 5 shows an example with three parallel registers.) The

number of parallel registers is left as a choice for the VC provider (or whoever is actually building the wrapper).

Regardless of the number of parallel registers, there should also be a mode that combines all the parallel wrapperchains into a single chain. Some VCs may require direct functional tests. Such VCs will have WP_PI port that will

have inputs coming directly from primary inputs of the chip. The response can still be captured in the wrapper

registers.

Table 1: VSIA VC Ports for VCs with TCB

Signal Name Required Description

WP_SI Yes Serial data input to wrapper register (n bits wide)

WP_SO Yes Serial data output from wrapper re gister (n bits wide)

TC_SI Yes Input to TCB

TC_SO Yes Output from TCB

TCLK Yes Clock controlling all memory elements in TCB

TC_RESET Yes Resets the TCB

TC_SHIFT Yes Sets the TCB in shift mode

TC_UPDATE Yes Updates the TCB

VC_SHIFT Yes Used to shift wrapper registers or scan chains

WP_CLK Clock-controlling memory elements of wrapper register (may

be TCLK or system clock)

WP_PI Functional Parallel load values for functional test

VC_SI Scan Scan inputs

VC_SO Scan Scan outputs

TC_CAPTURE Optional Only needed if capturing status in TCB

Yes required for all VCs

Scan required for VCs with scan

Optional Use of signal determined by VC provider

Table 2: VSIA VC Ports for VCs with Normal VC Ports

Signal Name Description

Clocks Clocks used to operate the VC

Asyncs Asynchronous signals such as resets

Func_in Functional inputs to VC that are not async



Optional Use of signal determined by VC provider


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As mentioned earlier, VC_SI and VC_SO are the inputs and outputs of the scan chains if they are used. TCLK,

TC_RESET, TC_SHIFT, TC_UPDATE, and TC_CAPTURE all control the Test Control Block. Details about theTest Control Block are given later. VC_SHIFT is a special input that is used to enable shift the scan chains or the

wrappers (or both) depending on the test mode.

Table 2 also lists ports that are used for normal VC operation. Most of the normal pins fall into the Func_in orFunc_out categories. These are normal functional inputs and outputs of the VC that will be accessed through the

wrapper cells. There are also some special inputs, clocks and asyncs which will not be accessed through thewrapper because of their nature of operation. Clocks are signals that drive control inputs of memory elements.Asyncs drive asynchronous sets and resets of memory elements, or any other special controls that require accurate

timing. The provider may, of course, synchronize such signals, and thus make it possible to add them to the

wrapper. Control of the clocks and asyncs will be the responsibility of the integrator, and thus should be welldocumented by the provider. Under certain conditions (described later), a wrapper may not require a TCB. In such

cases, the ports in Table 3 are needed.

Table 3: VSIA VC Ports for VCs With No TCB


WP_SI Yes Serial data input to wrapper register (n bits wide)

WP_SO Yes Serial data output from wrapper register (n bits wide)

WP_SHIFTMODE Yes Sets the wrapper cells into shift mode

WP_HOLD_IN Yes Sets the input wrapper cells in hold mode

WP_HOLD_OUT Yes Sets the output wrapper cells in hold mode

WP_BP Yes Bypasses the wrapper chains (required for a s ingle chain; can

be used if bypassing all wrapper chains)

WP_SINGLEWPMODE Yes Indicates that wrapper is hooked into a single chain

VC_SI Scan Scans inputs

VC_SO Scan Scans outputs

VC_BP Scan optional Bypasses the scan chains

Table 4: Normal VC Ports

Signal Name Description

Clocks Clocks used to operate the VC

Asyncs Asynchronous signals such as resets

Func_in Functional inputs to the VC that are not asynchronous

Func_out Functional outputs of the VC




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4.1 Rules WP_SI and WP_SO of the same VC shall be the same width.

VC_SI and VC_SO of the same VC shall be the same width.

A special mode shall be provided to make all wrappers appear as a single chain. WP_SI[0] will be theinput of such a chain, and WP_SO[0] will be the output.

The special single chain wrapper shall be bypassed.

Scan chain inputs and outputs need not be wrapped.

The Test Control Block (TCB) shall not be bypassed.

VC_SHIFT shall be used to shift scan chains and wrapper registers.

TCLK shall control all memory elements of TCB.

The VC provider shall specify which clock will be used for the wrapper cells. If more than one clock is

used, the VC provider shall specify the sequence of the clocks. (TCLK is preferred.)

If the VC has async signals, sufficient information shall be provided on how and when to control them.

This shall be done for all required test modes, and not just for the VC internal test modes.

4.2 Recommendations Scan chains and wrapper chains should end with anti-skew memory elements (output on the negative

edge). The anti-skew memory element should be before the output pin of the wrapper (after the mux). This is

shown in Figure 9 as MAS.

TCLK should be separate from the system clock.

TCLK should be used for the wrapper register cells and bypass registers.

VCs should have no async signals (or at least keep them to a minimum) in the functional design.

All wrapper chains should be bypassed. Only the single chain mode has to be bypassed. The regular

wrapper chains should be bypassed as well.

Scan chains should be of reasonable lengths. If scan chains are used, chains should be less than 500 scan elements,to avoid having very long chains that could become difficult or impossible for the integrator to have reasonably

sized chains at the top level. The number of scan chains should not be more than 32, as a very large number of

scan chains out of a VC complicates matters for the integrator and introduces unnecessary anti-skew elements. If

there are more than 16K scan elements, the 32-chain limit should be maintained, and longer (but balanced) chainsshould be maintained. Note that this recommendation is intended for current designs, and although the multi-chainphilosophy is expected to hold for future designs, the numbers used here may not scale.

4.3 Permissions WP_SI (and thus WP_SO) of different VCs do not have to be the same width.

VC_SI (and thus VC_SO) of different VCs do not have to be the same width.

Although wrapper cells are not required for scan chains, they may be added to the design. However,proper operation should be maintained.

The integrator may mix wrapper registers and scan chains to optimize overall test times. (See the dotted

lines in Figure 9.)

Scan chains may have different lengths.

The VC provider may share functional memory elements for wrapper cells.


22/41




There are several control signals that are used to control the wrapper register and bypass register. These signals

shall be generated by the TCB. Since these signals are internal to the wrapped VC, names and structures forgenerating them will not be mandated. An example of these signals are summarized in Table 5. Two important

signals that will be derived from these signals are: SCAN_SHIFT = VC_SCANMODE & VC_SHIFT

WP_SHIFT = WP_SHIFTMODE & VC_SHIFT

4.4 Wrapper Register

As explained earlier, the wrapper register is used to gain access to the boundaries of the VC. Even though Figur e 1illustrates the wrapper as a single chain, this would generally not be practical because of the large bandwidth ofdata that is required to apply the tests to all the VCs. The bandwidth problem is addressed in Figure 2 b y using an

input bus called WP_SI and an output bus called WP_SO. The actual number of bits is left as a choice to the

designer of the wrapper.

The wrapper register consists of wrapper cells. There are two types of wrapper cells: input wrapper cells and

output wrapper cells.

The definition of the input wrapper cell is given in Table 6. An example implementation is shown in Figure 3.Note that while the example shows an edge-triggered memory element, using LSSD or any other clocking scheme

is permitted.

Table 5: Example of Internal Control Signals


WP_SHIFTMODE Yes Sets the wrapper cells into shift mode

WP_HOLD_IN Yes Sets the input wrapper cells in hold modeSignal Name Required Description

WP_HOLD_OUT Yes Sets the output wrapper cells in hold mode

WP_BP Yes Bypasses the wrapper chains

WP_SAFE SafeWp Activates safety in wrapper cells

WP_PI_ACTIVE Func Hooks up external sources to VC wrapper cells

VC_ BP Scan Bypasses scan chains; required for scan designs only

VC_SCANMODE Scan Scan_mode signal, used to fix any scan violations in the VC.Optional

VC_BISTMODE BIST Sets the VC into BIST mode and fixes any BIST violation

problems



BIST required for VCs with BIST

SafeWP required if any safety wrapper cells are used


23/41




Figure 3: Example of Input Wrapper Cell

Table 6 defines three basic operations:

Shifting: During this operation the wrapper cell is loaded with values to be applied in a VC internal test.This operation is also used for shifting out results captured from an interconnect test.

Applying: After values have been shifted in to the wrapper, they need to be applied to test the VC. During

the application, the shift operation is stopped, so the SO remains unchanged regardless of the number of

clock pulses applied. This allows holding values for multiple cycles when applying an internal test,circumventing any multiple clocking problems within VCs.

Capturing: In this mode, the input wrapper cell captures values at the input of the VC (such as theinterconnect). This mode is also used for normal mode.

The definition of the output wrapper cell is very similar to that of the input wrapper cell. The two kinds of cells

are identical except for the naming of the inputs and outputs . An example implementation is shown in Figure 4.Note that while the example shows an edge-triggered memory element, using LSSD or any other clocking scheme

is permitted.

*VCO = VC Output

Table 6: Input Wrapper Cell Definition

Control

InputsOutputs Comment

Control

InputsOutputs

WP_SHIFT WP_HOLD_IN SO VCI

1 d SI - Shifts wrappers

0 1 SO- SO Applies wrapper values

0 0 Func_In Func_In Normal Op / Capture input to VC

Table 7: Output Wrapper Cell Definition

Control


Control

InputsOutputs

WP_SHIFT WP_HOLD_OUT SO Func_Out

1 d SI - Shifts wrappers


0 0 VCO VCO Normal Op / Capture VCO

F u n c _ i n

V C I n p u t

W P _ H O L D _ I NW P _ S H I F TS I

W P C L K S O

11


24/41




Figure 4: Example of Output Wrapper Cell

Table 7 defines three basic operations:

Shifting: During this operation the wrapper cell is loaded with values to be applied in an interconnecttest. This operation is also used for shifting out results captured from a VC internal test.

Applying: After values have been shifted in to the wrapper, they need to be applied to test the

interconnect. During the application, the shift operation is stopped, so that SO remains unchanged

regardless of the number of clock pulses applied. This allows holding values for multiple cycles whenapplying an interconnect test, circumventing any skew problems between VCs. Func_out has the value

of the wrapper cells.

Capturing: In this mode, the output wrapper cell captures values at the output of the VC. This mode is

also used for normal operation.

4.4.1 Rules

The input wrapper cell shall be defined as in Table 6.

The output wrapper cell shall be defined as in Table 7.

Figure 5 shows wrapper cells connected. In this figure, the wrapper cells on the left of the VC are input wrapper

cells and those on the right of the VC are output wrapper cells. While the figure shows the input wrappers

preceding the output wrappers, this is not an actual requirement. It is shown only for illustration.

Figure 5: Wrapper Cells in Action

V C O u t p u t

F u n c _ o u t

W P _ H O L D _ O U TW P _ S H I F TS I

W P _ C L K S O

11

Func_

out

Func_

in

VC

Output(VCO)

VCInput(VCI)

T C L K

W P _ S H I F T

W P _ H O L D _ I N W P _ H O L D _ O U T

W P _ S I W P _ S O

S I

S O

S O

S I

S I

S O

S O


25/41




4.4.2 Wrapper Cells With Protection

As the wrapper registers shift, random values are applied to VCI and Func_out. This could be a problem if the VCdoes not expect certain combinations of inputs, and such combinations could cause damage to the VC and the chip

overall. Another problem can occur while capturing interconnect tests in the input wrapper cells. If the VC is notprepared to handle arbitrary inputs, an interconnect test can cause damage to the VC and chip.

The first problem can be alleviated by filling in fixed values to the dont care outputs of the tables. The value

chosen will depend on the value that is safe for the VC. For example, the table below shows a wrapper cell whoseoutput is 0 when the wrapper register is shifting.

The second problem can be fixed with protection cells. Protection cells have a mode that prevents the output from

changing values. Table 8 and Table 9 s how input wrapper cells with 0-protection and 1-protection respectively.During an interconnect test, for example, WP_SAFE would be set to 1, so capturing the values in input wrappercells can cause no damage to the VC. Figure 6 shows example implementations. Note that, although the example

shows an edge-triggered memory element, using LSSD or any other clocking scheme is permitted

Table 8: Input Wrapper Cell With 0-Output During Shift

Control


Control

InputsOutputs

WP_SHIFT WP_HOLD_IN SO VCI

1 d SI 0 Shifts wrappers


0 0 Func_In Func_In Normal Op / Capture input to VC

Table 9: Input Wrapper Cell Definition With 0-Protection

Control


Control


WP_SAFE WP_SHIFT WP_HOLD_IN SO VCI

1 1 d SI 0 Shifts wrappers

1 0 1 SO- 0

1 0 0 VCO 0 Captures input to VC

0 1 d SI - Shifts wrappers

0 0 1 SO- SO Applies wrapper values

0 0 0 Func_In Func_In Normal Op


26/41




Figure 6: Examples of Input Wrapper Cell With Protection

4.4.3 Permissions

To avoid undesired inputs to the VC, the wrapper may contain protection cells as defined in Tables 9 and 10.

Some VC s may not have any DFT structures and can only be tested using functional tests. Even VCs with DFT

structures may also require functional tests if the DFT structures do not provide adequate coverage. For such VCs,

a special wrapper may be used to allow direct access to the inputs of the wrappers. In essence, these cells have anadditional data input, which can be connected to the primary input of the chip (or whatever source is used to drive

the functional vectors). This input is referred to as a parallel input, because no shifting in the wrapper registerswill be performed during the application of such a test. Table 11 shows the definition of such a wrapper cell. Anexample of a circuit is shown in Figure 7.

Table 10: Input Wrapper Cell Definition With 1-Protection

Control


Control


WP_SAFE WP_SHIFT WP_HOLD_IN SO VCI

1 1 d SI 1 Shifts wrappers

1 0 1 SO- 1

1 0 0 Func_In 1 Captures input to VC

0 1 d SI - Shifts wrappers

0 0 1 SO- SO Applies wrapper

values

0 0 0 Func_In Func_In Normal Op

Func_

in

VCInput

WP_HOLD_IN

W P_ SH I FTSI

W P C L K SO

11

W P _ S A F E

& Func_

in

VCInput

WP_HOLD_IN

W P_ SH I FTSI

W P C L K SO

11

W P _ S A F E

+

0 - s a f e C e l l 1 - s a f e C e l l


27/41




Figure 7: Example of Wrapper With External Source

If a wrapper cell has external source as well as protection, the external source operation will have

precedence over protection. For protection to be active, a VC user must turn off external source operation

(WP_PI_ACTIVE = 0).

If a VC has bidirectional ports or tristated ports, a signal called GLOBAL_TRI_OFF will be made

available by the VC provider. When this signal is active, all tristate drivers out of the VC will be turnedoff. (See Figure 8.) The integrator will make sure that this signal is activated at the appropriate times.

It is recommended not to use any tristates or bidirectionals at the outputs of a VC.

Figure 8: Global Control of VC Tristate Outputs

Table 11: Input Wrapper Cell Definition With External Source

Inputs Outputs Comment Inputs Outputs Comment

WP_PI_ACTIVE WP_SHIFT WP_HOLD_I

N

SO

(TCLK^)

VCI

1 d d - WP_PI Applying externalinput

0 1 d SI - Shifts wrapper

0 0 1 SO- SO Applies wrappervalues

0 0 0 VCO VCO Normal Op

Fun

c_

in

VCInput

WP_HOLD_IN

W P_ SHI FTSI

W P C L K SO

11

W P_ PI _ ACT I VE

1-safe Cel l

1

Out Wrapper

Out Wrapper

In Wrapper

&V C

GLOBAL_TRI_OFF


28/41




4.5 Bypass Register

The bypass register is used to improve test time by reducing the number of clock cycles needed to get test vectors

through the wrapper registers and scan chains. Data is captured on the rising edge of TCLK, and made availableon the negative edge of TCLK of the next cycle to avoid clock-skew problems. This requirement can be achieved

using the circuit Figure 9. Since the scan chains and wrapper registers also require anti-skew elements, they can

share the anti-skew element with the bypass registers. This is shown in Figure 9.

Figure 9: Example Bypass Register with Anti-Skew Latch

4.6 Test Control Block

The test control block manages all the control signals used by the wrapper register cells and the bypass register.

It also manages control signals used for internal DFT structures such as scan or BIST. The TCB can be viewed as

an instruction register, as the values shifted into the TCB determine the test performed. Under certain conditions(discussed later in this section) the TCB may be not be needed. Even though we are not mandating a particularimplementation, an example implementation will be used in the following discussion, to help describe the

functionality of the TCB. All rules, recommendations, and permissions apply to all implementations and not justto the one discussed here.

In our example implementation, the TCB consists of a number of TCB cells. Each cell corresponds to one of the

control signals of the VC. Since the contents of the TCB are control signals, the TCB needs to have a shadow

register to prevent random perturbations on control signals. The number of cells in the TCB depend on the testneeds for the individual VC. The definition of the TCB cell is shown in Table 12. The table shows two control

signals, TC_SHIFT and TC_UPDATE. When TC_SHIFT is 1, the TCB shifts, and when TC_UPDATE is 1, TCBupdates the values that were shifted in, applying them to the internals of the VC. If both TC_UPDATE and

TC_SHIFT are 0, then the TCB goes in to a pause mode (as in the JTAG pause states). TC_SHIFT and

TC_UPDATE should not both be 1 at the same time.

Table 12: TCB Cell Definition

Control

InputsOutputs Comments

Control

InputsOutputs Comments

TC_RESET TC_SHIFT TC_UPDATE SO

(TCLK^)

DO

(TCLKv)

1 - - 0 0 Resets to functional mode

0 1 0 SI DO- TCB shifts new instructions

0 0 1 SO- SO- TCB updates instructions

0 0 0 SO- DO- TCB pauses

- 1 1 - - Not allowed

F F

V C _ S O

W P _ S OV C _ S I

W P _ S I

W P_C LK

W P _ T D I _ B Y P A S S

W P _ S I _ B Y P A S S

Wrapper Regs

Scan Cha ins


29/41




An implementation example of the TCB cell is shown in Figure 10. Here, two flip-flops are used to implement the

TCB cell definition. The upper flip-flip is used to shift in the values, and the lower one is used for the update. TheTCB cells are combined together as in Figure 11 to form the TCB. The general structure of the TCB is similar to

that of any shift register with an update signal. To load instructions (such as control signals), TC_SHIFT is set to1, and TC_UPDATE is set to 0. TCLK is pulsed as many times as needed to shift in the instruction. Once that iscompleted, TC_SHIFT is set to 0, and TC_UPDATE is set to 1. A single cycle of TCLK is applied. The VC is

now in the appropriate test mode. The AND gates in Figure 12 are included to control shift operations of the

wrapper register or the scan chains. As pointed out in the beginning of the document, VC_SHIFT is a dynamicinput signal. The TCB cell corresponding the AND gate will determine if that dynamic signal is activated or not.

In other words, the TCB controls the dynamic signals operation. Waveforms for extest instruction are shown in

Appendix A.

Figure 10: TCB Register Sample

Figure 11: TCB Cell Implementation

The circuit in Figure 11 shows the minimum requirements for the TCB. The TCB may also be used to capture

status values to be shifted out. If this feature is used, the status bits should be clearly defined. Also, the status bitshould not be expected until the test is completed. An example of where capture may be used is in BIST. A bit

may be captured to indicate the status of the BIST test. The result of the test is not needed until it is completed.The definition of the TCB cell with capture is shown in Table 13, the example circuit in Figure 12. The complete

circuit is shown in Figure 13. In addition to the operations described for the circuit in Figure 11, the circuit inFigure 13 has the capture feature. To capture status values, set TC_CAPTURE to 1 for one TCLK cycle, then setTC_CAPTURE to 0, and TC_SHIFT to 1. Apply as many TCLK cycles as needed.

V C _ S H I F T

T C _ S H I F T

T C _ S I

T C _ U P D A T E

T C _ R E S E T

T C _ S H I F T

S I

T C _ U P D A T E

D O

S O

T C L K

T C _ S H I F T

S I

T C _ U P D A T E

D O

S O

T C L K

T C _ S H I F T

S I

T C _ U P D A T E

D O

S O

T C L K

T C _ S H I F T

S I

T C _ U P D A T E

D O

S O

T C L K

T C _ C L K

T C _ S O

&&

F F1

F F

1

SO

D O

TC_SHIFT

T C _ U P D A T E T C_ R ES E T

TCLK

SI


30/41




Note : For TC_SHIFT, TC_UPDATE, and TC_CAPTURE, only one of these can be set to 1 at any one time.

Figure 12: TCB Cell With Capture Option

Figure 13: TCB Register With Capture Option

Table 13: TCB Cell Definition With Capture

Inputs Outputs Comment Inputs Outputs Comment Inputs

TC_RESET TC_SHIFT TC_UPDATE TC_CAPTURE SO

(TCLK^)

DO

(TCLKv)

1 - - - 0 0 Resets to functional mode

0 1 0 0 SI DO- TCB shifts new instruction

0 0 1 0 SO- SO- TCB updates instruction

0 0 0 1 DI DO- TCB captures statussignals

0 0 0 0 SO- DO- TCB pauses

F F1

F F

1

SO

D O

T C _ C A P T U R E

T C _ U P D A T E T C _ R E S E T

T C L K

D I

1

T C _ S H I F T

S I

T C _ C A P T U R E

T C _ S H I F T

T C _ S I

U P D A T E

T C _ R E S E T

S I

U P D A T E

DO

S O

T C L K

S I

U P D A T E

DO

S O

T C L K

S I

U P D A T E

DO

S O

T C L K

S I

U P D A T E

DO

S O

T C L K

T C _ C L K

T C _ S OS S SS C C C C


31/41




4.6.1 Rules TC_SHIFT and TC_UPDATE shall be treated as separate signals to allow for pausing.

An anti-skew memory element is required at the end of the TCB.

The anti-skew memory element should not be counted as part of the size of the TCB.

Reset should put the VC in normal operation (all TCB cells = 0).

Not more than one of TC_SHIFT, TC_UPDATE, and TC_CAPTURE should be active in the same cycle. TCLK will be used to operate the TCB.

A TCB is required if more than the minimum number of control bits are needed for the VC.

If a TCB is not used, the names given in Table 12 will be used. If a TCB is used, control signals in

Table 13 are internal to the VC, and thus names are not mandated (although it is recommended to use thesame names).

If a TCB is not used, the timing information of each of the control signals needs to be completely

specified. It will be left to the integrator to connect these control signals.

4.6.2 Note

The integrator for the TCB is optional in the very simple cases. However, if any complex structure is included(such as BIST and protection wrappers), then a TCB is required. Scan is an interesting special case. Even though

VC_SCANMODE will not be available for a TCB-free VC, scan can still operate using VC_SHIFT signal(required in any case, to control wrapper cells). The only catch is that the scan chains and wrapper cells will alwaysshift together.

4.6.3 Permissions The VC integrator may hook up TC_UPDATE to the inverse of TC_SHIFT if it is determined that no

pausing is necessary.

The capture of status bits in the TCB above is an optional feature.

Additional instructions and control bits may be added to implement additional test functions notdescribed in this document.

4.6.4 Recommendations

A VC should have a TCB. Avoid the use of TCB-free VCs.

The TCB cells should implement individual control bits. Decoding of control bits is allowed as long asthe result is deglitched.

TCLK should be separate from the system clock.

Avoid async signals (or keep them to a minimum) in the functional design.


32/41





33/41




5. Instructions

Section 4 describes the architecture for test access. Table 5 shows a summary of the control signals. There are

many ways to generate these control signals. The recommended approach is to assign each control bit to one of

the TCB cells. Even though this may result in more than a minimum number of TCB cells, it allows for maximumflexibility in control of the VC. In such an architecture, the values shifted into the TCB define an instruction that

sets the VC into the appropriate test mode. Several instructions are required, which correspond directly to the VC

requirements described in Section 3. Table 14 shows the TCB cell settings required for the different instructions.The rest of this section describes the different instructions in some detail.

5.1 Normal Operation InstructionIn normal operation, the VC operates in its functional mode. The instruction for normal operation is an all-0

instruction. This instruction can be activated by either shifting in all 0s into the TCB, or by setting TC_RESET to1. During normal operation, it is recommended that the wrappers and bypass registers hold their values, and that

TCLK is turned off.

5.2 Safe State (Isolation)

When this instruction is loaded, the VC should be in a safe state as it is not being tested. All flip-flops should haveknown states, and all busses should be conflict-free and not floating. Requirements for VC Testing (Section 3)describes safe state in more detail.

When in safe state, all bypass registers should be activated (WP_BP = 1 and VC_SO_BP = 1). This saves test time

for data that is flowing through the VC wrappers and chains. If protection wrapper cells are used, they should bein protection mode (WP_SAFE = 1).

5.3 External Test

External test is used to test the interconnect between VCs. This could be simple wires or UDL. We are reallytesting Func_in and Func_out in this test. For this test the following is required:

VC internals should be in a safe state.

VC_SO should be bypassed.

Table 14: Example of TCB Cell Assignments for Instructions

WP_SHIFT

MODE*

WP_HOLD_

IN*

WP_HOLD_

OUT*

WP_BP*

WP_SINGLE

WP

MODE*

WP_SAFE

WP_PI_ACTIVE

VC _BP VC_BIST_

MODE

VC_SCAN_

MODE

Normal 0 0 0 0 0 0 0 0 0 0

VC_EXT 1 0 1 0 0 1 0 1 0 0

EXTSinglewp

1 0 1 0 1 1 0 1 0 0

SCAN 1 1 0 0 0 1 0 0 0 1

Func X 0 0 0 0 X 1 0 0 0

BIST 1 1 1 0 0 1 0 0 1 1

Safe 0 0 X 1 0 1 0 1 0 0

*indicates required signals


34/41




WP_SO should not be bypassed.

VCs not involved in external test should be in safe state, and should be loaded with safe state instruction.

5.4 Internal Tests

Internal tests are tests for the VC itself. Multiple tests are permitted. During any internal test, all bypasses should

be disabled. Input wrapper cells are configured to drive the VC input. WP_SHIFTMODE should be set to 1.

VC_SHIFT determines whether the wrapper is shifting or holding.

5.4.1 Scan

For scan, VC_SCAN_MODE is set to 1, so that VC_SHIFT can be used to control the scan chains.

5.4.2 Iddq

VCs not under test should be in a low-power state. The pattern application depends on the type of patterns used

for Iddq testing. Thus, there is no specific instruction for Iddq in the specification.

5.4.3 Functional

Functional test is very important for legacy VCs that have no DFT structures. In functional test mode,

WP_PI_ACTIVE is set to 1 to allow direct access to all the VC inputs.

5.4.4 BIST

For BIST operation, VC_BIST_MODE should be set to 1. If multiple BIST modes are designed in the VC,

multiple bits may be used.


35/41




A. Appendix

A.1 Extest Example

In this appendix, a small example of application of extest operation is shown. The circuit contains two VCs, VC1and VC2. (Refer to Section A.1, Example Verilog Model soc.v, below.) The VCs have two inputs and twooutputs, so they have four wrapper cells each. The wrapper registers are hooked up as a single register betweenboth VCs. This is not necessarily the best way of doing it. The most effective application depends on the actual

design. The TCBs are hooked up in series to each other. The TCB consists of four bits in the order shown in Table

15. According to Table 14, the values in Table 15 are needed for extest.

The TCBs of both wrappers are also connected serially, so 0011 is shifted in serially (twice in a scan chain, thelast bit is shifted in first). In the waveform, this happens between times 25s and 175s. During that time, TC_SHIFT

is set high and VC_SHIFT is set low, making the TCB shift while the wrappers hold their values. After the TCB

shifting is complete, TC_UPDATE updates the TCB, and the scanning of the data begins. Here we only shift forfour cycles, to load up the first VC. VC_SHIFT is then turned off for one cycle, causing the second VC to capturethe functional input coming from the wrapper outputs of the first VC. The output is then shifted out. All the verilog

code is shown on the following pages, and the waveform is shown after that.

A.1.1 Example Verilog model soc.v

module soc (TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK,TC_SO,

a,b,x,y,z,

WP_SI, WP_SO);

input TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK; // inputs to TCB

output TC_SO; // outputs from TCB

// wrapper stuff

input WP_SI;

output WP_SO;

// SOC functional inputs

input a,b;

// SOC functional outputs

output x,y,z;

wrapped_vc VC1

(.TC_RESET(TC_RESET),.VC_SHIFT(VC_SHIFT),.TC_SHIFT(TC_SHIFT),

.TC_SI(TC_SI),.TC_UPDATE(TC_UPDATE),.TCLK(TCLK),.TC_SO(tc_so1),

.Func_in({a,b}), .Func_out({p,q}),

.WP_SI(WP_SI), .WP_SO(wp_so1));

Table 15:

Index in TCB Name Value

1 WP_SHIFTMODE 1

2 WP_HOLDOUT 1

3 WP_HOLDIN 0

4 WP_BP 0


36/41




wrapped_vc VC2


.TC_SI(tc_so1),.TC_UPDATE(TC_UPDATE),.TCLK(TCLK),.TC_SO(TC_SO),

.Func_in({p,q}), .Func_out({y,z}),

.WP_SI(wp_so1), .WP_SO(WP_SO));

endmodule

module antiskew (SI, clk, SO);

input SI, clk;

output SO;

reg SO;

always @(negedge clk) begin

SO = SI;

end

endmodule

module bypass_reg (WP_SI,WP_CLK, VC_WP_BYPASS);

input WP_SI,WP_CLK;

output VC_WP_BYPASS;

reg VC_WP_BYPASS;

always @(posedge WP_CLK) begin

VC_WP_BYPASS = WP_SI;

end

endmodule

module mas (WP_BP, VC_WP_BYPASS, WP_SO, WP_SO_beforeskew, WP_CLK);

input WP_BP, VC_WP_BYPASS, WP_SO_beforeskew, WP_CLK;

output WP_SO;

wire choice;

reg WP_SO;

assign choice = (WP_BP) ? VC_WP_BYPASS : WP_SO_beforeskew ;

always @(negedge WP_CLK) begin

WP_SO = choice;

end

endmodule

module oscillator (CLK);

output CLK;

reg CLK;

initial begin

$monitor ("%f %d\n",$time, CLK);


37/41




CLK = 0;

end

always begin

#10 CLK = ~CLK;

end

endmodule

module tcb(TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK,TC_SO,

WP_BP, WP_HOLD_IN, WP_HOLD_OUT, WP_SHIFT);

input TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK;

output TC_SO, WP_BP, WP_HOLD_IN, WP_HOLD_OUT, WP_SHIFT;

tcb_cell wp_shiftmode

(.TC_RESET(TC_RESET),.TC_SHIFT(TC_SHIFT),.TC_UPDATE(TC_UPDATE),.TCLK(TCLK),

.SI(TC_SI), .SO(so1), .DO(WP_SHIFTMODE));

tcb_cell wp_hold_out


.SI(so1), .SO(so2), .DO(WP_HOLD_OUT));

tcb_cell wp_hold_in


.SI(so2), .SO(so3), .DO(WP_HOLD_IN));

tcb_cell wp_bp


.SI(so3), .SO(so4), .DO(WP_BP));

and wp_shift(WP_SHIFT, WP_SHIFTMODE, VC_SHIFT);

antiskew tc_so (.SI(so4), .clk(TCLK), .SO(TC_SO));

endmodule

module wrapped_vc (TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK,TC_SO,

Func_in, Func_out, WP_SI, WP_SO);



// wrapper stuff

input WP_SI;

output WP_SO;

// input wrappers

input [1:0] Func_in;

// output wrappers

output [1:0] Func_out;

wire [1:0] VCI;

wire [1:0] VCO;

wrapper WRAPPER


.TC_SI(TC_SI),.TC_UPDATE(TC_UPDATE),.TCLK(TCLK),.TC_SO(TC_SO),


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.Func_in(Func_in), .Func_out(Func_out),

.WP_SI(WP_SI), .WP_SO(WP_SO), .VCI(VCI), .VCO(VCO));

// Instantiation of VC should go here

endmodule

module wrapper (TC_RESET,VC_SHIFT,TC_SHIFT,TC_SI,TC_UPDATE,TCLK,TC_SO,

Func_in, Func_out,VCI, VCO, WP_SI, WP_SO);



// wrapper stuff

input WP_SI;

output WP_SO;

// input wrappers


output [1:0] VCI;

// output wrappers

input [1:0] VCO;output [1:0] Func_out;

tcb TCB (.TC_RESET(TC_RESET),.VC_SHIFT(VC_SHIFT),.TC_SHIFT(TC_SHIFT),

.TC_SI(TC_SI),.TC_UPDATE(TC_UPDATE),.TCLK(TCLK),.TC_SO(TC_SO),

.WP_BP(WP_BP), .WP_HOLD_IN(WP_HOLD_IN), .WP_HOLD_OUT(WP_HOLD_OUT),

.WP_SHIFT(WP_SHIFT));

wrapper_reg WRAPPER_REG

(.WP_CLK(TCLK),.WP_SHIFT(WP_SHIFT),.WP_HOLD_IN(WP_HOLD_IN),.WP_HOLD_OUT(WP_

HOLD_OUT),.Func_in(Func_in), .Func_out(Func_out), .VCI(VCI),

.VCO(VCO),

.WP_SI(WP_SI), .WP_SO_beforeskew(WP_SO_beforeskew));

bypass_reg bypass (.WP_SI(WP_SI), .WP_CLK(TCLK),

.VC_WP_BYPASS(VC_WP_BYPASS));

mas MAS (.WP_BP(WP_BP), .VC_WP_BYPASS(VC_WP_BYPASS), .WP_SO(WP_SO),

.WP_SO_beforeskew(WP_SO_beforeskew),.WP_CLK(TCLK));

endmodule

module wrapper_reg (WP_CLK,WP_SHIFT,WP_HOLD_IN,WP_HOLD_OUT,

Func_in, Func_out, VCI, VCO, WP_SI, WP_SO_beforeskew);

input WP_CLK,WP_SHIFT,WP_HOLD_IN,WP_HOLD_OUT, WP_SI;

output WP_SO_beforeskew;

// input wrappers


output [1:0] VCI;

// output wrappers


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input [1:0] VCO;

output [1:0] Func_out;

wp_cell_in i1 (.Func_in(Func_in[0]), .WP_SHIFT(WP_SHIFT), .WP_CLK(WP_CLK),

.WP_HOLD_IN(WP_HOLD_IN), .VCI(VCI[0]),

.SI(WP_SI), .SO(so1));

wp_cell_in i2 (.Func_in(Func_in[1]), .WP_SHIFT(WP_SHIFT), .WP_CLK(WP_CLK),

.WP_HOLD_IN(WP_HOLD_IN), .VCI(VCI[1]),

.SI(so1), .SO(so2));

wp_cell_out o1 (.Func_out(Func_out[0]), .WP_SHIFT(WP_SHIFT),

.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .VCO(VCO[0]),

.SI(so2), .SO(so3));

wp_cell_out o2 (.Func_out(Func_out[1]), .WP_SHIFT(WP_SHIFT),

.WP_CLK(WP_CLK), .WP_HOLD_OUT(WP_HOLD_OUT), .VCO(VCO[1]),

.SI(so3), .SO(WP_SO_beforeskew));

endmodule

module tcb_cell(TC_RESET, TC_SHIFT, TC_UPDATE, TCLK, SI, SO, DO);

input TC_RESET, TC_SHIFT, TC_UPDATE, TCLK, SI;

output SO, DO;

reg SO;

reg DO;

always @(TCLK) begin

if (TC_RESET)

SO = 0;

else begin

if (TCLK === 1'b1) begin

if (TC_SHIFT)SO = SI;

else

SO = SO;

end else begin

if (TC_UPDATE)

DO = SO;

else

DO = DO;

end

end

end

endmodulemodule wp_cell_in (Func_in,WP_SHIFT,SI, WP_HOLD_IN, WP_CLK, SO,VCI);

input Func_in,WP_SHIFT,SI, WP_HOLD_IN, WP_CLK;

output SO,VCI;

reg SO;

assign VCI = (WP_HOLD_IN) ? SO : Func_in ;


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always @(posedge WP_CLK) begin

if(WP_SHIFT)

SO = SI;

else

if (WP_HOLD_IN == 1'b1)

SO = SO;

else

SO = Func_in;

end

endmodule

module wp_cell_out (Func_out,WP_SHIFT,SI, WP_HOLD_OUT, WP_CLK, SO,VCO);

input VCO,WP_SHIFT,SI, WP_HOLD_OUT, WP_CLK;

output SO,Func_out;

reg SO;

assign Func_out = (WP_HOLD_OUT) ? SO : VCO;

always @(posedge WP_CLK) beginif(WP_SHIFT)

SO = SI;

else

if (WP_HOLD_OUT == 1'b1)

SO = SO;

else

SO = VCO;

end

endmodule


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A.1.2 Waveforms

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