Vu Luu Computer Buses

8/17/2019 Vu Luu Computer Buses

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Computer Buses

SJSU - Fall 2008

CS 147Vu Luu


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Contents

1. Concepts

2. Measurement

3. Operat on


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Concepts

! " #us s a collect on o$ % res an& connectors t'rou(' %' c't'e &ata s transm tte&.

! )us * a&&ress #us + &ata #us , ata #us trans$ers actual &ata. , "&&ress #us trans$ers n$ormat on a#out &ata an& %'ere t

s'oul& (o.


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Concepts (cont.)

! Bus protocol rules &eterm n n( t'e $ormat an&transm ss on o$ &ata t'rou(' #us.

! Parallel bus &ata s transm tte& n parallel. , "&/anta(e $ast , sa&/anta(e ' (' cost $or lon( & stance transm ss on

nter$erence #et%een l nes at ' (' $re uenc .

! Serial bus &ata s transm tte& n ser al. , "&/anta(e lo% cost $or lon( & stance transm ss on no

nter$erence. , sa&/anta(e slo%

! Bus master 'e &e/ ce controls #us. Ot'er &e/ ces areslaves .


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Concepts (cont.)

! Local (system) bus C U ↔ ma n memor .

! Front side bus

, Or ( nal concept C U ↔ components

, Mo&ern 5ntel arc' tecture C U ↔ 6ort')r &(e c' pset

! Back side bus C U ↔ L2 cac'e

! Memory bus 6ort'#r &(e c' pset ↔ ma n memor

! AGP bus 6ort'#r &(e c' pset ↔ U

! SA! " SA! #LB! PC ! Fire$ire! %SB! PC &"'press busmot'er#oar& ↔ per p'eral &e/ ces.


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Measurement

! )us % &t' n& cates t'e num#er o$ % res n t'e #us $ortrans$err n( &ata.

! )us #an&% &t' re$ers to t'e total amount o$ &ata t'at cant'eoret call #e trans$erre& on t'e #us n a ( /en un t o$ t me.


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Bus Width (bit) Bandwidth (MB/s)16-bit ISA 16 15.9

EISA 32 31.8

VLB 32 127.2

PCI 32 127.264-bit PCI 2.1 (66 MHz) 64 508.6

AGP 8 32 2!133

"SB 2 1 S#$%-S&'' 1.5 Mbit*+

, ##-S&'' 12 Mbit*+Hi-S&'' 480 Mbit*+

,i '%i ' 400 1 400 Mbit*+

PCI-E & '++ 16 /' +i$ 2 16 8!000

idt and Band$idt o* Some +ypical Buses


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Sync ronous Bus vs. Async ronouse Bus

! " #us can #e class $ e& as one o$ t%o t pe s nc'ronousan& as nc'ronous.

! Sync ronous bus t'ere s a common cloc t'at

s nc'ron 9es #us operat ons.! Async ronous bus t'ere s no common cloc . )us

master an& sla/es 'a/e to :'an&s'a e; &ur n(transm ss on process.


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2. "$ter t'e /olta(es on t'e a&&ress l nes 'a/e #ecome sta#le C Uasserts M an& < l nes.

,

-


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3. Memor controller locates memor locat on an& loa&s t nto &atal nes.

,

-


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4. C U ta es &ata $rom &ata l nes an& t'en &e-asserts M an&< to release t'e #us.

,

-/


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1. C U puts a&&ress on t'e #us.

,


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2. C U asserts M an& < l nes.

,

-


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3. C U asserts MS?6 l ne. Memor controller locates an& loa&s&ata $rom memor to &ata l nes.

,

-


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@. C U ta es &ata $rom &ata l nes an& t'en &e-asserts M< an& MS?6.

,

-

/

/

0

0

0


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A. F nall memor controller &e-assert SS?6.

,

-

/

/

0

0

0

1


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Brid2e&based bus arc itectures

! S stem nclu&es a lot o$ #uses %' c' are se(re(ate& ##r &(es.

! "&/anta(e #uses can s multaneousl operate.

! 5ntel arc' tecture


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)r &( n( % t' "M processors


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)r &( n( % t' V5" C7 processors


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nternal Communication Met odolo2ies

! ro(ramme& 5BO poll n(D

! 5nterrupt-&r /e 5BO

! rect Memor "ccess M"D


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Pro2rammed 34 (pollin2)

! C U polls eac' &e/ ce to see$ t nee&s ser/ c n(.

! ra%#ac 'e C U %astest me $or poll n( &e/ ces #us -%a t.D


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nterrupt&5rive 34 (P 4)

! e/ ce re uestsser/ ce t'rou(' aspec al nterruptre uest l ne t'at (oes& rectl to t'e C U.

! 6o #us -%a t. Moree$$ c ent t'an 5O.


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5irect Memory Access (5MA)

! e/ ces trans$er &ata & rectl to an& $rom memor# passes t'e C U.

! Ver e$$ c ent mo&e. C U s $ree to &o ot'er operat ons.


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M$ '+ M i t + ' t' (MB*+)

M #ti-%$ MA 1 13.3

M #ti-%$ MA 2 16.6

"#t MA 0 16.7"#t MA 1 25.0

"#t MA 2 33.3

"#t MA 3 44.4

"#t MA 4 66.7

"#t MA 5 100

"#t MA 6 133

5MA modes in t e A+A inter*ace


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6e*erences

! Mur&occa M les an& Eeur n( V ncent. Computer Architecture and Organization: An Integrated Approach .Jo'n le G Sons 5nc. 2007. p.303 , p.31A.

! Ho9 ero C'arles. The PC Guide. 'ttp BB%%%.pc(u &e.comB.
http://www.pcguide.com/http://www.pcguide.com/

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