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Wafer On Wafer Technology for
Wafer Level Burn-InJune 7, 1999
Dave PedersenVP MOST/WOWFormFactor, Inc.
2June 7, 1999
Wafer On Wafer! WOW = Low cost integrated method of processing
memory die from wafers into memory modules! Interesting Feature Set:
" Easy to build (Ramp)" More reliable than CSPs" Enhanced Electrical Performance (Yield / Margin / Cost)" Flexible Manufacturing" Costs Less to produce
! Feature Set is made possible by the uniqueproperties of FFI’s MicrospringTM Contact" Reliable resilient temporary interconnect for test" Reliable resilient permanent final product interconnect
3June 7, 1999
FormFactor is a Company with a mission toreduce back-end semiconductor costs
Probe CardsWOW
Chip Scale Packaging Sockets
4June 7, 1999
Microspring Contact Technology1. Bond and shape a gold wire to form a spring“skeleton”
Use a regular wirebonder with FFI definedmodifications.
2. Create a free-standing spring “skeleton”Height uniformity achieved due to a FFI invented anddeveloped spark stabilization process
3. Overcoat the “Skeleton” with a spring alloy toform a Microspring contactSprings can be assembled on many substratetypes including FR4, Ceramic, and WholeWafers
5June 7, 1999
MicroSpringsTM on Silicon Technology(MOST) Wafer Cross Section
Re-route Trace
Silicon
Al Bond Pad
Microspring
•Microsprings can be located anywhere on the die surface including directly on the bond pads•Match standard footprints or design for enhanced performance
6June 7, 1999
MOST Assembly Methods
��������������������������������������������������������� ��������������������������������������������������������������������������������������������� ���������������������
flip
PCB substrateSprings on a Silicon Die
Flip and SMT Assemble on to low cost FR4
Soldered Directly to PCB Soldered Into PCB Vias
Best Signal Integrity
7June 7, 1999
The 3 Dimensional NaturalSemiconductor Interface
! low noise! low inductance! high bandwidth! less crosstalk! fewer alpha particles! matched impedance! improved decoupling
"enhanced moduleperformance
8June 7, 1999
RIMM Built with MOST Interconnect
9June 7, 1999
MOST Reduces Back End Costs! WHOLE WAFER PROCESSING
" Extends the wafer fabrication economy-of-scale to the back end: ! Wafer Level Chip Scale Assembly• Whole Wafer Burn-In• Wafer Level Full Test Capability
" Lower Direct Manufacturing Costs" Eliminates expensive packaging" Higher Through-Put" Increased Cycles of Learning" Reduced Inventory
10June 7, 1999
WOW Enables a Wafer Level Flow
Sort 1Laser Repair
Sort 2
AttachSprings
Wafer LevelBurn-in andlong cycle
test
Short cycle &High FrequencyFinal Test usingFFI Probe Card
Interface
Dicing(Saw)
ModuleAssembly
& Test
11June 7, 1999
Microspring as a Temporary ContactElement Test & BI
! Z Axis contact + over travelcreates a wiping action
! Gold to Gold contacts! Controlled force & scrub! High spring tip placement
accuracy across an 8”wafer allows for WholeWafer All Pin Contact
! Single Die Test & BIsockets become PCB pads& plastic XY registrationframes
12June 7, 1999
MOST Advantages for Full Wafer Contact! Individual compliance
" > 7 mils z-axis compliance" < +/-2 mils planarity spring to spring across 8”
wafer
! No contact element yield orreliability concerns" Contact element yield = packaging yield" No “repeating” contact failures" Contact compression element used only a few times
! Contacts on PCB pitch - not bondpad pitch" 0.5 mm to 1.0 mm contact pitch" Significantly reduces alignment challenges
! Optimized contact metallurgyand surfaces on MicroSpringand contactor
13June 7, 1999
WOW Wafer Level BI Solution
PCB
Backing Wafer
Wafer Under Test
Clamping Mechanism
Flex
Silicon Tiles Flex Connector
14June 7, 1999
Contactor Assembly Method! Si is a great material for building
contactors" TCE Matches Wafer Under Test" Interconnect materials and
processing is well understood" Many possible opportunities for
future enhancement
! Very difficult to cost effectivelyyield a 100% perfect, 3 layermetal, wafer with a diameter >8”
! A tile approach was developedto yield ~ 1” x 5” pieces of Siwith the necessary interconnect
15June 7, 1999
WOW Whole Wafer Contactor
Fixture Wafer
Blank Backing Wafer
Tile Top View
Silicon Tiles
Si Tiles are placed in a Si Fixtureand connected to a Si backing wafer
Device power & signal padsrouted to
Flex attach pads
10”
8”
16June 7, 1999
MOST Contact Pad Positional Accuracy
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
3-X 4-X 5-X 3-Y 4-Y 5-Y 3-Z 4-Z 5-Z
X - Y - Z Measurements on 3 Contactors
Inch
es *
e-0
3
Maximum & Minimum Readings of60 Data Points across 8" X 10" area
Target Range = +/- 2.0 mils
“X” “Y” “Z”
17June 7, 1999
Test Wafer Die Structures
! 7mm X 14mm Die Size! Aluminum Bond Pads! W/Ti Resistors! 72 Pin “Dual” Daisy Chain! 4 Heaters! 2 Interdigitated Thermal /
Mosisture Sense Resistors! Bulk Resistivity Structures
18June 7, 1999
MOST WLBI Results
! 8 Contactors were built" All with accuracy according to the previous chart" 1000 T/C -55C to +150C were run with no de-lamination or
degradation of the adhesive between the tiles & backing wafer
! Test Device wafers were clamped against againstthe contactors" Daisy chain pairs were tested from 25C to 150C" Whole wafers were tested" Spring compression and resiliency parameters were measured
19June 7, 1999
Normalized Resistance vs TemperatureR vs. Temp
0.98
1.00
1.02
1.04
1.06
1.08
1.10
0 20 40 60 80 100 120 140 160
Temp (C)
R R
atio
to 2
5C
Average increase between 24 and 150C = 8%(0.06% per degree, 600 ppm)
20June 7, 1999
Continuing Work
! Limited test on Test Device Wafer and long DaisyChains make accurate ppm measurements difficult" Subjective measurements look very promising" Qualitative tests getting underway
! Test Device and matching contactor have beenredesigned
! FFI is continuing to investigate low cost contactormethods and materials
21June 7, 1999
WOW Full Test @ Probe Solution
Controlled Impedance Tester Interface Board
Space transformer withMOST posts
3-pt Planarizer
Wafer Under Test
MOST microsprings
MicrospringInterposer
22June 7, 1999
Multiple Low Cost Product FlowsEnable Gradual Adoption
! WOW is primarily wafer based -- whole waferprocessing and may not be the lowest cost choicefor all die size and yield combinations
! 2 Additional Flows" Single Die Flow
• Conventional handling systems" Module Level Flow
• Redundancy Repair after burn-in• Self Socketing Die• Burn-in at the module level
23June 7, 1999
Challenge! MOST is proving itself to be a highly reliable, cost effective,
high performance, interconnect technology! Temporary Interconnect with MOST springs is being
demonstrated at:" Single Die Level" Multi Die (Module Level)" Wafer Level
! The door is open for major business opportunities" Cost Effective wafer alignment and clamping systems" Cost Effective wafer temperature forcing systems" Cost Effective wafer level test & B-I electronics