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Wake on LAN Hardware Implementation Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note

September 2008

Wake on LAN Hardware Implementation Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note September 20082 Order Number: 320300-002US

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Wake on LAN Hardware Implementation Utilizing the Intel® EP80579 Integrated Processor Product LineSeptember 2008 Application NoteOrder Number: 320300-002US 3

Application Note—Wake on LAN Hardware Implementation

Contents

1.0 Introduction ..............................................................................................................51.1 Reference Documents ..........................................................................................5

2.0 EP80579 Power Management for WoL .......................................................................5

3.0 PHY Interface for Supporting WoL .............................................................................6

4.0 PHY Interface for Non-Supporting WoL .....................................................................8

5.0 Reference Clock Isolation ..........................................................................................8

6.0 Resetting PHY Supporting WoL..................................................................................8

7.0 EEPROM.....................................................................................................................97.1 EEPROM Update with the EEPROM Update Utility......................................................97.2 EEPROM Update using Ethtool (Linux only) ........................................................... 13

8.0 PHY Address ............................................................................................................ 16

9.0 BIOS Requirements ................................................................................................. 17

10.0 Operating System Configuration .............................................................................. 1710.1 Microsoft Windows* XP Embedded....................................................................... 1710.2 Linux ............................................................................................................... 20

Figures3-1 PHY-MAC Typical Interface.............................................................................................76-2 PHY Reset ...................................................................................................................97-3 EEPROM Update Utility: Displaying Current Contents ....................................................... 107-4 EEPROM Update Utility: Dumping Contents to File........................................................... 117-5 Updating EEPROM Contents File.................................................................................... 117-6 EEPROM Update Utility: Updating EEPROM ..................................................................... 127-7 EEPROM Update Utility: Displaying Contents after Update ................................................ 137-8 Ethtool: Displaying Current Contents............................................................................. 147-9 Ethtool: Updating EEPROM........................................................................................... 157-10 Ethtool: Displaying Contents after Update...................................................................... 1610-11Power Management Settings ........................................................................................ 1810-12PME Setting ............................................................................................................... 1910-13Wake On Setting ........................................................................................................ 20

Tables2-1 EP80579 Power Well Requirements .................................................................................6

Wake on LAN Hardware Implementation—Application Note


Revision History

Date Revision Description

September 2008 002 Added Linux, EEPROM, and OS configuration information

August 2008 001 Initial release



1.0 Introduction

Wake on LAN (WoL) is a Power Management feature that allows a system to remotely wake up from a sleep mode via an Ethernet connection. A specific wake-up packet, such as a Magic Packet* containing the MAC address of the target computer, is sent through Ethernet to the target computer. The target computer checks the packet to ensure that the MAC address in the packet matches the MAC address for the target computer. If a match is confirmed, then the wake-up process starts at the target computer.

This application note provides guidance when designing with the Intel® EP80579 Integrated Processor product line (EP80579) for Wake on LAN (WoL) applications. This document focuses on the power rails and power management requirements to allow normal operation and wake up from a sleep mode. The power rail and power management requirements ensure that the hardware used to support WoL is active, ready to detect the Magic Packets, and wake the system. The document also covers EEPROM settings, BIOS requirements, and the operating system configuration required to enable WoL.

1.1 Reference Documents

The reader of this document should be familiar with material and concepts presented in the Ethernet PHY Selection Criteria for the Intel® EP80579 Integrated Processor Product Line.

It is extremely important that the designer reviews the above mentioned document. It provides the information required to decide which PHY device can be used in your specific design and the software support for it.

Note: Unless otherwise noted, technical documents are available through your Intel field sales representative or from http://www.intel.com/go/soc.

2.0 EP80579 Power Management for WoL

WoL hardware support is a power management feature designed to keep part of the system alive and able to detect specific Magic Packets that can wake the processor from a sleep state. The MAC and PHY are key hardware blocks that work with other supporting hardware blocks to detect Magic Packets while the system is in sleep mode.

The EP80579 has three internal Gigabit Ethernet MACs: MAC0, MAC1, and MAC2. Because only MAC0 supports WoL, the power management required to enable MAC0 is different from the power management for MAC1 and MAC2. The main difference is that the power rails for MAC0 are internally isolated from the other two MACs. This power rail isolation provides power isolation when the system is in standby mode or in any other supported sleep mode.

When designing for applications that require the implementation of WoL, power must be supplied at all times to the MAC and PHY (physical layer) that detect Magic Packets, in this case MAC0. Therefore, the designer must ensure that all suspended power wells for the EP80579 are connected to the standby power supplies. If power is not supplied correctly, or if standby power is not used for a single PHY for MAC0, WoL will not function. You must ensure this guideline is followed.

The following table describes the power wells required to ensure that the EP80579 MAC0 is powered correctly to support WoL. The power wells are required to maintain and follow the timing specified in the Intel® EP80579 Integrated Processor Product Line Datasheet.



3.0 PHY Interface for Supporting WoL

To support WoL, a single port PHY is required to ensure that standby power is applied only to the device supporting WoL when the EP80579 is in a sleep state. Almost any single port PHY device will work as long as it supports WoL. Power rails for the PHY and for MAC0 must be in sequence to ensure that the two devices are correctly operating at the same time. The list of supported PHYs may change. See the Ethernet PHY Selection Criteria for the Intel® EP80579 Integrated Processor Product Line for the latest information.

If the MAC1 and MAC2 ports are used in the design, then the power distribution for these two PHYs must come from the main power source, not from the standby source. If the power comes from the standby source, then the EP80579 will tend to sink current because one of the two devices is powered while the other is not. For example, during S3 or S4 sleep mode, MAC1 and MAC2 will power down, while MAC0 remains powered on. If the PHY connected to either MAC1 or MAC2 remains powered on when the EP80579 is powered-down, then current sinks will be experienced from the PHY to the EP80579.

When designing to support the WoL hardware feature, it is critical to ensure that the section in the circuit that is responsible for supporting power to the active section of the circuit carefully accounts for all power rails, and for interfaces that are to remain powered on while the system goes into a sleep state. The following diagram shows a typical interconnect between the EP80579 and a single port PHY device. All rails used to power the PHY are on standby, meaning power is active while the system is in sleep mode.

Table 2-1. EP80579 Power Well Requirements

Power Well Volts Description

VCC50_SUS 5.0 V Sustain power well 5.0 V for tolerance logic. Standby power.

VCCGBEPSUS 3.3 V Sustain power well 3.3 V for I/O logic Gigabit Ethernet Interface. Standby power.

VCCSUS25 2.5 V Sustain power well 2.5 V for Gigabit Ethernet Interface. Standby power.



Figure 3-1. PHY-MAC Typical Interface

Intel®EP80579

RJ45

PHY

MAGNETICS

1.2 KΩ

GBE0_RXCLK

GBE0

VCC_SBY (2.5 V)

GBE0_RXCTL

GBE0_RXDATA0

GBE0_RXDATA3GBE0_RXDATA2GBE0_RXDATA1

GBE0_TXCLKGBE0_TXCTL

GBE0_TXDATA0

GBE0_TXDATA3GBE0_TXDATA2GBE0_TXDATA1

1.2 KΩ

VCC_SBY (2.5 V)

EESKEECS

EEDIEEDO

4.7 KΩ

VCC_SBY (2.5 V)

VCC_SBY (2.5 V)

VCC_SBY (2.5 V)

EESKEECS

EEDIEEDO

ORG

4.7 KΩ

4.7 KΩ

MDIOMDC

1.5 KΩ

VCC_SBY (2.5 V)

EEPROM

CLOCK GENERATOR

VCC_SBY (2.5 V)

125MHz

25MHz

GBE_REFCLK

VCC_SBY (2.5 V)

100 Ω

49 Ω

GBE_RCOMPNGBE_RCOMPP

GBE_REFCLK_RMII

GBE_PME_WAKEPME_N

VCC_SBY (2.5 V)V_OUT

StandBy Regulator 2.5V

12 VoltV_IN

P_GOOD

GBE_AUX_PWR_GOOD

TXCLKTXCTL

TXDATA0

TXDATA3TXDATA2TXDATA1

RXCLKRXCTL

RXDATA0

RXDATA3RXDATA2RXDATA1

MDIOMDC

VCC_SBY (2.5 V)

VCC_SBY (3.3 V)

4.7 KΩ

49 Ω

Power to Center Tap must be connected to

VCC_SBY (2.5V)

Note:PHY Address must be matched as set by the software driver, normally 0 or 1 for MAC0

RESET

Look at Figure 6-2 PHY Reset

Or any other StandBy Source



4.0 PHY Interface for Non-Supporting WoL

The PHY or PHYs (if dual) used to interface with MAC1 and MAC2 can be powered from the common power source that is used for powering the system. Standby power is NOT recommended for this application because standby power will cause the PHY to remain actively powered while the MAC interfaces are powered-down during sleep mode.

If the system does not have a requirement to support WoL, then all PHYs can be powered from the main power source, including MAC0 and its corresponding PHY interface. This will ensure that when the system enters a sleep mode, the MAC section is fully powered-down and there are no currents floating from the PHY to the MAC or other interfacing components.

5.0 Reference Clock Isolation

When supporting WoL, isolation must be maintained between the section of the circuit that is in standby mode and the rest of the system. The two sections are to be power independent of each other and maintain isolation to avoid current-sinking to other devices. Therefore, the MAC and PHY reference clock should be isolated from other common source clocks that can be powered-down during sleep modes. To achieve this, a crystal oscillator or a clock oscillator that is powered by the same source that powers the PHY is recommended to supply the clock function only to the PHY and MAC that support WoL, isolating this clock from the system clock.

For the PHY that supports WoL (MAC0), standby power must be used for the clock. For the PHYs that do not support WoL, clock power should come from the main power source to power both the PHY and the crystal or clock oscillator.

6.0 Resetting PHY Supporting WoL

The PHY supporting WoL must remain undisturbed when the EP80579 is in sleep mode or is waking up. The reset signal and other vital signals, such as clock and power, previously mentioned in this document, can not be disturbed.

Generation and qualification of reset is an important design consideration, especially when supporting WoL. The recommended signal for resetting the PHY is PCIRST#, which is generated by the EP80579. This signal must be AND-gated with P_GOOD (power good) of the regulator that generates the standby supply that powers the PHY. This ensures that if the supply falls below the supply threshold, then the PHY will be reset and recover from a power failure.

The following figure provides an example of the circuit used to qualify the reset with the power good signal. It is important to note the rails used to power the AND-gate and the pull-up resistor, which are generated by the standby supplies, to ensure the rails are active when the system is in a sleep state.



7.0 EEPROM

The EEPROM contains sufficient information to bring up the link and configure the MAC for manageability and/or Advance Power Management (APM) wake up. The EEPROM must remain powered with power coming from a standby supply when the EP80579 is in sleep state S3 or S4. Because the EEPROM remains powered, it can ensure that if the MAC needs to be reconfigured at any point, then the EEPROM is available if the MAC attempts to read configuration data to program its registers.

If the Wake on LAN feature is to be enabled on a platform two bits within the EEPROM must be explicitly set. The Power Management bit (bit 3) in Initialization Control Word 1 and the APM Enable bit (bit 2) in Initialization Control Word 3 of MAC 0 must be set. Refer to the EEProm Address Map in the Intel® EP80579 Integrated Processor Product Line Datasheet for further description of these control words and individual bit definitions. These bits can be updated in the EEProm using either the EEProm Update Utility or ethtool for Linux based platforms. An example of each of these utilities is given below.

7.1 EEPROM Update with the EEPROM Update Utility

These steps show how to use the EEPROM Update Utility to ensure the above bits are set.

1. Display the existing contents of the EEPROM to ensure that the bits in Initialization Control Word 1 and Initialization Control Word 3 of MAC 0 have not already been set. Launch the application with ‘/d’ to display current content of the EEPROM. Example output is shown in Figure 7-3. Proceed to Step 2 if these bits have not been set.

UpdateTW32.EXE /d

Note: The output from the EEPROM Update Utility is dumped in “word” format.

Figure 6-2. PHY Reset

PCIRST#

Intel®

EP80579 PHY

RESET

VCC_SBY (2.5V)

VCC_SBY (2.5 V)V_OUT

Stand By Regulator 2.5V

12 Volt V_IN

P_GOOD

VCC_SBY (3.3 V)

4.7 KΩ

AND

VCC_SBY(2.5 V)



2. Dump the existing contents of the EEPROM to a file. Launch the application with “/s=<filename>” to dump the current contents of the EEPROM to a file. Example output is shown in Figure 7-4.

UpdateTW32.EXE /s=<filename>

Figure 7-3. EEPROM Update Utility: Displaying Current Contents



3. Edit the newly created file to set bit 3 in Initialization Control Word 1 and bit 2 in Initialization Control Word 3. Note the locations of these words in the Figure 7-5 below (yellow highlights). Care must be taken to preserve the values of other bits in these words that might have been previously set.

4. Update the EEPROM using the updated map file. Launch the application with “/f=<filename>” to update the contents of the EEPROM to the new contents contained in the specified file. Example output is shown in Figure 7-6.

Figure 7-4. EEPROM Update Utility: Dumping Contents to File

Figure 7-5. Updating EEPROM Contents File

Figure 7-5. Updating EEPROM Contents File



7.2 EEPROM Update using Ethtool (Linux only)

These steps show how to use Ethtool to ensure the EEPROM bits that are described in Section 7.0, “EEPROM” on page 9 are set.

1. Display the existing contents of the EEPROM to ensure that the bits in Initialization Control Word 1 and Initialization Control Word 3 of MAC 0 have not already been set. Launch the application with ‘-e eth0’ to display current contents of the EEPROM. Example output is shown in Figure 7-8. Proceed to Step 2 if they have not.

ethtool -e eth0

Note: The output of Ethtool is dumped in “byte” format with upper and lower bytes for each “word” swapped.

Figure 7-7. EEPROM Update Utility: Displaying Contents after Update



2. Set bit 3 in Initialization Control Word 1 and bit 2 in Initialization Control Word 3 for MAC 0. Care must be taken to preserve the values of other bits in these words that might have been previously set.

ethtool -E eth0 magic <key> offset 0x00 value 0x08

ethtool -E eth0 magic <key> offset 0x22 value 0x04

• key = 0x50418086 for accelerated SKUs.

• key = 0x50408086 for embedded SKUs.

Figure 7-8. Ethtool: Displaying Current Contents



3. Display the contents of the newly updated EEPROM to ensure the bits in the control words were successfully set.

ethtool -e eth0

Figure 7-9. Ethtool: Updating EEPROM



8.0 PHY Address

A PHY is expected to correspond to each of the three MACs. Each PHY is expected to be assigned a PHY address that matches the number assigned to one MAC. MAC0, MAC1, and MAC2 are each interfaced with the PHY device that has a corresponding PHY address as assigned by the software driver. Each has a different PHY address; none of them can be the same. When selecting single or dual PHYs, the PHY must be verified so that the PHY address can be strapped to the address assigned by the software driver.

Figure 7-10. Ethtool: Displaying Contents after Update



In some cases a dual PHY can only be strapped to address 0 and 1. If the dual PHY is interfaced with MAC1 and MAC2, a PHY address problem is created. The recommendation is to ensure that the PHY selected will allow address strapping to the PHY address that will be assigned based on the MAC with which it will interface.

9.0 BIOS Requirements

The platform BIOS must also be enabled to support WoL. This is done thru the implementation of ACPI methods described in section 7.3, “OEM-Supplied System-Level Control Methods” of the ACPI 3.0 specification. Verify with your BIOS vendors that these methods have been implemented.

10.0 Operating System Configuration

Once the platform EEPROM has been updated, the Wake on LAN settings in the OS must be configured to allow the platform to resume from S3 on reception of a Magic Packet. Examples of how to do this for Linux and Microsoft Windows* XP Embedded are provided below.

10.1 Microsoft Windows* XP Embedded

1. From the Power Management tab, check the box for “allow this device to bring the computer out of standby”.



2. From the Advanced tab, set the adapter’s Wake on Settings. This includes “Enable PME”, which should have value set to “OS Controlled” as shown in Figure 10-12 and “Wake On Settings”, which should have value “Wake on Magic Packet” as shown in Figure 10-13.

Figure 10-11. Power Management Settings



Figure 10-12. PME Setting



10.2 Linux

On Linux based systems Magic Packet WoL is enabled with ethtool. An example command is:

ethtool -s eth0 wol g

§ §

Figure 10-13. Wake On Setting