Warren W. Flack, Robert Hsieh, Gareth Kenyon Ultratech, Inc.

John Slabbekoorn, Bert Tobback, Tom Vandeweyer, Andy Miller IMEC

Introduction Lithography

TSV Process; Alignment System Experimental Methods Metrology

Targets; Tool Induced Shift

Results Summary

Introduction Lithography Experimental Methods Metrology Results Summary

Scaling the diameter of the TSV is a major driver for improvement in system performance and cost.

Reducing the size of via landing pads provide significant advantages for device design and final chip size.

Current via last diameters are approximately 30µm and are being scaled to 5µm and beyond.

With smaller TSV diameters, the back-to-front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations.

The goal of this study is to demonstrate <750nm back-to-front overlay capability as a stepping stone for next generation TSV scaling

Representation of complete TSV-last process1)Front-end and Back-end processing2)Temporary bonding and thinning3)TSV-last lithography4)TSV etch5)TSV filling, RDL and de-bonding from carrier.

1 2 3 4 5

•TSV scaling permits scaling of the landing pad & impacts device design•Sizing of the landing pad impacts overlay budget as less real estate is available for placement inaccuracy

Filled TSV

Landing Pad

Introduction Lithography Experimental Methods Metrology Results Summary

• IR transmits through silicon

• Top directed illumination allows for flexible placement of targets on the wafer

• Off axis IR camera implemented on stepper

• Measure XY positions of two features at different Z heights

• Together these features make up the Dual Side Align (DSA) alignment system

Introduction Lithography Experimental Methods Metrology Results Summary

Alignment requirement is that TSV etching will land completely on METAL1 pads for the 5 x 50µm TSV process

Two photo-resists were examined with thickness at 7.5µm: gh-line Novolak based resist requiring 1250mJ/cm2

i-line Chemical Amplified Resist (CAR) requiring 450mJ/cm2

Wafers are exposed, developed and then measured for overlay; Corrections are then made to optimize the alignment using a 920 point sampling plan

Once optimized, a less dense (115 point) sampling plan is used to monitor process stability

Dense sample of 184 steps, 920 total points

Reduced sample of 23 steps, 115 total points

• Once gathered, data is calculated and displayed as a vector plot

• The arrow scale (µm) is indicated in the top left corner and wafer notch is represented by the green spot.• 5 points per field• Creates a wafer map that gives rise to visual trends…

Introduction Lithography Experimental Methods Metrology Results Summary

The red arrows indicate DSA-SSM overlay verification locations.

DSA-SSM metrology target for 5µm diameter TSV’s. Process rules dictate all vias must be the same size, and so a target has to be integral to the process, but unique.

TSV-last process development reticle

Stepper Self Metrology (SSM) target

Photo-resist metrology target is defined as a cluster of 5µm TSV’s

Reference metrology target is defined as a large circular metal pad

The stage captures each target at a different Z heights to obtain in-focus images. Alignment error is calculated by the relative position of the targets

@ 0 µm focus @ -50 µm focus

oxide

Thinned Si wafer

referenceglue

Si Carrier

photoresist

cam

era • Tool Induced Shift (TIS) is an apparent

alignment offset caused by metrology

• Several parameters can influence TIS:

• Tilt in camera or wafer• Non-symmetric Illumination• Photo-resist processing

• The image shows a tilted camera viewing a pattern in photo-resist and a buried metal reference.

• The resist pattern appears shifted from the viewpoint of the camera with respect to the vertical

• TIS is an inherent error exhibited in all metrology systems

• Apparent error is actual error plus TIS

The apparent error (raw measurement) is the sum of actual error and TIS.

TIS can be conceptualized as a vector diagram

For a 180 degree rotation of the wafer the error associated with the wafer rotates, but the TIS component is stationary.

The actual error can now be determined from the difference between the 0 and 180 degree measurement, and the TIS can be determined from the sum.

The basic TIS calculations are summarized in equations (1) through (4). Subscript “0” denotes the zero degree orientation measurement, and “180” denotes the 180 degree orientation measurement.

2 2.

1800 YYTISy

2 1.

1800 XXTISx

2 3.

1800

,0

XXX corrected

2 4.

180

,0

0 YYY corrected

Introduction Lithography Experimental Methods Metrology Results Summary

• Each die on one wafer (with 115 die per wafer) was measured 5 separate times

• Average 3σ is 30nm in X and Y

• This is consistent with the requirement for >750 nm overlay performance

•Vector Plot depicting field point TIS estimate, derived from 0 degree and 180 degree measurements using equations 1 and 2.•Very consistent & repeatable, indicates robustness

Wafer #5 of 10 wafer production run. The average TIS offset is:

X = -155nm; Y = -453nm

Corrected Data

Calculation of corrected Overlay data from 0 degree and 180 degree measurements using equations 3 and 4

Wafer # 4 of 10 wafer production run. The 3σ is:

X = 658nm; Y = 515nm

• Lot overlay data shown is after TIS correction of the mean

• Reduced sampling shows a smaller Y 3σ compared to dense sampling

• The even and odd wafers show different repeating 3σ signatures

Dense Lot :X 3σ = 0.765Y 3σ = 0.599

Reduced Lot:X 3σ = 0.720Y 3σ = 0.392

An analysis of the X errors reveals non-linear errors. Characterized by examining the residuals. These are the

theoretical errors that remain after optimizing all possible linear grid and intra-field terms.

Denser sampling plan shows a larger X and Y 3σ The non-linear error signature, and having more sites

near the wafer edge for the dense sampling plan contributes to the difference between the two sampling plans.

1.0 1.0

• Non-linearity is readily visualised using the vector plots

• Non linearity errors cannot be corrected using traditional stepper terms such as scale, translation and magnification & are what remains

Even Wafer Odd Wafer

• A closer look yields a characteristic, alternating pattern, not attributable to the stepper.

• Investigation into the root cause of the odd/even error source is ongoing.

Odd Wafers (1,3,5,7,9)Per wafer residuals 3σ

Even Wafers (2,4,6,8,10)Per wafer residuals 3σ

X Y X Y0.699 0.348 0.464 0.304

Non-linear effects can be approached in various ways depending on the stability of the signature

For thinned substrates, significant distortions may come from processing steps other than lithography

Subdividing the wafer map into multiple alignment zones provides a flexible method to account for non-linear effects, because it allows for independent mapping and optimization of each zone

• Each zone can be independently mapped

• Each zone can have independent linear corrections

Even Wafer

Run Type

Raw DataWafer

ResidualQuadrant Residual

X 3 Y 3 X 3 Y 3 X 3 Y 3Standard Alignment 0.658 0.515 0.475 0.293 0.230 0.278Four zone mapping 0.664 0.557 0.332 0.358 0.187 0.264

• Comparison of standard alignment mapping and four quadrant mapping for an even and odd numbered wafer.

• Raw data overlay is not greatly improved, but gains are made in per wafer/quadrant residual, particularly with the odd numbered wafers

Odd WaferRun Type

Raw DataWafer

ResidualQuadrant Residual

X 3 Y 3 X 3 Y 3 X 3 Y 3Standard Alignment 0.859 0.543 0.715 0.362 0.293 0.278Four zone mapping 0.693 0.553 0.338 0.359 0.201 0.266

Scaling of TSV’s in the TSV-last process requires tighter specs on overlay.

Direct verification of TSV litho to the embedded reference layer is enabled by using the DSA alignment system combined with dedicated analysis software.

Non-linear effects on alternating wafers can be a limiting factor in the achievable overlay performance.

Gains are possible in the areas of wafer order effects & non-linear wafer signature using zonal alignment to minimize residual error

On good quality wafers the overlay performance is better than 750nm which is required for less than 5µm diameter TSV’s