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Chapter 2

Question Bank with answers

1. List any eight salient features of Pentium.

5. It has a Floating point unit for Faster internal operations 6. It has a Local advanced programmable interrupt controller , it speeds up upto 5 times for common operations including add, multiply and load, than 80486 7. It has a Branch Prediction Logic

To reduce the time required for a branch caused by internal delays.

When a branch instruction is encountered, microprocessor begins prefetch instruction at the branch address.

8. It has a Data Integrity and Error Detection logic Has significant error detection and data integrity capability.

Data parity checking is done on byte – byte basis.

Address parity checking and internal parity checking features are added.

9. It has a Dual Integer Processor which allows execution of two instructions per clock cycle 10. It has a Functional redundancy check to provide maximum error detection of the processor and interface to the processor .

A second processor ‘checker’ is used to execute in lock step with the ‘master’ processor.

It checks the master’s output and compares the value with the internal compute d values.

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An error signal is generated in case of mismatch

11. It has a Superscalar architecture, which has Three execution units One execution unit executes floating point instructions.

The other two (U pipe and V pipe) execute integer instructions.

Parallel execution of several instructions – superscalar processor.

2. Describe fire state pipelining mechanism of Pentium with neat diagram. ORWhat do you understand by superscalar execution in Pentium processor? Describe with neat diagram.

The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:1. Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned in pre-fetch

buffers for decoding.2. Decode1 : Instructions are decoded into the Pentium's internal instruction format. Branch

prediction also takes place at this stage.3. Decode2 : Same as above, and microcode ROM kicks in here, if necessary. Also, address

computations take place at this stage.4. Execute : The integer hardware executes the instruction.5. Write-back : The results of the computation are written back to the register file.

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1. Explain branch prediction in Pentium Processor.

Branch Prediction:1. The Pentium processor includes branch prediction logic to avoid pipeline stalls.2. If correctly, predict whether or not branch will be taken when branch instruction is executed if

branch prediction is not correct recycle penalty is applicable to u pipeline & 4 cycle penalty if branch is related to v pipeline.

3. The branch instructions occur frequently while running any application. These instructions change the normal sequential control flow of the program.

4. Branches may be of two types: Conditional branch: In case of conditional branch, the CPU has to wait till the execution

stage to determine whether the condition is met or not. Unconditional branch. It goes on executing.

5. The Pentium processor makes the dynamic branch prediction using a Branch Target Buffer (BTB).

6. To efficiently predict branches, the Pentium uses two prefetch buffers. One buffer prefetches code in linear fashion, while the other prefetches instructions based on address in the branch target buffer.

7. The Pentium processors prediction algorithm not only forecast the simple branch choices but also supports more complex branch prediction.

8. This is achieved by storing multiple branch address in the branch prediction buffer. The design of the branch target buffer allows 256 addresses to be stored and thus the prediction algorithm can forecast up to 256 branches

Branch Prediction Logic:-

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2. Explain any four floating point exception in Pentium processor

Answer The Pentium provides six floating point exceptions

1. Invalid operation (#I) Stack overflow or underflow (#IS)

Invalid arithmetic operation (#IA) 2. Divide-by-zero (#Z). 3. Demoralized operand (#D) 4. Numeric overflow (#O) 5. Numeric underflow (#U) 6. Inexact result (precision)(#P).

Each of the six exception classes have a corresponding flag bit in the FPU status word and a mask bit in the FPU control word.

Denormal: The denormal exception occurs if one or more of the operands is a denormal number. This exception is never regarded as an error. Divide-by-Zero Exception: A divide-by-zero exception occurs for a floating-point division operation if the divisor is zero and the dividend is finite and non-zero. It also occurs for other operations in which the operands are finite and the correct answer is infinite. When the divide by zero exception is masked, the result is +/-infinity. The following specific cases cause a zero-divide exception:

LOG(0.0)

LOG10(0.0)

Overflow Exception: An overflow exception occurs if the rounded result of a floating-point operation contains an exponent larger than the numeric processing unit can represent Underflow Exception: The underflow exception occurs if the rounded result has an exponent that is too small to be represented using the floating-point format of the result.

Inexact Exception: The inexact exception occurs if the rounded result of an operation is not equal to the unrounded result.

3. Describe Intel MMX architecture with register set and new data types.

Answer 1. In Pentium there are eight general purpose floating point registers in a floating point unit.

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2. Each of these eight registers are 80-bit wide for floating point operations, 64 bits are used for mantissa and rest of 16 bit for exponent. 3. Intel MMX instructions use these floating point registers as MMX registers and used only 64 bit mantissa portion of these registers to store MMX operands. 4. Thus MMX programmers virtually get new MMX registers each of 64bits.5. It is possible to use same set of registers as floating point registers and MMX register in the same program; it is preferable not to use them concurrently. 6. After a sequence of MMX instruction is executed, these registers should be cleared by an instruction ‘EMMS’ which implies empty MMX stack. 7. The floating point users should use same instruction after executing floating point instructions. 8. Although content switching between multimedia program execution and floating point execution is permissible. It is not recommended. 9. It is advisable that multimedia program developers should partition MMX instruction into separate library routine.

The MMX technology supports the following four data types. 1. Packed bytes-In this data types, eight bytes can be packed into one 64 bit quantity. 2. Packed word-Four words can be packed into 64 bit. 3. Packed double word-Two double words can be packed into 64 bit 4. One quadword-One single64 bit quantity.

4. List any eight special features of Pentium Pro-processor.

1. The Pentium Pro processor has 36 address lines

2. The Pentium Pro processor has an additional 256/512 KB L2 cache memory on chip.

3. On chip L2 cache speeds processing and reduces the number of components in a system.

4. The L2 cache is connected to BIU, BIU generates memory addresses and control signals

and passes or fetches data or instructions either to L1 data cache or L1 instruction cache.

5. The Instruction Fetch and Decode Unit (IFDU), contains three separate: instruction

decoders that decode three instructions simultaneously

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6. It also includes Branch Prediction Logic.

7. It predicts if the branch will be taken or not for a conditional jump instruction.

8. The instruction are then put into the instruction pool.

9. The instruction pool is a memory accessible with its content.

10. The execute unit consists of three units namely two integer execution unit and one

floating point unit , two integer and one floating instruction can be executed

simultaneously

11. Pentium Pro also has one jump execution unit (address generation unit).

12. The scheduling is performed by reservation station (RS) which can schedule up to five

events for execution and process four simultaneously.

5. Compare 80386 processor with Pentium processor

Sr. No

80386 Pentium

1 It is 32 bit processor with 32 bit data and address bus

It is 32 bit processor with 32 bit address bus and 64 bit data bus

2 It does not have superscalar and super pipelined architecture

It has superscalar super pipelined architecture

3 It uses co-processor 80387, for mathematical calculations

It has on-chip floating point unit

4 It has on-chip address translation cache, but cache is not available

It has two separate on chip cache for code and data memory

5 It has single ALU It has two ALUs6 It does not support Branch

PredictionIt supports branch prediction using prefetch buffers and branch target buffer

6. With the help of neat diagram describe the function of internal block of Pentium System Architecture.

(Diagram: 4 marks, explanation: 4 marks)

Pentium Architecture Pentium processor uses Superscalar architecture and hence can issue multiple instructions per

cycle. Multiple Instruction Issue (MII) capability.

Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row. 1. Pre-fetch/Fetch: Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.

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2. Decode1: Instructions are decoded into the Pentium's internal instruction format. Branch prediction also takes place at this stage.

3. Decode2: Same as above, and microcode ROM kicks in here, if necessary. Also, address computations take place at this stage. 4. Execute: The integer hardware executes the instruction. 5. Write-back: The results of the computation are written back to the register file.

Branch Prediction Unit: The Pentium processor fetches the branch target instruction before it executes the branch

instruction. The branch prediction algorithm speeds up the instruction execution. When a branching

occurs, a branch instruction address and target address is saved in Branch target Buffer (BTB).

These BTB records are used after decoding the branching instruction. CPU predicts whether the branch will be taken or not. If the prediction is correct, the process

continues and if prediction is incorrect, the CPU flushes the pipeline and fetches from the correct target address.

The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instruction and one for data. It allows the Pentium processor to fetch data and instructions from the cache simultaneously. When data is modified, only the data in the cache is changed. Memory data is changed only when the Pentium processor replaces the modified data in the cache with a different set of data. Floating Point Unit: There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of pipelining. First five are similar to integer unit. Since the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional error checking stage is there in FPU.

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7. Describe the general purpose registers and their functions in pentium processor with

neat diagram.

General purpose registers: • Four 32-bit registers can be used as ∗ Four 32-bit register (EAX, EBX, ECX, EDX) ∗ Four 16-bit register (AX, BX, CX, DX) ∗ Eight 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL) • Some registers have special use ∗ ECX for count in loop instructions

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8. State and describe the significance of separate code and data cache in Pentium

processor.

Separate 8K B instruction and Data Cache:

The figure shows the organization of instruction and data cache.

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The Pentium processor has 2 separate 8KB data and code Caches. But they need more bandwidth than the unified cache. Both the caches have TLB’s associated with them. The TLBs are used to convert the linear addresses to the respective physical addresses.

As the data cache stores only 8KB data and code cache stores only instructions, the lookup

process speed for Pentium increases.

Advantages of separate instruction and data caches: 1. Separate code and data cache memories effectively and efficiently executes the branch prediction. 2. Simultaneous cache look up is achieved by Pentium processor due to the separate data and code cache. 3. The separate cache memories raise the system performance i.e. an internal read request is performed more quickly than a bus cycle to memory. 4. They reduce the use of processor’s external bus when the same locations are accessed multiple times.

9. Draw the pipeline stages of floating point unit. Also write the names of stages in pipelining in Pentium processor.

The pipelining stages in the floating point unit of Pentium are:

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10. What is the purpose of MMX architecture designing? Write any four main features of this technology to fulfill its goals.

Intel’s MMX media enhancement technology is a major extension of the Intel Architecture that makes PCs into richer multimedia and communications platforms.

This technology introduces 57 instructions oriented to highly parallel operations with multimedia and communications data types.

These instructions use a technique known as SIMD (Single Instruction, Multiple Data) to deliver better performance for multimedia and communications computation.

Intel processors that provide MMX technology support are fully compatible with previous generations of the Intel Architecture

Features:

1. 57 new microprocessor instructions have been added that are designed to handle video, audio, and graphical data more efficiently.

2. New 64-bit integer data type (Quadword). (4 new MMX data types) 3. A new process, Single Instruction Multiple Data (SIMD), makes it possible for one instruction to perform the same operation on multiple data items. 4. The memory cache on the microprocessor has increased to 32 KB, meaning fewer accesses to memory that is off the microprocessor. 5. Eight 64 bits wide MMX technology registers have are added to support the Multimedia. 5. Write Combining: ⇒ The Write Combining technology of the P6 architecture can be used to achieve very high graphics I/O performance.

11. Write any four features of Pentium II processor.

1. It is a 32-bit processor. 2. It has a full 32-bit data bus. 3. It has an integrated math coprocessor (sometimes called a "floating point unit"). 4. It supports MMX instructions, which are useful for video decoding and playback, as well as 3D gaming. 5. It has it's L2 cache integrated into the processor die itself, rather than on the motherboard. This makes it slightly faster at the same clock speed, since it does not take as long to fetch data from the cache. 6. It has more L2 cache, and is packaged (in desktop processors) in a slot cartridge, rather than a socket.

12. What are the advancement available in Pentium pro inline with the Pentium architecture. Pentium pro is advanced from Pentium: Pentium pro having 12 stages of pipelining.(explain in detail) Dynamic execution of instruction (in detail) multiple branch instruction(in detail) Dual independent bus. Out of turn execution

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13. State the features of Pentium III processor.

1. Pentium III processor has 512KB full speed on chip L2 Cache with ECC(ERROR CORRECTING CODE) for high performance workstations/servers. Can work on WINDOWS 98, WINDOWS NT, 2000,LINUX OS.

2. PIII is incorporated with MMX technology.

3. Dynamic execution, micro-architecture incorporates unique combination of multiple branch prediction, data flow analysis and speculative execution.

4. It Supports power management capabilities like System management mode and

5. The Pentium III processor has Multiple low power states.

6. Pentium III is optimized for 32 bits applications running on advanced 32 bits OS.

7. It has 32KB L1 cache divided as 16KB instruction cache and 16KB data cache.

8. It has Quad quad word wide ie. 256 bits cache data bus , ways set associative cache

9. It provides improved cache hit rate.

10. It supports Multiprocessor system.

11. It Works on 1.0 GHz, 850, 800, 750, 700, 650 MHZ.

What do you meant by Dynamic execution of instruction in Pentium processor? ANS: (Dynamic execution of instruction description =4 marks ) Dynamic Execution Technology: ⇒

Dynamic execution incorporates the concepts of out-of-order and speculative execution. The Pentium processor’s implementation of these concepts removes the constraint of linear

instruction sequencing between the traditional fetch and execute phases of instruction execution.

Up to 3 instructions can be decoded per clock cycle. These decoded instructions are put into a buffer, which can hold up to 40 instructions.

Instructions are executed from this buffer when their operands are available (versus instruction order).

Up to 4 instructions can be executed per clock cycle.