Module 5.

TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS:

In this section, the crosstalk among the parallel multilevel interconnections inclu- ding the single-, bi-, and trilevel configurations is studied by modeling the intercon- nections as transmission lines. The model has been utilized to study the dependences of crosstalk voltage on interconnection parameters such as length, width, separation, interlevel distance, driving transistor resistance, and load capacitance.

The Model

As shown in Fig. 4.4.1, the interconnection line can be modeled as a transmission line driven by a unit step voltage source having resistance Rs, loaded by the capacitance CL, and coupled to the neighboring interconnection lines by the mutual capacitances and inductances (not shown in the figure). The resistance Rs is determined by the dimensions of the driving transistor and the capacitance CL is determined by the parasitic capacitances of the transistor loading the interconnection line. For the interconnection lines printed on or embedded in the semi-insulating

(262) (CROSSTALK ANALYSIS)

(FREQUENCY-DOMAIN MODAL ANALYSIS OF SINGLE-LEVEL INTERCONNECTIONS) (1)

FIGURE 4.4.1 Interconnection driven by unit step voltage source Vs of resistance Rs and terminated by load capacitance CL. The terminal endings on the neighboring interconnections are also shown. Interconnection capacitances as well as capacitive and inductive couplings between interconnections not shown.

GaAs substrate, quasi-TEM is the dominant mode of wave propagation and the transmission line equations are given as

(@x) (@t) @ V ðx; tÞ¼ —ΣR þ L @ ΣIðx; tÞð4:4:1Þ

(@x) (@t) @ Iðx; tÞ¼ —ΣG þ C @ ΣVðx; tÞð4:4:2Þ

where L and C are the inductance and capacitance matrices per unit length of the interconnections, R is determined by the resistance per unit length of the interconnections, and G is the conductance matrix determined by the conductivity of the substrate. For semi-insulating GaAs substrate, G can be neglected. The matrices L and C can be determined by the network analog method developed in Chapter 2. In the s domain, Eqs. (4.4.1) and (4.4.2) can be written as

d

dx Vðx; sÞ¼ —½R þ sL]Iðx; sÞð4:4:3Þ

d

dx Iðx; sÞ¼ —½G þ sC]V ðx; sÞð4:4:4Þ

(280) (CROSSTALK ANALYSIS)

(TRANSMISSION LINE ANALYSIS OF PARALLEL MULTILEVEL INTERCONNECTIONS) (279)

Defining

Z ¼ R þ sLY ¼ G þ sC

Eqs. (4.4.3) and (4.4.4) can be solved in the s domain, yielding

(rffiffiffippYZY xZY ‘ x)Vðx; sÞ¼ e—pffiZffiYffiffiðxÞViðsÞþ e—pffiZffiYffiffið‘—xÞVrðsÞð4:4:5Þ

(Z) (i) (r)Iðx; sÞ¼½e— ffiffiffiffið ÞV ðsÞ— e— ffiffiffiffið — ÞV ðsÞ]ð4:4:6Þ

In Eqs. (4.4.5) and (4.4.6), ‘ is the total length of the transmission line, ViðsÞ is the voltage vector of the incident wave at x ¼ 0, and VrðsÞ is that of the reflected wave at x ¼ ‘. At the end points x ¼ 0 and x ¼ ‘, Eqs. (4.4.5) and (4.4.6) yield

Vð0; sÞ ¼ ViðsÞþ e—pffiZffiYffiffi‘VrðsÞð4:4:7Þ

(Þ ¼ ) (Z½) (i) (r)Ið0; srYffiffiffi V ðsÞ— e—pffiZffiYffiffi‘V ðsÞ]ð4:4:8Þ

(rffiffiffipYZY‘)V ð‘; sÞ ¼ e—pffiZffiYffiffi‘ViðsÞþ VrðsÞð4:4:9Þ

(Z) (i) (r)Ið‘; sÞ ¼½e— ffiffiffiffi V ðsÞ— V ðsÞ]ð4:4:10Þ

Incorporating the boundary conditions determined by the lumped circuit elements connected to the interconnection line, that is,

V ð0; sÞ¼ VsðsÞ— RsIð0; sÞð4:4:11Þ

1

(L)V ð‘; sÞ¼ sC Ið‘; sÞð4:4:12Þ

we have

(i) (r) (sÞ) (Z½) (i) (r) (s)V ðsÞþ eð—pffiZffiYffiffiÞ‘V ðsÞ ¼ ð—R rYffiffiffi V ðsÞ— e—pffiZffiYffiffi‘V ðsÞ] þ V ðsÞð4:4:13Þ

(i) (r) (sCL) (Z) (i) (r)e—pffiZffiYffiffi‘V ðsÞþ V ðsÞ ¼ —. 1 ΣrYffiffiffi½e—pZffiffiYffiffi‘V ðsÞ— V ðsÞ]ð4:4:14Þ

which can be solved to yield, for ViðsÞ and VrðsÞ,

<8 "

rffiYffiffi#

pffiffiffiffi "

1 rffiYffiffi#—1"

1 rffiYffiffi#

(þ)

(:) (ZY ‘)VrðsÞ¼ VsðsÞ — 1 þ RsZ ½e] I —

sCLZ

I

sCLZ

"rffiYffiffi#Σ 1 Σ)—1

þ I — RsZepffiZffiYffiffi‘

ð4:4:15Þ

(ZY‘) (e—)ViðsÞ¼ —"e—

pffiZffiYffiffi‘ —

1 rffiYffiffi

pffiffiffiffi #—1Σ

(I þ)

1 e—

pffiZffiYffiffi‘Σ

VrðsÞð4:4:16Þ

sCLZsCL

(ðÞ) (ðÞ) (¼¼) (ð Þð Þ)The values for Vi s and Vr s can be substituted in Eqs. (4.4.7)–(4.4.10) to obtain the expressions for current and voltage at x 0 and x ‘ in the s domain. The load voltage is the element of V ‘; s that corresponds to the line on which the voltage source is applied. The other elements of V ‘; s represent the crosstalk voltages induced on the neighboring interconnection lines.

In principle, the time-domain response can be obtained by inverse Laplace transformation or by Fourier transformation. However, Fourier transformation results in errors due to a finite number of terms included in the summation. Therefore, the inverse Laplace transformation technique is used. If FðsÞ denotes the Laplace transform of f ðtÞ, then

(0)FðsÞ ¼ Z 1 f ðtÞe—st dtð4:4:17Þ

It can be shown [25] that, for t on the interval ð0; 2TÞ,

f ðtÞ ¼ hðtÞ— EðtÞð4:4:18Þ

(hðtÞ¼ 1 (FðaÞþX1 .ReΣF.a þkptΣcos.kptΣΣ— ImΣF.a þkptΣsin.kptΣΣΣ))where hðtÞ is given by

T2TT

k¼1

TT

ð4:4:19Þ

and the error EðtÞ is bounded by

EðtÞ ≤ M

eat

e2Tða—aÞ — 1

ð4:4:20Þ

(ð Þj ð Þj ≤ð — Þ) (ð Þ) (ΣΣ)where 1=T is the frequency step, M is a constant, and a is related to f t such that f t is an exponential of order a (i.e., f t Ceat). When 2T a a is large enough and we want our precision to be e, then a can be chosen to be [25]

(¼—)aalnðeÞ 2T

ð4:4:21Þ

(ð Þ) (ðÞ)Choosing a suitable value of T for the desired accuracy depends on the time range of interest (e.g., 0; ... ; tmax) and the computation time. When t is much smaller than 2T, then the approximation of f t by Eq. (4.4.19) converges very slowly because the frequency step determined by 1=T is too small and we need to include many terms for the summation to converge. On the other hand, if t is too close to 2T, then the error due to the term EðtÞ in Eq. (4.4.18) becomes large, as can be seen from Eq. (4.4.20). A good choice for T lies in the range 0:8 tmax, 1:2 tmax .

(k) (ð]ð]) (½]½])Numerical computations show that if we apply inverse Laplace transformation directly, then the summation converges very slowly for small values of t. This is because the frequency step determined by 1=T is too small for small t. To solve this problem, we can divide the time range 0; tmax into several time ranges 0; p tmax , pktmax; pk—1tmax ; ... ; ptmax; tmax and choose a different value of T for each time range such that T is not too large and the summation in Eq. (4.4.19) converges faster.

The value of p can be determined by a compromise between the desired accuracy and the computation time and is chosen to be 0.8.

Summation in Eq. (4.4.19) usually converges very slowly; it takes more than 5000 terms to achieve an accuracy of four significant digits. To overcome this problem, we can use the Wynn algorithm [25, 26] to accelerate the summation. The algorithm can be described as follows: For a summation series S defined as

(m)we define a 2D array as

S ¼

(Xm)n¼1

anm ¼ 1; 2; 3; ...ð4:4:22Þ

em

pþ1

¼ ep—1

1

(p) (p)þ em — em—1

p ¼ 1; 2; 3; ...ð4:4:23Þ

with

(0)em ¼ 0ð4:4:24Þ

(1)em ¼ Smð4:4:25Þ

In principle, em; em; em; em; .. . will be better approximations for the summation Sm in

3579

(9)Eq. (4.4.22). From numerical experiments, it can be found that em is the best choice for the present problem because higher order transformations result in rounding errors.

The Program DCMPVI

The computer program DCMPVI is based on the inverse Laplace transformation technique using the Wynn algorithm and the improved time range selection described above and was written in FORTRAN. It is presented in Appendix 4.1 on the accompanying ftp site. The interconnection capacitances and inductances used in the program are determined using the network analog method presented in Chapter 2 and include the fringing fields as well as the effects of shielding by the neighboring interconnections.

Numerical Simulations Using DCMPVI

The program DCMPVI has been used to study the dependence of the crosstalk among the interconnections in the configurations shown in Figs. 4.4.2a–c. One of the parameters is varied in a specific range while the others are kept fixed at their

typical values, chosen to be as follows: interconnection length ‘ ¼ 1000 mm, interconnection width W ¼ 1 mm, interconnection separation S ¼ 1 mm, inter- connection metal resistivity r ¼ 3 mK · cm, interlevel distances T12 and T23 are 2 mm, GaAs substrate thickness T ¼ 200 mm, driving transistor output resistance or

FIGURE 4.4.2 Schematic of (a) three single-level, (b) six bilevel, and (c) six trilevel interconnection configurations.

(¼)source resistance Rs ¼ 100 K, and loading transistor input capacitance or load capacitance CL 100 fF. The thickness of each interconnection line is kept at 0.5W. In the following discussion, the single-level interconnection configuration shown in Fig. 4.4.2a is assumed unless otherwise specified and the source is applied to one end of the second interconnection on the first level.

Magnitudes of the crosstalk voltages at the load on the first or third interconnection as functions of time in the range 0–200 ps for several values of the interconnection length are shown in Fig. 4.4.3. Figure 4.4.4 shows the

FIGURE 4.4.3 Crosstalk voltage waveforms in range 0–200 ps for several interconnection lengths for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.4 Dependence of maximum crosstalk voltage on interconnection length for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.5 Crosstalk voltage waveforms in range 0–200 ps for several interconnection widths for single-level interconnections in Fig. 4.4.2a.

dependence of the maximum crosstalk voltage on the interconnection length in the range 20–1000 mm. It shows that crosstalk increases almost linearly with length in the range 20–1000 mm. This is because the capacitance coupling the interconnec- tions increases almost linearly with length. For several interconnection widths, variations of the crosstalk voltages with time in the range 0–200 ps are shown in

Fig. 4.4.5, and Fig. 4.4.6 shows that the maximum crosstalk voltage is almost a logarithmic function of the interconnection width in the range 0.5–5 mm. As functions of time in the range 0–200 ps, crosstalk voltages for several interconnection separations are shown in Fig. 4.4.7, and Fig. 4.4.8 shows the dependence of the maximum crosstalk voltage on the interconnection separation in the range 0.5–5 mm. This figure shows that for separation of 0.5 mm and typical values of the other parameters, the maximum crosstalk voltage is nearly 15% of the input signal, which may be too large to allow error-free operation of some ICs.

Crosstalk voltages as a function of time in the range 0–200 ps for several values of the thickness of the GaAs substrate are shown in Fig. 4.4.9, and the dependence of maximum crosstalk voltage on substrate thickness in the range 5–200 mm is shown in Fig. 4.4.10. Crosstalk decreases somewhat with the decrease in the substrate thickness because of the increased shielding of the

coupling field lines by the ground plane. For various values of interconnection metal resistivity, variations of the crosstalk voltage on time in the range 0–500 ps

FIGURE 4.4.6 Dependence of maximum crosstalk voltage on interconnection width for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.7 Crosstalk voltage waveforms in range 0–200 ps for several interconnection separations for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.8 Dependence of maximum crosstalk voltage on interconnection separation for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.9 Crosstalk voltage waveforms in range 0–200 ps for several substrate thicknesses for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.10 Dependence of maximum crosstalk voltage on substrate thickness for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.11 Crosstalk voltage waveforms in range 0–500 ps for several interconnec- tion metal resistivities for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.12 Dependence of maximum crosstalk voltage on interconnection metal resistivity for single-level interconnections in Fig. 4.4.2a.

(·)are shown in Fig. 4.4.11, and the dependence of maximum crosstalk voltage on resistivity in the range 0.1–200 mK cm is shown in Fig. 4.4.12. It shows that the crosstalk decreases when the interconnection metal resistivity is increased. This is perhaps because increasing the interconnection resistance filters the high- frequency components from the input signal and their effect on the neighboring

lines is reduced.

For several values of source resistance, that is, the output resistance of the driving transistor, crosstalk voltages in the time range 0–200 ps are shown in Fig. 4.4.13, and Fig. 4.4.14 shows the dependence of maximum crosstalk voltage on source resistance in the range 0.1–1000 K. The effect of increasing the source resistance on the crosstalk can be understood in the same way as that of the interconnection resistivity, that is, the RC filtering effect on the input signal increases, thereby reducing the crosstalk voltage. Variations of the crosstalk voltage with time in the range 0–200 ps for several values of load capacitance, that is, the input capacitance of the loading transistor, are shown in Fig. 4.4.15, and Fig. 4.4.16 shows the de- pendence of maximum crosstalk voltage on load capacitance in the range 5–1000 fF. Figure 4.4.16 shows that crosstalk decreases rapidly with the increase of load capacitance. This is again due to increased filtering of the high-frequency components on the source line, resulting in reduced induced voltages on the neighboring lines.

FIGURE 4.4.13 Crosstalk voltage waveforms in range 0–200 ps for several source resistances for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.14 Dependence of maximum crosstalk voltage on source resistance for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.15 Crosstalk voltage waveforms in range 0–200 ps for several load capacitances for single-level interconnections in Fig. 4.4.2a.

FIGURE 4.4.16 Dependence of maximum crosstalk voltage on load capacitance for single- level interconnections in Fig. 4.4.2a.

FIGURE 4.4.17 Crosstalk voltage waveforms in range 0–200 ps for three and five interconnections in single-level configuration in Fig. 4.4.2a.

When the number of interconnection lines in the single-level configuration of Fig. 4.4.2a is increased from 3 to 5, Fig. 4.4.17 shows that the crosstalk voltage at the load end of the first-neighbor interconnections is reduced somewhat. This is due to the shielding effect of the second-neighbor lines. Crosstalk voltages induced at the load ends of the first- and second-neighbor interconnections in the time range 0–200 ps are shown in Fig. 4.4.18. This figure shows that the crosstalk on the second- neighbor interconnections is much less than that on the first-neighbor interconnec- tions. This is because the coupling capacitance between the source line and the second-neighbor interconnection line is less than that for the first-neighbor interconnection.

The crosstalk can also be calculated for the bilevel interconnection configuration shown in Fig. 4.4.2b, and the crosstalk voltages induced at the load ends of the first, fourth, and fifth interconnections in the time range 0–200 ps are shown in Fig. 4.4.19. It can be seen that the crosstalk on the fifth interconnection is the largest while that on the fourth interconnection is the smallest. This is because the fifth interconnection line is located just below the source interconnection, which results in the coupling capacitance being the largest while the coupling capacitance between the source interconnection and the fourth interconnection is the smallest due to the shielding effects of the first and the fifth interconnections. Comparison of these results with those for the single-level interconnections shows that the crosstalk voltage induced on the first-neighbor interconnections in the bilevel configuration is almost half of that in the single-level configuration. For the trilevel interconnection

FIGURE 4.4.18 Crosstalk voltage waveforms in range 0–200 ps at load ends of first- and second-neighbor lines for five single-level interconnections.

FIGURE 4.4.19 Crosstalk voltage waveforms in range 0–200 ps for first, fourth, and fifth lines in the bilevel interconnection configuration in Fig. 4.4.2b.

FIGURE 4.4.20 Crosstalk voltage waveforms in range 0–200 ps for first, fourth, and sixth lines in the trilevel interconnection configuration in Fig. 4.4.2c.

configuration, the crosstalk results are shown in Fig. 4.4.20 and can be understood in the same way as those for the bilevel interconnections.

ANALYSIS OF CROSSING INTERCONNECTIONS

In this section, the crosstalk signal induced in each crossing line embedded in the substrate due to the signal source applied to the main (driven) line printed on the top plane will be studied. Only the capacitive couplings will be considered in this analysis.

Mathematical Analysis

A schematic of the crossing interconnections analyzed in this section is shown in Fig. 4.5.1. A driving source is applied only on the main line on the top plane and the crossing lines in the second plane are not energized. As in the previous chapter, one way of analyzing this interconnection configuration is to divide it into three sections called the transmission line section, the crossing section, and the load section with the difference that each of the two sections of every crossing line on either side of the point of coupling with the main line should be modeled as a transmission line. The

FIGURE 4.5.1 Schematic of bilevel crossing interconnections analyzed in this section. Each crossing line is also terminated by source resistance Rs on one side and load capacitance CL on the other (not shown).

equivalent circuit used for studying the crosstalk in the crossing interconnections is shown in Fig. 4.5.2. The elements are defined as follows:

Vs ¼ voltage source

Rs ¼ source resistance

LB ¼ self-inductance of portion of driven line between two consecutive crossing lines RB ¼ resistance of portion of driven line between two consecutive crossing lines Cc ¼ coupling capacitance between main line and a crossing line

Rcl ¼ line resistance of a crossing line on left side of main line Rcr ¼ line resistance of a crossing line on right side of main line Lcl ¼ self-inductance of a crossing line on left side of main line Lcr ¼ self-inductance of a crossing line on right side of main line CL ¼ load capacitance

Rr ¼ resistance of portion of main line after crossing lines

FIGURE 4.5.2 Equivalent circuit of bilevel crossing interconnections including capacitive couplings. Inductive couplings not included.

(292) (CROSSTALK ANALYSIS)

(ANALYSIS OF CROSSING INTERCONNECTIONS) (291)

Lr ¼ self-inductance of portion of main line after crossing lines

(¼)Crground capacitance of portion of main line after crossing line (load section portion)

(¼) (pffiffiffiffi)Other symbols are defined as they appear. Following the same steps as in Section 3.4.1, the voltage and current in the s domain at the end of the transmission line section, that is, at x ‘, are given by

V ð‘; sÞ¼ e— ZY‘ViðsÞþ VrðsÞ

Ið‘; srYffiffiffi e—pffiZffiYffiffi‘V ðsÞ— V ðsÞ]

where

Þ¼Z½ir

VrðsÞ ¼ ½1 — R pffiYffiffiffi=ffiffiZffiffiffi]½1 — Z

V s e—pZY ‘ 1ZY=Z

(ffiffiffiffi Σpffiffiffiffiffiffiffiffiffið Þ—]sTX)pffiYffiffiffi=ffiffiZffiffiffi]e—2pffiZffiYffiffi‘ — ½1 þ R pffiYffiffiffi=ffiffiZffiffiffi]½1 þ Z

pffiYffiffiffi=ffiffiZffiffiffi]

(pffiYffiffiffi=ffiffiZffiffiffi]e—pffiZffiYffiffi‘ VrðsÞ)sTX

(ViðsÞ ¼ ½1 — Z)1 þ ZTXe—pffiZffiYffiffi‘

(TX)

sTX

ZTX ¼ Zp1 k ZX þ RB

1 — e—st

VsðsÞ ¼s

where Zx is the impedance of the crossing line as seen by the current flowing in the driven line given by

1

(c)Zx ¼ sC þ ðRcl

þ sLcl

þ RsÞ k .Rcr

þ sLcr

1

(Σþ)sCL

and the partial load Zp1 is given by

Zp1 ¼ Zp2 k Zx þ ZB

where

and so on, until

ZB ¼ RB þ sLBZp2 ¼ Zp3 k Zx þ ZB

(L) (.þk) (Σþ)Zpðn—2Þ ¼ Zpðn—1Þ k Zx þ ZB Zpðn—1Þ ¼ Zpn k Zx þ ZB

Zpn

¼ Z0

¼ Rr

1sL

sCrr

1

sCL

The current Ið‘; sÞ is the s domain input current for the crossing section.

In the crossing section, the driven line on the top plane and the second-level interconnections embedded in the substrate cross each other. This section is driven by the output of the transmission line section, and the output of this section drives the next section, that is, the load section. The driven line is coupled to the crossing lines by the coupling capacitances, which depend on the crossing area (which in turn depends on the line widths and the crossing angle), the interlevel separation, and the substrate’s dielectric constant. It is assumed that all the interconnection lines are of the same width, thickness, and material. The algorithm can be easily modified for different situations.

After some manipulation, it can be shown that the crosstalk voltage on the jth crossing line, that is, the voltage across the load capacitance on the jth crossing line, is given by the expression

(cross; j) (Þ¼ )Vðs

rYffiffiffi eð—pffiZffiYffiffiÞ‘0 V ðsÞ— V ðsÞ] × 1

(Z½) (i) (r) (sCL)where ‘0 is the length of the jth crossing line from the point of its coupling with the main line to its load CL,

Z ¼ R þ sLY ¼ G þ sC

(TX) (VrðsÞ¼ ½1 — Z) (pffiYffiffiffi=ffiffiZffiffiffi]e—2pffiZffiYffiffi‘0 — ½1 þ ZTX) (pffiYffiffiffi=ffiffiZffiffiffi])Vs;jðsÞe—pffiZffiYffiffi‘0 ½1 — ZTX pffiYffiffiffi=ffiffiZffiffiffi]

1 þ ZTXe—pffiZffiYffiffi‘0

(TX)

(ViðsÞ¼ ½1 — Z)and the equivalent of the source voltage for the jth crossing line is given by

(pffiYffiffiffi=ffiffiZffiffiffi]e—pffiZffiYffiffi‘0 VrðsÞ)Vs; j

ðsÞ ¼ ðIj — I

j—1

Þ× .Zx

(Σ—) 1

sCc

where Ij is the current flowing in the driven line after ‘‘seeing’’ the jth crossing line. The currents Ij ð j ¼ 1; 2; ... ; nÞ are given by

I ¼ I

Zx

1 TX Zx þ Zp1

I ¼ I

Zx

2 1 Zx þ Zp2

and so on, until

In ¼ I

Zxn—1 Zx þ Z0

(L)where ZL0

is the total impedance of the load section and In represents the current

flowing into the load section.

Simulation Results

(ð Þ)As mentioned earlier, the crosstalk effect can be studied by analyzing the plot of crosstalk voltage for a given set of interconnection parameters in a specific time range and plotting the maximum crosstalk voltage as a function of the interconnection parameter under investigation. To simulate the crosstalk effects in the embedded crossing interconnections due to a driven interconnection printed on top of the GaAs substrate, the computer program SPBIGV is presented in Appendix 4.2 on the accompanying ftp site. It incorporates the steps outlined above to find Vcross s and then uses the Pade´ approximation to carry out the inverse Laplace transformation. In the following results, one of the parameters is varied in a specific range while the other parameters are kept fixed at their typical values, which were selected to be the

(·)following: interconnection length 1000 mm, each, interconnection width 1.0 mm each, interconnection thickness 0.5 mm each, interconnection separation 1.0 mm each, interconnection material resistivity 3.0 mK cm, interlevel distance 2.0 mm, substrate thickness 200.0 mm, driving source resistance 100 K, and load capacitance 10 fF. In addition, the number of crossing lines is 25 and the crosstalk plots are those

for the 13th crossing interconnection. The frequency of the input square-wave train is 1 GHz.

Crosstalk voltage waveforms for several values of the interconnection length in the time range 0–100 ps are shown in Fig. 4.5.3, and the dependence of maximum crosstalk voltage on interconnection length in the range 100–2000 mm is shown in Fig. 4.5.4. For various values of the interconnection width, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.5, while the dependence

of the maximum crosstalk voltage on the interconnection widths in the range 0.2–

(·)2.0 mm is shown in Fig. 4.5.6. For several values of the interconnection material resistivity, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.7, and the dependence of maximum crosstalk voltage on resistivity in the range 1–100 mK cm is shown in Fig. 4.5.8.

Crosstalk voltage waveforms for several values of load capacitance in the time

range 0–100 ps are shown in Fig. 4.5.9, and the dependence of maximum crosstalk voltage on load capacitance in the range 5–200 fF is shown in Fig. 4.5.10. For various values of the driving source resistance, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.11, while the dependence of maximum crosstalk voltage on source resistance in the range 10–300 K is shown in Fig. 4.5.12.

FIGURE 4.5.3 Crosstalk voltage waveforms for several interconnection lengths in range 0–100 ps.

FIGURE 4.5.4 Dependence of maximum crosstalk voltage on interconnection lengths in range 100–2000 mm.

FIGURE 4.5.5 Crosstalk voltage waveforms for several interconnection widths in range 0–100 ps.

FIGURE 4.5.6 Dependence of maximum crosstalk voltage on interconnection widths in range 0.2–2.0 mm.

FIGURE 4.5.7 Crosstalk voltage waveforms for several interconnection material resistivities in range 0–100 ps.

FIGURE 4.5.8 Dependence of maximum crosstalk voltage on interconnection material resistivity in range 1–100 mK· cm.

FIGURE 4.5.9 Crosstalk voltage waveforms for several load capacitances in range 0–100 ps.

FIGURE 4.5.10 Dependence of maximum crosstalk voltage on load capacitance in range 5–200 fF.

FIGURE 4.5.11 Crosstalk voltage waveforms for several source resistances in range 0–100 ps.

FIGURE 4.5.12 Dependence of maximum crosstalk voltage on source resistance in range 10–300 K.

FIGURE 4.5.13 Crosstalk voltage waveforms for several interlevel distances in range 0–100 ps.

FIGURE 4.5.14 Dependence of maximum crosstalk voltage on interlevel distance in range 1–5 mm.

FIGURE 4.5.15 Crosstalk voltage waveforms for several crossing angles in range 0–100 ps.

FIGURE 4.5.16 Dependence of maximum crosstalk voltage on crossing angle in range 20○–90○.

FIGURE 4.5.17 Crosstalk voltage waveforms for several values of number of crossing interconnections in range 0–100 ps.

FIGURE 4.5.18 Dependence of maximum crosstalk voltage on number of crossing interconnections in range 8–70.

FIGURE 4.5.19 Crosstalk voltage waveforms for several values of frequency of input source in range 0–100 ps.

Crosstalk voltage waveforms for several values of interlevel distance in the time range 0–100 ps are shown in Fig. 4.5.13, and the dependence of maximum crosstalk voltage on interlevel distance in the range 1–5 mm is shown in Fig. 4.5.14. For various values of the crossing angle, crosstalk voltage waveforms in the time range

0–100 ps are shown in Fig. 4.5.15, while the dependence of maximum crosstalk voltage on crossing angle in the range 20○–100○ is shown in Fig. 4.5.16. For several values of the number of crossing lines, crosstalk voltage waveforms for the middle interconnection in the time range 0–100 ps are shown in Fig. 4.5.17, and the dependence of maximum crosstalk voltage on number of crossing lines in the range 8–70 is shown in Fig. 4.5.18. For several values of signal of frequency, crosstalk voltage waveforms in the time range 0–100 ps are shown in Fig. 4.5.19.

COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS

In this section, compact, that is, closed-form, expressions for the voltage waveforms under worst-case crosstalk conditions at the load end of a quiet interconnection are presented. First, two coupled interconnections are modeled as distributed RC networks [27], and then these are treated as open-circuit distributed RLC networks [22]. Finally, the analysis is extended to three coupled open-circuit interconnections modeled as distributed RLC networks [22]. An analysis of capacitively terminated single and coupled RLC interconnections is presented in [23].

(302) (CROSSTALK ANALYSIS)

(COMPACT EXPRESSIONS FOR CROSSTALK ANALYSIS) (301)

FIGURE 4.6.1 Two interconnection lines represented as coupled RC lines. (From [27].

# 1993 by IEEE.)

Distributed RC Model for Two Coupled Interconnections

Consider two interconnection lines of length ‘ each represented as distributed RC networks as shown in Fig. 4.6.1. Let R and C represent the total resistance and capacitance of each line, respectively, assumed equal for simplicity and CC represent the total coupling capacitance between the two interconnections. The two interconnections are driven by two step voltage sources VS1 and VS2 with internal resistances RS1 and RS2, respectively. Here, CL1 and CL2 are the capacitive loads on the two interconnections. The basic differential equations which govern the voltage waveforms V1 and V2 along these two coupled interconnections are described as

(¼ ðc1 þ c2Þ) I .@2V1Σ

(r) (1) (@x2)

.@V1Σ

(@t)

.@V2Σ

(@t)

(— cc) (ð4:6:1Þ) (¼ ðc1 þ c2Þ) 1 .@2V2Σ

(r) (2) (@x2)

.@V2Σ

(@t)

.@V1Σ

(@t)

(— cc) (ð4:6:2Þ)where r1 and r2 denote the resistances of the two lines per unit length, c1 and c2 denote the capacitances of the two lines, while cc denotes the coupling capacitance between the two lines per unit length. In other words, R1 ¼ r1ð‘Þ, R2 ¼ r2ð‘Þ, and CC ¼ ccð‘Þ. For simplicity, we will assume that r1 ¼ r2 ¼ r and c1 ¼ c2 ¼ c. Equations (4.6.1) and (4.6.2) can be solved to yield the following closed-form expressions for the load voltage waveforms V1ð‘; tÞ and V2ð‘; tÞ:

V ð‘; tÞ= V

þ K1 .ðV

þ V Þexp.— s1 · tΣ þ ðV

— V Þexp.— s1 · tΣΣ

1s12

S1S2

RCS1S2

RC þ 2RCC

ð4:6:3Þ

V ð‘; tÞ = V

þ K1 .ðV

þ V Þ exp.— s1 · tΣ — ðV

— V Þ exp.— s1 · tΣΣ

2s22

S1S2

RCS1S2

RC þ 2RCC

ð4:6:4Þ

where K1 and s1 are given by

(.Σ¼ —ðÞ) (1)K1:01 RT þ CT þ 14:6:5

RT þ CT þ p=4

1:04

s ¼

(2)

ð4:6:6Þ

(T) (T) (T) (T)1

R C þ R

þ C þ ð2=pÞ

(¼¼¼¼)with RTRS1=RRS2=R and CTCL1=CCL2=C. The relative errors of these coefficients are less than 3% for K1 and less than 4% for s1 for any values of RT and

CT . It should be noted that the exact value of K1 is 4=p and that of s1 is ðp=2Þ2 for

(½ðþ Þðþ Þ])RT ¼ CT ¼ 0. When RT ¼ CT 1, the exact value of K1 is —1 and that of s1 is 1= RT1 CT1 . Both these asymptotic values are correctly produced by the

expressions (4.6.5) and (4.6.6).

(¼)It is clear from expressions (4.6.3) and (4.6.4) that if VS1 VS2, that is, the two lines are driven by in-phase source signals, each line behaves as a distributed RC line with a capacitance C. On the other hand, if the two lines are driven by out-of-phase source signals, that is, if VS2 ¼ —VS1, then each line behaves as a distributed RC line with a capacitance equal to C þ 2CC.

(ðÞ¼)The peak value of V2 ‘; t when VS2 0 is the maximum crosstalk voltage induced at the load end of the second line by the coupling capacitance. It is this value that the designer needs to keep in mind to avoid malfunction of the circuit. It can be determined by differentiating Eq. (4.6.4) to be

. 1Σ1=2Z. ZΣ1

. Z Σ

where

V2; max ¼ VS1K1

1 þ 2Z

1 þ 2Z

(¼)ZCC C

= 2 VS1

1 þ Z

ð4:6:7Þ

The approximation at the right end of Eq. (4.6.7) holds when RT ¼ CT ¼ 0 and

Z ≤ 2.

In a special case when RS1 is zero and RS2 is finite, the maximum crosstalk voltage

is given by

(S1)V= V

.0:5 þ RT2Σ. Z Σ

2;max

1 þ RT21 þ Z

In this case, the crosstalk becomes worse than that predicted from Eq. (4.6.7).

A comparison between the voltage waveforms obtained using the compact expression (4.6.7) with that using SPICE (with each interconnection modeled as a 10-step RC ladder network) shows that the maximum error in the compact expression is less than 3% of VS1.

Simple expressions for the coupling capacitances between the interconnections can be derived from those given in Section 2.4. For a system of two lines on a ground plane, the coupling capacitance C12 is given by [27]

(C12 ¼ eox 1:82) (þ)".T Σ1:08

(H)

.WΣ0:32#. S

(H)

Σ—1:38

(ð4:6:8Þ)

(H þ 0:43)while for a system of three interconnections on a ground plane, the coupling capacitances are given by [27]

(C12 ¼ eox 1:93) (þ1:14)".T Σ1:1

(H)

.WΣ0:31#. S

(H)

Σ—1:45

(ð4:6:9Þ)

(H þ 0:51)Relative errors of these capacitance expressions are less than 15% for the values of

T=H, W=H, and S=H between 0.3 and 3.0.

Distributed RLC Model for Two Coupled Interconnections

Two coupled distributed RLC interconnections A (active) and Q (quiet) shown in Fig. 4.6.2 are described by the following partial differential equations [22]:

@2@@

@x2 VQðx; tÞ ¼ rðcgnd þ cmÞ @t VQðx; tÞ— rcm @t VAðx; tÞþ ½lsðc þ cmÞ

@2@2

— lmcm] @t2 VQðx; tÞþ ½lmðcgnd þ cmÞ— lscm] @t2 VAðx; tÞð4:6:10Þ

FIGURE 4.6.2 Two coupled distributed RLC interconnections A (active) and Q (quiet). (From [22]. # 2000 by IEEE.)

@2@@

@x2 VAðx; tÞ¼ rðcgnd þ cmÞ @t VAðx; tÞ— rcm @t VQðx; tÞþ ½lsðcgnd þ cmÞ

@2@2

— lmcm] @t2 VAðx; tÞþ ½lmðcgnd þ cmÞ— lscm] @t2 VQðx; tÞð4:6:11Þ

(¼)where VA is the transient voltage along the active interconnection, VQ is the transient voltage along the quiet interconnection, cgnd is the ground capacitance of the interconnection, cm is the mutual (coupling) capacitance between the interconnec- tions, ls is the self-inductance of each interconnection, and lm is the mutual (coupling) inductance between the two interconnections. Both lines A and Q are of finite length ‘ and are open circuited at the load ends, line A is driven by a voltage source VS having a source resistance RS whereas line Q is not driven by a voltage source though it is connected to a resistance RS at x 0. The resulting boundary conditions for current and voltage along the lines A and Q are as follows:

VAðx ¼ 0; tÞ ¼ VSðtÞ— RSIAðx ¼ 0; tÞð4:6:12Þ

VQðx ¼ 0; tÞ ¼ —RSIQðx ¼ 0; tÞð4:6:13Þ

IAðx ¼ ‘; tÞ ¼ 0ð4:6:14Þ

IQðx ¼ ‘; tÞ ¼ 0ð4:6:15Þ

Equations (4.6.10) and (4.6.11) can be decoupled in terms of the following voltages

Vþ and V— defined as

Vþ ¼ VA þ VQV— ¼ VA — VQ

The resulting set of decoupled partial differential equations is

@2@@2

@x2 Vþðx; tÞ¼ rc @t Vþðx; tÞþ ðls þ lmÞc @t2 Vþðx; tÞð4:6:16Þ

@2@@2

@x2 V—ðx; tÞ¼ rðc þ 2cmÞ @t V—ðx; tÞþ ðls — lmÞðc þ 2cmÞ @t2 V—ðx; tÞð4:6:17Þ

The boundary conditions for voltages Vþ and V— and for currents Iþ ¼ IA þ IQ and

I— ¼ IA — IQ can be derived from Eqs. (4.6.12) to (4.6.15) as follows:

Vþðx ¼ 0; tÞ¼ VSðtÞ— RSIþðx ¼ 0; tÞð4:6:18Þ

V—ðx ¼ 0; tÞ¼ VSðtÞ— RSI—ðx ¼ 0; tÞð4:6:19Þ

Iþðx ¼ ‘; tÞ¼ 0ð4:6:20Þ

I—ðx ¼ ‘; tÞ¼ 0ð4:6:21Þ

Equations (4.6.18)–(4.6.21) indicate that the boundary conditions for ðVþ; IþÞ and ðV—; I—Þ are the same as those for an open-circuit single line driven by a voltage source VS with an arbitrary resistance RS.

(ðÞ) (ðÞ)Equation (4.6.16) suggests that Vþ x; t is the solution for the voltage along either of the two interconnection lines when both are excited simultaneously. In this case, the mutual capacitance between the lines will be zero and each line will have its ground capacitance only. In this configuration, since the currents in the two lines are in the same direction, the effective inductance of each line will be the sum of its self- inductance and the mutual inductance between the two lines. On the other hand, Eq. (4.6.17) suggests that V— x; t is the solution for the voltage along the active interconnection line when the adjacent line is switching with opposite polarity. In this case, the mutual capacitance between the lines will be twice its previous value in addition to each line having its ground capacitance. In this configuration, since the currents in the two lines are equal in magnitude but opposite in direction, the effective inductance of the line will be the difference of its self-inductance and the mutual inductance between the two lines.

The worst-case crosstalk on the quiet line occurs when both lines are initially uncharged and the active line is connected to the voltage source. In this case, the voltage waveform induced on the quiet line is given by

VQð‘; tÞ¼ 1=2½Vfinð‘; t; l ¼ ls þ lm; c ¼ cgndÞ— Vfinð‘; t; l ¼ ls — lm; c ¼ cgnd þ 2cmÞ]

ð4:6:22Þ

(ðÞ)In Eq. (4.6.22), Vfin x; t represents the voltage waveform along a single interconnection line derived earlier in Chapter 3. It is given by

Vfinð‘; tÞ ¼ 2Vinfðx ¼ ‘; t; m ¼ 0Þ

(i!j!ðn — iÞ!)qn1

(n¼1 i¼0) (j¼0)þ 2e—r=ð2lÞt X X X ð—1ÞiFðn—iþjÞ nðn — 1 þ jÞ!

×Vinfðx ¼ ð2n þ 1Þ‘; t; m ¼ i þ jÞð4:6:23Þ

(t2 — ðx) (lcÞ2)where Vinfðx; t; mÞ denotes the voltage waveform along the semi-infinite line given by

(Vinfðx; t; mÞ¼ VS) (0Z0 þ RS) (pffilfficffiffi) (e—r=ð2lÞt I0)". ZΣ t — xpffilfficffi!m=2

(t þ x)

. r qffiffiffiffiffiffiffiffiffiffiffiffiffiffipffiffiffiffiffi ffiffiffiffiffiΣ

(2l)

þ 1 X1

t — xpffilfficffi!ðkþmÞ=2

(t þ x) (lc)

e—r=ð21Þt ½4 — ð1 þ FÞ2Fk—1]

(pffiffiffiffi) (2l) (2 k¼1)× IðkþmÞ

. r qffitffi2ffiffiffi—ffiffiffiffiffiðffiffixffiffipffiffiffiffilfficffiÞffiffi2ffiΣ#uðt — xpffilfficffiÞð4:6:24Þ

FIGURE 4.6.3 Three parallel coupled interconnections, each driven by voltage source VS having internal source resistance RS sandwiched between two virtual ground planes. (From [22]. # 2000 by IEEE.)

Distributed RLC Model for Three Coupled Interconnections

Three parallel coupled interconnections, each driven by a voltage source VS having an internal source resistance RS, sandwiched between two virtual ground planes as shown in Fig. 4.6.3 can be described by the partial differential equations [22]

(647564)@2 2 V1ðx; tÞ 3

2 Cgnd þ cm þ c13—cm—c13

3 @ 2 V1ðx; tÞ 3

@x2 V2ðx; tÞ ¼ r

V3ðx; tÞ

—cmCgnd þ 2cm—cm

(756475)—c13—cmCgnd þ cm þ c13

@t V2ðx; tÞ

V3ðx; tÞ

(647654) (75)2 l11 l12 l13 32 Cgnd þ cm þ c13—cm—c133

þ l12 l22 l23 l13 l23 l33

(6475) @ 2 V1ðx; tÞ 3

—cmCgnd þ 2cm—cm

—c13—cmCgnd þ cm þ c13

@t2 V2ðx; tÞð4:6:25Þ

V3ðx; tÞ

The inductance and capacitance matrices are connected by the following relationship:

24 l11 l12 l13 3524 Cgnd þ cm þ c13—cm—c13

3 1 21 0 0 3

(0 0 1)

l12 l22 l23

l13 l23 l33

—cmCgnd þ 2cm—cm

—c13—cmCgnd þ cm þ c13

5 ¼ v2 40 1 0 5

ð4:6:26Þ

where v is the speed of propagation of an electromagnetic wave in the dielectric medium where the interconnections are placed. From the symmetry of the interconnections, we will assume that the voltage waveforms on the outer interconnections 1 and 3 are the same and call them Voðx; tÞ. For this reason, the coupling capacitance c13 can be taken as effectively zero. On the same lines, we will represent the voltage waveform on the inner interconnection 2 as Viðx; tÞ. Then the

matrix equation (4.6.25) can be expressed as the following two coupled partial differential equations after setting c13 ¼ 0:

@2@@1 @2

@x2 Voðx; tÞ ¼ rðcgnd þ cmÞ @t Voðx; tÞ— rcm @t Viðx; tÞþ v2 @t2 Voðx; tÞð4:6:27Þ

@2@@1 @2

@x2 Viðx; tÞ ¼ —2rcm @t Voðx; tÞ— rðcgnd þ 2cmÞ @t Viðx; tÞþ v2 @t2 Viðx; tÞ ð4:6:28Þ

Equations (4.6.27) and (4.6.28) can be decoupled in terms of the voltages Vsum and

Vdiff defined as

The resulting equations are

Vsum ¼ 2Vo þ Við4:6:29Þ

Vdiff ¼ Vo — Við4:6:30Þ

@2@1 @2

@x2 Vsumðx; tÞ ¼ rcgnd @t Vsumðx; tÞþ v2 @t2 Vsumðx; tÞð4:6:31Þ

@2@1 @2

@x2 Vdiffðx; tÞ ¼ rðcgnd þ 3cmÞ @t Vdiff ðx; tÞþ v2 @t2 Vdiff ðx; tÞð4:6:32Þ

(ðÞ)The boundary conditions for (Vsum, Isum) and Vdiff; Idiff can be found from those for the inner and outer interconnections to be

Vsumðx ¼ 0Þ ¼ 2VSðtÞ— RSIsumðx ¼ 0Þð4:6:33Þ

Vdiffðx ¼ 0Þ ¼ VSðtÞ— RSIdiff ðx ¼ 0Þð4:6:34Þ

Isumðx ¼ ‘Þ ¼ 0ð4:6:35Þ

Idiff ðx ¼ ‘Þ ¼ 0ð4:6:36Þ

(ðÞ)According to Eqs. (4.6.31) and (4.6.32), the voltage waveforms for Vsumðx; tÞ and Vdiff x; t are the solutions for a single finite line though with different capacitance and inductance values. These can be used to find the voltage waveforms for the worst-case time delay and crosstalk scenarios.

(.¼¼)The worst-case crosstalk on the inner interconnection occurs when all three lines are initially uncharged and the two outer interconnections are made simultaneously active by turning on their sources. The resulting load voltage waveform for the inner (quiet) interconnection is then given by

VQð‘; t

2

(.)Þ ¼ 3 V

fin

(.¼¼)‘; t; l 1; c2c 2cgndv2

gndΣ

—Vfin

‘; t; l 1; c2c

ð2cgnd þ 3cmÞv2

gnd

þ 3cm

ΣΣð4:6:37Þ

(ðÞ)In Eq. (4.6.37), Vfin x; trepresents the voltage waveform along a single interconnection line derived earlier in Chapter 3. It is given by

Vfinð‘; tÞ ¼ 2Vinfðx ¼ ‘; t; m ¼ 0Þ

(i!j!ðn — iÞ!)qn1

(n¼1 i¼0) (j¼0)þ 2e—r=ð2lÞt X X X ð—1ÞiFðn—iþjÞ nðn — 1 þ jÞ!

×Vinfðx ¼ ð2n þ 1Þ‘; t; m ¼ i þ jÞð4:6:38Þ

(ðÞ) (t2 — ðx) (lcÞ2)where Vinf x; t; m denotes the voltage waveform along the semi-infinite line given by

(Vinfðx; t; mÞ ¼ VS) (0Z0 þ RS) (pffilfficffiffi) (e—r=ð2lÞt I0)". ZΣ t — xpffilfficffi!m=2

(t þ x)

. r qffiffiffiffiffiffiffiffiffiffiffiffiffiffipffiffiffiffiffi ffiffiffiffiffiΣ

(2l)

þ 1 X1

t — xpffilfficffi!ðkþmÞ=2

(t þ x) (lc)

e—r=ð21Þt ½4 — ð1 þ FÞ2Fk—1]

(pffiffiffiffi) (2l) (2 k¼1)× IðkþmÞ

. r qffitffi2ffiffiffi—ffiffiffiffiffiðffiffixffiffipffiffiffiffilfficffiÞffiffi2ffiΣ#uðt — xpffilfficffiÞð4:6:39Þ

Comparisons of the normalized load voltages obtained by the compact expressions for the distributed RLC interconnection model with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements are shown in Fig. 4.6.4 [22]. For these comparisons, the interconnection metal is assumed to be copper surrounded by a low-k dielectric. The interconnection parameters are as follows:

Interconnection length 3.6 cm

Interconnection cross section 2:1 mm × 2:1 mm Resistance per unit length 37.86 K/cm Driving source resistance 133.3 K

Lossless characteristic impedance Z0þ ¼ 266:32 K

Lossless characteristic impedance Z0— ¼ 88:77 K

Figure 4.6.4 shows that the HPICE waveforms approach the compact expression waveform as the number of RLC elements is increased in the HSPICE simulation. For the typical values of the interconnection and driving source parameters chosen in these comparisons, there is virtually complete agreement between the two waveforms for 500 or more RLC elements, lending excellent support to the compact expressions.

(HSPICE Simulation of 1 RLC Element Compact RLC Expression) ( HSPICE Simulation of 10 RLC Element Compact RLC Expression)0.400.40

0.300.30

(Vo/Vdd) (Vo/Vdd)0.200.20

0.100.10

0.00

0.0e+005.0e–101.0e–09

Time [sec] (a)

1.5e–092.0e–00

0.00

0.0e+005.0e–101.0e–09

Time [sec] (b)

1.5e–092.0e–00

(HSPICE Simulation of 50 RLC Element Compact RLC Expression) (HSPICE Simulation of 500 RLC Element Compact RLC Expression)0.400.40

0.300.30

(Vo/Vdd) (Vo/Vdd)0.200.20

0.100.10

0.00

0.0e+005.0e–101.0e–09

Time [sec] (c)

1.5e–092.0e–00

0.00

0.0e+005.0e–101.0e–09

Time [sec] (d)

1.5e–092.0e–00

FIGURE 4.6.4 Comparison of normalized load voltages obtained by compact expressions for distributed RLC interconnection model with those obtained by HSPICE with 1, 10, 50, and 500 lumped RLC elements. (From [22]. # 2000 by IEEE.)

MULTICONDUCTOR BUSES IN GaAs HIGH-SPEED LOGIC CIRCUITS

The propagation delays, crosstalk, and pulse distortion associated with multi- conductor interconnecting buses are critical issues in the design of large-scale and very large scale high-speed logic ICs on conventional or GaAs substrates. Modeling of these buses has received considerable attention in the literature, and it is widely accepted that the lumped models are inadequate for high-speed ICs. The validity of transmission line models has also been questioned [28] because these do not include either surface wave excitation or free-space line or load radiations. Nevertheless, it can be shown that the quasi-TEM models are satisfactory as long as coupling effects within a multiconductor bus (MBUS) rather than between distant MBUSes are concerned. In this section, a lossy quasi-TEM model of crosstalk for MBUSes on semi-insulating GaAs substrate [15] is presented.

The Model

(¼) (¼¼)A schematic of a high-speed VLSI bus made of N (common values of N are powers of 2, e.g., 8, 16, 32, .. .) parallel equispaced metallic strips deposited either on a semi-insulating substrate (GaAs ICs) or on a thin oxide layer placed on a semiconducting substrate (Si ICs) along with the lower conducting ground plane is shown in Fig. 4.7.1. Typical values of widths, thicknesses, and spacings of the conducting strips usually fall into the ranges w 1–10 mm, t 0:5–2 mm, and s 1–10 mm, respectively.

(½ ]½ ]½ ]) (½ ])Since we are interested in crosstalk between conductors within the same bus and not between distant buses (which are affected by surface wave excitations), we can describe the structure of Fig. 4.7.1 by a quasi-TEM model, that is, as a multiconductor transmission line characterized by the capacitance matrix C , inductance matrix L , resistance matrix R , and conductance matrix G whose elements are defined per unit length and, in principle, can depend on frequency. Since the GaAs substrate is almost lossless and the Si substrate can be considered lossless as long as the frequency is such that the onset of slow waves can be avoided, the conductance matrix can be neglected. Then, the signal propagation on the bus can be described by the well-known generalizations of Kirchhoff’s equations [29]:

@ vðz; tÞ ¼ —.½R]þ ½L] @ Σiðz; tÞ

(308) (CROSSTALK ANALYSIS)

(MULTICONDUCTOR BUSES IN GAAS HIGH-SPEED LOGIC CIRCUITS) (307)

@z@t

@@

ð4:7:1Þ

@z iðz; tÞ ¼ —½C] @t vðz; tÞ

(ðÞðÞ)where v z; t and i z; t are the N-component voltage and current vectors. As shown in Fig. 4.7.2, the input signals are fed into the bus by voltage generators having finite internal impedances (simulating the output of the driving stage) and the bus is loaded

on the right side by the input impedances of the next logic stage.

For low-speed signals, the MBUS behaves as RC lines resulting in mainly diffusive transients and strong signal distortion. Above a critical frequency which depends on the propagation mode considered, the bus behaves as lossy LC lines and propagation dominates. Therefore, for a wide range of input signal frequencies, simulation of the transient behavior of the bus can be performed by solving

FIGURE 4.7.1 Schematic of structure of MBUS. (From [15]. # 1989 by IEEE.)

FIGURE 4.7.2 Termination network for MBUS analyzed in this section. (From [15].

# 1989 by IEEE.)

Eqs. (4.7.1) through standard spectral-domain techniques, that is, Fourier analysis and back transformation.

First, the frequency-domain response of the N lines is determined. Using standard multiconductor line analysis [29], we define the series impedance matrix as

½Zs]¼ ½R]þ jo½L]

and the parallel admittance matrix as

½Yp]¼ jo½C]

A symmetrical grounded N-conductor line supports N propagation modes which are called even or odd depending on whether their potential distribution is even or odd with respect to the center of the line. The N complex modal propagation constants ki will be a solution of the eigenvalue problem:

(2)ðk ½U]þ ½Zs]½Yp]Þ½Mv] ¼ 0

where ½Mv] is the voltage eigenvector matrix and ½U] is the identity matrix. The current eigenvector matrix ½Mi] is then given by

(i) (v) (ki)½M ]¼ o½C]½M ] diag.1 Σ and the characteristic admittance matrix is given by

½Yc] ¼ ½Mi]½Mv]—1

The characteristic impedance matrix ½Zc] is the inverse of ½Yc] and the modal impedances are given by the eigenvalues of ½Zc]. The voltage and current vectors on

the lines are then given by

VðzÞ ¼ ½Mv]½WþðzÞþ W—ðzÞ]

IðzÞ ¼ ½Yc]½Mv]½WþðzÞ— W—ðzÞ]

ð4:7:2Þ

where

WT ¼ fWiTðzÞg

WiTðzÞ¼ WiTð0Þe;jkiz

ð4:7:3Þ

Wiþ and Wi— are the amplitudes of the progressive and regressive components of the ith mode, and ki is the propagation constant of the ith mode. The presence of generators and loads on the bus leads to the following boundary conditions:

Vð0Þ ¼ E — ½Zg]Ið0Þ

Vð‘Þ ¼ ½ZL]Ið‘Þ

ð4:7:4Þ

where E ¼ fEiðoÞg, ½Zg] ¼ diagfZgig, ½ZL]¼ diagfZLig, Ei is the voltage spectrum of the generator at the input of the ith strip, Zgi is the internal impedance of the ith generator and ZLi is the load impedance on the ith strip. Substituting Eqs. (4.7.2) and (4.7.3) into (4.7.4) leads to the following linear system for WTð‘Þ:

"ð½YL]— ½Yc]Þ½Mv]ð½YL]þ ½Yc]Þ½Mv]

#" Wþð‘Þ # ¼ " O # ð4:7:5Þ

ð½U]þ ½Zg]½Yc]Þ½Mv]½P]—1ð½U]— ½Zg]½Yc]Þ½Mv]½P]

where

W—ð‘ÞE

½P] ¼ diagfe—jki ‘g

After solving Eq. (4.7.5), the voltage and current spectra can be obtained from Eq. (4.7.2). The time-domain response can then be obtained by inverse Fourier transformation.

Lossless MBUS with Cyclic Boundary Conditions

(¼¼¼)The transient behavior of the MBUS can be analyzed by considering an idealized case of a lossless MBUS with cyclic boundary conditions which can be solved explicitly. If all load and generator impedances are equal and the signal is applied to the kth line only, that is, ZLi ZL, Zgi Zg, and Ei Edik, then the solution of Eq. (4.7.5) can be obtained to be

(ViðoÞ ¼ ) (exp j N nði — kÞ)( 1 XN—1 Σ

(N) (n¼0)

. 2p

ΣΣ)

(gnðoÞ) (EðoÞð4:7:6Þ)

where

gnðoÞ¼

ð1 — rnÞ½1 þ FnðoÞ]e—jkn ‘

(n) (n)2½1 — r F ðoÞe—2jkn ‘]

where rn and Fn are the reflection coefficients of Zg and ZL with respect to the characteristic impedance Zn of the nth mode. Equation (4.7.6) represents the output voltage spectra as superpositions of N modal line contributions. The time-domain output waveforms can be obtained by the inverse Fourier transformation to be

(viðtÞ¼ N) (exp j N nði — kÞ)1 (XN—1 Σ

(n¼0)

. 2p

ΣΣ)

(hnðtÞ) (ð4:7:7aÞ)

where hnðtÞ is the inverse Fourier transform of gnðoÞEðoÞ.

In the practically important case where the load is capacitive ¼ Cload, the

generator impedance is resistive ¼ Rgen, and the driving voltage is a unit step uðtÞ, then the modal line contribution hnðtÞ is given by

h ðtÞ ¼ ð1 — r Þ X1 rm½1 — Øn ðtn Þ]uðtn Þð4:7:7bÞ

where

nnn

m¼0

m mm

tn ¼ t — ð2m þ 1ÞT

11

T ¼a ¼

mnnvn

nZnCload

and

(m)Øn ðtÞ ¼ e—an t

(X) (k)m k¼0

.mΣð—1Þ

m—k

k

(Xk)ð2Þ

i¼0

ðantÞ

(i)i!

(ð Þ)Due to the superposition of echoes, the function hn t exhibits a staircase shape, as

shown in Fig. 4.7.3.

Simulation Results

(¼¼¼¼)First, the quasi-TEM model can be validated by comparison of the computed results with the experimentally measured results. Such a comparison for two coupled lines is shown in Fig. 4.7.4. The experimental results have been obtained from [30, 31]. For these results, the excitation is a tapered unit step with trise 40 ps and other parameters are w 1:5 mm, s 2 mm, t 0:5 mm,

(¼¼¼¼¼¼)h 400 mm, b 0, ‘ 3 mm, Rin 2100 K, Rout 380 K, er 12:8, and strip

(¼×)conductivity g 2:1 106 S=m.

Time-domain voltage responses of an eight-conductor MBUS to a unit 1-ns

voltage pulse applied to line 4 assuming lossless strips are shown in Fig. 4.7.5a.

FIGURE 4.7.3 For MBUS of Fig. 4.7.1 with lossless strips, typical modal line contribution of zeroth mode (solid line) in response to 1-ns unit square pulse (dashed curve). (From [15]. # 1989 by IEEE.)

(¼¼¼¼¼) (¼¼¼¼) (¼ ×)Fig. 4.7.5b shows these responses for lossy strips of conductivity g 4 107 S=m. Values of the other parameters are w 3 mm, s 4 mm, t 0:5 mm, h 400 mm, b 0, ‘ 5 mm, Rg 2100 K, Cload 20 fF, and er 12:9. The time-domain responses of the same structure as in Fig. 4.7.5 to a typical high-speed digital signal

FIGURE 4.7.4 Comparison of computed results with experimentally measured results for two coupled lines. Experimental results obtained from [3, 4]. Excitation is a tapered unit step with trise ¼ 40 ps and other parameters are w ¼ 1:5 mm, s ¼ 2 mm, t ¼ 0:5 mm, h ¼ 400 mm,

b ¼ 0, ‘ ¼ 3 mm, Rin ¼ 2100 K, Rout ¼ 380 K, er ¼ 12:8, and strip conductivity g ¼

2:1 × 106 S=m. (From [15]. # 1989 by IEEE.)

FIGURE 4.7.5 Time-domain voltage responses of eight-conductor MBUS to unit 1-ns voltage pulse applied to line 4 assuming (a) lossless strips and (b) lossy strips of conductivity g ¼ 4 × 107 S=m. Other parameters: w ¼ 3 mm, s ¼ 4 mm, t ¼ 0:5 mm, h ¼ 400 mm, b ¼ 0,

‘ ¼ 5 mm, Rg ¼ 2100 K, Cload ¼ 20 fF, er ¼ 12:9. (From [15]. # 1989 by IEEE.)

(¼)represented by a 0.2-ns square pulse applied to line 4 are shown in Fig. 4.7.6. For the MBUS structure of Fig. 4.7.5, the peak voltage couplings are plotted in Fig. 4.7.7. Figure 4.7.7a shows the effect of interconnection length for lossless strips, Fig. 4.7.7b shows the effect of lossy lines for ‘ 5 mm, and the effect of input signal rise time for lossy lines is shown in Fig. 4.7.7c.

FIGURE 4.7.6 Time-domain responses of structure of Fig. 4.7.1 to typical high-speed digital signal represented by 0.2-ns square pulse applied to line 4. (From [15]. # 1989 by IEEE.)

EXERCISES309

FIGURE 4.7.7 Peak voltage couplings for MBUS structure of Fig. 4.7.1: (a) effect of interconnection length for lossless strips, (b) effect of lossy lines for ‘ ¼ 5 mm, and (c) effect of input signal rise time for lossy lines. (From [15]. # 1989 by IEEE.)

EXERCISES

E4.1 Referring to the lumped-capacitance model of Fig. 4.1.1, show that the amplitude of the crosstalk voltage at time t is given by

(2)V2ðtÞ ¼ 1 ½e—t=t1 — e—t=t2 ]

(¼ ð þÞ¼ ðþþÞ)where t1R CCLand t2R 2CcCCL . Further prove that the maximum value of the crosstalk voltage is given by

V¼ 1 " expΣ.nc — 1Σ ln.1 þ ncΣΣ — expΣ.—nc þ 1Σ ln.1 þ ncΣΣ#

2; max2

2nc

1 — nc

2nc

1 — nc

where

(nc) C

c ¼ C þ Cc þ CL

E4.2 Referring to Fig. 4.2.2, show that the voltage and current on the kth conductor can be expressed in terms of the normal modes by the equations

(y) (k) (Z0y) (Z0y)Vk ðzÞ ¼ X ½Ayf e—jðk—1Þyejo½t—ðz=vyÞ] þ Ayre—jðk—1Þyejoðtþz=vyÞ]

I ðzÞ ¼ X ΣAyf e—jðk—1Þyejo½t—ðz=vyÞ] — Ayr e—jðk—1Þyejoðtþz=vyÞΣ

(y)

where z denotes the position on the conductor, o is the angular frequency, and Ayf and

Ayr are the amplitudes of the forward and backward voltage waves in the y mode.

E4.3 The mode wave amplitudes Ayf and Ayr in exercise E4.2 can be determined by using the known terminal conditions at both ends of each strip conductor. Assuming a variety of terminal conditions, find these amplitudes.

E4.4 Using the modifications suggested in Section 3.4.2, extend Section 4.5 to carry out a comprehensive analysis of crosstalk in the crossing interconnections shown in Fig. 3.4.7. Comment on the validity of the assumptions and approximations used in your analysis.

E4.5 A few methods of reducing crosstalk are discussed in this chapter. Can you think of other methods? Discuss the merits and drawbacks of each method that you propose.

E4.6 List and discuss the desirable characteristics of a numerical model that make it more suitable for inclusion in a CAD tool. Review the techniques presented in this chapter from the point of view of their suitability for inclusion in a CAD tool.

REFERENCES

1. J. Chilo and T. Arnaud, ‘‘Coupling Effects in the Time Domain for an Interconnecting Bus in High-Speed GaAs Logic Circuits,’’ IEEE Trans. Electron Devices, vol. ED-31, pp. 347–352, Mar. 1984.

2. M. Riddle, S. Ardalan, and J. Suh, ‘‘Derivation of the Voltage and Current Transfer Functions for Multiconductor Transmission Lines,’’ Proc. IEEE Int. Symp. Circuits Syst., pp. 2219–2222.

3. A. R. Djordjevic and T. K. Sarkar, ‘‘Analysis of Time Response of Lossy Multiconductor Transmission Line Networks,’’ IEEE Trans Microwave Theory Tech., vol. MTT-35, pp. 898–908, Oct. 1987.

(310) (CROSSTALK ANALYSIS)

REFERENCES311

4. F. Romeo and M. Santomauro, ‘‘Time Domain Simulation of n Coupled Transmis- sion Lines,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-35, pp. 131–137, Feb. 1987.

5. S. Seki and H. Hasegawa, ‘‘Analysis of Crosstalk in Very High-Speed LSI/VLSI Using a Coupled Multiconductor Stripline Model,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-32, pp. 1715–1720, Dec. 1984.

6. A. R. Djordevic, T. K. Sarkar, and R. F. Harrington, ‘‘Time Domain Response of Multiconductor Transmission Lines,’’ Proc. IEEE, vol. 75, pp. 743–764, June 1987.

7. S. Frankel, Multiconductor Transmission Line Analysis, Norwood, MA: Artech, 1977.

8. A. J. Gruodis and C. S. Chang, ‘‘Coupled Lossy Transmission Line Characterization and Simulation,’’ IBM J. Res. Dev., vol. 25, pp. 25–41, Jan. 1981.

9. A. R. Djordevic, T. K. Sarkar, and R. F. Harrington, ‘‘Analysis of Lossy Transmission Lines with Arbitrary Nonlinear Terminal Networks,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, pp. 660–666, June 1986.

10. J. Kim and J. F. McDonald, ‘‘Transient and Crosstalk Analysis of Slightly Lossy Interconnection Lines for Wafer Scale Integration and Wafer Scale Hybrid Packaging— Weak Coupling Case,’’ IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1369–1382, Nov. 1988.

11. S. P. Castillo, C. H. Chan, and R. Mittra, ‘‘Analysis of N-Conductor Transmission Line Systems with Non-Linear Loads with Applications to CAD Design of Digital Circuits,’’ Proc. Int. Symp. Electromagn. Compat., pp. 174–175, San Diego, CA, Sept. 16–18, 1986.

12. C. S. Chang, G. Crowder, and M. F. McAllister, ‘‘Crosstalk in Multilayer Ceramic Packaging,’’ Proc. IEEE Int. Symp. Circuits Syst., pp. 6–11, Chicago, IL, Apr. 1981.

13. H. R. Kaupp, ‘‘Pulse Crosstalk between Microstrip Transmission Lines,’’ Proc. 7th Int. Electron. Packaging Symp., pp. 1–12, Los Angeles, CA, Aug. 22–23, 1966.

14. J. C. Isaacs, Jr., and N. A. Strakhov, ‘‘Crosstalk in Uniformly Coupled Lossy Transmission Lines,’’ Bell Syst. Tech. J., vol. 52, pp. 101–115, Jan. 1973.

15. G. Ghione, I. Maio, and G. Vecchi, ‘‘Modeling of Multiconductor Buses and Analysis of Crosstalk, Propagation Delay and Pulse Distortion in High-Speed GaAs Logic Circuits,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-37, pp. 445–456, Mar. 1989.

16. H. You and M. Soma, ‘‘Crosstalk Analysis of Interconnection Lines and Packages in High- Speed Integrated Circuits,’’ IEEE Trans. Circuits Syst., vol. 37, no. 8, pp. 1019–1026, Aug. 1990.

17. A. K. Goel and Y. R. Huang, ‘‘Modelling of Crosstalk among the GaAs-Based VLSI Interconnections,’’ IEE Proc., vol. 136, Pt. G, no. 6, pp. 361–368, Dec. 1989.

18. Y. R. Huang, ‘‘Characterization of Multilevel Interconnections on GaAs-Based VLSI,’’

M. S. Thesis, Michigan Technological University, 1988.

19. P. J. Prabhakaran, ‘‘Analysis of Crossing Interconnections on GaAs-Based VLSICs,’’

M. S. Thesis, Michigan Technological University, 1989.

20. M. K. Mathur, ‘‘Workstation and Microcomputer Analyses of Crossing VLSI Intercon- nections,’’ M. S. Thesis, Michigan Technological University, 1991.

21. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part I: Single Line Transient, Time Delay and Overshoot Expressions,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2068–2077, Nov. 2000.

22. J. A. Davis and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multivel Networks,’’ IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078–2087, Nov. 2000.

23. R. Venkatesaran, J. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Molels—Part III: Transients in Single and Coupled Lines with Capacitive Load Termina- tion,’’ IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1081–1093, Apr. 2003.

24. R. Venkatesan, J. A. Davis, and J. D. Meindl, ‘‘Compact Distributed RLC Interconnect Models—Part IV: Unified Models for Time Delay, Crosstalk and Repeater Insertion,’’ IEEE Trans. Electron Devices, vol. 50, pp. 1094–1102, Apr. 2003.

25. K. S. Crump, ‘‘Numerical Inversion of Laplace Transforms Using a Fourier Series Approximation,’’ J. ACM, vol. 23, pp. 89–96, Jan. 1976.

26. R. M. Simon, M. T. Stroot, and G. H. Weiss, ‘‘Numerical Inversion of Laplace Transforms with Application to Percentage Labeled Mitoses Experiments,’’ Comput. Biomed. Res., vol. 5, pp. 596–607, 1972.

27. T. Sakurai, ‘‘Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI’s,’’ IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118–124, Jan. 1993.

28. T. K. Sarkar and J. R. Mosig, ‘‘Comparison of Quasi-Static and Exact Electromagnetic Fields from a Horizontal Electric Dipole above a Lossy Dielectric Backed by an Imperfect Ground Plane,’’ IEEE Trans. Microwave Theory Tech., vol. MTT-34, pp. 379–387, Apr. 1986.

29. J. Siegl, V. Tulaja, and R. Hoffman, ‘‘General Analysis of Interdigitated Microstrip Couplers,’’ Siemens Forsch.-u. Entwickl.-Ber., vol. 10, no. 4, pp. 228–236, 1981.

30. N. Moisan, ‘‘Etude Theorique et Experimentale Des Effets de Propagation dans les Circuits Logiques Rapides,’’ Ph.D. Thesis, Institut National des Sciences Appliquees de Rennes, France, Oct. 1986.

31. N. Moisan, J. M. Floc’h, and J. Citerne, ‘‘Efficient Modelling Technique of Lossy Microstrip Line Sections in Digital GaAs Circuits,’’ Proc. 16th European Microwave Conf., pp. 698–704, 1986.

(312) (CROSSTALK ANALYSIS)

CHAPTER FIVE

Electromigration-Induced Failure Analysis

The term electromigration refers to mass transport in metals under high-stress conditions especially under high current densities and high temperatures. This phenomenon has been studied in different metallizations during the last several years [1–61] and presents a key problem in VLSI circuits since it causes open-circuit and short-circuit failures in the VLSI interconnections. Currently, there is a trend to fabricate VLSI circuits on small chip areas to save space and reduce propagation delays. According to scaling theory for both bipolar and FET circuits, if the chip area is decreased by a factor k, the current density increases by at least the same factor in both cases, and this becomes one of the primary reasons for circuit failure. This chapter is organized as follows:

(●)Several factors related to electromigration in the VLSI interconnection metallizations are reviewed in Section 5.1. In this section, the basic problems that cause electromigration are outlined, the mechanisms and dependence of electromigration on several factors are discussed, testing and monitoring techniques and guidelines are presented, and the methods of reducing electromigration in VLSI interconnections are briefly discussed.

(●)Various models of IC reliability, including the series model of failure mechanism in VLSI interconnections, are presented in Section 5.2.

(●)A model of electromigration due to repetitive pulsed currents is developed in Section 5.3.

(●)Electromigration in the copper interconnections under direct current (DC) and alternating current (AC) conditions is discussed in Section 5.4.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel Copyright # 2007 John Wiley & Sons, Inc.

313

(●)The series model has been used to analyze electromigration-induced failure in several VLSI interconnection components, including multipath interconnec- tions, in Section 5.5.

(●)A few computer programs available for studying electromigration in VLSI interconnections are discussed briefly in Section 5.6.

ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW

Problems Caused by Electromigration

As mentioned earlier, smaller chip areas are desirable because device miniaturization has become a continuing trend in VLSI. To obtain a better understanding of the problems associated with electromigration, dimensional scaling and its effects on current density should be considered. Since different devices have different operational principles, scaling theories and problems may differ. For example, when the dimension of an FET device is reduced by a factor k, the time delay per circuit decreases while the power dissipation remains constant and the current density increases by a factor k. In bipolar devices, the scaling structure is nonlinear. Therefore, it is difficult to get a generalized picture of how scaling affects current density. Basic scaling theories for both FET and bipolar devices are summarized in Table 5.1.1. Despite this problem, it is possible to classify the problems caused by electromigration into two categories: geometry- and material-related problems [65–71].

Geometry-Related Problems

Geometry-related problems arise as a result of the reduction of interconnection dimensions to the micrometer or submicrometer range. In metal films, with grain size about the same or even larger than film thickness, the flux generated is confined mainly along grain boundaries. As a consequence, the small number of grains across the line increases the importance of each individual inhomogenous site of the grain structure and its effect on the overall mass flow pattern. That makes each individual divergent site potentially more damaging since a line can fail without requiring a

TABLE 5.1.1 Scaling of Device Parameters

Device ParametersFET [69]Bipolar [70] Device dimension1/k1/k

(~)Voltage1/k1

Current1/k1/k

Delay time/circuit1/k1/k

(~)Power density1k

Line resistancekk

Line current densityk~k2

(322) (ELECTROMIGRATION-INDUCED FAILURE ANALYSIS)

(ELECTROMIGRATION IN VLSI INTERCONNECTION METALLIZATIONS: OVERVIEW) (321)

statistical linkage of several divergent sites. Another problem concerns the device contacts and step coverages. As the dimensions of device contacts decrease, they become comparable to those of the interconnection lines, thus subjecting them to about the same amount of current densities as the conductor lines. In some cases, the stress generated by the abrupt structural variations in contacts and steps can play an important role in causing their failure.

Material-Related Problems

Material-related problems are basically caused by the high current densities. Three associated problems in electromigration are referred to as joule heating, current crowding, and material reactions.

(·)Joule Heating. As the chip size decreases, heat distribution becomes a serious problem. This is especially true in the case of bipolar VLSI because the power density increases by a factor k when the dimensions decrease by the same factor based on the constant-voltage assumption. For a metal wire that can afford a certain current density rate of about 105 A/m2 s before melting, joule heat generated by current density in the interconnection line exceeding half of this limit must be completely removed through the substrate and/or some passivation layer. Cooling rate has to be faster than the heating rate due to the current density to avoid overheating the line. Therefore, at high current density, say, above 106 A/cm2, any imperfection of the substrate may result in thermal runaway and destroy the line because of inadequate space for heat dissipation. This also results in raising the strip temperature, which accelerates the diffusion process, thus reducing the mean time to failure (MTF).

Current Crowding. Current crowding refers to uneven distribution of currents along the metallization lines. It occurs especially in metallizations with structural inhomogeneities. It can alter the local electromigration driving force, thus affecting the mass transport pattern. It can also cause the atoms in the metallization lines to migrate with different velocities, resulting in the formation of voids that cause open- circuit failure.

Material Reactions. Material reactions are part of the effects caused by electromigration. As significant mass accumulation and depletion occur, the amount of mass transport is significant enough to generate enough stress to induce extrusion in the passive layer. It can also change the electrical properties of the junction contacts [71]. Furthermore, the joule heat can suppress or promote any unwanted interfacial material reactions. These problems can alter the device and interconnection characteristics and degrade VLSI reliability [68].

Electromigration Mechanism and Factors

Much research has been carried out to study the electromigration pattern as well as the factors that affect electromigration [1–64, 72–135]. In this section, the basic mechanisms and associated factors affecting electromigration are discussed.

Mechanism

In general, a metallization line consists of an aggregate of metallic ions. These ions are held together by a binding force and opposed by a repulsive electrostatic force. At any given temperature, some of these ions may have sufficient energy to escape from the potential well that binds them in the lattice. When they reach the saddle point of the potential well, they are free from the lattice and become ‘‘activated.’’ The energy needed to achieve this is known as the activation energy. Since a metallization line also contains a certain concentration of vacancies, these ions can diffuse out of the lattice into an adjacent vacancy. This process is known as self- diffusion. In the absence of an electric current, the self-diffusion process is more or less isentropic; that is, the probability for each nearest ion around the vacancy to exchange with the vacancy is equal. Under no concentration gradient or chemical potential [104, 105], a random rearrangement of individual ions takes place resulting in no mass transportation. Once the current is applied, the situation changes. Now, there are two external forces exerted on the metallization, namely the frictional force and the electrostatic force. The frictional force is due to the momentum exchange with the crystal and its magnitude is proportional to the current density. The electrostatic force is due to the interactions between the electric fields created by the electrons and the positively charged metallic ions. The electric field due to the electrons will attract the positively charged metallic ions toward the cathode against the electron wind and its magnitude, denoted by E, is given by

E ¼ rJð5:1:1Þ

where r ¼ density of ions

J ¼ current density

Because of the presence of ‘‘shielding electrons,’’ the frictional force is always greater than the electrostatic force.

Consider a metal strip as shown in Fig. 5.1.1. The frictional force and the electrostatic force are denoted by F1 and F2, respectively. The frictional force is acting in the direction of the current flow and the electrostatic force is acting against the current flow. The electric field E also acts against the current flow. Since F1 is

FIGURE 5.1.1 Frictional and electrostatic forces (F1 and F2, respectively) inside current- carrying metal strip.

much greater than F2, the net force, denoted by F, will be in the direction of the current flow. Defining the direction of the net force being positive, we have

F ¼ F1 — F2 ¼ ðZmeÞEð5:1:2Þ

where Zme is the effective charge assigned to the migrated ion with Zm given by [22]

(2rN md)Zm ¼ Z. rd Nm — 1Σð5:1:3Þ

where Z ¼ electron-to-atom ratio

rd ¼ defect resistivity Nd ¼ density of defects r ¼ resistivity of metal N ¼ density of metal

mm ¼ effective electron mass

m ¼ free-electron mass

The first and the second terms in Eq. (5.1.3) correspond to the forces F1 and F2, respectively. According to the Nernst–Einstein equation, the average drift velocity v is given by

v ¼ mFð5:1:4Þ

where m ¼ mobility; ¼ D=fkT

D ¼ self-diffusion coefficient, ¼ D0 expð—Ea=kT Þ

f ¼ correlation factor depending on lattice structure; in most cases, f ¼ 1

k ¼ Boltzmann’s constant

Ea ¼ activation energy

T ¼ absolute temperature

The induced flux due to the creation of this frictional force is now given by [94]

cA ¼ Nvð5:1:5Þ

Combining Eqs. (5.1.1), (5.1.2), (5.1.4), and (5.1.5), we get

(fkT) (A)c ¼ NDrJ ðZmeÞð5:1:6Þ

or

(A) (fkT) (kT)c ¼ .ND0rJΣðZmeÞ exp.— Ea Σð5:1:7Þ

In general, cA may not be the same throughout the metallization because of structural inhomogeneities. Such a divergence of flux in the metallization is more likely to occur under high-current-density conditions. If the divergence becomes

significant, the original isentropic self-diffusion is perturbed and the ions moving along the current flow have a higher probability of exchanging positions with the vacancies. As a result, the original random process changes to a directional process in which the metallic ions move opposite to the electron wind direction while the vacancies move in the opposite direction. The metallic ions condense to form whiskers whereas the vacancies condense to form voids [105–108]. This process results in the change in the density of the metal ions with respect to time. The rate of this change, dN=dt, can be expressed as [33]

dN

dt ¼ —VdivðcAÞð5:1:8Þ

where V is volume and

(A) (dx) (dy) (dz)divðc Þ ¼ dcA þ dcA þ dcA

The formation of voids causes some of the metallization lines to fail, forcing the current to go through the rest of the lines and resulting in an increase in the current density and joule heat. This production of joule heat can increase the local temperature and cause more lines to fail [91]. Furthermore, as the whiskers and hilllocks form, a concentration gradient is produced which may create a stress- related force enhancing the mass transport process and causing more lines to fail [109–111]. All these processes continue as a loop, shown in Fig. 5.1.2, until the circuit fails to work. The MTF, or t50, is defined as the time taken for 50% of the lines to fail and is given by

(kT)MTF ¼ AJ—n exp.Ea Σð5:1:9Þ

where Ea ¼ activation energy

J ¼ current density

T ¼ temperature, K

A ¼ constant depending on geometry and material properties k ¼ Boltzmann’s constant

n ¼ constant ranging from 1 to 7

The value of n is stated last because of its variance found in different reference texts and research works [112]. Some of the n values reported in different works are listed in Table 5.1.2. The deviation of n values has been explained as due to the overestimation of joule heating resulting in low values of n and the underestimation

FIGURE 5.1.2 Schematic of various factors that contribute to electromigration in VLSI interconnection metallizations. (Modified from [91].)

of joule heating resulting in an apparent very large current density dependence and hence high values of n. In general, the correct value of n should lie between 1 and 2 [124]. If the cross-sectional area A is also taken into account [83], then Eq. (5.1.9) is modified as

(kT)MTF ¼ AJ—n exp.Ea Σð5:1:10Þ

It is also interesting to study the speed of the metallic ions and its relationship to MTF. According to Gimpelson [115], the migration velocity vm can be expressed as

(kT) (m)v ¼ GJ exp.— Ea Σð5:1:11Þ

TABLE 5.1.2 Values of the Exponent n from the Literature

(SourceCurrent DensitynHuntington and Grone [21]<0.5 MA/cm21Attardo [114]0.5–1 MA/cm21.5Black [83]0.45–2.88 MA/cm21–2 MA/cm22þ)Blair et al. [54]6–7

Chhabra and Ainslie [85]—1–3

Venables and Lye [90]—1

Sigsbee [88, 89]&1 MA/cm21

Vaidya et al. [62]—2

Danso and Tullos [51]0.168–0.704 MA/cm21.7

Chern et al. [41]—2.5 T 0.5

where G is a proportionality constant. Combining Eqs. (5.1.10) and (5.1.11), MTF can be expressed as

(n)MTF ¼ Gn A exp.— ðn — 1ÞEaΣð5:1:12Þ

ðvmÞkT

Factors

Some known factors that induce electromigration can be classified as follows.

Current Density. Current density is the key factor that contributes to the frictional forces as well as to the flux divergence. At a high current density, the momentum exchange between the current carriers and the metallic ions becomes significantly large resulting in a very large frictional force and flux divergence along the metallization lines resulting in mass transport that leads to line failure. It is obvious from Table 5.1.3 that the MTF decreases as the current density increases. This result has been verified by plenty of research work [1–61, 72–103, 116, 117].

Thermal Effects. Thermal gradients and the line temperature are two other important factors that cause electromigration. It has been reported that the electromigration process occurs in the direction from high temperature to low temperature and that thermal gradients are very important in the electromigration process because these can induce a thermal force that enhances further mass transport in the metallization lines [33, 94, 118, 119]. Thermal gradients are dependent on the metallization structure as well as on the processing techniques.

Line temperature is also an important factor in the electromigration process [12, 14, 120–124]. According to Eq. (5.1.9), the MTF decreases with the increase in line

TABLE 5.1.3 Dependence of MTF on Current Density for Three Aluminum Film Conductors of Cross-Sectional Area 10—7 cm2 and Temperature 160○C

MTF (h)

Current Density (MA/cm2)

Small Crystallite

Large Crystallite

Glassed Large Crystallite

0.1

15,500

120,000

0.2

4,000

30,000

0.4

960

7,800

65,000

0.6

450

3,300

29,000

0.8

250

1,900

15,000

1.0

155

1,250

11,000

2.0

40

300

2,700

4.0

10

75

700

6.0

—

33

370

8.0

—

18

Source: Data derived from [83].

TABLE 5.1.4 Dependence of MTF on Temperature for Three Aluminum Film Conductors of Cross-Sectional Area 10—7 cm2 and Carrying Current Density 1 MA / cm2

MTF (h)

Temperature (○C)

Small Crystallite

Large Crystallite

Glassed Large Crystallite

40

23,000

60

7,700

80

3,000

100

1,280

47,000

120

580

12,500

140

300

3,800

50,000

160

155

1,250

11,000

180

90

450

2,800

200

52

180

800

220

32

80

255

240

21

37

90

260

14

18

34

Source: Data derived from [83].

temperature. This conclusion can also be drawn from Table 5.1.4. In general, if the VLSI system is operating at room temperature under normal conditions, thermal effects can be considered insignificant.

Line Length and Line Width. Table 5.1.5 shows the relationship between the MTF and line length. As mentioned earlier, voids, hilllocks, and whiskers are formed along the interconnection line during electromigration, creating a stress-related force that enhances further electromigration. The magnitude of this force is proportional to the concentration gradient. If the lines are long, the concentration gradient will be much larger, resulting in shorter electromigration lifetime as compared to the shorter lines [125].

Much work has been done to study the effects of line width on the electromigration lifetime as well [126–129]. It has been found that the electromigration lifetime is inversely proportional to line width. This is because, for small line widths, the

TABLE 5.1.5 Dependence of MTF on Length of Interconnection Line with Width 2 lm and Median Grain Size 1.25 lm

Length (mm)

MTF (h)

10

530

20

380

30

325

40

315

Source: Data derived from [93].

TABLE 5.1.6 Dependence of MTF on Width of

Interconnection Line with Length 25 lm and Median Grain Size 0.75 lm

Width (mm)

MTF (h)

0.5

165

1.0

220

1.5

270

2.0

305

2.5

335

Source: Data derived from [93].

cross-sectional area will also be small, resulting in higher current density that may degrade the electromigration lifetime. Experimental data on this relationship are shown in Table 5.1.6.

Activation Energy and Material Structure. Activation energy of a metallization line depends on its material structure and, therefore, different metallization lines may have different values of activation energy. For VLSI interconnections, metallizations having high activation energy are desirable because they lead to enhanced stability. Material structure also affects the electromigration lifetime in many ways. Known aspects include grain orientation, grain size, and grain boundaries. Reports have shown that electromigration is related to structural inhomogeneity [33, 35, 36, 124]. An ideal metallization line is the one with uniform grain size and regular grain orientation. Unfortunately, this is not possible and there is always some degree of inhomogeneity that induces flux divergence [131, 134, 135]. As the metallization line becomes more inhomogenous in structure, this flux becomes more divergent, resulting in smaller MTF. Based on the previous studies, it is known that electromigration is confined mainly to the grain boundaries [6, 33, 35, 79, 84]. Smaller grain size means that more grain boundaries are available for electromigration. Table 5.1.7 shows the experimental relationship between grain size and MTF. The fact that smaller grain size degrades the electromigration lifetime has been verified by many researchers [39, 79, 93]. If the grain size is large enough to

TABLE 5.1.7 Dependence of MTF on Median Grain Size for Interconnection Line with Width 1 lm and Length 20 lm

Median Grain Size (mm)

MTF (h)

1.0

245

1.5

330

2.0

405

2.5

460

3.0

515

Source: Data derived from [93].

be comparable to the stripe width, then the single grain can act as a barrier to the migrating atoms [35, 130, 133, 135].